1 #include <system_def.h>
11 #include <hal_machperiph.h>
18 #include <ul_logreg.h>
20 #include "appl_defs.h"
21 #include "appl_fpga.h"
23 int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
30 snprintf(str, sizeof(str), "memusage maxaddr 0x%08lx\n", (unsigned long)maxaddr);
31 cmd_io_write(cmd_io, str, strlen(str));
36 int cmd_do_test_adc(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
38 printf("ADC: %ld %ld %ld %ld %ld\n", (LPC_ADC->DR[0] & 0xFFF0) >> 4,
39 (LPC_ADC->DR[1] & 0xFFF0) >> 4,
40 (LPC_ADC->DR[2] & 0xFFF0) >> 4,
41 (LPC_ADC->DR[3] & 0xFFF0) >> 4,
42 (LPC_ADC->DR[7] & 0xFFF0) >> 4);
46 #ifdef APPL_WITH_DISTORE_EEPROM_USER
47 int cmd_do_test_distore(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
49 appl_distore_user_set_check4change();
53 int cmd_do_test_diload(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
55 appl_distore_user_restore();
58 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
60 int cmd_do_test_loglevel_cb(ul_log_domain_t *domain, void *context)
63 cmd_io_t *cmd_io = (cmd_io_t *)context;
66 snprintf(s, sizeof(s) - 1, "%s (%d)\n\r", domain->name, domain->level);
67 cmd_io_puts(cmd_io, s);
71 int cmd_do_test_loglevel(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
77 if (!line || (si_skspace(&line), !*line))
79 ul_logreg_for_each_domain(cmd_do_test_loglevel_cb, cmd_io);
83 res = ul_log_domain_arg2levels(line);
86 return res >= 0 ? 0 : CMDERR_BADPAR;
89 int cmd_do_spimst_blocking(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
94 int spi_chan = (int)(intptr_t)des->info[0];
95 uint8_t *tx_buff = NULL;
96 uint8_t *rx_buff = NULL;
101 if ((opchar = cmd_opchar_check(cmd_io, des, param)) < 0)
105 return -CMDERR_OPCHAR;
108 spi_chan = *param[1] - '0';
110 spi_drv = spi_find_drv(NULL, spi_chan);
113 return -CMDERR_BADSUF;
119 if (isdigit((int)*p))
121 if (si_long(&p, &addr, 16) < 0)
122 return -CMDERR_BADPAR;
125 if (si_fndsep(&p, "({") < 0)
126 return -CMDERR_BADSEP;
128 if ((res = si_add_to_arr(&p, (void **)&tx_buff, &len, 16, 1, "})")) < 0)
129 return -CMDERR_BADPAR;
131 rx_buff = malloc(len);
136 res = spi_transfer(spi_drv, addr, len, tx_buff, rx_buff);
140 printf("SPI! %02lX ERROR\n", addr);
145 printf("SPI! %02lX ", addr);
148 for (i = 0; i < len; i++)
149 printf("%s%02X", i ? "," : "", tx_buff[i]);
153 for (i = 0; i < len; i++)
154 printf("%s%02X", i ? "," : "", rx_buff[i]);
171 int sdram_access_test(void)
174 unsigned int pattern;
175 size_t ramsz = SDRAM_SIZE;
183 pattern = 0x12abcdef;
185 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
188 pattern = pattern + 0x87654321;
192 printf("SDRAM write %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
197 pattern = 0x12abcdef;
199 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
203 printf("SDRAM error modify at %p (%08x)\n", ptr, *ptr ^ pattern);
208 pattern = pattern + 0x87654321;
212 printf("SDRAM modify %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
217 pattern = 0x12abcdef;
219 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
221 if (*(ptr++) != ~pattern)
223 printf("SDRAM error read at %p (%08x)\n", ptr, *ptr ^ pattern);
227 pattern = pattern + 0x87654321;
231 printf("SDRAM read %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
238 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
244 printf("SDRAM sum %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), pattern);
246 for (blksz = 1; blksz < 256 ; blksz *= 2)
253 for (cnt = ramsz / sizeof(*ptr); cnt; cnt -= blksz)
255 ptr = (typeof(ptr))SDRAM_BASE;
257 //ptr = (typeof(ptr))cmd_do_test_memusage;
258 //ptr = (typeof(ptr))&ptr;
259 for (i = blksz; i--;)
264 printf("SDRAM sum %d blksz %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), (int)blksz, pattern);
270 int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
275 #endif /*SDRAM_BASE*/
277 int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
279 pxmc_rocon_rx_data_hist_buff = NULL;
280 #ifndef PXMC_ROCON_TIMED_BY_RX_DONE
281 pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
282 #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
283 pxmc_rocon_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
285 pxmc_rocon_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
289 int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
291 printf("lxpwrrx period %ld latency %ld max %ld\n",
292 (long)pxmc_rocon_rx_cycle_time, (long)pxmc_rocon_rx_irq_latency,
293 (long)pxmc_rocon_rx_irq_latency_max);
299 int cmd_do_testfncapprox(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
313 long step = 1 << (30-7-18+1 +4);
316 if (si_ulong(&ps, &fnc, 0) < 0)
317 return -CMDERR_BADPAR;
320 if (!strcmp(ps, "all")) {
322 count = 0x80000000UL / step;
327 if (si_ulong(&ps, &val, 0) < 0)
328 return -CMDERR_BADPAR;
331 for (; count--; val += step) {
335 xb = __builtin_clz(x);
341 fpga_fncapprox_base[fnc] = xl;
343 /* dummy read to provide time to function aproximator to proceed computation */
344 res = fpga_fncapprox_base[fnc];
345 res = fpga_fncapprox_base[fnc];
351 yl = (1LL << 62) / xl;
354 xf = (double)xl * M_PI / 2.0 / (1UL << 30);
355 yl = round(sin(xf) * (1UL << 16));
358 xf = (double)xl * M_PI / 2.0 / (1UL << 30);
359 yl = round(cos(xf) * (1UL << 16));
367 if ((diff > 0) && (diff > diff_max))
369 else if ((diff < 0) && (-diff > diff_max))
376 printf("fnc=%ld val=0x%08lx res=0x%08lx ref=0x%08lx diff=%ld max %ld\n",
377 fnc, val, res, (unsigned long)yl, diff, diff_max);
382 int cmd_do_testtumblefw(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
392 pxmc_state_t *mcs = pxmc_main_list.pxml_arr[0];
394 fpga_tumbl_dmem[0] = 0;
397 if (si_long(&ps, &pwm_d, 0) < 0)
398 return -CMDERR_BADPAR;
401 if (si_ulong(&ps, &pwm_q, 0) < 0)
402 return -CMDERR_BADPAR;
404 irc = fpga_irc[0]->count;
405 ptofs = (int16_t)(mcs->pxms_ptofs - irc) + irc;
407 ptirc = mcs->pxms_ptirc;
408 ull = (1ULL << 32) * mcs->pxms_ptper;
409 ptreci = (ull + ptirc / 2) / ptirc;
411 fpga_tumbl_dmem[0] = 0;
412 fpga_tumbl_dmem[1] = pwm_d;
413 fpga_tumbl_dmem[2] = pwm_q;
415 fpga_tumbl_dmem[6] = ptirc;
416 fpga_tumbl_dmem[7] = ptreci;
417 fpga_tumbl_dmem[8] = ptofs;
419 fpga_tumbl_dmem[0] = 1;
421 printf("spd %ld\n",mcs->pxms_as);
427 cmd_des_t const cmd_des_test_memusage = {0, 0,
428 "memusage", "report memory usage", cmd_do_test_memusage,
435 cmd_des_t const cmd_des_test_adc = {0, 0,
436 "testadc", "adc test", cmd_do_test_adc,
443 #ifdef APPL_WITH_DISTORE_EEPROM_USER
444 cmd_des_t const cmd_des_test_distore = {0, 0,
445 "testdistore", "test DINFO store", cmd_do_test_distore,
452 cmd_des_t const cmd_des_test_diload = {0, 0,
453 "testdiload", "test DINFO load", cmd_do_test_diload,
459 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
461 cmd_des_t const cmd_des_test_loglevel = {0, 0,
462 "loglevel", "select logging level",
463 cmd_do_test_loglevel, {}
466 cmd_des_t const cmd_des_spimst = {0, CDESM_OPCHR | CDESM_WR,
467 "SPIMST", "SPI master communication request",
468 cmd_do_spimst_blocking, {(void *)0}
471 cmd_des_t const cmd_des_spimstx = {0, CDESM_OPCHR | CDESM_WR,
472 "SPIMST#", "SPI# master communication request",
473 cmd_do_spimst_blocking, {(void *) - 1}
477 cmd_des_t const cmd_des_testsdram = {0, 0,
478 "testsdram", "test SDRAM",
479 cmd_do_testsdram, {(void *)0}
481 #endif /*SDRAM_BASE*/
484 cmd_des_t const cmd_des_testlxpwrrx = {0, 0,
485 "testlxpwrrx", "capture data stream from lxpwr",
486 cmd_do_testlxpwrrx, {(void *)0}
489 cmd_des_t const cmd_des_testlxpwrstat = {0, 0,
490 "testlxpwrstat", "lxpwr interrupt statistic",
491 cmd_do_testlxpwrstat, {(void *)0}
494 cmd_des_t const cmd_des_testfncapprox = {0, 0,
495 "testfncapprox", "test of function approximator",
496 cmd_do_testfncapprox, {(void *)0}
499 cmd_des_t const cmd_des_testtumblefw = {0, 0,
500 "testtumblefw", "test Tumble coprocesor firmware",
501 cmd_do_testtumblefw, {(void *)0}
504 cmd_des_t const *const cmd_appl_tests[] =
506 &cmd_des_test_memusage,
508 #ifdef APPL_WITH_DISTORE_EEPROM_USER
509 &cmd_des_test_distore,
510 &cmd_des_test_diload,
511 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
512 &cmd_des_test_loglevel,
517 #endif /*SDRAM_BASE*/
518 &cmd_des_testlxpwrrx,
519 &cmd_des_testlxpwrstat,
520 &cmd_des_testfncapprox,
521 &cmd_des_testtumblefw,