1 # TOP - Name of the top-level module
2 # DEVICE - Name of the FPGA device (device-package-speed)
3 # PRJ - Name of .prj file with names of all source files. See XST manual.
4 # UCF - Name of the user constraints file
5 # SEARCH_DIRS - Directories to search when searching for netlists (.ngc, ...).
7 # INTSTYLE - Style of screen output. (ise | xflow | silent)
10 # - synthesize : Synthesize all VHDL and Verilog source files, libraries, etc.
11 # defined in PRJ files and produces NGC file.
12 # - translate : Translate all netlist files (.ngc, ...) into the NGD file,
13 # where the design is described in terms of deneral logic elements
14 # such as (RAM, flip-flop, XOR, ...).
15 # - map : Map the general logic from NGD file to the components in the
16 # target FPGA and produces NCD_MAP file.
17 # - par : PAR stands for Plase & Route. This procedure takes NCD_MAP file,
18 # places all components and makes routes between them (depending
19 # on the chosen optimization mode) and produces NCD file.
20 # - clean : Clean build directory, dependency (*.d) files and call
21 # - all : Transfer placed and routed NCD file into the bit file, which can
22 # be then used to configure particular FPGA
24 # Dependicies are handled, so in most cases only 'download' target is called.
26 DEVICE := xc6slx9-2tqg144
31 REQB := $(OUT)/$(OUTB)
32 PRJ := lx_rocon_top.prj
34 SEARCH_DIRS := ipcore_dir
38 #===============================================================================
39 # Abbreviations of frequently used file names.
44 NCD_MAP := $(OUTB)_map.ncd
48 REQ_NGC := $(REQB).ngc
49 REQ_NGD := $(REQB).ngd
50 REQ_PCF := $(REQB).pcf
51 REQ_NCD_MAP := $(REQB)_map.ncd
52 REQ_NCD := $(REQB).ncd
53 REQ_BIT := $(REQB).bit
56 #===============================================================================
58 # Attempt to create a output directory.
59 $(shell [ -d ${OUT} ] || mkdir -p ${OUT})
61 # Verify if it was successful.
62 OUTPUT_DIR := $(shell cd $(OUT) && /bin/pwd)
63 $(if $(OUTPUT_DIR),,$(error output directory "$(OUT)" does not exist))
65 #===============================================================================
71 re-synthesize $(REQ_NGC): $(addprefix $(REQ_SRC)/,$(PRJ))
75 $(addprefix -ifn $(SRC)/,$(PRJ)) \
82 -keep_hierarchy soft \
83 -opt_level 1" | xst | tee xst.log
86 re-translate $(REQ_NGD): $(REQ_NGC) $(REQ_UCF)
88 ngdbuild -intstyle $(INTSTYLE) -p $(DEVICE) -uc $(SRC)/$(UCF) \
89 $(addprefix -sd $(SRC)/,$(SEARCH_DIRS)) \
94 re-map $(REQ_NCD_MAP) $(REQ_PCF): $(REQ_NGD)
96 map -intstyle $(INTSTYLE) -o $(NCD_MAP) $(NGD) $(PCF)
99 re-par $(REQ_NCD): $(REQ_NCD_MAP) $(REQ_PCF)
101 par -intstyle $(INTSTYLE) $(NCD_MAP) -w $(NCD) $(PCF)
104 re-gen $(REQ_BIT): $(REQ_NCD)
106 bitgen -w $(NCD) $(OUTB) $(PCF)
108 #===============================================================================
115 synthesize: $(REQ_NGC)
118 translate: $(REQ_NGD)
121 map: $(REQ_NCD_MAP) $(REQ_PCF)