]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/blob - hw/lx_rocon_top.prj
FPGA: Bugfixes, custom packaging and added testing modules
[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_top.prj
1 vhdl work "dff.vhd"
2 vhdl work "qcounter.vhd"
3 vhdl work "irc_reader.vhd"
4 vhdl work "irc_register.vhd"
5 vhdl work "ipcore_dir/control_bram.vhd"
6 vhdl work "bcd.vhd"
7 vhdl work "bus_irc.vhd"
8 vhdl work "bus_id.vhd"
9 vhdl work "bus_control_bram.vhd"
10 vhdl work "bus_bcd.vhd"
11 vhdl work "lx_rocon_top.vhd"