hw/lx-rocon_tumbl/lx_rocon_tumbl.vhd

   1 library ieee;
   2
   3 use ieee.std_logic_1164.all;
   4 use ieee.std_logic_arith.all;
   5 use ieee.std_logic_unsigned.all;
   6 use ieee.numeric_std.all;
   7 use work.mbl_Pkg.all;
   8 use work.lx_rocon_pkg.all;
   9
  10 -- Tumbl configured as a coprocessor for lx_rocon
  11 -- Uses 10 bits width address bus with HW barrel and multiplier
  12
  13 entity lx_rocon_tumbl is
  14         generic
  15         (
  16                 IMEM_ABITS_g : positive := 11;
  17                 DMEM_ABITS_g : positive := 12;
  18                 --
  19                 USE_HW_MUL_g :  boolean := true;
  20                 USE_BARREL_g :  boolean := true;
  21                 COMPATIBILITY_MODE_g : boolean := false
  22         );
  23         port
  24         (
  25                 clk_i        :  in std_logic;
  26                 rst_i        :  in std_logic;
  27           halt_i       :  in std_logic;
  28                 int_i        :  in std_logic;
  29                 trace_i      :  in std_logic;
  30                 trace_kick_i :  in std_logic;
  31
  32                 -- Program counter
  33                 pc_o         : out std_logic_vector(31 downto 0);
  34
  35                 -- Internal halt (remove with trace kick)
  36                 halted_o     : out std_logic;
  37                 halt_code_o  : out std_logic_vector(4 downto 0);
  38
  39                 -- Internal memory (instruction)
  40                 imem_clk  : in std_logic;
  41     imem_en   : in std_logic;
  42     imem_we   : in std_logic_vector(3 downto 0);
  43     imem_addr : in std_logic_vector(8 downto 0);
  44     imem_din  : in std_logic_vector(31 downto 0);
  45     imem_dout : out std_logic_vector(31 downto 0);
  46
  47                 -- Internal memory (data)
  48                 dmem_clk  : in std_logic;
  49     dmem_en   : in std_logic;
  50     dmem_we   : in std_logic_vector(3 downto 0);
  51     dmem_addr : in std_logic_vector(9 downto 0);
  52     dmem_din  : in std_logic_vector(31 downto 0);
  53     dmem_dout : out std_logic_vector(31 downto 0);
  54
  55                 -- External memory bus
  56                 XMEMB_sel_o :  out std_logic;
  57                 XMEMB_i     :  in DMEMB2CORE_Type;
  58                 XMEMB_o     :  out CORE2DMEMB_Type;
  59                 --
  60                 bad_op_o    :  out std_logic
  61         );
  62 end entity lx_rocon_tumbl;
  63
  64 architecture rtl of lx_rocon_tumbl is
  65
  66         constant DMEM_TEST_c : std_logic_vector((31-DMEM_ABITS_g) downto 0) := (others => '0');
  67
  68         signal imem_clken_s  : std_logic;
  69         signal imem_addr_s   : std_logic_vector(31 downto 0);
  70         signal imem_data_s   : std_logic_vector(31 downto 0);
  71         signal gprf_clken_s  : std_logic;
  72         signal core_clken_s  : std_logic;
  73         signal pc_ctrl_s     : std_logic;
  74         signal c2dmemb_s     : CORE2DMEMB_Type;
  75         signal dmem_data_s   : std_logic_vector(31 downto 0);
  76         signal DMEMB_i_s     : DMEMB2CORE_Type;
  77
  78         signal MEM2CTRL_s    : MEM2CTRL_Type;
  79         signal INT_CTRL_s    : INT_CTRL_Type;
  80         signal ID2CTRL_s     : ID2CTRL_Type;
  81
  82         signal IF2ID_s,      IF2ID_r      : IF2ID_Type;
  83         signal ID2EX_s,      ID2EX_r      : ID2EX_Type;
  84         signal ID2GPRF_s                  : ID2GPRF_Type;
  85         signal GPRF2EX_s                  : GPRF2EX_Type;
  86         signal EX2IF_s,      EX2IF_r      : EX2IF_Type;
  87         signal EX2CTRL_s                  : EX2CTRL_Type;
  88         signal EX2MEM_s,     EX2MEM_r     : EX2MEM_Type;
  89         signal EX_WRB_s,     EX_WRB_r     : WRB_Type;
  90         signal MEM_WRB_s                  : WRB_Type;
  91         signal IMM_LOCK_s,   IMM_LOCK_r   : IMM_LOCK_Type;
  92         signal HAZARD_WRB_s, HAZARD_WRB_r : HAZARD_WRB_Type;
  93         signal EX2MSR_s                   : MSR_Type;
  94         signal MSR2EX_s                   : MSR_Type;
  95         signal MEM_REG_s,    MEM_REG_r    : MEM_REG_Type;
  96         signal dmem_sel_s,   dmem_sel_r   : std_logic;
  97         signal bad_op_s                   : std_logic;
  98         signal HALT_s                     : HALT_Type;
  99         signal ext_halt_s                 : std_logic;
 100
 101         signal imem_really_clken_s        : std_logic;
 102         signal dmem_really_sel_s          : std_logic;
 103         signal gprf_really_clken_s        : std_logic;
 104
 105 begin
 106
 107         -- select internal data memory when all address bits above DMEM_ABITS_g are zero
 108         dmem_sel_s  <= '1' when (c2dmemb_s.addr(31 downto DMEM_ABITS_g) = DMEM_TEST_c)
 109                                                                         else '0';
 110         XMEMB_sel_o <= not dmem_sel_s;
 111         XMEMB_o     <= c2dmemb_s;
 112         pc_o        <= ID2EX_r.program_counter; -- Program counter for EXEQ
 113         halted_o    <= HALT_s.halt;
 114         halt_code_o <= HALT_s.halt_code;
 115         bad_op_o    <= bad_op_s;
 116         ext_halt_s  <= halt_i;
 117
 118         imem_really_clken_s <= imem_clken_s and core_clken_s;
 119         dmem_really_sel_s   <= dmem_sel_s and core_clken_s;
 120         gprf_really_clken_s <= gprf_clken_s and core_clken_s;
 121
 122         I_IMEM: lx_rocon_imem
 123         port map
 124         (
 125                 clk_i => clk_i,
 126                 cs_i  => imem_really_clken_s,
 127                 adr_i => imem_addr_s((IMEM_ABITS_g-1) downto 2),
 128                 dat_o => imem_data_s,
 129
 130                 clk_m => imem_clk,
 131                 en_m => imem_en,
 132                 we_m => imem_we,
 133                 addr_m => imem_addr,
 134                 din_m => imem_din,
 135                 dout_m => imem_dout
 136         );
 137
 138         I_DMEM: lx_rocon_dmem
 139         port map
 140         (
 141                 clk_i  => clk_i,
 142                 ce_i   => dmem_really_sel_s,
 143                 adr_i  => c2dmemb_s.addr((DMEM_ABITS_g-1) downto 2),
 144                 wre_i  => c2dmemb_s.wre,
 145                 bsel_i => c2dmemb_s.bSel,
 146                 dat_i  => c2dmemb_s.data,
 147                 dat_o  => dmem_data_s,
 148
 149                 clk_m => dmem_clk,
 150                 en_m => dmem_en,
 151                 we_m => dmem_we,
 152                 addr_m => dmem_addr,
 153                 din_m => dmem_din,
 154                 dout_m => dmem_dout
 155         );
 156
 157         I_FETCH: fetch
 158         port map
 159         (
 160                 prog_cntr_i => IF2ID_r.program_counter,
 161                 inc_pc_i    => pc_ctrl_s,
 162                 EX2IF_i     => EX2IF_r,
 163                 IF2ID_o     => IF2ID_s
 164         );
 165
 166         I_DECODE: decode
 167         generic map(USE_HW_MUL_g, USE_BARREL_g, COMPATIBILITY_MODE_g)
 168         port map
 169         (
 170                 IF2ID_i     => IF2ID_r,
 171                 imem_data_i => imem_data_s,
 172                 --
 173                 ID2GPRF_o   => ID2GPRF_s,
 174                 ID2EX_o     => ID2EX_s,
 175                 --
 176                 INT_CTRL_i  => INT_CTRL_s,
 177                 ID2CTRL_o   => ID2CTRL_s,
 178                 --
 179                 noLiteOpc_o => bad_op_s
 180         );
 181
 182         I_GPRF: lx_rocon_gprf_abd
 183         port map
 184         (
 185                 clk_i        => clk_i,
 186                 rst_i        => rst_i,
 187                 clken_i      => gprf_really_clken_s,
 188                 --
 189                 ID2GPRF_i    => ID2GPRF_s,
 190                 MEM_WRB_i    => MEM_WRB_s,
 191                 GPRF2EX_o    => GPRF2EX_s
 192         );
 193
 194         I_EXEQ: exeq
 195         generic map(USE_HW_MUL_g, USE_BARREL_g, COMPATIBILITY_MODE_g)
 196         port map
 197         (
 198                 ID2EX_i      => ID2EX_r,
 199                 GPRF2EX_i    => GPRF2EX_s,
 200                 EX2IF_o      => EX2IF_s,
 201                 EX2CTRL_o    => EX2CTRL_s,
 202                 HALT_o       => HALT_s,
 203                 --
 204                 EX_WRB_i     => EX_WRB_r,
 205                 EX_WRB_o     => EX_WRB_s,
 206                 MEM_WRB_i    => MEM_WRB_s,
 207                 --
 208                 HAZARD_WRB_i => HAZARD_WRB_r,
 209                 HAZARD_WRB_o => HAZARD_WRB_s,
 210                 --
 211                 IMM_LOCK_i   => IMM_LOCK_r,
 212                 IMM_LOCK_o   => IMM_LOCK_s,
 213                 --
 214                 MSR_i        => MSR2EX_s,
 215                 MSR_o        => EX2MSR_s,
 216                 --
 217                 EX2MEM_o     => EX2MEM_s
 218         );
 219
 220         -- this is a very simple address block decoder, just "internal" dmem or "external"
 221         -- clken and int hardwired for fast internal data-memory
 222         DMEMB_i_s.clken <= '1'          when (dmem_sel_s = '1') else XMEMB_i.clken;
 223         DMEMB_i_s.data  <=  dmem_data_s when (dmem_sel_r = '1') else XMEMB_i.data;
 224         DMEMB_i_s.int   <= XMEMB_i.int;
 225
 226         I_MEM: mem
 227         port map
 228         (
 229                 EX2MEM_i    => EX2MEM_r,
 230                 MEM_WRB_o   => MEM_WRB_s,
 231                 --
 232                 DMEMB_i     => DMEMB_i_s,
 233                 DMEMB_o     => c2dmemb_s,
 234                 --
 235                 MEM_REG_i  => MEM_REG_r,
 236                 MEM_REG_o  => MEM_REG_s,
 237                 --
 238                 MEM2CTRL_o => MEM2CTRL_s
 239         );
 240
 241         I_CTRL: core_ctrl
 242         generic map (COMPATIBILITY_MODE_g)
 243         port map
 244         (
 245                 clk_i           => clk_i,
 246                 rst_i           => rst_i,
 247                 halt_i          => ext_halt_s,
 248                 bad_op_i        => bad_op_s,
 249                 int_i           => int_i,
 250                 trace_i         => trace_i,
 251                 trace_kick_i    => trace_kick_i,
 252                 core_clken_o    => core_clken_s,
 253                 -- specific fetch i/o
 254                 imem_addr_o     => imem_addr_s,
 255                 imem_clken_o    => imem_clken_s,
 256                 pc_ctrl_o       => pc_ctrl_s,
 257                 -- fetch to decode pipeline registers
 258                 IF2ID_REG_i     => IF2ID_s,
 259                 IF2ID_REG_o     => IF2ID_r,
 260                 -- decode to exeq pipeline registers
 261                 ID2EX_REG_i     => ID2EX_s,
 262                 ID2EX_REG_o     => ID2EX_r,
 263                 -- GPRF control
 264                 gprf_clken_o    => gprf_clken_s,
 265                 -- exeq to fetch feedback registers
 266                 EX2IF_REG_i     => EX2IF_s,
 267                 EX2IF_REG_o     => EX2IF_r,
 268                 EX2CTRL_REG_i   => EX2CTRL_s,
 269                 -- exeq to core (halting)
 270                 exeq_halt_i     => HALT_s.halt,
 271                 -- exeq to mem pipeline registers
 272                 EX2MEM_REG_i    => EX2MEM_s,
 273                 EX2MEM_REG_o    => EX2MEM_r,
 274                 -- mem pipeline register
 275                 MEM_REG_i       => MEM_REG_s,
 276                 MEM_REG_o       => MEM_REG_r,
 277                 -- decode control i/o
 278                 ID2CTRL_i       => ID2CTRL_s,
 279                 INT_CTRL_o      => INT_CTRL_s,
 280                 -- exeq control i/o
 281                 EX_WRB_i        => EX_WRB_s,
 282                 EX_WRB_o        => EX_WRB_r,
 283                 -- data hazard i/o
 284                 HAZARD_WRB_i    => HAZARD_WRB_s,
 285                 HAZARD_WRB_o    => HAZARD_WRB_r,
 286                 -- for handling the 'IMM' instruction
 287                 IMM_LOCK_i      => IMM_LOCK_s,
 288                 IMM_LOCK_o      => IMM_LOCK_r,
 289                 -- for handling the Machine Status Register
 290                 MSR_i           => EX2MSR_s,
 291                 MSR_o           => MSR2EX_s,
 292                 -- miscellaneous
 293                 MEM2CTRL_i      => MEM2CTRL_s
 294         );
 295
 296         regd_proc: process(clk_i, rst_i)
 297         begin
 298                 if clk_i = '1' and clk_i'event then
 299                         if (rst_i = '1') then           -- synchronous reset ...
 300                                 dmem_sel_r <= '1';
 301                         else                            -- delay select_external_mem (needed for reading ...)
 302                                 if (DMEMB_i_s.clken = '1') then
 303                                         dmem_sel_r <= dmem_sel_s;   -- OR c2dmemb_s.wre; ??
 304                                 end if;
 305                         end if;
 306                 end if;
 307         end process regd_proc;
 308
 309 end architecture rtl;