1 -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
3 -- Copyright (c) 2014, Pavel Pisa <pisa@cmp.felk.cvut.cz>
4 -- Designed for PiKRON company robotic controller
5 -- All rights reserved.
7 -- Redistribution and use in source and binary forms, with or without
8 -- modification, are permitted provided that the following conditions are met:
10 -- 1. Redistributions of source code must retain the above copyright notice, this
11 -- list of conditions and the following disclaimer.
12 -- 2. Redistributions in binary form must reproduce the above copyright notice,
13 -- this list of conditions and the following disclaimer in the documentation
14 -- and/or other materials provided with the distribution.
16 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
17 -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
20 -- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 -- Can be used and distributed under GPLv3 license as well
30 use ieee.std_logic_1164.all;
31 use ieee.std_logic_unsigned.all;
32 use ieee.numeric_std.all;
33 use work.util_pkg.all;
34 use work.lx_rocon_pkg.all;
36 entity lx_crosdom_ser_fifo is
39 fifo_len_g : positive := 8;
40 sync_adj_g : integer := 0
44 -- Asynchronous clock domain interface
45 acd_clock_i : in std_logic;
46 acd_miso_i : in std_logic;
47 acd_sync_i : in std_logic;
50 reset_i : in std_logic;
51 -- Output synchronous with clk_i
52 miso_o : out std_logic;
53 sync_o : out std_logic;
54 data_ready_o : out std_logic
56 end lx_crosdom_ser_fifo;
58 architecture Behavioral of lx_crosdom_ser_fifo is
59 signal fifo_bits_s : std_logic_vector(0 to fifo_len_g - 1);
60 signal fifo_bits_r : std_logic_vector(0 to fifo_len_g - 1);
62 signal acd_miso_r : std_logic;
63 signal acd_sync_r : std_logic;
64 signal acd_sync_prev_s : std_logic;
65 signal acd_sync_prev_r : std_logic;
67 signal acd_in_loc_s : natural range 0 to fifo_len_g - 1;
68 signal acd_in_loc_r : natural range 0 to fifo_len_g - 1;
70 signal out_loc_s : natural range 0 to fifo_len_g - 1;
71 signal out_loc_r : natural range 0 to fifo_len_g - 1;
73 signal out_sync_s : std_logic_vector(0 to fifo_len_g / 2 - 1);
74 signal out_sync_r : std_logic_vector(0 to fifo_len_g / 2 - 1);
76 signal out_miso_s : std_logic;
78 attribute REGISTER_DUPLICATION : string;
79 attribute REGISTER_DUPLICATION of fifo_bits_s : signal is "NO";
80 attribute REGISTER_DUPLICATION of fifo_bits_r : signal is "NO";
81 attribute REGISTER_DUPLICATION of acd_sync_r : signal is "NO";
82 attribute REGISTER_DUPLICATION of out_sync_s : signal is "NO";
83 attribute REGISTER_DUPLICATION of out_sync_r : signal is "NO";
86 sync_o <= out_sync_r(max(-sync_adj_g, 0));
91 process (acd_miso_r, acd_sync_r, acd_sync_prev_r, acd_in_loc_r, fifo_bits_r)
93 acd_sync_prev_s <= acd_sync_r;
94 fifo_bits_s <= fifo_bits_r;
95 if (acd_sync_r = '1') and (acd_sync_prev_r = '0') then
97 fifo_bits_s(0) <= acd_miso_r;
99 fifo_bits_s(acd_in_loc_r) <= acd_miso_r;
100 if acd_in_loc_r /= fifo_len_g - 1 then
101 acd_in_loc_s <= acd_in_loc_r + 1;
111 wait until acd_clock_i'event and acd_clock_i = '1';
113 acd_miso_r <= acd_miso_i;
114 acd_sync_r <= acd_sync_i;
115 acd_sync_prev_r <= acd_sync_prev_s;
116 acd_in_loc_r <= acd_in_loc_s;
117 fifo_bits_r <= fifo_bits_s;
121 process (fifo_bits_r, out_loc_r, out_sync_r, acd_sync_r)
123 out_sync_s <= out_sync_r(1 to out_sync_r'length - 1 ) & acd_sync_r;
124 if out_sync_r(max(sync_adj_g, 0)) = '0' then
128 out_miso_s <= fifo_bits_r(out_loc_r);
129 if out_loc_r /= fifo_len_g - 1 then
130 out_loc_s <= out_loc_r + 1;
140 wait until clk_i'event and clk_i = '1';
142 out_loc_r <= out_loc_s;
143 miso_o <= out_miso_s;
144 out_sync_r <= out_sync_s;