hw/bus_irc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_unsigned.all;
   4 use ieee.numeric_std.all;
   5 use work.mbl_pkg.all;
   6 use work.lx_rocon_pkg.all;
   7
   8 -- IRC bus interconnect
   9 entity bus_irc is
  10         port
  11         (
  12                 clk_i        : in std_logic;
  13                 reset_i      : in std_logic;
  14                 -- Data bus
  15                 address_i    : in std_logic_vector(4 downto 0);
  16                 next_ce_i    : in std_logic;
  17                 data_i       : in std_logic_vector(31 downto 0);
  18                 data_o       : out std_logic_vector(31 downto 0);
  19                 --
  20                 bls_i        : in std_logic_vector(3 downto 0);
  21                 -- Signals for IRC
  22                 irc_i        : in IRC_INPUT_Array_Type(7 downto 0)
  23         );
  24 end bus_irc;
  25
  26 architecture Behavioral of bus_irc is
  27
  28         signal irc_o_s              : IRC_OUTPUT_Array_Type(7 downto 0);
  29         signal reset_index_event_s  : std_logic_vector(7 downto 0);
  30         signal reset_index_event2_s : std_logic_vector(7 downto 0);
  31         signal reset_ab_error_s     : std_logic_vector(7 downto 0);
  32         signal state_o_s            : std_logic_vector(3 downto 0);
  33         signal state_o_r            : std_logic_vector(3 downto 0);
  34         --
  35         signal irc_en_s             : std_logic;
  36         signal irc_bls_s            : std_logic_vector(3 downto 0);
  37         signal irc_addr_s           : std_logic_vector(3 downto 0);
  38         signal irc_data_s           : std_logic_vector(31 downto 0);
  39         signal irc_out_s            : std_logic;
  40         signal irc_out_r            : std_logic;
  41         --
  42         signal reset_reg_s          : std_logic;
  43         signal reset_reg_r          : std_logic;
  44         signal reset_reg_wr_s       : std_logic;
  45         --
  46         signal reset_s              : std_logic;
  47         signal ce_s                 : std_logic;
  48
  49 begin
  50
  51 irc0 : irc_reader
  52         port map
  53         (
  54                 clk_i                => clk_i,
  55                 reset_i              => reset_s,
  56                 irc_i                => irc_i(0),
  57                 reset_index_event_i  => reset_index_event_s(0),
  58                 reset_index_event2_i => reset_index_event2_s(0),
  59                 reset_ab_error_i     => reset_ab_error_s(0),
  60                 irc_o                => irc_o_s(0)
  61         );
  62
  63 irc1 : irc_reader
  64         port map
  65         (
  66                 clk_i                => clk_i,
  67                 reset_i              => reset_s,
  68                 irc_i                => irc_i(1),
  69                 reset_index_event_i  => reset_index_event_s(1),
  70                 reset_index_event2_i => reset_index_event2_s(1),
  71                 reset_ab_error_i     => reset_ab_error_s(1),
  72                 irc_o                => irc_o_s(1)
  73         );
  74
  75 irc2 : irc_reader
  76         port map
  77         (
  78                 clk_i                => clk_i,
  79                 reset_i              => reset_s,
  80                 irc_i                => irc_i(2),
  81                 reset_index_event_i  => reset_index_event_s(2),
  82                 reset_index_event2_i => reset_index_event2_s(2),
  83                 reset_ab_error_i     => reset_ab_error_s(2),
  84                 irc_o                => irc_o_s(2)
  85         );
  86
  87 irc3 : irc_reader
  88         port map
  89         (
  90                 clk_i                => clk_i,
  91                 reset_i              => reset_s,
  92                 irc_i                => irc_i(3),
  93                 reset_index_event_i  => reset_index_event_s(3),
  94                 reset_index_event2_i => reset_index_event2_s(3),
  95                 reset_ab_error_i     => reset_ab_error_s(3),
  96                 irc_o                => irc_o_s(3)
  97         );
  98
  99 irc4 : irc_reader
 100         port map
 101         (
 102                 clk_i                => clk_i,
 103                 reset_i              => reset_s,
 104                 irc_i                => irc_i(4),
 105                 reset_index_event_i  => reset_index_event_s(4),
 106                 reset_index_event2_i => reset_index_event2_s(4),
 107                 reset_ab_error_i     => reset_ab_error_s(4),
 108                 irc_o                => irc_o_s(4)
 109         );
 110
 111 irc5 : irc_reader
 112         port map
 113         (
 114                 clk_i                => clk_i,
 115                 reset_i              => reset_s,
 116                 irc_i                => irc_i(5),
 117                 reset_index_event_i  => reset_index_event_s(5),
 118                 reset_index_event2_i => reset_index_event2_s(5),
 119                 reset_ab_error_i     => reset_ab_error_s(5),
 120                 irc_o                => irc_o_s(5)
 121         );
 122
 123 irc6 : irc_reader
 124         port map
 125         (
 126                 clk_i                => clk_i,
 127                 reset_i              => reset_s,
 128                 irc_i                => irc_i(6),
 129                 reset_index_event_i  => reset_index_event_s(6),
 130                 reset_index_event2_i => reset_index_event2_s(6),
 131                 reset_ab_error_i     => reset_ab_error_s(6),
 132                 irc_o                => irc_o_s(6)
 133         );
 134
 135 irc7 : irc_reader
 136         port map
 137         (
 138                 clk_i                => clk_i,
 139                 reset_i              => reset_s,
 140                 irc_i                => irc_i(7),
 141                 reset_index_event_i  => reset_index_event_s(7),
 142                 reset_index_event2_i => reset_index_event2_s(7),
 143                 reset_ab_error_i     => reset_ab_error_s(7),
 144                 irc_o                => irc_o_s(7)
 145         );
 146
 147 irc_proc : irc_proc_main
 148         generic map
 149         (
 150                 num_irc_g            => 8
 151         )
 152         port map
 153         (
 154                 clk_i                => clk_i,
 155                 reset_i              => reset_s,
 156                 -- IRC
 157                 irc_i(0)             => irc_o_s(0).count,
 158                 irc_i(1)             => irc_o_s(1).count,
 159                 irc_i(2)             => irc_o_s(2).count,
 160                 irc_i(3)             => irc_o_s(3).count,
 161                 irc_i(4)             => irc_o_s(4).count,
 162                 irc_i(5)             => irc_o_s(5).count,
 163                 irc_i(6)             => irc_o_s(6).count,
 164                 irc_i(7)             => irc_o_s(7).count,
 165                 irc_index_reset_o    => reset_index_event_s,
 166                 -- BRAM
 167                 mem_clk_i            => clk_i,
 168                 mem_en_i             => irc_en_s,
 169                 mem_we_i             => irc_bls_s,
 170                 mem_addr_i           => irc_addr_s,
 171                 mem_data_i           => data_i,
 172                 mem_data_o           => irc_data_s
 173         );
 174
 175         reset_s <= reset_reg_r or reset_i;
 176
 177 wire_in:
 178         process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
 179         begin
 180
 181                 -- init values
 182                 irc_en_s             <= '0';
 183                 irc_out_s            <= '0';
 184                 irc_bls_s            <= (others => '0');
 185                 irc_addr_s           <= (others => '0');
 186                 reset_ab_error_s     <= (others => '0');
 187                 reset_index_event2_s <= (others => '0');
 188                 state_o_s            <= (others => '0');
 189                 reset_reg_s          <= '0';
 190                 reset_reg_wr_s       <= '0';
 191
 192                 -- Incoming bus request
 193                 if next_ce_i = '1' then
 194                         -- Mapping:
 195                         -- 0 & axis & irc / index - (all read from bram) (R/W)
 196                         -- 1 & axis & 0           - status register (R/W)
 197                         -- 1 & 000  & 1           - reset
 198                         if address_i(4) = '0' then
 199
 200                                 irc_addr_s    <= address_i(3 downto 0);
 201                                 irc_en_s      <= '1';
 202                                 irc_bls_s     <= bls_i;
 203                                 irc_out_s     <= '1';
 204
 205                         -- Maybe these would be better to latch in next_ce_i cycle,
 206                         -- and then just pass them
 207                         elsif address_i(0) = '0' then
 208
 209                                 state_o_s(0) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.mark;
 210                                 state_o_s(1) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.ab_error;
 211                                 state_o_s(2) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index_event;
 212                                 state_o_s(3) <= irc_o_s(to_integer(unsigned(address_i(3 downto 1)))).state.index;
 213
 214                                 if bls_i(0) = '1' then
 215                                         if data_i(1) = '1' then
 216                                                 reset_ab_error_s(to_integer(unsigned(address_i(3 downto 1))))     <= '1';
 217                                         end if;
 218                                         if data_i(2) = '1' then
 219                                                 reset_index_event2_s(to_integer(unsigned(address_i(3 downto 1)))) <= '1';
 220                                         end if;
 221                                 end if;
 222                         elsif address_i = "10001" then
 223
 224                                 if bls_i(0) = '1' then
 225                                         reset_reg_s    <= data_i(0);
 226                                         reset_reg_wr_s <= '1';
 227                                 else
 228                                         -- Ugh, hack :-)
 229                                         state_o_s(0)          <= reset_reg_r;
 230                                         state_o_s(3 downto 1) <= (others => '0');
 231                                 end if;
 232
 233                         end if;
 234
 235                 end if;
 236         end process;
 237
 238 wire_out:
 239         process(ce_s, irc_data_s, irc_out_r, state_o_r)
 240         begin
 241
 242                 data_o <= (others => '0');
 243
 244                 if ce_s = '1' then
 245
 246                         if irc_out_r = '1' then
 247                                 data_o <= irc_data_s;
 248                         else
 249                                 data_o(3 downto 0) <= state_o_r;
 250                         end if;
 251
 252                 end if;
 253         end process;
 254
 255 update:
 256         process
 257         begin
 258                 wait until clk_i'event and clk_i= '1';
 259                 ce_s      <= next_ce_i;
 260                 irc_out_r <= irc_out_s;
 261                 state_o_r <= state_o_s;
 262
 263                 if reset_i = '1' then
 264                         reset_reg_r <= '1';
 265                 elsif reset_reg_wr_s = '1' then
 266                         reset_reg_r <= reset_reg_s;
 267                 end if;
 268
 269         end process;
 270
 271 end Behavioral;
 272