]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/tree - hw/tb/
Testbed changed to work when samples save is controlled from data ready signal.
[fpga/lx-cpu1/lx-dad.git] / hw / tb /
drwxr-xr-x   ..
-rw-r--r-- 30 .gitignore
-rw-r--r-- 1136 Makefile
-rw-r--r-- 5770 lx_dad_top_tb.vhd
-rw-r--r-- 9232 test-lx-dad.gtkw