Testbed changed to work when samples save is controlled from data ready signal.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/hw/tb/lx_dad_top_tb.vhd b/hw/tb/lx_dad_top_tb.vhd
index a033b1f816b6e07ca86ce120748cd1d5ecdf7c49..d46d4a8a3ab5bdc6ee5593ded198653289a0ca96 100644 (file)
--- a/hw/tb/lx_dad_top_tb.vhd
+++ b/hw/tb/lx_dad_top_tb.vhd
@@ -79,7 +79,7 @@ BEGIN
           phi2       => open,
           phi_rst    => open,
           LED_1      => open,
-          sck_o      => open,
+          sck_o      => adc_sck,
           cnv_o      => open,
           phist      => open,
           sck_i      => adc_sck,
@@ -181,11 +181,14 @@ BEGIN
                mcu_write(x"1005", x"00000009"); -- 9
                mcu_write(x"1006", x"00000040"); -- 599
                mcu_write(x"1007", x"00000050"); -- 609
-               mcu_write(x"1008", x"00000050"); -- 5023999
+               mcu_write(x"1008", x"00002000"); -- 5023999
                mcu_write(x"1009", x"00000008"); -- 499
 
-               mcu_write(x"1000", x"00000009");
-               -- mcu_write(x"1000", x"00000011");
+               mcu_write(x"100C", x"00000010");
+
+               mcu_write(x"1000", x"00000009"); -- standard
+               -- mcu_write(x"1000", x"00000011"); -- leakage
+               -- mcu_write(x"1000", x"00000021"); -- multi
 
                -- Simulate external master accesses example bus memory
                xmem_loop: loop