--constant CLK_MASTER_FREQ: unsigned := 50000000;
signal cntra : unsigned(31 downto 0) := (others => '0');
- signal pixel : integer range 0 to 2047;
+ signal pixel : integer range 0 to 8191;
+ signal spd_cntr : integer range 0 to 3;
signal cntrb : unsigned(31 downto 0) := (others => '0');
signal finished_i : std_logic:='0';
signal stability_m : std_logic;
- type states_i is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle);
+ type states_i is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle, ispd, ispdb);
signal state_i : states_i;
type meas_states is (normal, multi_per_pixel, leakage);
bank <= '0';
ce_o <= '0';
bls_o <= "0000";
+ spd_cntr <= 3;
elsif rising_edge(clk_i) then
ce_o <= '0';
bls_o <= "0000";
ph_rst <= '1';
end if;
end case;
- when normal =>
+ when normal | multi_per_pixel =>
case state_i is
when i0 =>
- if pixel > 0 and pixel < 1025 then
- mem_o <= "00000000000000"&adc_data_i;
- --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
- addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
- bls_o <= "1111";
- ce_o <= '1';
+ if state_meas = normal then
+ if pixel > 0 and pixel < 1025 then
+ mem_o <= "00000000000000"&adc_data_i;
+ --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
+ addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
+ bls_o <= "1111";
+ ce_o <= '1';
+ end if;
end if;
state_i <= i1;
cntra<=t1;
cntra<=t4;
when i4 =>
phi_1 <= '0';
- if pixel = 1026 then
- bank <= not bank;
- state_i <= iddle;
- cntra <= (others => '0');
- if run_single_i = '1' and run_single_last = '0' then
- run_single_last <= '1';
- end if;
- if run_single_i = '1' and run_single_last = '1' then
- run_single_i <= '0';
- run_single_last <= '0';
- finished <= '1';
+ if state_meas = normal then
+ if pixel = 1026 then
+ bank <= not bank;
+ state_i <= iddle;
+ cntra <= (others => '0');
+ if run_single_i = '1' and run_single_last = '0' then
+ run_single_last <= '1';
+ end if;
+ if run_single_i = '1' and run_single_last = '1' then
+ run_single_i <= '0';
+ run_single_last <= '0';
+ finished <= '1';
+ end if;
+ else
+ state_i <= i5;
+ cntra<=t5;
end if;
else
- state_i <= i5;
- cntra<=t5;
+ if pixel > 4095 then
+ state_i <= iddle;
+ bank <= '1';
+ cntra <= (others => '0');
+ if run_readout = '1' and run_single_last = '0' then
+ run_single_last <= '1';
+ end if;
+ if run_readout = '1' and run_single_last = '1' then
+ run_single_i <= '0';
+ run_single_last <= '0';
+ finished <= '1';
+ end if;
+ else
+ state_i <= i5;
+ cntra<=t5;
+ end if;
end if;
when i5 =>
phi_2 <= '1';
- state_i <= i6;
- cntra <= t6;
+ if state_meas = normal then
+ state_i <= i6;
+ cntra <= t6;
+ else
+ state_i <= ispd;
+ end if;
+ when ispd =>
+ conv_start <= '1';
+ cntra <= t9 - to_unsigned(75,cntra'length);
+ state_i <= ispdb;
+ when ispdb =>
+ if pixel < 2049 then
+ conv_start <= '0';
+ cntra <= to_unsigned(74,cntra'length);
+ mem_o <= "00000000000000"&adc_data_i;
+ addr_o <= std_logic_vector(to_unsigned((pixel-1),11));
+ bls_o <= "1111";
+ ce_o <= '1';
+ end if;
+ pixel <= pixel +1;
+ if spd_cntr = 0 then
+ spd_cntr <= 3;
+ state_i <= i0;
+ else
+ spd_cntr <= spd_cntr - 1;
+ state_i <= ispd;
+ end if;
when i6 =>
state_i <= i0;
-- start the readout from adc