);
end component;
+ -- Dualported memory for example componenet
+ component lx_example_mem
+ port
+ (
+ -- Memory wiring for internal state automata use
+ clk_i : in std_logic;
+ ce_i : in std_logic;
+ adr_i : in std_logic_vector(9 downto 0);
+ bls_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+ -- Memory wiring for Master CPU
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(9 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
-- Measurement interconnect
component bus_measurement
port