hw/lx_dad_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 -- Disable next libraries for simulation in GHDL
   6 --library unisim;
   7 --use unisim.vcomponents.all;
   8
   9 use work.lx_dad_pkg.all;
  10
  11 -- lx_dad_top - wires the modules with the outside world
  12
  13 -- ======================================================
  14 --  MASTER CPU EXTERNAL MEMORY BUS
  15 -- ======================================================
  16 --
  17 -- Master cpu memory bus has the following wires:
  18 --
  19 -- - address[15..0]          The address, used to mark chip enable
  20 -- - data_in[31..0]          The data coming to bus
  21 -- - data_out[31..0]         The data coming from bus, multiplexed
  22 -- - bls[3..0]               Write enable for respective bytes
  23
  24 entity lx_dad_top is
  25         port
  26         (
  27                 -- External
  28                 --clk_cpu     : in std_logic;
  29                 clk_50m     : in std_logic;
  30                 --
  31                 cs0_xc      : in std_logic;
  32                 --
  33                 rd          : in std_logic;
  34                 bls         : in std_logic_vector(3 downto 0);
  35                 address     : in std_logic_vector(15 downto 0);
  36                 data        : inout std_logic_vector(31 downto 0);
  37                 --
  38                 init        : in std_logic;
  39                 -- signal connected to external JK FF
  40                 event_jk_j  : out std_logic
  41         );
  42 end lx_dad_top;
  43
  44 architecture Behavioral of lx_dad_top is
  45
  46         -- Reset signal
  47         signal reset_s                  : std_logic;
  48         signal init_s                   : std_logic;
  49         -- Peripherals on the memory buses
  50         -- Example memory
  51         signal example_out_s            : std_logic_vector(31 downto 0);
  52         signal example_ce_s             : std_logic;
  53         -- Measurement (Master)
  54         signal meas_out_s               : std_logic_vector(31 downto 0);
  55         signal meas_ce_s                : std_logic;
  56         -- Signals for external bus transmission
  57         signal data_i_s                 : std_logic_vector(31 downto 0);
  58         signal data_o_s                 : std_logic_vector(31 downto 0);
  59         -- Signals for internal transaction
  60         signal last_address_s           : std_logic_vector(15 downto 0);
  61         signal next_last_address_s      : std_logic_vector(15 downto 0);
  62         signal next_address_hold_s      : std_logic;
  63         signal address_hold_s           : std_logic;
  64         signal last_rd_s                : std_logic;
  65         signal next_last_rd_s           : std_logic;
  66         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
  67         signal next_last_bls_s          : std_logic_vector(3 downto 0);
  68
  69         -- Reading logic for Master CPU:
  70         -- Broadcast rd only till ta (transaction acknowledge)
  71         -- is received, then latch the data till the state of
  72         -- rd or address changes
  73         --
  74         -- Data latching is synchronous - it's purpose is to
  75         -- provide stable data for CPU on the bus
  76         signal cs0_xc_f_s          : std_logic;
  77         signal rd_f_s              : std_logic; -- Filtered RD
  78         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
  79         -- signal next_i_rd_s         : std_logic;
  80         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
  81         signal next_last_i_rd_s    : std_logic;
  82         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
  83         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
  84         --
  85         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
  86         --
  87         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
  88         --
  89         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
  90         signal next_data_read_s    : std_logic_vector(31 downto 0);
  91
  92         -- Writing logic:
  93         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
  94         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
  95         signal next_i_bls_s        : std_logic_vector(3 downto 0);
  96         --
  97         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
  98         signal next_data_write_s   : std_logic_vector(31 downto 0);
  99
 100         -- signal s0   : std_logic;
 101         -- signal s1   : std_logic;
 102         -- signal s2   : std_logic;
 103
 104         -- XST attributes
 105         attribute REGISTER_DUPLICATION : string;
 106         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 107         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 108         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 109         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 110         attribute REGISTER_DUPLICATION of address : signal is "NO";
 111         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 112         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 113         attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
 114
 115 begin
 116
 117 -- Example connection
 118 memory_bus_example: bus_example
 119         port map
 120         (
 121                 clk_i          => clk_50m,
 122                 reset_i        => reset_s,
 123                 ce_i           => example_ce_s,
 124                 bls_i          => i_bls_s,
 125                 address_i      => address_f_s(11 downto 0),
 126                 data_i         => data_i_s,
 127                 data_o         => example_out_s
 128                 --
 129                 --
 130                 -- additional externally connected signals goes there
 131         );
 132
 133 -- Measurement
 134 memory_bus_measurement: bus_measurement
 135         port map
 136         (
 137                 clk_i     => clk_50m,
 138                 reset_i   => reset_s,
 139                 ce_i      => meas_ce_s,
 140                 address_i => address_f_s(1 downto 0),
 141                 bls_i     => i_bls_s,
 142                 data_i    => data_i_s,
 143                 data_o    => meas_out_s
 144         );
 145
 146 -- Reset
 147 dff_reset: dff2
 148         port map
 149         (
 150                 clk_i   => clk_50m,
 151                 d_i     => init_s,
 152                 q_o     => reset_s
 153         );
 154
 155         -- Reset
 156         init_s          <= not init;
 157
 158         -- Signalling
 159         data_i_s        <= data_write_s;
 160
 161
 162         event_jk_j <= '0';
 163
 164 -- Bus update
 165 memory_bus_logic:
 166         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
 167                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 168                 data_o_s, data_read_s, last_address_s, address_f_s)
 169         begin
 170                 -- Defaults
 171                 next_i_rd_cycle2_s <= '0';
 172                 next_address_hold_s <= '0';
 173
 174                 -- Check if we have chip select
 175                 if cs0_xc_f_s = '1' then
 176
 177                         -- Reading
 178                         if rd_f_s = '1' then
 179                                 -- Internal read
 180                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 181                                         i_rd_s <= '1';
 182                                         next_i_rd_cycle2_s <= '1';
 183                                         next_last_i_rd_s  <= '1';
 184                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 185                                         i_rd_s <= '1';            -- peripherals demands 2 cycles to read
 186                                         next_last_i_rd_s  <= '1';
 187                                 else
 188                                         i_rd_s            <= '0';
 189                                         next_last_i_rd_s  <= '0';
 190                                 end if;
 191
 192                                 if last_i_rd_s = '1' then
 193                                         -- Latch data we just read - they are valid in this cycle
 194                                         next_data_read_s <= data_o_s;
 195                                 else
 196                                         next_data_read_s <= data_read_s;
 197                                 end if;
 198                         else
 199                         --      -- Not reading, anything goes
 200                         --      data_read_s       <= (others => 'X');
 201                                 next_data_read_s  <= data_read_s;
 202                                 i_rd_s            <= '0';
 203                                 next_last_i_rd_s  <= '0';
 204                         end if;
 205
 206                         next_last_rd_s            <= rd_f_s;
 207
 208                         -- Data for write are captured only when BLS signals are stable
 209                         if bls_f_s /= "0000" then
 210                                 next_data_write_s <= data_f_s;
 211                                 next_address_hold_s <= '1';
 212                         else
 213                                 next_data_write_s <= data_write_s;
 214                         end if;
 215
 216                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 217                                 next_last_address_s <= address_f_s;
 218                         else
 219                                 next_last_address_s <= last_address_s;
 220                         end if;
 221                 else
 222                         next_last_rd_s <= '0';
 223                         i_rd_s <= '0';
 224                         next_last_i_rd_s <= '0';
 225
 226                         next_i_bls_s <= "0000";
 227                         next_data_write_s <= data_write_s;
 228                         next_data_read_s  <= data_read_s;
 229                         next_last_address_s <= last_address_s;
 230                 end if;
 231
 232                 -- Data for write are captured at/before BLS signals are negated
 233                 -- and actual write cycle takes place exacly after BLS negation
 234                 if ((last_bls_s and not bls_f_s) /= "0000") or
 235                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 236                         next_i_bls_s <= last_bls_s;
 237                         next_last_bls_s   <= "0000";
 238                         next_address_hold_s <= '1';
 239                 else
 240                         next_i_bls_s <= "0000";
 241                         if cs0_xc_f_s = '1' then
 242                                 next_last_bls_s <= bls_f_s;
 243                         else
 244                                 next_last_bls_s <= "0000" ;
 245                         end if;
 246                 end if;
 247
 248         end process;
 249
 250 -- Bus update
 251 memory_bus_update:
 252         process
 253         begin
 254
 255                 wait until clk_50m = '1' and clk_50m'event;
 256
 257                 address_hold_s <= next_address_hold_s;
 258
 259                 -- Synchronized external signals with main clock domain
 260                 cs0_xc_f_s     <= not cs0_xc;
 261                 bls_f_s        <= not bls;
 262                 rd_f_s         <= not rd;
 263                 data_f_s       <= data;
 264                 if address_hold_s = '0' then
 265                         address_f_s <= address;
 266                 else
 267                         address_f_s <= next_last_address_s;
 268                 end if;
 269
 270                 -- Synchronoust state andvance to next period
 271                 last_bls_s     <= next_last_bls_s;
 272                 last_rd_s      <= next_last_rd_s;
 273                 i_bls_s        <= next_i_bls_s;
 274                 -- i_rd_s         <= next_i_rd_s;
 275                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 276                 last_i_rd_s    <= next_last_i_rd_s;
 277                 data_write_s   <= next_data_write_s;
 278                 last_address_s <= next_last_address_s;
 279                 data_read_s    <= next_data_read_s;
 280
 281         end process;
 282
 283 -- Do the actual wiring here
 284 memory_bus_wiring:
 285         process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s)
 286         begin
 287
 288                 -- Inactive by default
 289                 example_ce_s           <= '0';
 290                 meas_ce_s              <= '0';
 291                 data_o_s               <= (others => '0');
 292
 293                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 294
 295                         -- Memory Map (16-bit address @ 32-bit each)
 296
 297                         -- Each address is seen as 32-bit entry now
 298                         -- 0x0000 - 0x0FFF: Example memory
 299                         -- 0x1FFC - 0x1FFF: Measurement
 300                         -- 0x2000 - 0x8FFF: Free space
 301
 302                         if address_f_s < "0001000000000000" then                  -- Tumbl
 303                                 example_ce_s           <= '1';
 304                                 data_o_s               <= example_out_s;
 305                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 306                                 meas_ce_s              <= '1';
 307                                 data_o_s               <= meas_out_s;
 308                         end if;
 309
 310                 end if;
 311
 312         end process;
 313
 314 -- If RD and BLS is not high, we must keep DATA at high impedance
 315 -- or the FPGA collides with SDRAM (damaging each other)
 316 memory_bus_out:
 317         process(cs0_xc, rd, data_read_s)
 318         begin
 319
 320                 -- CS0 / RD / BLS are active LOW
 321                 if cs0_xc = '0' and rd = '0' then
 322                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 323                         -- Maybe check this later.
 324                         -- if last_i_rd_s = '1' then
 325                         --   data <= data_o_s;
 326                         -- else
 327                         data <= data_read_s;
 328                         -- end if;
 329                 else
 330                         -- IMPORTANT!!!
 331                         data <= (others => 'Z');
 332                 end if;
 333
 334         end process;
 335
 336 end Behavioral;
 337