hw/bus_example.vhd

   1 library ieee;
   2
   3 use ieee.std_logic_1164.all;
   4 use ieee.numeric_std.all;
   5 use work.lx_dad_pkg.all;
   6
   7 -- Connects example memory
   8
   9 entity bus_example is
  10         port
  11         (
  12                 -- Clock
  13                 clk_i        : in std_logic;
  14                 -- Chip enable
  15                 ce_i         : in std_logic;
  16                 -- Global Reset
  17                 reset_i      : in std_logic;
  18                 -- Master CPU peripheral bus
  19                 bls_i        : in std_logic_vector(3 downto 0);
  20                 address_i    : in std_logic_vector(11 downto 0);
  21                 data_i       : in std_logic_vector(31 downto 0);
  22                 data_o       : out std_logic_vector(31 downto 0)
  23
  24                 -- Non bus signals
  25                 --
  26                 -- Add there external component signals
  27   );
  28 end bus_example;
  29
  30 architecture Behavioral of bus_example is
  31
  32         signal example_mem_ce_s   : std_logic;
  33         signal example_mem_ce_r   : std_logic;
  34         signal example_mem_bls_s  : std_logic_vector(3 downto 0);
  35         signal example_mem_dout_s : std_logic_vector(31 downto 0);
  36 begin
  37
  38 example_mem_instance: lx_example_mem
  39         port map
  40         (
  41                 -- Memory wiring for internal state automata use
  42                 clk_i  => clk_i,
  43                 ce_i   => '0',
  44                 adr_i  => (others => '0'),
  45                 bls_i  => (others => '0'),
  46                 dat_i  => (others => '0'),
  47                 dat_o  => open,
  48                 -- Memory wiring for Master CPU
  49                 clk_m  => clk_i,
  50                 en_m   => example_mem_ce_s,
  51                 we_m   => example_mem_bls_s,
  52                 addr_m => address_i(9 downto 0),
  53                 din_m  => data_i,
  54                 dout_m => example_mem_dout_s
  55         );
  56
  57 decoder_logic: process(ce_i, address_i, bls_i)
  58         begin
  59                 example_mem_ce_s <= '0';
  60                 example_mem_bls_s <= (others => '0');
  61
  62                 if ce_i = '1' and address_i(11 downto 10) = "00" then
  63                         example_mem_ce_s <= '1';
  64                         example_mem_bls_s <= bls_i;
  65                 end if;
  66         end process;
  67
  68 output_multiplexer: process(example_mem_ce_r, example_mem_dout_s)
  69         begin
  70                 data_o <= (others => '0');
  71
  72                 if example_mem_ce_r = '1' then
  73                         data_o <= example_mem_dout_s;
  74                 end if;
  75         end process;
  76
  77 sync_update:
  78         process
  79         begin
  80                 wait until clk_i = '1' and clk_i'event;
  81
  82                 example_mem_ce_r <= example_mem_ce_s;
  83         end process;
  84
  85
  86 end Behavioral;