hw/clockgen.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 use work.lx_dad_pkg.all;
   6
   7 entity clockgen is
   8         port
   9         (
  10                 -- inputs
  11                 clk_i   : in std_logic;
  12                 reset_i : in std_logic;
  13                 sck_i   : in std_logic;
  14                 SDI             : in std_logic;
  15                 -- outputs
  16                 phi_1   : out std_logic;
  17                 phi_2   : out std_logic;
  18                 phi_st  : out std_logic;
  19                 ph_rst  : out std_logic;
  20         --      LED             : out std_logic;
  21                 sck_o   : out std_logic;
  22                 cnv_o   : out std_logic;
  23
  24
  25                 mem_o           : out std_logic_vector(31 downto 0);
  26
  27                 --memory related outputs
  28                 addr_o  : out std_logic_vector(10 downto 0);
  29                 bls_o   : out std_logic_vector(3 downto 0);
  30                 ce_o    : out std_logic;
  31
  32                 -- mem related inputs
  33
  34                 addr_i  : in std_logic_vector(3 downto 0);
  35                 data_i  : in std_logic_vector(31 downto 0);
  36                 ce_i    : in std_logic;
  37                 bls_i   : in std_logic_vector(3 downto 0);
  38                 data_o  : out std_logic_vector(31 downto 0)
  39
  40         );
  41 end clockgen;
  42
  43 architecture rtl of clockgen is
  44
  45         --constant CLK_MASTER_FREQ: unsigned := 50000000;
  46
  47         signal cntra    : unsigned(31 downto 0) := (others => '0');
  48         signal pixel            : integer range 0 to 8191;
  49         signal spd_cntr : integer range 0 to 3;
  50
  51         signal cntrb    : unsigned(31 downto 0) := (others => '0');
  52
  53         signal bank             : std_logic;
  54
  55         signal run_readout      : std_logic;
  56         signal conv_start       : std_logic;
  57         signal adc_data_i       : std_logic_vector(17 downto 0);
  58         signal adc_drdy_i       : std_logic;
  59         signal run_single       : std_logic;
  60         signal run_single_last : std_logic;
  61         signal run_single_i     : std_logic;
  62         signal finished         : std_logic:='0';
  63         signal finished_i       : std_logic:='0';
  64         signal stability_m      : std_logic;
  65
  66         type    states_i        is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle, ispd, ispdb);
  67         signal  state_i         : states_i;
  68
  69         type    meas_states is (normal, multi_per_pixel, leakage);
  70         signal state_meas       : meas_states;
  71
  72         signal  t1              : unsigned(31 downto 0);
  73         signal  t2              : unsigned(31 downto 0);
  74         signal  t3              : unsigned(31 downto 0);
  75         signal  t4              : unsigned(31 downto 0);
  76         signal  t5              : unsigned(31 downto 0);
  77         signal  t6              : unsigned(31 downto 0);
  78         signal  t7              : unsigned(31 downto 0);
  79         signal          t8              : unsigned(31 downto 0);
  80         signal          t9              : unsigned(31 downto 0) ;
  81
  82
  83         signal alive_cntr : integer range 0 to 24999999:=0;
  84         signal LED_latch  : std_logic:='1';
  85
  86 begin
  87
  88         snsor_adc_interface:lx_adc_if
  89         generic map
  90         (
  91                 adc_res         => 18,
  92                 conv_cycles     => 85
  93         )
  94         port map
  95         (
  96                 clk_i           => clk_i,
  97                 rst_i           => reset_i,
  98                 conv_start      => conv_start,
  99                 sck_o           => sck_o,
 100                 cnv_o           => cnv_o,
 101                 data_o          => adc_data_i,
 102                 drdy_o          => adc_drdy_i,
 103                 sck_i           => sck_i,
 104                 SDI                     => sdi
 105         );
 106
 107         -- adc_read : process(reset_i,clk_i)
 108         -- begin
 109                 -- if reset_i = '1' then
 110                 -- elsif rising_edge(clk_i) then
 111                         -- if adc_drdy_i = '1' and pixel < 1025 then
 112                                 --mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
 113                                 -- mem_o <= std_logic_vector(to_unsigned((pixel),32));
 114                                 -- addr_o <= bank & std_logic_vector(to_unsigned((pixel),10));
 115                                 -- bls_o <= "1111";
 116                                 -- ce_o <= '1';
 117                         -- end if;
 118                 -- end if;
 119         -- end process;
 120
 121         interf : process(reset_i,clk_i)
 122         begin
 123                 if reset_i = '1' then                   -- set default timing
 124                         t1 <= "00000000000000000000000000000110";       --6
 125                         t2 <= "00000000000000000000001111101000";       --9
 126                         t3 <= "00000000000000000000010001111101";       --1149
 127                         t4 <= "00000000000000000000001111101000";       --14
 128                         t5 <= "00000000000000000000000000000110";       --6
 129                         t6 <= "00000000000000000000001001010111";       --599
 130                         t7 <= "00000000000000000000001010010010";       --658
 131                         t8 <= "00000000000000000001001100010000";       --4880
 132                         t9 <= "00000000000000000000000111110011";
 133                         data_o <= (others => '0');
 134                         run_single <= '0';
 135                         run_readout <= '0';
 136                 elsif rising_edge(clk_i) then
 137                         run_single <= '0';
 138                         if finished = '1' then
 139                                 run_readout <= '0';
 140                                 finished_i <= '1';
 141                         end if;
 142                         if ce_i = '1' and bls_i /= "0000" then
 143                                 if addr_i = "0000" then
 144                                         run_readout <= data_i(0);       --start/stop the readout
 145                                         if data_i(1) = '1'  then
 146                                                 run_readout <= '1';
 147                                                 run_single <= '1';
 148                                         end if;
 149                                         if data_i(3) = '1' then
 150                                                 state_meas <= normal;
 151                                         elsif data_i(4) = '1' then
 152                                                 state_meas <= leakage;
 153                                         end if;
 154                                 elsif addr_i = "0001" then
 155                                         t1 <= unsigned(data_i);
 156                                 elsif addr_i = "0010" then
 157                                         t2 <= unsigned(data_i);
 158                                 elsif addr_i = "0011" then
 159                                         t3 <= unsigned(data_i);
 160                                 elsif addr_i = "0100" then
 161                                         t4 <= unsigned(data_i);
 162                                 elsif addr_i = "0101" then
 163                                         t5 <= unsigned(data_i);
 164                                 elsif addr_i = "0110" then
 165                                         t6 <= unsigned(data_i);
 166                                 elsif addr_i <= "0111" then
 167                                         t7 <= unsigned(data_i);
 168                                 elsif addr_i <= "1000" then
 169                                         t8 <= unsigned(data_i);
 170                                 elsif addr_i <= "1001" then
 171                                         t9 <= unsigned(data_i);
 172                                 end if;
 173                         end if;
 174                         if ce_i = '1' then
 175                                 if addr_i = "0000" then
 176                                         data_o <= (others => '0');
 177                                         data_o(2) <= not bank;
 178                                         data_o(6) <= finished_i;
 179                                         data_o(0) <= run_readout;
 180                                         if state_meas = leakage then
 181                                                 data_o(4) <= '1';
 182                                         elsif state_meas = normal then
 183                                                 data_o(3) <= '1';
 184                                         elsif state_meas = multi_per_pixel then
 185                                                 data_o(5) <= '1';
 186                                         end if;
 187                                         finished_i <= '0';
 188                                 elsif addr_i = "0001" then
 189                                         data_o <= std_logic_vector(t1);
 190                                 elsif addr_i = "0010" then
 191                                         data_o <= std_logic_vector(t2);
 192                                 elsif addr_i = "0011" then
 193                                         data_o <= std_logic_vector(t3);
 194                                 elsif addr_i = "0100" then
 195                                         data_o <= std_logic_vector(t4);
 196                                 elsif addr_i = "0101" then
 197                                         data_o <= std_logic_vector(t5);
 198                                 elsif addr_i = "0110" then
 199                                         data_o <= std_logic_vector(t6);
 200                                 elsif addr_i = "0111" then
 201                                         data_o <= std_logic_vector(t7);
 202                                 elsif addr_i = "1000" then
 203                                         data_o <= std_logic_vector(t8);
 204                                 elsif addr_i = "1001" then
 205                                         data_o <= std_logic_vector(t9);
 206                                 end if;
 207                         end if;
 208                 end if;
 209         end process;
 210
 211
 212         proc : process(clk_i, reset_i)
 213         begin
 214                 if reset_i='1' then
 215                         state_i <= i0;
 216                         cntra <= (others => '0');
 217                         pixel <= 0;
 218                         phi_st <= '0';
 219                         bank <= '0';
 220                         ce_o <= '0';
 221                         bls_o <= "0000";
 222                         spd_cntr <= 3;
 223                 elsif rising_edge(clk_i) then
 224                         ce_o <= '0';
 225                         bls_o <= "0000";
 226                         conv_start <= '0';
 227                         finished <= '0';
 228                         if run_single = '1' then
 229                                 run_single_i <= '1';
 230                         end if;
 231                         if run_readout = '1' then
 232                                 cntrb <= cntrb + 1;
 233                         else
 234                                 cntrb <= (others => '0');
 235                         end if;
 236                 --      if start_readout = '1' then
 237                 --              pixel <= 0;
 238                 --      end if;
 239                         if cntra = 0 then
 240                                 case state_meas is
 241                                 when leakage =>
 242                                         case state_i is
 243                                         when i0 =>
 244                                                 if pixel > 0 then
 245                                                         mem_o <= "00000000000000"&adc_data_i;
 246                                                         --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
 247                                                         addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
 248                                                         bls_o <= "1111";
 249                                                         ce_o <= '1';
 250                                                 end if;
 251                                                 if pixel > 1023 then
 252                                                         bank <= not bank;
 253                                                         state_i <= iddle;
 254                                                         if run_single_i = '1' and run_single_last = '0' then
 255                                                                 run_single_last <= '1';
 256                                                         end if;
 257                                                         if run_single_i = '1' and run_single_last = '1' then
 258                                                                 run_single_i <= '0';
 259                                                                 run_single_last <= '0';
 260                                                                 finished <= '1';
 261                                                         end if;
 262                                                 end if;
 263                                                 pixel <= pixel +1;
 264                                                 conv_start <= '1';
 265                                                 cntra <= t9;
 266                                         when others =>
 267                                                 pixel <= 0;
 268                                                 cntra <= (others => '0');
 269                                                 ph_rst <= '0';
 270                                                 if  cntrb > t8 then
 271                                                         state_i <= i0;
 272                                                         cntra <= t9;
 273                                                         cntrb <= (others => '0');
 274                                                         ph_rst <= '1';
 275                                                 end if;
 276                                         end case;
 277                                 when normal | multi_per_pixel =>
 278                                         case state_i is
 279                                         when i0 =>
 280                                                 if state_meas = normal then
 281                                                         if pixel > 0 and pixel < 1025 then
 282                                                                 mem_o <= "00000000000000"&adc_data_i;
 283                                                                 --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
 284                                                                 addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
 285                                                                 bls_o <= "1111";
 286                                                                 ce_o <= '1';
 287                                                         end if;
 288                                                 end if;
 289                                                 state_i <= i1;
 290                                                 cntra<=t1;
 291                                                 phi_2 <= '0';
 292                                         when i1 =>
 293                                                 state_i <= i2;
 294                                                 phi_1 <= '1';
 295                                                 cntra<=t2;
 296                                         when i2 =>
 297                                                 state_i <= i3;
 298                                                 ph_rst <= '0';
 299                                                 cntra<=t3;
 300                                         when i3 =>
 301                                                 ph_rst <= '1';
 302                                                 phi_st <= '0';
 303                                                 state_i <= i4;
 304                                                 cntra<=t4;
 305                                         when i4 =>
 306                                                 phi_1 <= '0';
 307                                                 if state_meas = normal then
 308                                                         if pixel = 1026 then
 309                                                                 bank <= not bank;
 310                                                                 state_i <= iddle;
 311                                                                 cntra <= (others => '0');
 312                                                                 if run_single_i = '1' and run_single_last = '0' then
 313                                                                         run_single_last <= '1';
 314                                                                 end if;
 315                                                                 if run_single_i = '1' and run_single_last = '1' then
 316                                                                         run_single_i <= '0';
 317                                                                         run_single_last <= '0';
 318                                                                         finished <= '1';
 319                                                                 end if;
 320                                                         else
 321                                                                 state_i <= i5;
 322                                                                 cntra<=t5;
 323                                                         end if;
 324                                                 else
 325                                                         if pixel > 4095 then
 326                                                                 state_i <= iddle;
 327                                                                 bank <= '1';
 328                                                                 cntra <= (others => '0');
 329                                                                 if run_readout = '1' and run_single_last = '0' then
 330                                                                         run_single_last <= '1';
 331                                                                 end if;
 332                                                                 if run_readout = '1' and run_single_last = '1' then
 333                                                                         run_single_i <= '0';
 334                                                                         run_single_last <= '0';
 335                                                                         finished <= '1';
 336                                                                 end if;
 337                                                         else
 338                                                                 state_i <= i5;
 339                                                                 cntra<=t5;
 340                                                         end if;
 341                                                 end if;
 342                                         when i5 =>
 343                                                 phi_2 <= '1';
 344                                                 if state_meas = normal then
 345                                                         state_i <= i6;
 346                                                         cntra <= t6;
 347                                                 else
 348                                                         state_i <= ispd;
 349                                                 end if;
 350                                         when ispd =>
 351                                                 conv_start <= '1';
 352                                                 cntra <= t9 - to_unsigned(75,cntra'length);
 353                                                 state_i <= ispdb;
 354                                         when ispdb =>
 355                                                 if pixel < 2049 then
 356                                                         conv_start <= '0';
 357                                                         cntra <= to_unsigned(74,cntra'length);
 358                                                         mem_o <= "00000000000000"&adc_data_i;
 359                                                         addr_o <= std_logic_vector(to_unsigned((pixel-1),11));
 360                                                         bls_o <= "1111";
 361                                                         ce_o <= '1';
 362                                                 end if;
 363                                                 pixel <= pixel +1;
 364                                                 if spd_cntr = 0 then
 365                                                         spd_cntr <= 3;
 366                                                         state_i <= i0;
 367                                                 else
 368                                                         spd_cntr <= spd_cntr - 1;
 369                                                         state_i <= ispd;
 370                                                 end if;
 371                                         when i6 =>
 372                                                 state_i <= i0;
 373                                                 -- start the readout from adc
 374                                                 cntra <= t7;
 375                                                 if run_readout = '1' then
 376                                                         if pixel > 0 then
 377                                                                 conv_start <= '1';
 378                                                         end if;
 379                                                         if pixel = 0 then
 380                                                                 phi_st <= '1';
 381                                                         end if;
 382                                                 end if;
 383                                                 pixel <= pixel + 1;
 384                                         when others =>
 385                                                 if cntrb > t8 then
 386                                                         cntrb <= (others => '0');
 387                                                         state_i <= i1;
 388                                                 end if;
 389                                                 pixel <= 0;
 390                                                 phi_1 <= '0';
 391                                                 phi_2 <= '0';
 392                                                 ph_rst <= '0';
 393                                                 cntra <= (others => '0');
 394                                         end case;
 395                                 when others =>
 396                                 end case;
 397                         else
 398                                 cntra <= cntra - 1;
 399                         end if;
 400                 end if;
 401         end process;
 402
 403         alive : process(clk_i,reset_i)
 404         begin
 405                 if reset_i = '1' then
 406                         alive_cntr <= 0;
 407                         --LED <= '1';
 408                         LED_latch<= '1';
 409                 elsif rising_edge(clk_i) then
 410                         alive_cntr<=alive_cntr+1;
 411                         if alive_cntr = 24999999 then
 412                                 LED_latch <= not LED_latch;
 413                         --      LED <= LED_latch;
 414                                 alive_cntr<=0;
 415                         end if;
 416                 end if;
 417         end process;
 418 end architecture;