3 use ieee.std_logic_1164.all;
4 use ieee.numeric_std.all;
5 use work.lx_dad_pkg.all;
7 -- Connects example memory
17 reset_i : in std_logic;
18 -- Master CPU peripheral bus
19 bls_i : in std_logic_vector(3 downto 0);
20 address_i : in std_logic_vector(11 downto 0);
21 data_i : in std_logic_vector(31 downto 0);
22 data_o : out std_logic_vector(31 downto 0)
26 -- Add there external component signals
30 architecture Behavioral of bus_example is
32 signal example_mem_ce_s : std_logic;
33 signal example_mem_ce_r : std_logic;
34 signal example_mem_bls_s : std_logic_vector(3 downto 0);
35 signal example_mem_dout_s : std_logic_vector(31 downto 0);
38 example_mem_instance: lx_example_mem
41 -- Memory wiring for internal state automata use
44 adr_i => (others => '0'),
45 bls_i => (others => '0'),
46 dat_i => (others => '0'),
48 -- Memory wiring for Master CPU
50 en_m => example_mem_ce_s,
51 we_m => example_mem_bls_s,
52 addr_m => address_i(9 downto 0),
54 dout_m => example_mem_dout_s
57 decoder_logic: process(ce_i, address_i, bls_i)
59 example_mem_ce_s <= '0';
60 example_mem_bls_s <= (others => '0');
62 if ce_i = '1' and address_i(11 downto 10) = "00" then
63 example_mem_ce_s <= '1';
64 example_mem_bls_s <= bls_i;
68 output_multiplexer: process(example_mem_ce_r, example_mem_dout_s)
70 data_o <= (others => '0');
72 if example_mem_ce_r = '1' then
73 data_o <= example_mem_dout_s;
80 wait until clk_i = '1' and clk_i'event;
82 example_mem_ce_r <= example_mem_ce_s;