+2012-08-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (LA25_LUI_MICROMIPS_1, LA25_LUI_MICROMIPS_2):
+ Remove macros, folding them into...
+ (LA25_LUI_MICROMIPS): ... this new macro.
+ (LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise into...
+ (LA25_J_MICROMIPS): ... this new macro.
+ (LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise
+ into...
+ (LA25_ADDIU_MICROMIPS): ... this new macro.
+ (bfd_put_micromips_32, bfd_get_micromips_32): New functions.
+ (mips_elf_create_la25_stub): Use them.
+ (check_br32_dslot, check_br32, check_relocated_bzc): Likewise.
+ (_bfd_mips_elf_relax_section): Likewise.
+
+ * elf32-ppc.c (ppc_elf_relocate_section): Assert that dynindx is
+ not minus one.
+ * elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
+
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elflink.c (_bfd_elf_merge_symbol): Also override the version
+ a dynamic symbol defaulted to if preempted with a hidden or
+ internal definition.
+
+ * elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Look up
+ the options section in the output rather than input BFD to
+ decide if to add a DT_MIPS_OPTIONS tag.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config.bfd: Wrap mips*el-*-linux* and mips*-*-linux* into
+ #ifdef BFD64.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (mips_elf_calculate_relocation): Fix the handling
+ of protected symbols.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elflink.c (bfd_elf_record_link_assignment): Remove --defsym
+ symbols special case.
+
+ * elf64-mips.c (mips16_elf64_howto_table_rela): Correct src_mask
+ field initializers throughout.
+ * elfn32-mips.c (elf_mips16_howto_table_rela): Likewise.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * elfxx-mips.c (mips_elf_perform_relocation): Update the
+ cross-mode jump message.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
targ_selvecs="bfd_elf32_ntradlittlemips_vec bfd_elf32_tradbigmips_vec bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec"
want64=true
;;
-#endif
mips*el-*-linux*)
targ_defvec=bfd_elf32_tradlittlemips_vec
targ_selvecs="bfd_elf32_tradbigmips_vec ecoff_little_vec ecoff_big_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradlittlemips_vec bfd_elf32_ntradbigmips_vec bfd_elf64_tradbigmips_vec"
targ_selvecs="bfd_elf32_tradlittlemips_vec ecoff_big_vec ecoff_little_vec bfd_elf32_ntradbigmips_vec bfd_elf64_tradbigmips_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradlittlemips_vec"
want64=true
;;
-#ifdef BFD64
mips64*el-*-freebsd* | mips64*el-*-kfreebsd*-gnu)
# FreeBSD vectors
targ_defvec=bfd_elf32_ntradlittlemips_freebsd_vec
;
else
{
+ BFD_ASSERT (h->dynindx != -1);
indx = h->dynindx;
unresolved_reloc = FALSE;
}
|| h->root.type == bfd_link_hash_undefweak))
|| !SYMBOL_REFERENCES_LOCAL (info, h))
{
+ BFD_ASSERT (h->dynindx != -1);
unresolved_reloc = FALSE;
outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
outrel.r_addend = rel->r_addend;
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GD", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_LDM", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GOTTPREL", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
;
else
{
+ BFD_ASSERT (h->elf.dynindx != -1);
indx = h->elf.dynindx;
unresolved_reloc = FALSE;
}
else if (!SYMBOL_CALLS_LOCAL (info, &h->elf)
&& !is_opd
&& r_type != R_PPC64_TOC)
- outrel.r_info = ELF64_R_INFO (h->elf.dynindx, r_type);
+ {
+ BFD_ASSERT (h->elf.dynindx != -1);
+ outrel.r_info = ELF64_R_INFO (h->elf.dynindx, r_type);
+ }
else
{
/* This symbol is local, or marked to become local,
h->def_regular = 1;
- if (provide && hidden)
+ if (hidden)
{
bed = get_elf_backend_data (output_bfd);
h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN;
vh->root.type = h->root.type;
h->root.type = bfd_link_hash_indirect;
(*bed->elf_backend_copy_indirect_symbol) (info, vh, h);
- /* Protected symbols will override the dynamic definition
- with default version. */
- if (ELF_ST_VISIBILITY (sym->st_other) == STV_PROTECTED)
+
+ h->root.u.i.link = (struct bfd_link_hash_entry *) vh;
+ if (ELF_ST_VISIBILITY (sym->st_other) != STV_PROTECTED)
{
- h->root.u.i.link = (struct bfd_link_hash_entry *) vh;
- vh->dynamic_def = 1;
- vh->ref_dynamic = 1;
+ /* If the new symbol is hidden or internal, completely undo
+ any dynamic link state. */
+ (*bed->elf_backend_hide_symbol) (info, h, TRUE);
+ h->forced_local = 0;
+ h->ref_dynamic = 0;
}
else
- {
- h->root.type = vh->root.type;
- vh->ref_dynamic = 0;
- /* We have to hide it here since it was made dynamic
- global with extra bits when the symbol info was
- copied from the old dynamic definition. */
- (*bed->elf_backend_hide_symbol) (info, vh, TRUE);
- }
+ h->ref_dynamic = 1;
+
+ h->def_dynamic = 0;
+ h->dynamic_def = 0;
+ /* FIXME: Should we check type and size for protected symbol? */
+ h->size = 0;
+ h->type = 0;
+
h = vh;
}
else
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GD", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_LDM", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_DTPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_GOTTPREL", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_HI16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
_bfd_mips_elf_generic_reloc, /* special_function */
"R_MIPS16_TLS_TPREL_LO16", /* name */
FALSE, /* partial_inplace */
- 0x0000ffff, /* src_mask */
+ 0, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
#define LA25_LUI(VAL) (0x3c190000 | (VAL)) /* lui t9,VAL */
#define LA25_J(VAL) (0x08000000 | (((VAL) >> 2) & 0x3ffffff)) /* j VAL */
#define LA25_ADDIU(VAL) (0x27390000 | (VAL)) /* addiu t9,t9,VAL */
-#define LA25_LUI_MICROMIPS_1(VAL) (0x41b9) /* lui t9,VAL */
-#define LA25_LUI_MICROMIPS_2(VAL) (VAL)
-#define LA25_J_MICROMIPS_1(VAL) (0xd400 | (((VAL) >> 17) & 0x3ff)) /* j VAL */
-#define LA25_J_MICROMIPS_2(VAL) ((VAL) >> 1)
-#define LA25_ADDIU_MICROMIPS_1(VAL) (0x3339) /* addiu t9,t9,VAL */
-#define LA25_ADDIU_MICROMIPS_2(VAL) (VAL)
+#define LA25_LUI_MICROMIPS(VAL) \
+ (0x41b90000 | (VAL)) /* lui t9,VAL */
+#define LA25_J_MICROMIPS(VAL) \
+ (0xd4000000 | (((VAL) >> 1) & 0x3ffffff)) /* j VAL */
+#define LA25_ADDIU_MICROMIPS(VAL) \
+ (0x33390000 | (VAL)) /* addiu t9,t9,VAL */
/* This structure is passed to mips_elf_sort_hash_table_f when sorting
the dynamic symbols. */
0x24180000 /* li t8, <pltindex> */
};
\f
+/* microMIPS 32-bit opcode helper installer. */
+
+static void
+bfd_put_micromips_32 (const bfd *abfd, bfd_vma opcode, bfd_byte *ptr)
+{
+ bfd_put_16 (abfd, (opcode >> 16) & 0xffff, ptr);
+ bfd_put_16 (abfd, opcode & 0xffff, ptr + 2);
+}
+
+/* microMIPS 32-bit opcode helper retriever. */
+
+static bfd_vma
+bfd_get_micromips_32 (const bfd *abfd, const bfd_byte *ptr)
+{
+ return (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+}
+\f
/* Look up an entry in a MIPS ELF linker hash table. */
#define mips_elf_link_hash_lookup(table, string, create, copy, follow) \
&& (target_is_16_bit_code_p
|| target_is_micromips_code_p))));
- local_p = h == NULL || SYMBOL_REFERENCES_LOCAL (info, &h->root);
+ local_p = (h == NULL
+ || (h->got_only_for_calls
+ ? SYMBOL_CALLS_LOCAL (info, &h->root)
+ : SYMBOL_REFERENCES_LOCAL (info, &h->root)));
gp0 = _bfd_get_gp_value (input_bfd);
gp = _bfd_get_gp_value (abfd);
jalx_opcode = 0x1d;
}
- /* If the opcode is not JAL or JALX, there's a problem. */
+ /* If the opcode is not JAL or JALX, there's a problem. We cannot
+ convert J or JALS to JALX. */
if (!ok)
{
(*_bfd_error_handler)
- (_("%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled."),
+ (_("%B: %A+0x%lx: Unsupported jump between ISA modes; consider recompiling with interlinking enabled."),
input_bfd,
input_section,
(unsigned long) relocation->r_offset);
if (IRIX_COMPAT (dynobj) == ict_irix6
&& (bfd_get_section_by_name
- (dynobj, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
+ (output_bfd, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
&& !MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_OPTIONS, 0))
return FALSE;
}
loc += offset;
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
- loc);
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
- loc + 2);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
- loc + 4);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
- loc + 6);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_LUI_MICROMIPS (target_high),
+ loc);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low),
+ loc + 4);
}
else
{
loc += offset;
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_1 (target_high),
- loc);
- bfd_put_16 (hti->output_bfd, LA25_LUI_MICROMIPS_2 (target_high),
- loc + 2);
- bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_1 (target), loc + 4);
- bfd_put_16 (hti->output_bfd, LA25_J_MICROMIPS_2 (target), loc + 6);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_1 (target_low),
- loc + 8);
- bfd_put_16 (hti->output_bfd, LA25_ADDIU_MICROMIPS_2 (target_low),
- loc + 10);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_LUI_MICROMIPS (target_high), loc);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_J_MICROMIPS (target), loc + 4);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low), loc + 8);
bfd_put_32 (hti->output_bfd, 0, loc + 12);
}
else
unsigned long opcode;
int bdsize;
- opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (find_match (opcode, ds_insns_32_bd32) >= 0)
/* 32-bit branch/jump with a 32-bit delay slot. */
bdsize = 4;
{
unsigned long opcode;
- opcode = (bfd_get_16 (abfd, ptr) << 16) | bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (MATCH (opcode, j_insn_32)
/* J */
|| MATCH (opcode, bc_insn_32)
const Elf_Internal_Rela *irel;
unsigned long opcode;
- opcode = bfd_get_16 (abfd, ptr);
- opcode <<= 16;
- opcode |= bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
if (find_match (opcode, bzc_insns_32) < 0)
return FALSE;
if (irel->r_offset + 4 > sec->size)
continue;
- opcode = bfd_get_16 (abfd, ptr ) << 16;
- opcode |= bfd_get_16 (abfd, ptr + 2);
+ opcode = bfd_get_micromips_32 (abfd, ptr);
/* This is the pc-relative distance from the instruction the
relocation is applied to, to the symbol referred. */
continue;
}
- nextopc = bfd_get_16 (abfd, contents + irel[1].r_offset ) << 16;
- nextopc |= bfd_get_16 (abfd, contents + irel[1].r_offset + 2);
+ nextopc = bfd_get_micromips_32 (abfd, contents + irel[1].r_offset);
/* Give up unless the same register is used with both
relocations. */
nextopc = (addiupc_insn.match
| ADDIUPC_REG_FIELD (OP32_TREG (nextopc)));
- bfd_put_16 (abfd, (nextopc >> 16) & 0xffff,
- contents + irel[1].r_offset);
- bfd_put_16 (abfd, nextopc & 0xffff,
- contents + irel[1].r_offset + 2);
+ bfd_put_micromips_32 (abfd, nextopc,
+ contents + irel[1].r_offset);
}
/* Can't do anything, give up, sigh... */
| BZC32_REG_FIELD (reg)
| (opcode & 0xffff)); /* Addend value. */
- bfd_put_16 (abfd, (opcode >> 16) & 0xffff, ptr);
- bfd_put_16 (abfd, opcode & 0xffff, ptr + 2);
+ bfd_put_micromips_32 (abfd, opcode, ptr);
/* Delete the 16-bit delay slot NOP: two bytes from
irel->offset + 4. */
unsigned long n32opc;
bfd_boolean relaxed = FALSE;
- n32opc = bfd_get_16 (abfd, ptr + 4) << 16;
- n32opc |= bfd_get_16 (abfd, ptr + 6);
+ n32opc = bfd_get_micromips_32 (abfd, ptr + 4);
if (MATCH (n32opc, nop_insn_32))
{
{
/* JAL with 32-bit delay slot that is changed to a JALS
with 16-bit delay slot. */
- bfd_put_16 (abfd, (jal_insn_32_bd16.match >> 16) & 0xffff,
- ptr);
- bfd_put_16 (abfd, jal_insn_32_bd16.match & 0xffff,
- ptr + 2);
+ bfd_put_micromips_32 (abfd, jal_insn_32_bd16.match, ptr);
/* Delete 2 bytes from irel->r_offset + 6. */
delcnt = 2;
+ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
+ (is_opcode_valid): Remove coprocessor instruction exclusions.
+ Replace OPCODE_IS_MEMBER with opcode_is_member.
+ (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ (macro): Remove coprocessor instruction exclusions.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-31 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/c-mips.texi (MIPS Opts): Correct a typo in the -mips5
+ option.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.
+ (s_cplocal, s_cprestore, s_cpreturn): Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn): Also handle moving delay-slot
+ instruction across frags for fixed branches.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * frags.c (frag_grow): Never shrink the obstack size requested
+ below the default.
+
* config/tc-mips.c (ISA_SUPPORTS_DSP_ASE): Also set if microMIPS
mode.
(ISA_SUPPORTS_DSPR2_ASE): Likewise.
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
-/* True if CPU does not implement the all the coprocessor insns. For these
- CPUs only those COP insns are accepted that are explicitly marked to be
- available on the CPU. ISA membership for COP insns is ignored. */
-#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
-
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
#define MF_HILO_INSN(PINFO) \
((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
-/* Returns true for a (non floating-point) coprocessor instruction. Reading
- or writing the condition code is only possible on the coprocessors and
- these insns are not marked with INSN_COP. Thus for these insns use the
- condition-code flags. */
-#define COP_INSN(PINFO) \
- (PINFO != INSN_MACRO \
- && ((PINFO) & (FP_S | FP_D)) == 0 \
- && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
-
/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
has been selected. This implies, in particular, that addresses of text
labels have their LSB set. */
if (mips_opts.ase_mcu)
isa |= INSN_MCU;
- /* Don't accept instructions based on the ISA if the CPU does not implement
- all the coprocessor insns. */
- if (NO_ISA_COP (mips_opts.arch)
- && COP_INSN (mo->pinfo))
- isa = 0;
-
- if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
+ if (!opcode_is_member (mo, isa, mips_opts.arch))
return FALSE;
/* Check whether the instruction or macro requires single-precision or
static bfd_boolean
is_opcode_valid_16 (const struct mips_opcode *mo)
{
- return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
+ return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
}
/* Return TRUE if the size of the microMIPS opcode MO matches one
move_insn (ip, delay.frag, delay.where);
move_insn (&delay, ip->frag, ip->where + insn_length (ip));
}
- else if (relaxed_branch)
+ else if (relaxed_branch || delay.frag != ip->frag)
{
/* Add the delay slot instruction to the end of the
current frag and shrink the fixed part of the
tempreg = AT;
used_at = 1;
ld_noat:
- if (coproc
- && NO_ISA_COP (mips_opts.arch)
- && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
- {
- as_bad (_("Opcode not supported on this processor: %s"),
- mips_cpu_info_from_arch (mips_opts.arch)->name);
- break;
- }
-
if (offset_expr.X_op != O_constant
&& offset_expr.X_op != O_symbol)
{
s = "c3";
copz:
gas_assert (!mips_opts.micromips);
- if (NO_ISA_COP (mips_opts.arch)
- && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
- {
- as_bad (_("Opcode not supported on this processor: %s"),
- mips_cpu_info_from_arch (mips_opts.arch)->name);
- break;
- }
-
/* For now we just do C (same as Cz). The parameter will be
stored in insn_opcode by mips_ip. */
macro_build (NULL, s, "C", ip->insn_opcode);
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
+ ignore_rest_of_line ();
+ return;
+ }
+
/* .cpload should be in a .set noreorder section. */
if (mips_opts.noreorder == 0)
as_warn (_(".cpload not in noreorder section"));
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
+ ignore_rest_of_line ();
+ return;
+ }
+
reg1 = tc_get_register (0);
SKIP_WHITESPACE ();
if (*input_line_pointer != ',')
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
+ ignore_rest_of_line ();
+ return;
+ }
+
mips_gp_register = tc_get_register (0);
demand_empty_rest_of_line ();
}
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
+ ignore_rest_of_line ();
+ return;
+ }
+
mips_cprestore_offset = get_absolute_expression ();
mips_cprestore_valid = 1;
return;
}
+ if (mips_opts.mips16)
+ {
+ as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
+ ignore_rest_of_line ();
+ return;
+ }
+
macro_start ();
if (mips_cpreturn_register == -1)
{
@itemx -mips2
@itemx -mips3
@itemx -mips4
-@itemx -mips5xo
+@itemx -mips5
@itemx -mips32
@itemx -mips32r2
@itemx -mips64
if (newc < 0)
as_fatal (_("can't extend frag %u chars"), nchars);
- /* Force to allocate at least NEWC bytes. */
+ /* Force to allocate at least NEWC bytes, but not less than the
+ default. */
oldc = obstack_chunk_size (&frchain_now->frch_obstack);
- obstack_chunk_size (&frchain_now->frch_obstack) = newc;
+ if (newc > oldc)
+ obstack_chunk_size (&frchain_now->frch_obstack) = newc;
while (obstack_room (&frchain_now->frch_obstack) < nchars)
{
+ * gas/mips/mips.exp: Set has_newabi for all Linux targets.
+ * gas/mips/cfi-n64-1.d: Adjust for targets that do not infer the
+ ISA from the ABI.
+ * gas/mips/elf-rel-got-n32.d: Likewise.
+ * gas/mips/elf-rel-got-n64.d: Likewise.
+ * gas/mips/elf-rel-xgot-n32.d: Likewise.
+ * gas/mips/elf-rel-xgot-n64.d: Likewise.
+ * gas/mips/elf-rel18.d: Likewise.
+ * gas/mips/elf-rel28-n32.d: Likewise.
+ * gas/mips/elf-rel28-n64.d: Likewise.
+ * gas/mips/jal-newabi.d: Likewise.
+ * gas/mips/ldstla-n64-shared.d: Likewise.
+ * gas/mips/ldstla-n64-sym32.d: Likewise.
+ * gas/mips/ldstla-n64.d: Likewise.
+ * gas/mips/macro-warn-1-n32.d: Likewise.
+ * gas/mips/macro-warn-2-n32.d: Likewise.
+ * gas/mips/n32-consec.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/mips.exp: Set has_newabi for mips*-sde-elf* too.
+ * gas/mips/elf-rel-got-n32.s: Adjust padding.
+ * gas/mips/elf-rel-got-n64.s: Likewise.
+ * gas/mips/elf-rel23.s: Likewise.
+ * gas/mips/elf-rel28.s: Likewise.
+ * gas/mips/n32-consec.s: Likewise.
+ * gas/mips/elf-rel-xgot-n32.d: Adjust output expected.
+ * gas/mips/elf-rel-xgot-n64.d: Likewise.
+ * gas/mips/elf-rel23.d: Likewise.
+ * gas/mips/elf-rel23a.d: Likewise.
+ * gas/mips/elf-rel23b.d: Likewise.
+ * gas/mips/elf-rel28-n32.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/branch-swap-2.l: New list test.
+ * gas/mips/branch-swap-2.s: New test source.
+ * gas/mips/mips.exp: Run the new test.
+
* gas/mips/micromips@mips32-dsp.d: New test.
* gas/mips/micromips@mips32-dspr2.d: New test.
* gas/mips/mips32-dsp.s: Update padding.
--- /dev/null
+# as: -xnone -W
+# objdump: -d
+# name: ia64 psn
+
+.*: +file format elf64-ia64.*
+
+Disassembly of section \.text:
+
+0+000 <AAAAA-0x1.*>:
+ 0: 08 00 04 05 60 19 \[MMI\] lfetch.count \[r2\],1,64
+ 6: 40 f8 5a c0 32 00 lfetch.count \[r22\],5,-64
+ c: 00 00 04 00 nop.i 0x0
+ 10: 08 40 3c 2f 62 19 \[MMI\] lfetch.count.nt1 \[r23\],9,960
+ 16: b0 80 ea c5 32 00 lfetch.count.nt1 \[r122\],12,-1024
+ 1c: 00 00 04 00 nop.i 0x0
+ 20: 08 78 08 0b 64 19 \[MMI\] lfetch.count.nt2 \[r5\],16,128
+ 26: 30 e1 3e c8 32 00 lfetch.count.nt2 \[r15\],20,-256
+ 2c: 00 00 04 00 nop.i 0x0
+ 30: 08 b8 20 fb 66 19 \[MMI\] lfetch.count.nta \[r125\],24,512
+ 36: c0 79 22 cc 32 00 lfetch.count.nta \[r8\],29,960
+ 3c: 00 00 04 00 nop.i 0x0
+ 40: 08 08 43 25 60 19 \[MMI\] lfetch.count.d4 \[r18\],34,-1024
+ 46: d0 77 fe c5 32 00 lfetch.count.d5 \[r127\],62,896
+ 4c: 00 00 04 00 nop.i 0x0
+ 50: 09 f0 43 15 64 19 \[MMI\] lfetch.count.d6 \[r10\],63,-1024
+ 56: f0 07 82 cd 32 20 lfetch.count.d7 \[r96\],64,0
+ 5c: 10 04 08 50 tf.z p1,p2=32;;
+ 60: 02 00 00 00 01 00 \[MII\] nop.m 0x0
+ 66: 20 08 02 0e 28 60 tf.z p2,p7=32;;
+ 6c: 18 04 08 50 tf.z.unc p3,p2=32
+ 70: 00 00 00 00 01 00 \[MII\] nop.m 0x0
+ 76: 40 18 02 06 28 a0 tf.z p4,p3=33
+ 7c: 50 04 10 58 tf.z.and p5,p4=34
+ 80: 00 00 00 00 01 00 \[MII\] nop.m 0x0
+ 86: 50 3c 02 0c 2c c0 tf.nz.and p5,p6=35
+ 8c: 70 04 14 58 tf.z.and p6,p5=35
+ 90: 00 00 00 00 01 00 \[MII\] nop.m 0x0
+ 96: 70 f8 03 8c 28 a0 tf.z.or p7,p6=63
+ 9c: 78 04 18 51 tf.nz.or p5,p6=35
+ a0: 00 00 00 00 01 00 \[MII\] nop.m 0x0
+ a6: 70 18 02 8c 2c e0 tf.z.or.andcm p7,p6=33
+ ac: 58 04 18 59 tf.nz.or.andcm p7,p6=34
+ b0: 00 00 00 00 01 00 \[MII\] nop.m 0x0
+ b6: 60 0c 02 8e 2c c0 tf.nz.or.andcm p6,p7=32
+ bc: 30 04 1c 59 tf.z.or.andcm p6,p7=33
+ c0: 11 00 00 00 01 00 \[MIB\] nop.m 0x0
+ c6: 00 1c 02 0c 28 00 tf.z.unc p0,p6=33
+ cc: 00 00 00 20 nop.b 0x0;;
+ d0: 08 00 02 24 60 19 \[MMI\] lfetch.d4 \[r18\]
+ d6: 00 00 00 02 00 00 nop.m 0x0
+ dc: 00 00 04 00 nop.i 0x0
+ e0: 0a 00 02 26 7e 19 \[MMI\] lfetch.fault.excl.d7 \[r19\];;
+ e6: 10 10 3a c0 32 00 lfetch.count \[r14\],2,128
+ ec: 01 50 58 00 sxt4 r8=r10
+ f0: 0a f8 13 17 60 19 \[MMI\] lfetch.count.d4 \[r11\],64,256;;
+ f6: 00 04 44 d4 32 00 lfetch.excl.d5 \[r17\]
+ fc: 00 00 04 00 nop.i 0x0
+ 100: 0b 00 02 20 74 19 \[MMI\] lfetch.fault.d6 \[r16\];;
+ 106: 70 01 e0 03 00 60 mov dahr7=7
+ 10c: 00 48 68 73 clz r3=r9;;
+ 110: 00 b0 00 e0 01 00 \[MII\] mov dahr6=6
+ 116: 20 48 20 34 3c 40 mpy4 r2=r9,r8
+ 11c: 90 40 78 78 mpyshl4 r2=r9,r8
+ 120: 0b a8 00 d0 01 00 \[MMI\] mov dahr5=5;;
+ 126: 40 01 80 03 00 00 mov dahr4=4
+ 12c: 00 00 04 00 nop.i 0x0;;
+ 130: 11 98 00 b0 01 00 \[MIB\] mov dahr3=3
+ 136: 80 10 0c 00 40 00 add r8=r2,r3
+ 13c: 00 00 00 20 nop.b 0x0;;
+ 140: 0b 90 00 a0 01 00 \[MMI\] mov dahr2=2;;
+ 146: 10 01 20 03 00 00 mov dahr1=1
+ 14c: 00 00 04 00 nop.i 0x0;;
+ 150: 10 80 00 80 01 00 \[MIB\] mov dahr0=0
+ 156: 00 00 00 02 00 00 nop.i 0x0
+ 15c: 00 00 00 20 nop.b 0x0
+ 160: 08 60 00 0a 20 04 \[MMI\] mov r12=dahr\[r5\]
+ 166: a0 07 dc 40 08 00 mov r122=dahr\[r55\]
+ 16c: 00 00 04 00 nop.i 0x0
+ 170: 08 00 74 83 80 11 \[MMI\] st1 \[r65\]=r93
+ 176: 00 e8 06 05 23 00 st1.d1 \[r65\]=r93
+ 17c: 00 00 04 00 nop.i 0x0
+ 180: 08 00 74 83 82 11 \[MMI\] st1.d1 \[r65\]=r93
+ 186: 00 e8 06 09 23 00 st1.d2 \[r65\]=r93
+ 18c: 00 00 04 00 nop.i 0x0
+ 190: 08 00 74 83 84 11 \[MMI\] st1.d2 \[r65\]=r93
+ 196: 00 e8 06 0d 23 00 st1.nta \[r65\]=r93
+ 19c: 00 00 04 00 nop.i 0x0
+ 1a0: 08 00 74 83 86 11 \[MMI\] st1.nta \[r65\]=r93
+ 1a6: 00 ec 06 01 23 00 st1.d4 \[r65\]=r93
+ 1ac: 00 00 04 00 nop.i 0x0
+ 1b0: 08 00 76 83 82 11 \[MMI\] st1.d5 \[r65\]=r93
+ 1b6: 00 ec 06 09 23 00 st1.d6 \[r65\]=r93
+ 1bc: 00 00 04 00 nop.i 0x0
+ 1c0: 08 00 76 83 86 11 \[MMI\] st1.d7 \[r65\]=r93
+ 1c6: 00 e8 06 11 23 00 st2 \[r65\]=r93
+ 1cc: 00 00 04 00 nop.i 0x0
+ 1d0: 08 00 74 83 8a 11 \[MMI\] st2.d1 \[r65\]=r93
+ 1d6: 00 e8 06 15 23 00 st2.d1 \[r65\]=r93
+ 1dc: 00 00 04 00 nop.i 0x0
+ 1e0: 08 00 74 83 8c 11 \[MMI\] st2.d2 \[r65\]=r93
+ 1e6: 00 e8 06 19 23 00 st2.d2 \[r65\]=r93
+ 1ec: 00 00 04 00 nop.i 0x0
+ 1f0: 08 00 74 83 8e 11 \[MMI\] st2.nta \[r65\]=r93
+ 1f6: 00 e8 06 1d 23 00 st2.nta \[r65\]=r93
+ 1fc: 00 00 04 00 nop.i 0x0
+ 200: 08 00 76 83 88 11 \[MMI\] st2.d4 \[r65\]=r93
+ 206: 00 ec 06 15 23 00 st2.d5 \[r65\]=r93
+ 20c: 00 00 04 00 nop.i 0x0
+ 210: 08 00 76 83 8c 11 \[MMI\] st2.d6 \[r65\]=r93
+ 216: 00 ec 06 1d 23 00 st2.d7 \[r65\]=r93
+ 21c: 00 00 04 00 nop.i 0x0
+ 220: 08 00 74 83 90 11 \[MMI\] st4 \[r65\]=r93
+ 226: 00 e8 06 25 23 00 st4.d1 \[r65\]=r93
+ 22c: 00 00 04 00 nop.i 0x0
+ 230: 08 00 74 83 92 11 \[MMI\] st4.d1 \[r65\]=r93
+ 236: 00 e8 06 29 23 00 st4.d2 \[r65\]=r93
+ 23c: 00 00 04 00 nop.i 0x0
+ 240: 08 00 74 83 94 11 \[MMI\] st4.d2 \[r65\]=r93
+ 246: 00 e8 06 2d 23 00 st4.nta \[r65\]=r93
+ 24c: 00 00 04 00 nop.i 0x0
+ 250: 08 00 74 83 96 11 \[MMI\] st4.nta \[r65\]=r93
+ 256: 00 ec 06 21 23 00 st4.d4 \[r65\]=r93
+ 25c: 00 00 04 00 nop.i 0x0
+ 260: 08 00 76 83 92 11 \[MMI\] st4.d5 \[r65\]=r93
+ 266: 00 ec 06 29 23 00 st4.d6 \[r65\]=r93
+ 26c: 00 00 04 00 nop.i 0x0
+ 270: 08 00 76 83 96 11 \[MMI\] st4.d7 \[r65\]=r93
+ 276: 00 e8 06 31 23 00 st8 \[r65\]=r93
+ 27c: 00 00 04 00 nop.i 0x0
+ 280: 08 00 74 83 9a 11 \[MMI\] st8.d1 \[r65\]=r93
+ 286: 00 e8 06 35 23 00 st8.d1 \[r65\]=r93
+ 28c: 00 00 04 00 nop.i 0x0
+ 290: 08 00 74 83 9c 11 \[MMI\] st8.d2 \[r65\]=r93
+ 296: 00 e8 06 39 23 00 st8.d2 \[r65\]=r93
+ 29c: 00 00 04 00 nop.i 0x0
+ 2a0: 08 00 74 83 9e 11 \[MMI\] st8.nta \[r65\]=r93
+ 2a6: 00 e8 06 3d 23 00 st8.nta \[r65\]=r93
+ 2ac: 00 00 04 00 nop.i 0x0
+ 2b0: 08 00 76 83 98 11 \[MMI\] st8.d4 \[r65\]=r93
+ 2b6: 00 ec 06 35 23 00 st8.d5 \[r65\]=r93
+ 2bc: 00 00 04 00 nop.i 0x0
+ 2c0: 08 00 76 83 9c 11 \[MMI\] st8.d6 \[r65\]=r93
+ 2c6: 00 ec 06 3d 23 00 st8.d7 \[r65\]=r93
+ 2cc: 00 00 04 00 nop.i 0x0
+ 2d0: 08 00 74 83 81 11 \[MMI\] st16 \[r65\]=r93,ar.csd
+ 2d6: 00 e8 06 03 23 00 st16 \[r65\]=r93,ar.csd
+ 2dc: 00 00 04 00 nop.i 0x0
+ 2e0: 08 00 74 83 83 11 \[MMI\] st16.d1 \[r65\]=r93,ar.csd
+ 2e6: 00 e8 06 07 23 00 st16.d1 \[r65\]=r93,ar.csd
+ 2ec: 00 00 04 00 nop.i 0x0
+ 2f0: 08 00 74 83 85 11 \[MMI\] st16.d2 \[r65\]=r93,ar.csd
+ 2f6: 00 e8 06 0b 23 00 st16.d2 \[r65\]=r93,ar.csd
+ 2fc: 00 00 04 00 nop.i 0x0
+ 300: 08 00 74 83 87 11 \[MMI\] st16.nta \[r65\]=r93,ar.csd
+ 306: 00 e8 06 0f 23 00 st16.nta \[r65\]=r93,ar.csd
+ 30c: 00 00 04 00 nop.i 0x0
+ 310: 08 00 76 83 81 11 \[MMI\] st16.d4 \[r65\]=r93,ar.csd
+ 316: 00 ec 06 07 23 00 st16.d5 \[r65\]=r93,ar.csd
+ 31c: 00 00 04 00 nop.i 0x0
+ 320: 08 00 76 83 85 11 \[MMI\] st16.d6 \[r65\]=r93,ar.csd
+ 326: 00 ec 06 0f 23 00 st16.d7 \[r65\]=r93,ar.csd
+ 32c: 00 00 04 00 nop.i 0x0
+ 330: 08 00 74 83 87 11 \[MMI\] st16.nta \[r65\]=r93,ar.csd
+ 336: 00 e8 06 0f 23 00 st16.nta \[r65\]=r93,ar.csd
+ 33c: 00 00 04 00 nop.i 0x0
+ 340: 08 00 76 83 81 11 \[MMI\] st16.d4 \[r65\]=r93,ar.csd
+ 346: 00 ec 06 07 23 00 st16.d5 \[r65\]=r93,ar.csd
+ 34c: 00 00 04 00 nop.i 0x0
+ 350: 08 00 76 83 85 11 \[MMI\] st16.d6 \[r65\]=r93,ar.csd
+ 356: 00 ec 06 0f 23 00 st16.d7 \[r65\]=r93,ar.csd
+ 35c: 00 00 04 00 nop.i 0x0
+ 360: 08 00 74 83 a0 11 \[MMI\] st1.rel \[r65\]=r93
+ 366: 00 e8 06 45 23 00 st1.rel.d1 \[r65\]=r93
+ 36c: 00 00 04 00 nop.i 0x0
+ 370: 08 00 74 83 a2 11 \[MMI\] st1.rel.d1 \[r65\]=r93
+ 376: 00 e8 06 49 23 00 st1.rel.d2 \[r65\]=r93
+ 37c: 00 00 04 00 nop.i 0x0
+ 380: 08 00 74 83 a4 11 \[MMI\] st1.rel.d2 \[r65\]=r93
+ 386: 00 e8 06 4d 23 00 st1.rel.nta \[r65\]=r93
+ 38c: 00 00 04 00 nop.i 0x0
+ 390: 08 00 74 83 a6 11 \[MMI\] st1.rel.nta \[r65\]=r93
+ 396: 00 ec 06 41 23 00 st1.rel.d4 \[r65\]=r93
+ 39c: 00 00 04 00 nop.i 0x0
+ 3a0: 08 00 76 83 a2 11 \[MMI\] st1.rel.d5 \[r65\]=r93
+ 3a6: 00 ec 06 49 23 00 st1.rel.d6 \[r65\]=r93
+ 3ac: 00 00 04 00 nop.i 0x0
+ 3b0: 08 00 76 83 a6 11 \[MMI\] st1.rel.d7 \[r65\]=r93
+ 3b6: 00 e8 06 51 23 00 st2.rel \[r65\]=r93
+ 3bc: 00 00 04 00 nop.i 0x0
+ 3c0: 08 00 74 83 aa 11 \[MMI\] st2.rel.d1 \[r65\]=r93
+ 3c6: 00 e8 06 55 23 00 st2.rel.d1 \[r65\]=r93
+ 3cc: 00 00 04 00 nop.i 0x0
+ 3d0: 08 00 74 83 ac 11 \[MMI\] st2.rel.d2 \[r65\]=r93
+ 3d6: 00 e8 06 59 23 00 st2.rel.d2 \[r65\]=r93
+ 3dc: 00 00 04 00 nop.i 0x0
+ 3e0: 08 00 74 83 ae 11 \[MMI\] st2.rel.nta \[r65\]=r93
+ 3e6: 00 e8 06 5d 23 00 st2.rel.nta \[r65\]=r93
+ 3ec: 00 00 04 00 nop.i 0x0
+ 3f0: 08 00 76 83 a8 11 \[MMI\] st2.rel.d4 \[r65\]=r93
+ 3f6: 00 ec 06 55 23 00 st2.rel.d5 \[r65\]=r93
+ 3fc: 00 00 04 00 nop.i 0x0
+ 400: 08 00 76 83 ac 11 \[MMI\] st2.rel.d6 \[r65\]=r93
+ 406: 00 ec 06 5d 23 00 st2.rel.d7 \[r65\]=r93
+ 40c: 00 00 04 00 nop.i 0x0
+ 410: 08 00 74 83 b0 11 \[MMI\] st4.rel \[r65\]=r93
+ 416: 00 e8 06 65 23 00 st4.rel.d1 \[r65\]=r93
+ 41c: 00 00 04 00 nop.i 0x0
+ 420: 08 00 74 83 b2 11 \[MMI\] st4.rel.d1 \[r65\]=r93
+ 426: 00 e8 06 69 23 00 st4.rel.d2 \[r65\]=r93
+ 42c: 00 00 04 00 nop.i 0x0
+ 430: 08 00 74 83 b4 11 \[MMI\] st4.rel.d2 \[r65\]=r93
+ 436: 00 e8 06 6d 23 00 st4.rel.nta \[r65\]=r93
+ 43c: 00 00 04 00 nop.i 0x0
+ 440: 08 00 74 83 b6 11 \[MMI\] st4.rel.nta \[r65\]=r93
+ 446: 00 ec 06 61 23 00 st4.rel.d4 \[r65\]=r93
+ 44c: 00 00 04 00 nop.i 0x0
+ 450: 08 00 76 83 b2 11 \[MMI\] st4.rel.d5 \[r65\]=r93
+ 456: 00 ec 06 69 23 00 st4.rel.d6 \[r65\]=r93
+ 45c: 00 00 04 00 nop.i 0x0
+ 460: 08 00 76 83 b6 11 \[MMI\] st4.rel.d7 \[r65\]=r93
+ 466: 00 e8 06 71 23 00 st8.rel \[r65\]=r93
+ 46c: 00 00 04 00 nop.i 0x0
+ 470: 08 00 74 83 ba 11 \[MMI\] st8.rel.d1 \[r65\]=r93
+ 476: 00 e8 06 75 23 00 st8.rel.d1 \[r65\]=r93
+ 47c: 00 00 04 00 nop.i 0x0
+ 480: 08 00 74 83 bc 11 \[MMI\] st8.rel.d2 \[r65\]=r93
+ 486: 00 e8 06 79 23 00 st8.rel.d2 \[r65\]=r93
+ 48c: 00 00 04 00 nop.i 0x0
+ 490: 08 00 74 83 be 11 \[MMI\] st8.rel.nta \[r65\]=r93
+ 496: 00 e8 06 7d 23 00 st8.rel.nta \[r65\]=r93
+ 49c: 00 00 04 00 nop.i 0x0
+ 4a0: 08 00 76 83 b8 11 \[MMI\] st8.rel.d4 \[r65\]=r93
+ 4a6: 00 ec 06 75 23 00 st8.rel.d5 \[r65\]=r93
+ 4ac: 00 00 04 00 nop.i 0x0
+ 4b0: 08 00 76 83 bc 11 \[MMI\] st8.rel.d6 \[r65\]=r93
+ 4b6: 00 ec 06 7d 23 00 st8.rel.d7 \[r65\]=r93
+ 4bc: 00 00 04 00 nop.i 0x0
+ 4c0: 08 00 74 83 a1 11 \[MMI\] st16.rel \[r65\]=r93,ar.csd
+ 4c6: 00 e8 06 43 23 00 st16.rel \[r65\]=r93,ar.csd
+ 4cc: 00 00 04 00 nop.i 0x0
+ 4d0: 08 00 74 83 a3 11 \[MMI\] st16.rel.d1 \[r65\]=r93,ar.csd
+ 4d6: 00 e8 06 47 23 00 st16.rel.d1 \[r65\]=r93,ar.csd
+ 4dc: 00 00 04 00 nop.i 0x0
+ 4e0: 08 00 74 83 a3 11 \[MMI\] st16.rel.d1 \[r65\]=r93,ar.csd
+ 4e6: 00 e8 06 47 23 00 st16.rel.d1 \[r65\]=r93,ar.csd
+ 4ec: 00 00 04 00 nop.i 0x0
+ 4f0: 08 00 74 83 a5 11 \[MMI\] st16.rel.d2 \[r65\]=r93,ar.csd
+ 4f6: 00 e8 06 4b 23 00 st16.rel.d2 \[r65\]=r93,ar.csd
+ 4fc: 00 00 04 00 nop.i 0x0
+ 500: 08 00 74 83 a5 11 \[MMI\] st16.rel.d2 \[r65\]=r93,ar.csd
+ 506: 00 e8 06 4b 23 00 st16.rel.d2 \[r65\]=r93,ar.csd
+ 50c: 00 00 04 00 nop.i 0x0
+ 510: 08 00 74 83 a7 11 \[MMI\] st16.rel.nta \[r65\]=r93,ar.csd
+ 516: 00 e8 06 4f 23 00 st16.rel.nta \[r65\]=r93,ar.csd
+ 51c: 00 00 04 00 nop.i 0x0
+ 520: 08 00 76 83 a1 11 \[MMI\] st16.rel.d4 \[r65\]=r93,ar.csd
+ 526: 00 ec 06 47 23 00 st16.rel.d5 \[r65\]=r93,ar.csd
+ 52c: 00 00 04 00 nop.i 0x0
+ 530: 08 00 76 83 a5 11 \[MMI\] st16.rel.d6 \[r65\]=r93,ar.csd
+ 536: 00 ec 06 4f 23 00 st16.rel.d7 \[r65\]=r93,ar.csd
+ 53c: 00 00 04 00 nop.i 0x0
+ 540: 08 00 74 83 a7 11 \[MMI\] st16.rel.nta \[r65\]=r93,ar.csd
+ 546: 00 e8 06 4f 23 00 st16.rel.nta \[r65\]=r93,ar.csd
+ 54c: 00 00 04 00 nop.i 0x0
+ 550: 08 00 76 83 a1 11 \[MMI\] st16.rel.d4 \[r65\]=r93,ar.csd
+ 556: 00 ec 06 47 23 00 st16.rel.d5 \[r65\]=r93,ar.csd
+ 55c: 00 00 04 00 nop.i 0x0
+ 560: 08 00 76 83 a5 11 \[MMI\] st16.rel.d6 \[r65\]=r93,ar.csd
+ 566: 00 ec 06 4f 23 00 st16.rel.d7 \[r65\]=r93,ar.csd
+ 56c: 00 00 04 00 nop.i 0x0
+ 570: 08 00 74 83 d8 11 \[MMI\] st8.spill \[r65\]=r93
+ 576: 00 e8 06 b5 23 00 st8.spill.d1 \[r65\]=r93
+ 57c: 00 00 04 00 nop.i 0x0
+ 580: 08 00 74 83 da 11 \[MMI\] st8.spill.d1 \[r65\]=r93
+ 586: 00 e8 06 b9 23 00 st8.spill.d2 \[r65\]=r93
+ 58c: 00 00 04 00 nop.i 0x0
+ 590: 08 00 74 83 dc 11 \[MMI\] st8.spill.d2 \[r65\]=r93
+ 596: 00 e8 06 bd 23 00 st8.spill.nta \[r65\]=r93
+ 59c: 00 00 04 00 nop.i 0x0
+ 5a0: 08 00 74 83 de 11 \[MMI\] st8.spill.nta \[r65\]=r93
+ 5a6: 00 ec 06 b1 23 00 st8.spill.d4 \[r65\]=r93
+ 5ac: 00 00 04 00 nop.i 0x0
+ 5b0: 08 00 76 83 da 11 \[MMI\] st8.spill.d5 \[r65\]=r93
+ 5b6: 00 ec 06 b9 23 00 st8.spill.d6 \[r65\]=r93
+ 5bc: 00 00 04 00 nop.i 0x0
+ 5c0: 08 00 76 83 de 11 \[MMI\] st8.spill.d7 \[r65\]=r93
+ 5c6: 00 00 f0 c0 32 00 lfetch \[r60\]
+ 5cc: 00 00 04 00 nop.i 0x0
+ 5d0: 08 00 00 78 62 19 \[MMI\] lfetch.nt1 \[r60\]
+ 5d6: 00 00 f0 c4 32 00 lfetch.nt1 \[r60\]
+ 5dc: 00 00 04 00 nop.i 0x0
+ 5e0: 08 00 00 78 64 19 \[MMI\] lfetch.nt2 \[r60\]
+ 5e6: 00 00 f0 c8 32 00 lfetch.nt2 \[r60\]
+ 5ec: 00 00 04 00 nop.i 0x0
+ 5f0: 08 00 00 78 66 19 \[MMI\] lfetch.nta \[r60\]
+ 5f6: 00 00 f0 cc 32 00 lfetch.nta \[r60\]
+ 5fc: 00 00 04 00 nop.i 0x0
+ 600: 08 00 02 78 60 19 \[MMI\] lfetch.d4 \[r60\]
+ 606: 00 04 f0 c4 32 00 lfetch.d5 \[r60\]
+ 60c: 00 00 04 00 nop.i 0x0
+ 610: 08 00 02 78 64 19 \[MMI\] lfetch.d6 \[r60\]
+ 616: 00 04 f0 cc 32 00 lfetch.d7 \[r60\]
+ 61c: 00 00 04 00 nop.i 0x0
+ 620: 08 00 68 79 90 19 \[MMI\] stfs \[r60\]=f90
+ 626: 00 d0 f2 24 33 00 stfs.d1 \[r60\]=f90
+ 62c: 00 00 04 00 nop.i 0x0
+ 630: 08 00 68 79 92 19 \[MMI\] stfs.d1 \[r60\]=f90
+ 636: 00 d0 f2 28 33 00 stfs.d2 \[r60\]=f90
+ 63c: 00 00 04 00 nop.i 0x0
+ 640: 08 00 68 79 94 19 \[MMI\] stfs.d2 \[r60\]=f90
+ 646: 00 d0 f2 2c 33 00 stfs.nta \[r60\]=f90
+ 64c: 00 00 04 00 nop.i 0x0
+ 650: 08 00 68 79 96 19 \[MMI\] stfs.nta \[r60\]=f90
+ 656: 00 d4 f2 20 33 00 stfs.d4 \[r60\]=f90
+ 65c: 00 00 04 00 nop.i 0x0
+ 660: 08 00 6a 79 92 19 \[MMI\] stfs.d5 \[r60\]=f90
+ 666: 00 d4 f2 28 33 00 stfs.d6 \[r60\]=f90
+ 66c: 00 00 04 00 nop.i 0x0
+ 670: 08 00 6a 79 96 19 \[MMI\] stfs.d7 \[r60\]=f90
+ 676: 00 d0 f2 30 33 00 stfd \[r60\]=f90
+ 67c: 00 00 04 00 nop.i 0x0
+ 680: 08 00 68 79 9a 19 \[MMI\] stfd.d1 \[r60\]=f90
+ 686: 00 d0 f2 34 33 00 stfd.d1 \[r60\]=f90
+ 68c: 00 00 04 00 nop.i 0x0
+ 690: 08 00 68 79 9c 19 \[MMI\] stfd.d2 \[r60\]=f90
+ 696: 00 d0 f2 38 33 00 stfd.d2 \[r60\]=f90
+ 69c: 00 00 04 00 nop.i 0x0
+ 6a0: 08 00 68 79 9e 19 \[MMI\] stfd.nta \[r60\]=f90
+ 6a6: 00 d0 f2 3c 33 00 stfd.nta \[r60\]=f90
+ 6ac: 00 00 04 00 nop.i 0x0
+ 6b0: 08 00 6a 79 98 19 \[MMI\] stfd.d4 \[r60\]=f90
+ 6b6: 00 d4 f2 34 33 00 stfd.d5 \[r60\]=f90
+ 6bc: 00 00 04 00 nop.i 0x0
+ 6c0: 08 00 6a 79 9c 19 \[MMI\] stfd.d6 \[r60\]=f90
+ 6c6: 00 d4 f2 3c 33 00 stfd.d7 \[r60\]=f90
+ 6cc: 00 00 04 00 nop.i 0x0
+ 6d0: 08 00 68 79 88 19 \[MMI\] stf8 \[r60\]=f90
+ 6d6: 00 d0 f2 14 33 00 stf8.d1 \[r60\]=f90
+ 6dc: 00 00 04 00 nop.i 0x0
+ 6e0: 08 00 68 79 8a 19 \[MMI\] stf8.d1 \[r60\]=f90
+ 6e6: 00 d0 f2 18 33 00 stf8.d2 \[r60\]=f90
+ 6ec: 00 00 04 00 nop.i 0x0
+ 6f0: 08 00 68 79 8c 19 \[MMI\] stf8.d2 \[r60\]=f90
+ 6f6: 00 d0 f2 1c 33 00 stf8.nta \[r60\]=f90
+ 6fc: 00 00 04 00 nop.i 0x0
+ 700: 08 00 68 79 8e 19 \[MMI\] stf8.nta \[r60\]=f90
+ 706: 00 d4 f2 10 33 00 stf8.d4 \[r60\]=f90
+ 70c: 00 00 04 00 nop.i 0x0
+ 710: 08 00 6a 79 8a 19 \[MMI\] stf8.d5 \[r60\]=f90
+ 716: 00 d4 f2 18 33 00 stf8.d6 \[r60\]=f90
+ 71c: 00 00 04 00 nop.i 0x0
+ 720: 08 00 6a 79 8e 19 \[MMI\] stf8.d7 \[r60\]=f90
+ 726: 00 d0 f2 00 33 00 stfe \[r60\]=f90
+ 72c: 00 00 04 00 nop.i 0x0
+ 730: 08 00 68 79 82 19 \[MMI\] stfe.d1 \[r60\]=f90
+ 736: 00 d0 f2 04 33 00 stfe.d1 \[r60\]=f90
+ 73c: 00 00 04 00 nop.i 0x0
+ 740: 08 00 68 79 84 19 \[MMI\] stfe.d2 \[r60\]=f90
+ 746: 00 d0 f2 08 33 00 stfe.d2 \[r60\]=f90
+ 74c: 00 00 04 00 nop.i 0x0
+ 750: 08 00 68 79 86 19 \[MMI\] stfe.nta \[r60\]=f90
+ 756: 00 d0 f2 0c 33 00 stfe.nta \[r60\]=f90
+ 75c: 00 00 04 00 nop.i 0x0
+ 760: 08 00 6a 79 80 19 \[MMI\] stfe.d4 \[r60\]=f90
+ 766: 00 d4 f2 04 33 00 stfe.d5 \[r60\]=f90
+ 76c: 00 00 04 00 nop.i 0x0
+ 770: 08 00 6a 79 84 19 \[MMI\] stfe.d6 \[r60\]=f90
+ 776: 00 d4 f2 0c 33 00 stfe.d7 \[r60\]=f90
+ 77c: 00 00 04 00 nop.i 0x0
+ 780: 08 00 68 79 d8 19 \[MMI\] stf.spill \[r60\]=f90
+ 786: 00 d0 f2 b4 33 00 stf.spill.d1 \[r60\]=f90
+ 78c: 00 00 04 00 nop.i 0x0
+ 790: 08 00 68 79 da 19 \[MMI\] stf.spill.d1 \[r60\]=f90
+ 796: 00 d0 f2 b8 33 00 stf.spill.d2 \[r60\]=f90
+ 79c: 00 00 04 00 nop.i 0x0
+ 7a0: 08 00 68 79 dc 19 \[MMI\] stf.spill.d2 \[r60\]=f90
+ 7a6: 00 d0 f2 bc 33 00 stf.spill.nta \[r60\]=f90
+ 7ac: 00 00 04 00 nop.i 0x0
+ 7b0: 08 00 68 79 de 19 \[MMI\] stf.spill.nta \[r60\]=f90
+ 7b6: 00 d4 f2 b0 33 00 stf.spill.d4 \[r60\]=f90
+ 7bc: 00 00 04 00 nop.i 0x0
+ 7c0: 08 00 6a 79 da 19 \[MMI\] stf.spill.d5 \[r60\]=f90
+ 7c6: 00 d4 f2 b8 33 00 stf.spill.d6 \[r60\]=f90
+ 7cc: 00 00 04 00 nop.i 0x0
+ 7d0: 08 00 6a 79 de 19 \[MMI\] stf.spill.d7 \[r60\]=f90
+ 7d6: 90 07 f4 21 30 00 ldfs f121=\[r125\]
+ 7dc: 00 00 04 00 nop.i 0x0
+ 7e0: 08 c8 03 fa 12 18 \[MMI\] ldfs.nt1 f121=\[r125\]
+ 7e6: 90 07 f4 25 30 00 ldfs.nt1 f121=\[r125\]
+ 7ec: 00 00 04 00 nop.i 0x0
+ 7f0: 08 c8 03 fa 14 18 \[MMI\] ldfs.d2 f121=\[r125\]
+ 7f6: 90 07 f4 29 30 00 ldfs.d2 f121=\[r125\]
+ 7fc: 00 00 04 00 nop.i 0x0
+ 800: 08 c8 03 fa 16 18 \[MMI\] ldfs.nta f121=\[r125\]
+ 806: 90 07 f4 2d 30 00 ldfs.nta f121=\[r125\]
+ 80c: 00 00 04 00 nop.i 0x0
+ 810: 08 c8 03 fb 10 18 \[MMI\] ldfs.d4 f121=\[r125\]
+ 816: 90 07 f6 25 30 00 ldfs.d5 f121=\[r125\]
+ 81c: 00 00 04 00 nop.i 0x0
+ 820: 08 c8 03 fb 14 18 \[MMI\] ldfs.d6 f121=\[r125\]
+ 826: 90 07 f6 2d 30 00 ldfs.d7 f121=\[r125\]
+ 82c: 00 00 04 00 nop.i 0x0
+ 830: 08 c8 03 fa 18 18 \[MMI\] ldfd f121=\[r125\]
+ 836: 90 07 f4 35 30 00 ldfd.nt1 f121=\[r125\]
+ 83c: 00 00 04 00 nop.i 0x0
+ 840: 08 c8 03 fa 1a 18 \[MMI\] ldfd.nt1 f121=\[r125\]
+ 846: 90 07 f4 39 30 00 ldfd.d2 f121=\[r125\]
+ 84c: 00 00 04 00 nop.i 0x0
+ 850: 08 c8 03 fa 1c 18 \[MMI\] ldfd.d2 f121=\[r125\]
+ 856: 90 07 f4 3d 30 00 ldfd.nta f121=\[r125\]
+ 85c: 00 00 04 00 nop.i 0x0
+ 860: 08 c8 03 fa 1e 18 \[MMI\] ldfd.nta f121=\[r125\]
+ 866: 90 07 f6 31 30 00 ldfd.d4 f121=\[r125\]
+ 86c: 00 00 04 00 nop.i 0x0
+ 870: 08 c8 03 fb 1a 18 \[MMI\] ldfd.d5 f121=\[r125\]
+ 876: 90 07 f6 39 30 00 ldfd.d6 f121=\[r125\]
+ 87c: 00 00 04 00 nop.i 0x0
+ 880: 08 c8 03 fb 1e 18 \[MMI\] ldfd.d7 f121=\[r125\]
+ 886: 90 07 f4 11 30 00 ldf8 f121=\[r125\]
+ 88c: 00 00 04 00 nop.i 0x0
+ 890: 08 c8 03 fa 0a 18 \[MMI\] ldf8.nt1 f121=\[r125\]
+ 896: 90 07 f4 15 30 00 ldf8.nt1 f121=\[r125\]
+ 89c: 00 00 04 00 nop.i 0x0
+ 8a0: 08 c8 03 fa 0c 18 \[MMI\] ldf8.d2 f121=\[r125\]
+ 8a6: 90 07 f4 19 30 00 ldf8.d2 f121=\[r125\]
+ 8ac: 00 00 04 00 nop.i 0x0
+ 8b0: 08 c8 03 fa 0e 18 \[MMI\] ldf8.nta f121=\[r125\]
+ 8b6: 90 07 f4 1d 30 00 ldf8.nta f121=\[r125\]
+ 8bc: 00 00 04 00 nop.i 0x0
+ 8c0: 08 c8 03 fb 08 18 \[MMI\] ldf8.d4 f121=\[r125\]
+ 8c6: 90 07 f6 15 30 00 ldf8.d5 f121=\[r125\]
+ 8cc: 00 00 04 00 nop.i 0x0
+ 8d0: 08 c8 03 fb 0c 18 \[MMI\] ldf8.d6 f121=\[r125\]
+ 8d6: 90 07 f6 1d 30 00 ldf8.d7 f121=\[r125\]
+ 8dc: 00 00 04 00 nop.i 0x0
+ 8e0: 08 c8 03 fa 00 18 \[MMI\] ldfe f121=\[r125\]
+ 8e6: 90 07 f4 05 30 00 ldfe.nt1 f121=\[r125\]
+ 8ec: 00 00 04 00 nop.i 0x0
+ 8f0: 08 c8 03 fa 02 18 \[MMI\] ldfe.nt1 f121=\[r125\]
+ 8f6: 90 07 f4 09 30 00 ldfe.d2 f121=\[r125\]
+ 8fc: 00 00 04 00 nop.i 0x0
+ 900: 08 c8 03 fa 04 18 \[MMI\] ldfe.d2 f121=\[r125\]
+ 906: 90 07 f4 0d 30 00 ldfe.nta f121=\[r125\]
+ 90c: 00 00 04 00 nop.i 0x0
+ 910: 08 c8 03 fa 06 18 \[MMI\] ldfe.nta f121=\[r125\]
+ 916: 90 07 f6 01 30 00 ldfe.d4 f121=\[r125\]
+ 91c: 00 00 04 00 nop.i 0x0
+ 920: 08 c8 03 fb 02 18 \[MMI\] ldfe.d5 f121=\[r125\]
+ 926: 90 07 f6 09 30 00 ldfe.d6 f121=\[r125\]
+ 92c: 00 00 04 00 nop.i 0x0
+ 930: 08 c8 03 fb 06 18 \[MMI\] ldfe.d7 f121=\[r125\]
+ 936: 90 07 f4 61 30 00 ldfs.s f121=\[r125\]
+ 93c: 00 00 04 00 nop.i 0x0
+ 940: 08 c8 03 fa 32 18 \[MMI\] ldfs.s.nt1 f121=\[r125\]
+ 946: 90 07 f4 65 30 00 ldfs.s.nt1 f121=\[r125\]
+ 94c: 00 00 04 00 nop.i 0x0
+ 950: 08 c8 03 fa 34 18 \[MMI\] ldfs.s.d2 f121=\[r125\]
+ 956: 90 07 f4 69 30 00 ldfs.s.d2 f121=\[r125\]
+ 95c: 00 00 04 00 nop.i 0x0
+ 960: 08 c8 03 fa 36 18 \[MMI\] ldfs.s.nta f121=\[r125\]
+ 966: 90 07 f4 6d 30 00 ldfs.s.nta f121=\[r125\]
+ 96c: 00 00 04 00 nop.i 0x0
+ 970: 08 c8 03 fb 30 18 \[MMI\] ldfs.s.d4 f121=\[r125\]
+ 976: 90 07 f6 65 30 00 ldfs.s.d5 f121=\[r125\]
+ 97c: 00 00 04 00 nop.i 0x0
+ 980: 08 c8 03 fb 34 18 \[MMI\] ldfs.s.d6 f121=\[r125\]
+ 986: 90 07 f6 6d 30 00 ldfs.s.d7 f121=\[r125\]
+ 98c: 00 00 04 00 nop.i 0x0
+ 990: 08 c8 03 fa 38 18 \[MMI\] ldfd.s f121=\[r125\]
+ 996: 90 07 f4 75 30 00 ldfd.s.nt1 f121=\[r125\]
+ 99c: 00 00 04 00 nop.i 0x0
+ 9a0: 08 c8 03 fa 3a 18 \[MMI\] ldfd.s.nt1 f121=\[r125\]
+ 9a6: 90 07 f4 79 30 00 ldfd.s.d2 f121=\[r125\]
+ 9ac: 00 00 04 00 nop.i 0x0
+ 9b0: 08 c8 03 fa 3c 18 \[MMI\] ldfd.s.d2 f121=\[r125\]
+ 9b6: 90 07 f4 7d 30 00 ldfd.s.nta f121=\[r125\]
+ 9bc: 00 00 04 00 nop.i 0x0
+ 9c0: 08 c8 03 fa 3e 18 \[MMI\] ldfd.s.nta f121=\[r125\]
+ 9c6: 90 07 f6 71 30 00 ldfd.s.d4 f121=\[r125\]
+ 9cc: 00 00 04 00 nop.i 0x0
+ 9d0: 08 c8 03 fb 3a 18 \[MMI\] ldfd.s.d5 f121=\[r125\]
+ 9d6: 90 07 f6 79 30 00 ldfd.s.d6 f121=\[r125\]
+ 9dc: 00 00 04 00 nop.i 0x0
+ 9e0: 08 c8 03 fb 3e 18 \[MMI\] ldfd.s.d7 f121=\[r125\]
+ 9e6: 90 07 f4 51 30 00 ldf8.s f121=\[r125\]
+ 9ec: 00 00 04 00 nop.i 0x0
+ 9f0: 08 c8 03 fa 2a 18 \[MMI\] ldf8.s.nt1 f121=\[r125\]
+ 9f6: 90 07 f4 55 30 00 ldf8.s.nt1 f121=\[r125\]
+ 9fc: 00 00 04 00 nop.i 0x0
+ a00: 08 c8 03 fa 2c 18 \[MMI\] ldf8.s.d2 f121=\[r125\]
+ a06: 90 07 f4 59 30 00 ldf8.s.d2 f121=\[r125\]
+ a0c: 00 00 04 00 nop.i 0x0
+ a10: 08 c8 03 fa 2e 18 \[MMI\] ldf8.s.nta f121=\[r125\]
+ a16: 90 07 f4 5d 30 00 ldf8.s.nta f121=\[r125\]
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+ a30: 08 c8 03 fb 2c 18 \[MMI\] ldf8.s.d6 f121=\[r125\]
+ a36: 90 07 f6 5d 30 00 ldf8.s.d7 f121=\[r125\]
+ a3c: 00 00 04 00 nop.i 0x0
+ a40: 08 c8 03 fa 20 18 \[MMI\] ldfe.s f121=\[r125\]
+ a46: 90 07 f4 45 30 00 ldfe.s.nt1 f121=\[r125\]
+ a4c: 00 00 04 00 nop.i 0x0
+ a50: 08 c8 03 fa 22 18 \[MMI\] ldfe.s.nt1 f121=\[r125\]
+ a56: 90 07 f4 49 30 00 ldfe.s.d2 f121=\[r125\]
+ a5c: 00 00 04 00 nop.i 0x0
+ a60: 08 c8 03 fa 24 18 \[MMI\] ldfe.s.d2 f121=\[r125\]
+ a66: 90 07 f4 4d 30 00 ldfe.s.nta f121=\[r125\]
+ a6c: 00 00 04 00 nop.i 0x0
+ a70: 08 c8 03 fa 26 18 \[MMI\] ldfe.s.nta f121=\[r125\]
+ a76: 90 07 f6 41 30 00 ldfe.s.d4 f121=\[r125\]
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+ a80: 08 c8 03 fb 22 18 \[MMI\] ldfe.s.d5 f121=\[r125\]
+ a86: 90 07 f6 49 30 00 ldfe.s.d6 f121=\[r125\]
+ a8c: 00 00 04 00 nop.i 0x0
+ a90: 08 c8 03 fb 26 18 \[MMI\] ldfe.s.d7 f121=\[r125\]
+ a96: 90 07 f4 a1 30 00 ldfs.a f121=\[r125\]
+ a9c: 00 00 04 00 nop.i 0x0
+ aa0: 08 c8 03 fa 52 18 \[MMI\] ldfs.a.nt1 f121=\[r125\]
+ aa6: 90 07 f4 a5 30 00 ldfs.a.nt1 f121=\[r125\]
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+ ab0: 08 c8 03 fa 54 18 \[MMI\] ldfs.a.d2 f121=\[r125\]
+ ab6: 90 07 f4 a9 30 00 ldfs.a.d2 f121=\[r125\]
+ abc: 00 00 04 00 nop.i 0x0
+ ac0: 08 c8 03 fa 56 18 \[MMI\] ldfs.a.nta f121=\[r125\]
+ ac6: 90 07 f4 ad 30 00 ldfs.a.nta f121=\[r125\]
+ acc: 00 00 04 00 nop.i 0x0
+ ad0: 08 c8 03 fb 50 18 \[MMI\] ldfs.a.d4 f121=\[r125\]
+ ad6: 90 07 f6 a5 30 00 ldfs.a.d5 f121=\[r125\]
+ adc: 00 00 04 00 nop.i 0x0
+ ae0: 08 c8 03 fb 54 18 \[MMI\] ldfs.a.d6 f121=\[r125\]
+ ae6: 90 07 f6 ad 30 00 ldfs.a.d7 f121=\[r125\]
+ aec: 00 00 04 00 nop.i 0x0
+ af0: 08 c8 03 fa 58 18 \[MMI\] ldfd.a f121=\[r125\]
+ af6: 90 07 f4 b5 30 00 ldfd.a.nt1 f121=\[r125\]
+ afc: 00 00 04 00 nop.i 0x0
+ b00: 08 c8 03 fa 5a 18 \[MMI\] ldfd.a.nt1 f121=\[r125\]
+ b06: 90 07 f4 b9 30 00 ldfd.a.d2 f121=\[r125\]
+ b0c: 00 00 04 00 nop.i 0x0
+ b10: 08 c8 03 fa 5c 18 \[MMI\] ldfd.a.d2 f121=\[r125\]
+ b16: 90 07 f4 bd 30 00 ldfd.a.nta f121=\[r125\]
+ b1c: 00 00 04 00 nop.i 0x0
+ b20: 08 c8 03 fa 5e 18 \[MMI\] ldfd.a.nta f121=\[r125\]
+ b26: 90 07 f6 b1 30 00 ldfd.a.d4 f121=\[r125\]
+ b2c: 00 00 04 00 nop.i 0x0
+ b30: 08 c8 03 fb 5a 18 \[MMI\] ldfd.a.d5 f121=\[r125\]
+ b36: 90 07 f6 b9 30 00 ldfd.a.d6 f121=\[r125\]
+ b3c: 00 00 04 00 nop.i 0x0
+ b40: 08 c8 03 fb 5e 18 \[MMI\] ldfd.a.d7 f121=\[r125\]
+ b46: 90 07 f4 91 30 00 ldf8.a f121=\[r125\]
+ b4c: 00 00 04 00 nop.i 0x0
+ b50: 08 c8 03 fa 4a 18 \[MMI\] ldf8.a.nt1 f121=\[r125\]
+ b56: 90 07 f4 95 30 00 ldf8.a.nt1 f121=\[r125\]
+ b5c: 00 00 04 00 nop.i 0x0
+ b60: 08 c8 03 fa 4c 18 \[MMI\] ldf8.a.d2 f121=\[r125\]
+ b66: 90 07 f4 99 30 00 ldf8.a.d2 f121=\[r125\]
+ b6c: 00 00 04 00 nop.i 0x0
+ b70: 08 c8 03 fa 4e 18 \[MMI\] ldf8.a.nta f121=\[r125\]
+ b76: 90 07 f4 9d 30 00 ldf8.a.nta f121=\[r125\]
+ b7c: 00 00 04 00 nop.i 0x0
+ b80: 08 c8 03 fb 48 18 \[MMI\] ldf8.a.d4 f121=\[r125\]
+ b86: 90 07 f6 95 30 00 ldf8.a.d5 f121=\[r125\]
+ b8c: 00 00 04 00 nop.i 0x0
+ b90: 08 c8 03 fb 4c 18 \[MMI\] ldf8.a.d6 f121=\[r125\]
+ b96: 90 07 f6 9d 30 00 ldf8.a.d7 f121=\[r125\]
+ b9c: 00 00 04 00 nop.i 0x0
+ ba0: 08 c8 03 fa 40 18 \[MMI\] ldfe.a f121=\[r125\]
+ ba6: 90 07 f4 85 30 00 ldfe.a.nt1 f121=\[r125\]
+ bac: 00 00 04 00 nop.i 0x0
+ bb0: 08 c8 03 fa 42 18 \[MMI\] ldfe.a.nt1 f121=\[r125\]
+ bb6: 90 07 f4 89 30 00 ldfe.a.d2 f121=\[r125\]
+ bbc: 00 00 04 00 nop.i 0x0
+ bc0: 08 c8 03 fa 44 18 \[MMI\] ldfe.a.d2 f121=\[r125\]
+ bc6: 90 07 f4 8d 30 00 ldfe.a.nta f121=\[r125\]
+ bcc: 00 00 04 00 nop.i 0x0
+ bd0: 08 c8 03 fa 46 18 \[MMI\] ldfe.a.nta f121=\[r125\]
+ bd6: 90 07 f6 81 30 00 ldfe.a.d4 f121=\[r125\]
+ bdc: 00 00 04 00 nop.i 0x0
+ be0: 08 c8 03 fb 42 18 \[MMI\] ldfe.a.d5 f121=\[r125\]
+ be6: 90 07 f6 89 30 00 ldfe.a.d6 f121=\[r125\]
+ bec: 00 00 04 00 nop.i 0x0
+ bf0: 08 c8 03 fb 46 18 \[MMI\] ldfe.a.d7 f121=\[r125\]
+ bf6: 90 07 f4 e1 30 00 ldfs.sa f121=\[r125\]
+ bfc: 00 00 04 00 nop.i 0x0
+ c00: 08 c8 03 fa 72 18 \[MMI\] ldfs.sa.nt1 f121=\[r125\]
+ c06: 90 07 f4 e5 30 00 ldfs.sa.nt1 f121=\[r125\]
+ c0c: 00 00 04 00 nop.i 0x0
+ c10: 08 c8 03 fa 74 18 \[MMI\] ldfs.sa.d2 f121=\[r125\]
+ c16: 90 07 f4 e9 30 00 ldfs.sa.d2 f121=\[r125\]
+ c1c: 00 00 04 00 nop.i 0x0
+ c20: 08 c8 03 fa 76 18 \[MMI\] ldfs.sa.nta f121=\[r125\]
+ c26: 90 07 f4 ed 30 00 ldfs.sa.nta f121=\[r125\]
+ c2c: 00 00 04 00 nop.i 0x0
+ c30: 08 c8 03 fb 70 18 \[MMI\] ldfs.sa.d4 f121=\[r125\]
+ c36: 90 07 f6 e5 30 00 ldfs.sa.d5 f121=\[r125\]
+ c3c: 00 00 04 00 nop.i 0x0
+ c40: 08 c8 03 fb 74 18 \[MMI\] ldfs.sa.d6 f121=\[r125\]
+ c46: 90 07 f6 ed 30 00 ldfs.sa.d7 f121=\[r125\]
+ c4c: 00 00 04 00 nop.i 0x0
+ c50: 08 c8 03 fa 78 18 \[MMI\] ldfd.sa f121=\[r125\]
+ c56: 90 07 f4 f5 30 00 ldfd.sa.nt1 f121=\[r125\]
+ c5c: 00 00 04 00 nop.i 0x0
+ c60: 08 c8 03 fa 7a 18 \[MMI\] ldfd.sa.nt1 f121=\[r125\]
+ c66: 90 07 f4 f9 30 00 ldfd.sa.d2 f121=\[r125\]
+ c6c: 00 00 04 00 nop.i 0x0
+ c70: 08 c8 03 fa 7c 18 \[MMI\] ldfd.sa.d2 f121=\[r125\]
+ c76: 90 07 f4 fd 30 00 ldfd.sa.nta f121=\[r125\]
+ c7c: 00 00 04 00 nop.i 0x0
+ c80: 08 c8 03 fa 7e 18 \[MMI\] ldfd.sa.nta f121=\[r125\]
+ c86: 90 07 f6 f1 30 00 ldfd.sa.d4 f121=\[r125\]
+ c8c: 00 00 04 00 nop.i 0x0
+ c90: 08 c8 03 fb 7a 18 \[MMI\] ldfd.sa.d5 f121=\[r125\]
+ c96: 90 07 f6 f9 30 00 ldfd.sa.d6 f121=\[r125\]
+ c9c: 00 00 04 00 nop.i 0x0
+ ca0: 08 c8 03 fb 7e 18 \[MMI\] ldfd.sa.d7 f121=\[r125\]
+ ca6: 90 07 f4 d1 30 00 ldf8.sa f121=\[r125\]
+ cac: 00 00 04 00 nop.i 0x0
+ cb0: 08 c8 03 fa 6a 18 \[MMI\] ldf8.sa.nt1 f121=\[r125\]
+ cb6: 90 07 f4 d5 30 00 ldf8.sa.nt1 f121=\[r125\]
+ cbc: 00 00 04 00 nop.i 0x0
+ cc0: 08 c8 03 fa 6c 18 \[MMI\] ldf8.sa.d2 f121=\[r125\]
+ cc6: 90 07 f4 d9 30 00 ldf8.sa.d2 f121=\[r125\]
+ ccc: 00 00 04 00 nop.i 0x0
+ cd0: 08 c8 03 fa 6e 18 \[MMI\] ldf8.sa.nta f121=\[r125\]
+ cd6: 90 07 f4 dd 30 00 ldf8.sa.nta f121=\[r125\]
+ cdc: 00 00 04 00 nop.i 0x0
+ ce0: 08 c8 03 fb 68 18 \[MMI\] ldf8.sa.d4 f121=\[r125\]
+ ce6: 90 07 f6 d5 30 00 ldf8.sa.d5 f121=\[r125\]
+ cec: 00 00 04 00 nop.i 0x0
+ cf0: 08 c8 03 fb 6c 18 \[MMI\] ldf8.sa.d6 f121=\[r125\]
+ cf6: 90 07 f6 dd 30 00 ldf8.sa.d7 f121=\[r125\]
+ cfc: 00 00 04 00 nop.i 0x0
+ d00: 08 c8 03 fa 60 18 \[MMI\] ldfe.sa f121=\[r125\]
+ d06: 90 07 f4 c5 30 00 ldfe.sa.nt1 f121=\[r125\]
+ d0c: 00 00 04 00 nop.i 0x0
+ d10: 08 c8 03 fa 62 18 \[MMI\] ldfe.sa.nt1 f121=\[r125\]
+ d16: 90 07 f4 c9 30 00 ldfe.sa.d2 f121=\[r125\]
+ d1c: 00 00 04 00 nop.i 0x0
+ d20: 08 c8 03 fa 64 18 \[MMI\] ldfe.sa.d2 f121=\[r125\]
+ d26: 90 07 f4 cd 30 00 ldfe.sa.nta f121=\[r125\]
+ d2c: 00 00 04 00 nop.i 0x0
+ d30: 08 c8 03 fa 66 18 \[MMI\] ldfe.sa.nta f121=\[r125\]
+ d36: 90 07 f6 c1 30 00 ldfe.sa.d4 f121=\[r125\]
+ d3c: 00 00 04 00 nop.i 0x0
+ d40: 08 c8 03 fb 62 18 \[MMI\] ldfe.sa.d5 f121=\[r125\]
+ d46: 90 07 f6 c9 30 00 ldfe.sa.d6 f121=\[r125\]
+ d4c: 00 00 04 00 nop.i 0x0
+ d50: 08 c8 03 fb 66 18 \[MMI\] ldfe.sa.d7 f121=\[r125\]
+ d56: 90 07 f4 b1 31 00 ldf.fill f121=\[r125\]
+ d5c: 00 00 04 00 nop.i 0x0
+ d60: 08 c8 03 fa da 18 \[MMI\] ldf.fill.nt1 f121=\[r125\]
+ d66: 90 07 f4 b5 31 00 ldf.fill.nt1 f121=\[r125\]
+ d6c: 00 00 04 00 nop.i 0x0
+ d70: 08 c8 03 fa dc 18 \[MMI\] ldf.fill.d2 f121=\[r125\]
+ d76: 90 07 f4 b9 31 00 ldf.fill.d2 f121=\[r125\]
+ d7c: 00 00 04 00 nop.i 0x0
+ d80: 08 c8 03 fa de 18 \[MMI\] ldf.fill.nta f121=\[r125\]
+ d86: 90 07 f4 bd 31 00 ldf.fill.nta f121=\[r125\]
+ d8c: 00 00 04 00 nop.i 0x0
+ d90: 08 c8 03 fb d8 18 \[MMI\] ldf.fill.d4 f121=\[r125\]
+ d96: 90 07 f6 b5 31 00 ldf.fill.d5 f121=\[r125\]
+ d9c: 00 00 04 00 nop.i 0x0
+ da0: 08 c8 03 fb dc 18 \[MMI\] ldf.fill.d6 f121=\[r125\]
+ da6: 90 07 f6 bd 31 00 ldf.fill.d7 f121=\[r125\]
+ dac: 00 00 04 00 nop.i 0x0
+ db0: 08 c8 03 fa 10 19 \[MMI\] ldfs.c.clr f121=\[r125\]
+ db6: 90 07 f4 25 32 00 ldfs.c.clr.nt1 f121=\[r125\]
+ dbc: 00 00 04 00 nop.i 0x0
+ dc0: 08 c8 03 fa 12 19 \[MMI\] ldfs.c.clr.nt1 f121=\[r125\]
+ dc6: 90 07 f4 29 32 00 ldfs.c.clr.d2 f121=\[r125\]
+ dcc: 00 00 04 00 nop.i 0x0
+ dd0: 08 c8 03 fa 14 19 \[MMI\] ldfs.c.clr.d2 f121=\[r125\]
+ dd6: 90 07 f4 2d 32 00 ldfs.c.clr.nta f121=\[r125\]
+ ddc: 00 00 04 00 nop.i 0x0
+ de0: 08 c8 03 fa 16 19 \[MMI\] ldfs.c.clr.nta f121=\[r125\]
+ de6: 90 07 f6 21 32 00 ldfs.c.clr.d4 f121=\[r125\]
+ dec: 00 00 04 00 nop.i 0x0
+ df0: 08 c8 03 fb 12 19 \[MMI\] ldfs.c.clr.d5 f121=\[r125\]
+ df6: 90 07 f6 29 32 00 ldfs.c.clr.d6 f121=\[r125\]
+ dfc: 00 00 04 00 nop.i 0x0
+ e00: 08 c8 03 fb 16 19 \[MMI\] ldfs.c.clr.d7 f121=\[r125\]
+ e06: 90 07 f4 31 32 00 ldfd.c.clr f121=\[r125\]
+ e0c: 00 00 04 00 nop.i 0x0
+ e10: 08 c8 03 fa 1a 19 \[MMI\] ldfd.c.clr.nt1 f121=\[r125\]
+ e16: 90 07 f4 35 32 00 ldfd.c.clr.nt1 f121=\[r125\]
+ e1c: 00 00 04 00 nop.i 0x0
+ e20: 08 c8 03 fa 1c 19 \[MMI\] ldfd.c.clr.d2 f121=\[r125\]
+ e26: 90 07 f4 39 32 00 ldfd.c.clr.d2 f121=\[r125\]
+ e2c: 00 00 04 00 nop.i 0x0
+ e30: 08 c8 03 fa 1e 19 \[MMI\] ldfd.c.clr.nta f121=\[r125\]
+ e36: 90 07 f4 3d 32 00 ldfd.c.clr.nta f121=\[r125\]
+ e3c: 00 00 04 00 nop.i 0x0
+ e40: 08 c8 03 fb 18 19 \[MMI\] ldfd.c.clr.d4 f121=\[r125\]
+ e46: 90 07 f6 35 32 00 ldfd.c.clr.d5 f121=\[r125\]
+ e4c: 00 00 04 00 nop.i 0x0
+ e50: 08 c8 03 fb 1c 19 \[MMI\] ldfd.c.clr.d6 f121=\[r125\]
+ e56: 90 07 f6 3d 32 00 ldfd.c.clr.d7 f121=\[r125\]
+ e5c: 00 00 04 00 nop.i 0x0
+ e60: 08 c8 03 fa 08 19 \[MMI\] ldf8.c.clr f121=\[r125\]
+ e66: 90 07 f4 15 32 00 ldf8.c.clr.nt1 f121=\[r125\]
+ e6c: 00 00 04 00 nop.i 0x0
+ e70: 08 c8 03 fa 0a 19 \[MMI\] ldf8.c.clr.nt1 f121=\[r125\]
+ e76: 90 07 f4 19 32 00 ldf8.c.clr.d2 f121=\[r125\]
+ e7c: 00 00 04 00 nop.i 0x0
+ e80: 08 c8 03 fa 0c 19 \[MMI\] ldf8.c.clr.d2 f121=\[r125\]
+ e86: 90 07 f4 1d 32 00 ldf8.c.clr.nta f121=\[r125\]
+ e8c: 00 00 04 00 nop.i 0x0
+ e90: 08 c8 03 fa 0e 19 \[MMI\] ldf8.c.clr.nta f121=\[r125\]
+ e96: 90 07 f6 11 32 00 ldf8.c.clr.d4 f121=\[r125\]
+ e9c: 00 00 04 00 nop.i 0x0
+ ea0: 08 c8 03 fb 0a 19 \[MMI\] ldf8.c.clr.d5 f121=\[r125\]
+ ea6: 90 07 f6 19 32 00 ldf8.c.clr.d6 f121=\[r125\]
+ eac: 00 00 04 00 nop.i 0x0
+ eb0: 08 c8 03 fb 0e 19 \[MMI\] ldf8.c.clr.d7 f121=\[r125\]
+ eb6: 90 07 f4 01 32 00 ldfe.c.clr f121=\[r125\]
+ ebc: 00 00 04 00 nop.i 0x0
+ ec0: 08 c8 03 fa 02 19 \[MMI\] ldfe.c.clr.nt1 f121=\[r125\]
+ ec6: 90 07 f4 05 32 00 ldfe.c.clr.nt1 f121=\[r125\]
+ ecc: 00 00 04 00 nop.i 0x0
+ ed0: 08 c8 03 fa 04 19 \[MMI\] ldfe.c.clr.d2 f121=\[r125\]
+ ed6: 90 07 f4 09 32 00 ldfe.c.clr.d2 f121=\[r125\]
+ edc: 00 00 04 00 nop.i 0x0
+ ee0: 08 c8 03 fa 06 19 \[MMI\] ldfe.c.clr.nta f121=\[r125\]
+ ee6: 90 07 f4 0d 32 00 ldfe.c.clr.nta f121=\[r125\]
+ eec: 00 00 04 00 nop.i 0x0
+ ef0: 08 c8 03 fb 00 19 \[MMI\] ldfe.c.clr.d4 f121=\[r125\]
+ ef6: 90 07 f6 05 32 00 ldfe.c.clr.d5 f121=\[r125\]
+ efc: 00 00 04 00 nop.i 0x0
+ f00: 08 c8 03 fb 04 19 \[MMI\] ldfe.c.clr.d6 f121=\[r125\]
+ f06: 90 07 f6 0d 32 00 ldfe.c.clr.d7 f121=\[r125\]
+ f0c: 00 00 04 00 nop.i 0x0
+ f10: 08 c8 03 fa 30 19 \[MMI\] ldfs.c.nc f121=\[r125\]
+ f16: 90 07 f4 65 32 00 ldfs.c.nc.nt1 f121=\[r125\]
+ f1c: 00 00 04 00 nop.i 0x0
+ f20: 08 c8 03 fa 32 19 \[MMI\] ldfs.c.nc.nt1 f121=\[r125\]
+ f26: 90 07 f4 69 32 00 ldfs.c.nc.d2 f121=\[r125\]
+ f2c: 00 00 04 00 nop.i 0x0
+ f30: 08 c8 03 fa 34 19 \[MMI\] ldfs.c.nc.d2 f121=\[r125\]
+ f36: 90 07 f4 6d 32 00 ldfs.c.nc.nta f121=\[r125\]
+ f3c: 00 00 04 00 nop.i 0x0
+ f40: 08 c8 03 fa 36 19 \[MMI\] ldfs.c.nc.nta f121=\[r125\]
+ f46: 90 07 f6 61 32 00 ldfs.c.nc.d4 f121=\[r125\]
+ f4c: 00 00 04 00 nop.i 0x0
+ f50: 08 c8 03 fb 32 19 \[MMI\] ldfs.c.nc.d5 f121=\[r125\]
+ f56: 90 07 f6 69 32 00 ldfs.c.nc.d6 f121=\[r125\]
+ f5c: 00 00 04 00 nop.i 0x0
+ f60: 08 c8 03 fb 36 19 \[MMI\] ldfs.c.nc.d7 f121=\[r125\]
+ f66: 90 07 f4 71 32 00 ldfd.c.nc f121=\[r125\]
+ f6c: 00 00 04 00 nop.i 0x0
+ f70: 08 c8 03 fa 3a 19 \[MMI\] ldfd.c.nc.nt1 f121=\[r125\]
+ f76: 90 07 f4 75 32 00 ldfd.c.nc.nt1 f121=\[r125\]
+ f7c: 00 00 04 00 nop.i 0x0
+ f80: 08 c8 03 fa 3c 19 \[MMI\] ldfd.c.nc.d2 f121=\[r125\]
+ f86: 90 07 f4 79 32 00 ldfd.c.nc.d2 f121=\[r125\]
+ f8c: 00 00 04 00 nop.i 0x0
+ f90: 08 c8 03 fa 3e 19 \[MMI\] ldfd.c.nc.nta f121=\[r125\]
+ f96: 90 07 f4 7d 32 00 ldfd.c.nc.nta f121=\[r125\]
+ f9c: 00 00 04 00 nop.i 0x0
+ fa0: 08 c8 03 fb 38 19 \[MMI\] ldfd.c.nc.d4 f121=\[r125\]
+ fa6: 90 07 f6 75 32 00 ldfd.c.nc.d5 f121=\[r125\]
+ fac: 00 00 04 00 nop.i 0x0
+ fb0: 08 c8 03 fb 3c 19 \[MMI\] ldfd.c.nc.d6 f121=\[r125\]
+ fb6: 90 07 f6 7d 32 00 ldfd.c.nc.d7 f121=\[r125\]
+ fbc: 00 00 04 00 nop.i 0x0
+ fc0: 08 c8 03 fa 28 19 \[MMI\] ldf8.c.nc f121=\[r125\]
+ fc6: 90 07 f4 55 32 00 ldf8.c.nc.nt1 f121=\[r125\]
+ fcc: 00 00 04 00 nop.i 0x0
+ fd0: 08 c8 03 fa 2a 19 \[MMI\] ldf8.c.nc.nt1 f121=\[r125\]
+ fd6: 90 07 f4 59 32 00 ldf8.c.nc.d2 f121=\[r125\]
+ fdc: 00 00 04 00 nop.i 0x0
+ fe0: 08 c8 03 fa 2c 19 \[MMI\] ldf8.c.nc.d2 f121=\[r125\]
+ fe6: 90 07 f4 5d 32 00 ldf8.c.nc.nta f121=\[r125\]
+ fec: 00 00 04 00 nop.i 0x0
+ ff0: 08 c8 03 fa 2e 19 \[MMI\] ldf8.c.nc.nta f121=\[r125\]
+ ff6: 90 07 f6 51 32 00 ldf8.c.nc.d4 f121=\[r125\]
+ ffc: 00 00 04 00 nop.i 0x0
+ 1000: 08 c8 03 fb 2a 19 \[MMI\] ldf8.c.nc.d5 f121=\[r125\]
+ 1006: 90 07 f6 59 32 00 ldf8.c.nc.d6 f121=\[r125\]
+ 100c: 00 00 04 00 nop.i 0x0
+ 1010: 08 c8 03 fb 2e 19 \[MMI\] ldf8.c.nc.d7 f121=\[r125\]
+ 1016: 90 07 f4 41 32 00 ldfe.c.nc f121=\[r125\]
+ 101c: 00 00 04 00 nop.i 0x0
+ 1020: 08 c8 03 fa 22 19 \[MMI\] ldfe.c.nc.nt1 f121=\[r125\]
+ 1026: 90 07 f4 45 32 00 ldfe.c.nc.nt1 f121=\[r125\]
+ 102c: 00 00 04 00 nop.i 0x0
+ 1030: 08 c8 03 fa 24 19 \[MMI\] ldfe.c.nc.d2 f121=\[r125\]
+ 1036: 90 07 f4 49 32 00 ldfe.c.nc.d2 f121=\[r125\]
+ 103c: 00 00 04 00 nop.i 0x0
+ 1040: 08 c8 03 fa 26 19 \[MMI\] ldfe.c.nc.nta f121=\[r125\]
+ 1046: 90 07 f4 4d 32 00 ldfe.c.nc.nta f121=\[r125\]
+ 104c: 00 00 04 00 nop.i 0x0
+ 1050: 08 c8 03 fb 20 19 \[MMI\] ldfe.c.nc.d4 f121=\[r125\]
+ 1056: 90 07 f6 45 32 00 ldfe.c.nc.d5 f121=\[r125\]
+ 105c: 00 00 04 00 nop.i 0x0
+ 1060: 08 c8 03 fb 24 19 \[MMI\] ldfe.c.nc.d6 f121=\[r125\]
+ 1066: 90 07 f6 4d 32 00 ldfe.c.nc.d7 f121=\[r125\]
+ 106c: 00 00 04 00 nop.i 0x0
+ 1070: 08 c0 03 28 00 10 \[MMI\] ld1 r120=\[r20\]
+ 1076: 80 07 50 04 20 00 ld1.nt1 r120=\[r20\]
+ 107c: 00 00 04 00 nop.i 0x0
+ 1080: 08 c0 03 28 02 10 \[MMI\] ld1.nt1 r120=\[r20\]
+ 1086: 80 07 50 08 20 00 ld1.d2 r120=\[r20\]
+ 108c: 00 00 04 00 nop.i 0x0
+ 1090: 08 c0 03 28 04 10 \[MMI\] ld1.d2 r120=\[r20\]
+ 1096: 80 07 50 0c 20 00 ld1.nta r120=\[r20\]
+ 109c: 00 00 04 00 nop.i 0x0
+ 10a0: 08 c0 03 28 06 10 \[MMI\] ld1.nta r120=\[r20\]
+ 10a6: 80 07 52 00 20 00 ld1.d4 r120=\[r20\]
+ 10ac: 00 00 04 00 nop.i 0x0
+ 10b0: 08 c0 03 29 02 10 \[MMI\] ld1.d5 r120=\[r20\]
+ 10b6: 80 07 52 08 20 00 ld1.d6 r120=\[r20\]
+ 10bc: 00 00 04 00 nop.i 0x0
+ 10c0: 08 c0 03 29 06 10 \[MMI\] ld1.d7 r120=\[r20\]
+ 10c6: 80 07 50 10 20 00 ld2 r120=\[r20\]
+ 10cc: 00 00 04 00 nop.i 0x0
+ 10d0: 08 c0 03 28 0a 10 \[MMI\] ld2.nt1 r120=\[r20\]
+ 10d6: 80 07 50 14 20 00 ld2.nt1 r120=\[r20\]
+ 10dc: 00 00 04 00 nop.i 0x0
+ 10e0: 08 c0 03 28 0c 10 \[MMI\] ld2.d2 r120=\[r20\]
+ 10e6: 80 07 50 18 20 00 ld2.d2 r120=\[r20\]
+ 10ec: 00 00 04 00 nop.i 0x0
+ 10f0: 08 c0 03 28 0e 10 \[MMI\] ld2.nta r120=\[r20\]
+ 10f6: 80 07 50 1c 20 00 ld2.nta r120=\[r20\]
+ 10fc: 00 00 04 00 nop.i 0x0
+ 1100: 08 c0 03 29 08 10 \[MMI\] ld2.d4 r120=\[r20\]
+ 1106: 80 07 52 14 20 00 ld2.d5 r120=\[r20\]
+ 110c: 00 00 04 00 nop.i 0x0
+ 1110: 08 c0 03 29 0c 10 \[MMI\] ld2.d6 r120=\[r20\]
+ 1116: 80 07 52 1c 20 00 ld2.d7 r120=\[r20\]
+ 111c: 00 00 04 00 nop.i 0x0
+ 1120: 08 c0 03 28 10 10 \[MMI\] ld4 r120=\[r20\]
+ 1126: 80 07 50 24 20 00 ld4.nt1 r120=\[r20\]
+ 112c: 00 00 04 00 nop.i 0x0
+ 1130: 08 c0 03 28 12 10 \[MMI\] ld4.nt1 r120=\[r20\]
+ 1136: 80 07 50 28 20 00 ld4.d2 r120=\[r20\]
+ 113c: 00 00 04 00 nop.i 0x0
+ 1140: 08 c0 03 28 14 10 \[MMI\] ld4.d2 r120=\[r20\]
+ 1146: 80 07 50 2c 20 00 ld4.nta r120=\[r20\]
+ 114c: 00 00 04 00 nop.i 0x0
+ 1150: 08 c0 03 28 16 10 \[MMI\] ld4.nta r120=\[r20\]
+ 1156: 80 07 52 20 20 00 ld4.d4 r120=\[r20\]
+ 115c: 00 00 04 00 nop.i 0x0
+ 1160: 08 c0 03 29 12 10 \[MMI\] ld4.d5 r120=\[r20\]
+ 1166: 80 07 52 28 20 00 ld4.d6 r120=\[r20\]
+ 116c: 00 00 04 00 nop.i 0x0
+ 1170: 08 c0 03 29 16 10 \[MMI\] ld4.d7 r120=\[r20\]
+ 1176: 80 07 50 30 20 00 ld8 r120=\[r20\]
+ 117c: 00 00 04 00 nop.i 0x0
+ 1180: 08 c0 03 28 1a 10 \[MMI\] ld8.nt1 r120=\[r20\]
+ 1186: 80 07 50 34 20 00 ld8.nt1 r120=\[r20\]
+ 118c: 00 00 04 00 nop.i 0x0
+ 1190: 08 c0 03 28 1c 10 \[MMI\] ld8.d2 r120=\[r20\]
+ 1196: 80 07 50 38 20 00 ld8.d2 r120=\[r20\]
+ 119c: 00 00 04 00 nop.i 0x0
+ 11a0: 08 c0 03 28 1e 10 \[MMI\] ld8.nta r120=\[r20\]
+ 11a6: 80 07 50 3c 20 00 ld8.nta r120=\[r20\]
+ 11ac: 00 00 04 00 nop.i 0x0
+ 11b0: 08 c0 03 29 18 10 \[MMI\] ld8.d4 r120=\[r20\]
+ 11b6: 80 07 52 34 20 00 ld8.d5 r120=\[r20\]
+ 11bc: 00 00 04 00 nop.i 0x0
+ 11c0: 08 c0 03 29 1c 10 \[MMI\] ld8.d6 r120=\[r20\]
+ 11c6: 80 07 52 3c 20 00 ld8.d7 r120=\[r20\]
+ 11cc: 00 00 04 00 nop.i 0x0
+ 11d0: 08 c0 03 28 20 10 \[MMI\] ld1.s r120=\[r20\]
+ 11d6: 80 07 50 44 20 00 ld1.s.nt1 r120=\[r20\]
+ 11dc: 00 00 04 00 nop.i 0x0
+ 11e0: 08 c0 03 28 22 10 \[MMI\] ld1.s.nt1 r120=\[r20\]
+ 11e6: 80 07 50 48 20 00 ld1.s.d2 r120=\[r20\]
+ 11ec: 00 00 04 00 nop.i 0x0
+ 11f0: 08 c0 03 28 24 10 \[MMI\] ld1.s.d2 r120=\[r20\]
+ 11f6: 80 07 50 4c 20 00 ld1.s.nta r120=\[r20\]
+ 11fc: 00 00 04 00 nop.i 0x0
+ 1200: 08 c0 03 28 26 10 \[MMI\] ld1.s.nta r120=\[r20\]
+ 1206: 80 07 52 40 20 00 ld1.s.d4 r120=\[r20\]
+ 120c: 00 00 04 00 nop.i 0x0
+ 1210: 08 c0 03 29 22 10 \[MMI\] ld1.s.d5 r120=\[r20\]
+ 1216: 80 07 52 48 20 00 ld1.s.d6 r120=\[r20\]
+ 121c: 00 00 04 00 nop.i 0x0
+ 1220: 08 c0 03 29 26 10 \[MMI\] ld1.s.d7 r120=\[r20\]
+ 1226: 80 07 50 50 20 00 ld2.s r120=\[r20\]
+ 122c: 00 00 04 00 nop.i 0x0
+ 1230: 08 c0 03 28 2a 10 \[MMI\] ld2.s.nt1 r120=\[r20\]
+ 1236: 80 07 50 54 20 00 ld2.s.nt1 r120=\[r20\]
+ 123c: 00 00 04 00 nop.i 0x0
+ 1240: 08 c0 03 28 2c 10 \[MMI\] ld2.s.d2 r120=\[r20\]
+ 1246: 80 07 50 58 20 00 ld2.s.d2 r120=\[r20\]
+ 124c: 00 00 04 00 nop.i 0x0
+ 1250: 08 c0 03 28 2e 10 \[MMI\] ld2.s.nta r120=\[r20\]
+ 1256: 80 07 50 5c 20 00 ld2.s.nta r120=\[r20\]
+ 125c: 00 00 04 00 nop.i 0x0
+ 1260: 08 c0 03 29 28 10 \[MMI\] ld2.s.d4 r120=\[r20\]
+ 1266: 80 07 52 54 20 00 ld2.s.d5 r120=\[r20\]
+ 126c: 00 00 04 00 nop.i 0x0
+ 1270: 08 c0 03 29 2c 10 \[MMI\] ld2.s.d6 r120=\[r20\]
+ 1276: 80 07 52 5c 20 00 ld2.s.d7 r120=\[r20\]
+ 127c: 00 00 04 00 nop.i 0x0
+ 1280: 08 c0 03 28 30 10 \[MMI\] ld4.s r120=\[r20\]
+ 1286: 80 07 50 64 20 00 ld4.s.nt1 r120=\[r20\]
+ 128c: 00 00 04 00 nop.i 0x0
+ 1290: 08 c0 03 28 32 10 \[MMI\] ld4.s.nt1 r120=\[r20\]
+ 1296: 80 07 50 68 20 00 ld4.s.d2 r120=\[r20\]
+ 129c: 00 00 04 00 nop.i 0x0
+ 12a0: 08 c0 03 28 34 10 \[MMI\] ld4.s.d2 r120=\[r20\]
+ 12a6: 80 07 50 6c 20 00 ld4.s.nta r120=\[r20\]
+ 12ac: 00 00 04 00 nop.i 0x0
+ 12b0: 08 c0 03 28 36 10 \[MMI\] ld4.s.nta r120=\[r20\]
+ 12b6: 80 07 52 60 20 00 ld4.s.d4 r120=\[r20\]
+ 12bc: 00 00 04 00 nop.i 0x0
+ 12c0: 08 c0 03 29 32 10 \[MMI\] ld4.s.d5 r120=\[r20\]
+ 12c6: 80 07 52 68 20 00 ld4.s.d6 r120=\[r20\]
+ 12cc: 00 00 04 00 nop.i 0x0
+ 12d0: 08 c0 03 29 36 10 \[MMI\] ld4.s.d7 r120=\[r20\]
+ 12d6: 80 07 50 70 20 00 ld8.s r120=\[r20\]
+ 12dc: 00 00 04 00 nop.i 0x0
+ 12e0: 08 c0 03 28 3a 10 \[MMI\] ld8.s.nt1 r120=\[r20\]
+ 12e6: 80 07 50 74 20 00 ld8.s.nt1 r120=\[r20\]
+ 12ec: 00 00 04 00 nop.i 0x0
+ 12f0: 08 c0 03 28 3c 10 \[MMI\] ld8.s.d2 r120=\[r20\]
+ 12f6: 80 07 50 78 20 00 ld8.s.d2 r120=\[r20\]
+ 12fc: 00 00 04 00 nop.i 0x0
+ 1300: 08 c0 03 28 3e 10 \[MMI\] ld8.s.nta r120=\[r20\]
+ 1306: 80 07 50 7c 20 00 ld8.s.nta r120=\[r20\]
+ 130c: 00 00 04 00 nop.i 0x0
+ 1310: 08 c0 03 29 38 10 \[MMI\] ld8.s.d4 r120=\[r20\]
+ 1316: 80 07 52 74 20 00 ld8.s.d5 r120=\[r20\]
+ 131c: 00 00 04 00 nop.i 0x0
+ 1320: 08 c0 03 29 3c 10 \[MMI\] ld8.s.d6 r120=\[r20\]
+ 1326: 80 07 52 7c 20 00 ld8.s.d7 r120=\[r20\]
+ 132c: 00 00 04 00 nop.i 0x0
+ 1330: 08 c0 03 28 40 10 \[MMI\] ld1.a r120=\[r20\]
+ 1336: 80 07 50 84 20 00 ld1.a.nt1 r120=\[r20\]
+ 133c: 00 00 04 00 nop.i 0x0
+ 1340: 08 c0 03 28 42 10 \[MMI\] ld1.a.nt1 r120=\[r20\]
+ 1346: 80 07 50 88 20 00 ld1.a.d2 r120=\[r20\]
+ 134c: 00 00 04 00 nop.i 0x0
+ 1350: 08 c0 03 28 44 10 \[MMI\] ld1.a.d2 r120=\[r20\]
+ 1356: 80 07 50 8c 20 00 ld1.a.nta r120=\[r20\]
+ 135c: 00 00 04 00 nop.i 0x0
+ 1360: 08 c0 03 28 46 10 \[MMI\] ld1.a.nta r120=\[r20\]
+ 1366: 80 07 52 80 20 00 ld1.a.d4 r120=\[r20\]
+ 136c: 00 00 04 00 nop.i 0x0
+ 1370: 08 c0 03 29 42 10 \[MMI\] ld1.a.d5 r120=\[r20\]
+ 1376: 80 07 52 88 20 00 ld1.a.d6 r120=\[r20\]
+ 137c: 00 00 04 00 nop.i 0x0
+ 1380: 08 c0 03 29 46 10 \[MMI\] ld1.a.d7 r120=\[r20\]
+ 1386: 80 07 50 90 20 00 ld2.a r120=\[r20\]
+ 138c: 00 00 04 00 nop.i 0x0
+ 1390: 08 c0 03 28 4a 10 \[MMI\] ld2.a.nt1 r120=\[r20\]
+ 1396: 80 07 50 94 20 00 ld2.a.nt1 r120=\[r20\]
+ 139c: 00 00 04 00 nop.i 0x0
+ 13a0: 08 c0 03 28 4c 10 \[MMI\] ld2.a.d2 r120=\[r20\]
+ 13a6: 80 07 50 9c 20 00 ld2.a.nta r120=\[r20\]
+ 13ac: 00 00 04 00 nop.i 0x0
+ 13b0: 08 c0 03 28 4e 10 \[MMI\] ld2.a.nta r120=\[r20\]
+ 13b6: 80 07 52 90 20 00 ld2.a.d4 r120=\[r20\]
+ 13bc: 00 00 04 00 nop.i 0x0
+ 13c0: 08 c0 03 29 4a 10 \[MMI\] ld2.a.d5 r120=\[r20\]
+ 13c6: 80 07 52 98 20 00 ld2.a.d6 r120=\[r20\]
+ 13cc: 00 00 04 00 nop.i 0x0
+ 13d0: 08 c0 03 29 4e 10 \[MMI\] ld2.a.d7 r120=\[r20\]
+ 13d6: 80 07 50 a0 20 00 ld4.a r120=\[r20\]
+ 13dc: 00 00 04 00 nop.i 0x0
+ 13e0: 08 c0 03 28 52 10 \[MMI\] ld4.a.nt1 r120=\[r20\]
+ 13e6: 80 07 50 a4 20 00 ld4.a.nt1 r120=\[r20\]
+ 13ec: 00 00 04 00 nop.i 0x0
+ 13f0: 08 c0 03 28 54 10 \[MMI\] ld4.a.d2 r120=\[r20\]
+ 13f6: 80 07 50 a8 20 00 ld4.a.d2 r120=\[r20\]
+ 13fc: 00 00 04 00 nop.i 0x0
+ 1400: 08 c0 03 28 56 10 \[MMI\] ld4.a.nta r120=\[r20\]
+ 1406: 80 07 50 ac 20 00 ld4.a.nta r120=\[r20\]
+ 140c: 00 00 04 00 nop.i 0x0
+ 1410: 08 c0 03 29 50 10 \[MMI\] ld4.a.d4 r120=\[r20\]
+ 1416: 80 07 52 a4 20 00 ld4.a.d5 r120=\[r20\]
+ 141c: 00 00 04 00 nop.i 0x0
+ 1420: 08 c0 03 29 54 10 \[MMI\] ld4.a.d6 r120=\[r20\]
+ 1426: 80 07 52 ac 20 00 ld4.a.d7 r120=\[r20\]
+ 142c: 00 00 04 00 nop.i 0x0
+ 1430: 08 c0 03 28 58 10 \[MMI\] ld8.a r120=\[r20\]
+ 1436: 80 07 50 b4 20 00 ld8.a.nt1 r120=\[r20\]
+ 143c: 00 00 04 00 nop.i 0x0
+ 1440: 08 c0 03 28 5a 10 \[MMI\] ld8.a.nt1 r120=\[r20\]
+ 1446: 80 07 50 b8 20 00 ld8.a.d2 r120=\[r20\]
+ 144c: 00 00 04 00 nop.i 0x0
+ 1450: 08 c0 03 28 5c 10 \[MMI\] ld8.a.d2 r120=\[r20\]
+ 1456: 80 07 50 bc 20 00 ld8.a.nta r120=\[r20\]
+ 145c: 00 00 04 00 nop.i 0x0
+ 1460: 08 c0 03 28 5e 10 \[MMI\] ld8.a.nta r120=\[r20\]
+ 1466: 80 07 52 b4 20 00 ld8.a.d5 r120=\[r20\]
+ 146c: 00 00 04 00 nop.i 0x0
+ 1470: 08 c0 03 29 5c 10 \[MMI\] ld8.a.d6 r120=\[r20\]
+ 1476: 80 07 52 bc 20 00 ld8.a.d7 r120=\[r20\]
+ 147c: 00 00 04 00 nop.i 0x0
+ 1480: 08 c0 03 28 60 10 \[MMI\] ld1.sa r120=\[r20\]
+ 1486: 80 07 50 c4 20 00 ld1.sa.nt1 r120=\[r20\]
+ 148c: 00 00 04 00 nop.i 0x0
+ 1490: 08 c0 03 28 62 10 \[MMI\] ld1.sa.nt1 r120=\[r20\]
+ 1496: 80 07 50 c8 20 00 ld1.sa.d2 r120=\[r20\]
+ 149c: 00 00 04 00 nop.i 0x0
+ 14a0: 08 c0 03 28 64 10 \[MMI\] ld1.sa.d2 r120=\[r20\]
+ 14a6: 80 07 50 cc 20 00 ld1.sa.nta r120=\[r20\]
+ 14ac: 00 00 04 00 nop.i 0x0
+ 14b0: 08 c0 03 28 66 10 \[MMI\] ld1.sa.nta r120=\[r20\]
+ 14b6: 80 07 52 c0 20 00 ld1.sa.d4 r120=\[r20\]
+ 14bc: 00 00 04 00 nop.i 0x0
+ 14c0: 08 c0 03 29 62 10 \[MMI\] ld1.sa.d5 r120=\[r20\]
+ 14c6: 80 07 52 c8 20 00 ld1.sa.d6 r120=\[r20\]
+ 14cc: 00 00 04 00 nop.i 0x0
+ 14d0: 08 c0 03 29 66 10 \[MMI\] ld1.sa.d7 r120=\[r20\]
+ 14d6: 80 07 50 d0 20 00 ld2.sa r120=\[r20\]
+ 14dc: 00 00 04 00 nop.i 0x0
+ 14e0: 08 c0 03 28 6a 10 \[MMI\] ld2.sa.nt1 r120=\[r20\]
+ 14e6: 80 07 50 d4 20 00 ld2.sa.nt1 r120=\[r20\]
+ 14ec: 00 00 04 00 nop.i 0x0
+ 14f0: 08 c0 03 28 6c 10 \[MMI\] ld2.sa.d2 r120=\[r20\]
+ 14f6: 80 07 50 d8 20 00 ld2.sa.d2 r120=\[r20\]
+ 14fc: 00 00 04 00 nop.i 0x0
+ 1500: 08 c0 03 28 6e 10 \[MMI\] ld2.sa.nta r120=\[r20\]
+ 1506: 80 07 50 dc 20 00 ld2.sa.nta r120=\[r20\]
+ 150c: 00 00 04 00 nop.i 0x0
+ 1510: 08 c0 03 29 68 10 \[MMI\] ld2.sa.d4 r120=\[r20\]
+ 1516: 80 07 52 d4 20 00 ld2.sa.d5 r120=\[r20\]
+ 151c: 00 00 04 00 nop.i 0x0
+ 1520: 08 c0 03 29 6c 10 \[MMI\] ld2.sa.d6 r120=\[r20\]
+ 1526: 80 07 52 dc 20 00 ld2.sa.d7 r120=\[r20\]
+ 152c: 00 00 04 00 nop.i 0x0
+ 1530: 08 c0 03 28 72 10 \[MMI\] ld4.sa.nt1 r120=\[r20\]
+ 1536: 80 07 50 e4 20 00 ld4.sa.nt1 r120=\[r20\]
+ 153c: 00 00 04 00 nop.i 0x0
+ 1540: 08 c0 03 28 74 10 \[MMI\] ld4.sa.d2 r120=\[r20\]
+ 1546: 80 07 50 e8 20 00 ld4.sa.d2 r120=\[r20\]
+ 154c: 00 00 04 00 nop.i 0x0
+ 1550: 08 c0 03 28 76 10 \[MMI\] ld4.sa.nta r120=\[r20\]
+ 1556: 80 07 50 ec 20 00 ld4.sa.nta r120=\[r20\]
+ 155c: 00 00 04 00 nop.i 0x0
+ 1560: 08 c0 03 29 70 10 \[MMI\] ld4.sa.d4 r120=\[r20\]
+ 1566: 80 07 52 e4 20 00 ld4.sa.d5 r120=\[r20\]
+ 156c: 00 00 04 00 nop.i 0x0
+ 1570: 08 c0 03 29 74 10 \[MMI\] ld4.sa.d6 r120=\[r20\]
+ 1576: 80 07 52 ec 20 00 ld4.sa.d7 r120=\[r20\]
+ 157c: 00 00 04 00 nop.i 0x0
+ 1580: 08 c0 03 28 78 10 \[MMI\] ld8.sa r120=\[r20\]
+ 1586: 80 07 50 f4 20 00 ld8.sa.nt1 r120=\[r20\]
+ 158c: 00 00 04 00 nop.i 0x0
+ 1590: 08 c0 03 28 7a 10 \[MMI\] ld8.sa.nt1 r120=\[r20\]
+ 1596: 80 07 50 f8 20 00 ld8.sa.d2 r120=\[r20\]
+ 159c: 00 00 04 00 nop.i 0x0
+ 15a0: 08 c0 03 28 7c 10 \[MMI\] ld8.sa.d2 r120=\[r20\]
+ 15a6: 80 07 50 fc 20 00 ld8.sa.nta r120=\[r20\]
+ 15ac: 00 00 04 00 nop.i 0x0
+ 15b0: 08 c0 03 28 7e 10 \[MMI\] ld8.sa.nta r120=\[r20\]
+ 15b6: 80 07 52 f0 20 00 ld8.sa.d4 r120=\[r20\]
+ 15bc: 00 00 04 00 nop.i 0x0
+ 15c0: 08 c0 03 29 7a 10 \[MMI\] ld8.sa.d5 r120=\[r20\]
+ 15c6: 80 07 52 f8 20 00 ld8.sa.d6 r120=\[r20\]
+ 15cc: 00 00 04 00 nop.i 0x0
+ 15d0: 08 c0 03 29 7e 10 \[MMI\] ld8.sa.d7 r120=\[r20\]
+ 15d6: 80 07 50 00 21 00 ld1.bias r120=\[r20\]
+ 15dc: 00 00 04 00 nop.i 0x0
+ 15e0: 08 c0 03 28 82 10 \[MMI\] ld1.bias.nt1 r120=\[r20\]
+ 15e6: 80 07 50 04 21 00 ld1.bias.nt1 r120=\[r20\]
+ 15ec: 00 00 04 00 nop.i 0x0
+ 15f0: 08 c0 03 28 84 10 \[MMI\] ld1.bias.d2 r120=\[r20\]
+ 15f6: 80 07 50 08 21 00 ld1.bias.d2 r120=\[r20\]
+ 15fc: 00 00 04 00 nop.i 0x0
+ 1600: 08 c0 03 28 86 10 \[MMI\] ld1.bias.nta r120=\[r20\]
+ 1606: 80 07 50 0c 21 00 ld1.bias.nta r120=\[r20\]
+ 160c: 00 00 04 00 nop.i 0x0
+ 1610: 08 c0 03 29 80 10 \[MMI\] ld1.bias.d4 r120=\[r20\]
+ 1616: 80 07 52 04 21 00 ld1.bias.d5 r120=\[r20\]
+ 161c: 00 00 04 00 nop.i 0x0
+ 1620: 08 c0 03 29 84 10 \[MMI\] ld1.bias.d6 r120=\[r20\]
+ 1626: 80 07 52 0c 21 00 ld1.bias.d7 r120=\[r20\]
+ 162c: 00 00 04 00 nop.i 0x0
+ 1630: 08 c0 03 28 88 10 \[MMI\] ld2.bias r120=\[r20\]
+ 1636: 80 07 50 14 21 00 ld2.bias.nt1 r120=\[r20\]
+ 163c: 00 00 04 00 nop.i 0x0
+ 1640: 08 c0 03 28 8a 10 \[MMI\] ld2.bias.nt1 r120=\[r20\]
+ 1646: 80 07 50 18 21 00 ld2.bias.d2 r120=\[r20\]
+ 164c: 00 00 04 00 nop.i 0x0
+ 1650: 08 c0 03 28 8c 10 \[MMI\] ld2.bias.d2 r120=\[r20\]
+ 1656: 80 07 50 1c 21 00 ld2.bias.nta r120=\[r20\]
+ 165c: 00 00 04 00 nop.i 0x0
+ 1660: 08 c0 03 28 8e 10 \[MMI\] ld2.bias.nta r120=\[r20\]
+ 1666: 80 07 52 10 21 00 ld2.bias.d4 r120=\[r20\]
+ 166c: 00 00 04 00 nop.i 0x0
+ 1670: 08 c0 03 29 8a 10 \[MMI\] ld2.bias.d5 r120=\[r20\]
+ 1676: 80 07 52 18 21 00 ld2.bias.d6 r120=\[r20\]
+ 167c: 00 00 04 00 nop.i 0x0
+ 1680: 08 c0 03 29 8e 10 \[MMI\] ld2.bias.d7 r120=\[r20\]
+ 1686: 80 07 50 20 21 00 ld4.bias r120=\[r20\]
+ 168c: 00 00 04 00 nop.i 0x0
+ 1690: 08 c0 03 28 92 10 \[MMI\] ld4.bias.nt1 r120=\[r20\]
+ 1696: 80 07 50 24 21 00 ld4.bias.nt1 r120=\[r20\]
+ 169c: 00 00 04 00 nop.i 0x0
+ 16a0: 08 c0 03 28 94 10 \[MMI\] ld4.bias.d2 r120=\[r20\]
+ 16a6: 80 07 50 28 21 00 ld4.bias.d2 r120=\[r20\]
+ 16ac: 00 00 04 00 nop.i 0x0
+ 16b0: 08 c0 03 28 96 10 \[MMI\] ld4.bias.nta r120=\[r20\]
+ 16b6: 80 07 50 2c 21 00 ld4.bias.nta r120=\[r20\]
+ 16bc: 00 00 04 00 nop.i 0x0
+ 16c0: 08 c0 03 29 90 10 \[MMI\] ld4.bias.d4 r120=\[r20\]
+ 16c6: 80 07 52 24 21 00 ld4.bias.d5 r120=\[r20\]
+ 16cc: 00 00 04 00 nop.i 0x0
+ 16d0: 08 c0 03 29 94 10 \[MMI\] ld4.bias.d6 r120=\[r20\]
+ 16d6: 80 07 52 2c 21 00 ld4.bias.d7 r120=\[r20\]
+ 16dc: 00 00 04 00 nop.i 0x0
+ 16e0: 08 c0 03 28 98 10 \[MMI\] ld8.bias r120=\[r20\]
+ 16e6: 80 07 50 34 21 00 ld8.bias.nt1 r120=\[r20\]
+ 16ec: 00 00 04 00 nop.i 0x0
+ 16f0: 08 c0 03 28 9a 10 \[MMI\] ld8.bias.nt1 r120=\[r20\]
+ 16f6: 80 07 50 38 21 00 ld8.bias.d2 r120=\[r20\]
+ 16fc: 00 00 04 00 nop.i 0x0
+ 1700: 08 c0 03 28 9c 10 \[MMI\] ld8.bias.d2 r120=\[r20\]
+ 1706: 80 07 50 3c 21 00 ld8.bias.nta r120=\[r20\]
+ 170c: 00 00 04 00 nop.i 0x0
+ 1710: 08 c0 03 28 9e 10 \[MMI\] ld8.bias.nta r120=\[r20\]
+ 1716: 80 07 52 30 21 00 ld8.bias.d4 r120=\[r20\]
+ 171c: 00 00 04 00 nop.i 0x0
+ 1720: 08 c0 03 29 9a 10 \[MMI\] ld8.bias.d5 r120=\[r20\]
+ 1726: 80 07 52 38 21 00 ld8.bias.d6 r120=\[r20\]
+ 172c: 00 00 04 00 nop.i 0x0
+ 1730: 08 c0 03 29 9e 10 \[MMI\] ld8.bias.d7 r120=\[r20\]
+ 1736: 80 07 50 40 21 00 ld1.acq r120=\[r20\]
+ 173c: 00 00 04 00 nop.i 0x0
+ 1740: 08 c0 03 28 a2 10 \[MMI\] ld1.acq.nt1 r120=\[r20\]
+ 1746: 80 07 50 44 21 00 ld1.acq.nt1 r120=\[r20\]
+ 174c: 00 00 04 00 nop.i 0x0
+ 1750: 08 c0 03 28 a4 10 \[MMI\] ld1.acq.d2 r120=\[r20\]
+ 1756: 80 07 50 48 21 00 ld1.acq.d2 r120=\[r20\]
+ 175c: 00 00 04 00 nop.i 0x0
+ 1760: 08 c0 03 28 a6 10 \[MMI\] ld1.acq.nta r120=\[r20\]
+ 1766: 80 07 50 4c 21 00 ld1.acq.nta r120=\[r20\]
+ 176c: 00 00 04 00 nop.i 0x0
+ 1770: 08 c0 03 29 a0 10 \[MMI\] ld1.acq.d4 r120=\[r20\]
+ 1776: 80 07 52 44 21 00 ld1.acq.d5 r120=\[r20\]
+ 177c: 00 00 04 00 nop.i 0x0
+ 1780: 08 c0 03 29 a4 10 \[MMI\] ld1.acq.d6 r120=\[r20\]
+ 1786: 80 07 50 50 21 00 ld2.acq r120=\[r20\]
+ 178c: 00 00 04 00 nop.i 0x0
+ 1790: 08 c0 03 28 aa 10 \[MMI\] ld2.acq.nt1 r120=\[r20\]
+ 1796: 80 07 50 54 21 00 ld2.acq.nt1 r120=\[r20\]
+ 179c: 00 00 04 00 nop.i 0x0
+ 17a0: 08 c0 03 28 ac 10 \[MMI\] ld2.acq.d2 r120=\[r20\]
+ 17a6: 80 07 50 58 21 00 ld2.acq.d2 r120=\[r20\]
+ 17ac: 00 00 04 00 nop.i 0x0
+ 17b0: 08 c0 03 28 ae 10 \[MMI\] ld2.acq.nta r120=\[r20\]
+ 17b6: 80 07 50 5c 21 00 ld2.acq.nta r120=\[r20\]
+ 17bc: 00 00 04 00 nop.i 0x0
+ 17c0: 08 c0 03 29 a8 10 \[MMI\] ld2.acq.d4 r120=\[r20\]
+ 17c6: 80 07 52 54 21 00 ld2.acq.d5 r120=\[r20\]
+ 17cc: 00 00 04 00 nop.i 0x0
+ 17d0: 08 c0 03 29 ac 10 \[MMI\] ld2.acq.d6 r120=\[r20\]
+ 17d6: 80 07 52 5c 21 00 ld2.acq.d7 r120=\[r20\]
+ 17dc: 00 00 04 00 nop.i 0x0
+ 17e0: 08 c0 03 28 b0 10 \[MMI\] ld4.acq r120=\[r20\]
+ 17e6: 80 07 50 64 21 00 ld4.acq.nt1 r120=\[r20\]
+ 17ec: 00 00 04 00 nop.i 0x0
+ 17f0: 08 c0 03 28 b2 10 \[MMI\] ld4.acq.nt1 r120=\[r20\]
+ 17f6: 80 07 50 68 21 00 ld4.acq.d2 r120=\[r20\]
+ 17fc: 00 00 04 00 nop.i 0x0
+ 1800: 08 c0 03 28 b4 10 \[MMI\] ld4.acq.d2 r120=\[r20\]
+ 1806: 80 07 50 6c 21 00 ld4.acq.nta r120=\[r20\]
+ 180c: 00 00 04 00 nop.i 0x0
+ 1810: 08 c0 03 28 b6 10 \[MMI\] ld4.acq.nta r120=\[r20\]
+ 1816: 80 07 52 60 21 00 ld4.acq.d4 r120=\[r20\]
+ 181c: 00 00 04 00 nop.i 0x0
+ 1820: 08 c0 03 29 b2 10 \[MMI\] ld4.acq.d5 r120=\[r20\]
+ 1826: 80 07 52 68 21 00 ld4.acq.d6 r120=\[r20\]
+ 182c: 00 00 04 00 nop.i 0x0
+ 1830: 08 c0 03 29 b6 10 \[MMI\] ld4.acq.d7 r120=\[r20\]
+ 1836: 80 07 50 70 21 00 ld8.acq r120=\[r20\]
+ 183c: 00 00 04 00 nop.i 0x0
+ 1840: 08 c0 03 28 ba 10 \[MMI\] ld8.acq.nt1 r120=\[r20\]
+ 1846: 80 07 50 74 21 00 ld8.acq.nt1 r120=\[r20\]
+ 184c: 00 00 04 00 nop.i 0x0
+ 1850: 08 c0 03 28 bc 10 \[MMI\] ld8.acq.d2 r120=\[r20\]
+ 1856: 80 07 50 78 21 00 ld8.acq.d2 r120=\[r20\]
+ 185c: 00 00 04 00 nop.i 0x0
+ 1860: 08 c0 03 28 be 10 \[MMI\] ld8.acq.nta r120=\[r20\]
+ 1866: 80 07 50 7c 21 00 ld8.acq.nta r120=\[r20\]
+ 186c: 00 00 04 00 nop.i 0x0
+ 1870: 08 c0 03 29 b8 10 \[MMI\] ld8.acq.d4 r120=\[r20\]
+ 1876: 80 07 52 74 21 00 ld8.acq.d5 r120=\[r20\]
+ 187c: 00 00 04 00 nop.i 0x0
+ 1880: 08 c0 03 29 bc 10 \[MMI\] ld8.acq.d6 r120=\[r20\]
+ 1886: 80 07 52 7c 21 00 ld8.acq.d7 r120=\[r20\]
+ 188c: 00 00 04 00 nop.i 0x0
+ 1890: 08 c0 03 28 d8 10 \[MMI\] ld8.fill r120=\[r20\]
+ 1896: 80 07 50 b4 21 00 ld8.fill.nt1 r120=\[r20\]
+ 189c: 00 00 04 00 nop.i 0x0
+ 18a0: 08 c0 03 28 da 10 \[MMI\] ld8.fill.nt1 r120=\[r20\]
+ 18a6: 80 07 50 b8 21 00 ld8.fill.d2 r120=\[r20\]
+ 18ac: 00 00 04 00 nop.i 0x0
+ 18b0: 08 c0 03 28 dc 10 \[MMI\] ld8.fill.d2 r120=\[r20\]
+ 18b6: 80 07 50 bc 21 00 ld8.fill.nta r120=\[r20\]
+ 18bc: 00 00 04 00 nop.i 0x0
+ 18c0: 08 c0 03 28 de 10 \[MMI\] ld8.fill.nta r120=\[r20\]
+ 18c6: 80 07 52 b0 21 00 ld8.fill.d4 r120=\[r20\]
+ 18cc: 00 00 04 00 nop.i 0x0
+ 18d0: 08 c0 03 29 da 10 \[MMI\] ld8.fill.d5 r120=\[r20\]
+ 18d6: 80 07 52 b8 21 00 ld8.fill.d6 r120=\[r20\]
+ 18dc: 00 00 04 00 nop.i 0x0
+ 18e0: 08 c0 03 29 de 10 \[MMI\] ld8.fill.d7 r120=\[r20\]
+ 18e6: 80 07 50 00 22 00 ld1.c.clr r120=\[r20\]
+ 18ec: 00 00 04 00 nop.i 0x0
+ 18f0: 08 c0 03 28 02 11 \[MMI\] ld1.c.clr.nt1 r120=\[r20\]
+ 18f6: 80 07 50 04 22 00 ld1.c.clr.nt1 r120=\[r20\]
+ 18fc: 00 00 04 00 nop.i 0x0
+ 1900: 08 c0 03 28 04 11 \[MMI\] ld1.c.clr.d2 r120=\[r20\]
+ 1906: 80 07 50 08 22 00 ld1.c.clr.d2 r120=\[r20\]
+ 190c: 00 00 04 00 nop.i 0x0
+ 1910: 08 c0 03 28 06 11 \[MMI\] ld1.c.clr.nta r120=\[r20\]
+ 1916: 80 07 50 0c 22 00 ld1.c.clr.nta r120=\[r20\]
+ 191c: 00 00 04 00 nop.i 0x0
+ 1920: 08 c0 03 29 00 11 \[MMI\] ld1.c.clr.d4 r120=\[r20\]
+ 1926: 80 07 52 04 22 00 ld1.c.clr.d5 r120=\[r20\]
+ 192c: 00 00 04 00 nop.i 0x0
+ 1930: 08 c0 03 29 04 11 \[MMI\] ld1.c.clr.d6 r120=\[r20\]
+ 1936: 80 07 52 0c 22 00 ld1.c.clr.d7 r120=\[r20\]
+ 193c: 00 00 04 00 nop.i 0x0
+ 1940: 08 c0 03 28 08 11 \[MMI\] ld2.c.clr r120=\[r20\]
+ 1946: 80 07 50 14 22 00 ld2.c.clr.nt1 r120=\[r20\]
+ 194c: 00 00 04 00 nop.i 0x0
+ 1950: 08 c0 03 28 0a 11 \[MMI\] ld2.c.clr.nt1 r120=\[r20\]
+ 1956: 80 07 50 18 22 00 ld2.c.clr.d2 r120=\[r20\]
+ 195c: 00 00 04 00 nop.i 0x0
+ 1960: 08 c0 03 28 0c 11 \[MMI\] ld2.c.clr.d2 r120=\[r20\]
+ 1966: 80 07 50 1c 22 00 ld2.c.clr.nta r120=\[r20\]
+ 196c: 00 00 04 00 nop.i 0x0
+ 1970: 08 c0 03 28 0e 11 \[MMI\] ld2.c.clr.nta r120=\[r20\]
+ 1976: 80 07 52 10 22 00 ld2.c.clr.d4 r120=\[r20\]
+ 197c: 00 00 04 00 nop.i 0x0
+ 1980: 08 c0 03 29 0a 11 \[MMI\] ld2.c.clr.d5 r120=\[r20\]
+ 1986: 80 07 52 18 22 00 ld2.c.clr.d6 r120=\[r20\]
+ 198c: 00 00 04 00 nop.i 0x0
+ 1990: 08 c0 03 29 0e 11 \[MMI\] ld2.c.clr.d7 r120=\[r20\]
+ 1996: 80 07 50 20 22 00 ld4.c.clr r120=\[r20\]
+ 199c: 00 00 04 00 nop.i 0x0
+ 19a0: 08 c0 03 28 12 11 \[MMI\] ld4.c.clr.nt1 r120=\[r20\]
+ 19a6: 80 07 50 24 22 00 ld4.c.clr.nt1 r120=\[r20\]
+ 19ac: 00 00 04 00 nop.i 0x0
+ 19b0: 08 c0 03 28 14 11 \[MMI\] ld4.c.clr.d2 r120=\[r20\]
+ 19b6: 80 07 50 28 22 00 ld4.c.clr.d2 r120=\[r20\]
+ 19bc: 00 00 04 00 nop.i 0x0
+ 19c0: 08 c0 03 28 16 11 \[MMI\] ld4.c.clr.nta r120=\[r20\]
+ 19c6: 80 07 50 2c 22 00 ld4.c.clr.nta r120=\[r20\]
+ 19cc: 00 00 04 00 nop.i 0x0
+ 19d0: 08 c0 03 29 10 11 \[MMI\] ld4.c.clr.d4 r120=\[r20\]
+ 19d6: 80 07 52 24 22 00 ld4.c.clr.d5 r120=\[r20\]
+ 19dc: 00 00 04 00 nop.i 0x0
+ 19e0: 08 c0 03 29 14 11 \[MMI\] ld4.c.clr.d6 r120=\[r20\]
+ 19e6: 80 07 52 2c 22 00 ld4.c.clr.d7 r120=\[r20\]
+ 19ec: 00 00 04 00 nop.i 0x0
+ 19f0: 08 c0 03 28 18 11 \[MMI\] ld8.c.clr r120=\[r20\]
+ 19f6: 80 07 50 34 22 00 ld8.c.clr.nt1 r120=\[r20\]
+ 19fc: 00 00 04 00 nop.i 0x0
+ 1a00: 08 c0 03 28 1a 11 \[MMI\] ld8.c.clr.nt1 r120=\[r20\]
+ 1a06: 80 07 50 38 22 00 ld8.c.clr.d2 r120=\[r20\]
+ 1a0c: 00 00 04 00 nop.i 0x0
+ 1a10: 08 c0 03 28 1c 11 \[MMI\] ld8.c.clr.d2 r120=\[r20\]
+ 1a16: 80 07 50 3c 22 00 ld8.c.clr.nta r120=\[r20\]
+ 1a1c: 00 00 04 00 nop.i 0x0
+ 1a20: 08 c0 03 28 1e 11 \[MMI\] ld8.c.clr.nta r120=\[r20\]
+ 1a26: 80 07 52 30 22 00 ld8.c.clr.d4 r120=\[r20\]
+ 1a2c: 00 00 04 00 nop.i 0x0
+ 1a30: 08 c0 03 29 1a 11 \[MMI\] ld8.c.clr.d5 r120=\[r20\]
+ 1a36: 80 07 52 38 22 00 ld8.c.clr.d6 r120=\[r20\]
+ 1a3c: 00 00 04 00 nop.i 0x0
+ 1a40: 08 c0 03 29 1e 11 \[MMI\] ld8.c.clr.d7 r120=\[r20\]
+ 1a46: 80 07 50 40 22 00 ld1.c.nc r120=\[r20\]
+ 1a4c: 00 00 04 00 nop.i 0x0
+ 1a50: 08 c0 03 28 22 11 \[MMI\] ld1.c.nc.nt1 r120=\[r20\]
+ 1a56: 80 07 50 44 22 00 ld1.c.nc.nt1 r120=\[r20\]
+ 1a5c: 00 00 04 00 nop.i 0x0
+ 1a60: 08 c0 03 28 24 11 \[MMI\] ld1.c.nc.d2 r120=\[r20\]
+ 1a66: 80 07 50 48 22 00 ld1.c.nc.d2 r120=\[r20\]
+ 1a6c: 00 00 04 00 nop.i 0x0
+ 1a70: 08 c0 03 28 26 11 \[MMI\] ld1.c.nc.nta r120=\[r20\]
+ 1a76: 80 07 50 4c 22 00 ld1.c.nc.nta r120=\[r20\]
+ 1a7c: 00 00 04 00 nop.i 0x0
+ 1a80: 08 c0 03 29 20 11 \[MMI\] ld1.c.nc.d4 r120=\[r20\]
+ 1a86: 80 07 52 44 22 00 ld1.c.nc.d5 r120=\[r20\]
+ 1a8c: 00 00 04 00 nop.i 0x0
+ 1a90: 08 c0 03 29 26 11 \[MMI\] ld1.c.nc.d7 r120=\[r20\]
+ 1a96: 80 07 50 50 22 00 ld2.c.nc r120=\[r20\]
+ 1a9c: 00 00 04 00 nop.i 0x0
+ 1aa0: 08 c0 03 28 2a 11 \[MMI\] ld2.c.nc.nt1 r120=\[r20\]
+ 1aa6: 80 07 50 54 22 00 ld2.c.nc.nt1 r120=\[r20\]
+ 1aac: 00 00 04 00 nop.i 0x0
+ 1ab0: 08 c0 03 28 2c 11 \[MMI\] ld2.c.nc.d2 r120=\[r20\]
+ 1ab6: 80 07 50 58 22 00 ld2.c.nc.d2 r120=\[r20\]
+ 1abc: 00 00 04 00 nop.i 0x0
+ 1ac0: 08 c0 03 28 2e 11 \[MMI\] ld2.c.nc.nta r120=\[r20\]
+ 1ac6: 80 07 50 5c 22 00 ld2.c.nc.nta r120=\[r20\]
+ 1acc: 00 00 04 00 nop.i 0x0
+ 1ad0: 08 c0 03 29 28 11 \[MMI\] ld2.c.nc.d4 r120=\[r20\]
+ 1ad6: 80 07 52 54 22 00 ld2.c.nc.d5 r120=\[r20\]
+ 1adc: 00 00 04 00 nop.i 0x0
+ 1ae0: 08 c0 03 29 2c 11 \[MMI\] ld2.c.nc.d6 r120=\[r20\]
+ 1ae6: 80 07 52 5c 22 00 ld2.c.nc.d7 r120=\[r20\]
+ 1aec: 00 00 04 00 nop.i 0x0
+ 1af0: 08 c0 03 28 30 11 \[MMI\] ld4.c.nc r120=\[r20\]
+ 1af6: 80 07 50 64 22 00 ld4.c.nc.nt1 r120=\[r20\]
+ 1afc: 00 00 04 00 nop.i 0x0
+ 1b00: 08 c0 03 28 32 11 \[MMI\] ld4.c.nc.nt1 r120=\[r20\]
+ 1b06: 80 07 50 68 22 00 ld4.c.nc.d2 r120=\[r20\]
+ 1b0c: 00 00 04 00 nop.i 0x0
+ 1b10: 08 c0 03 28 34 11 \[MMI\] ld4.c.nc.d2 r120=\[r20\]
+ 1b16: 80 07 50 6c 22 00 ld4.c.nc.nta r120=\[r20\]
+ 1b1c: 00 00 04 00 nop.i 0x0
+ 1b20: 08 c0 03 28 36 11 \[MMI\] ld4.c.nc.nta r120=\[r20\]
+ 1b26: 80 07 52 60 22 00 ld4.c.nc.d4 r120=\[r20\]
+ 1b2c: 00 00 04 00 nop.i 0x0
+ 1b30: 08 c0 03 29 32 11 \[MMI\] ld4.c.nc.d5 r120=\[r20\]
+ 1b36: 80 07 52 68 22 00 ld4.c.nc.d6 r120=\[r20\]
+ 1b3c: 00 00 04 00 nop.i 0x0
+ 1b40: 08 c0 03 29 36 11 \[MMI\] ld4.c.nc.d7 r120=\[r20\]
+ 1b46: 80 07 50 70 22 00 ld8.c.nc r120=\[r20\]
+ 1b4c: 00 00 04 00 nop.i 0x0
+ 1b50: 08 c0 03 28 3a 11 \[MMI\] ld8.c.nc.nt1 r120=\[r20\]
+ 1b56: 80 07 50 74 22 00 ld8.c.nc.nt1 r120=\[r20\]
+ 1b5c: 00 00 04 00 nop.i 0x0
+ 1b60: 08 c0 03 28 3c 11 \[MMI\] ld8.c.nc.d2 r120=\[r20\]
+ 1b66: 80 07 50 78 22 00 ld8.c.nc.d2 r120=\[r20\]
+ 1b6c: 00 00 04 00 nop.i 0x0
+ 1b70: 08 c0 03 28 3e 11 \[MMI\] ld8.c.nc.nta r120=\[r20\]
+ 1b76: 80 07 50 7c 22 00 ld8.c.nc.nta r120=\[r20\]
+ 1b7c: 00 00 04 00 nop.i 0x0
+ 1b80: 08 c0 03 29 38 11 \[MMI\] ld8.c.nc.d4 r120=\[r20\]
+ 1b86: 80 07 52 74 22 00 ld8.c.nc.d5 r120=\[r20\]
+ 1b8c: 00 00 04 00 nop.i 0x0
+ 1b90: 08 c0 03 29 3c 11 \[MMI\] ld8.c.nc.d6 r120=\[r20\]
+ 1b96: 80 07 52 7c 22 00 ld8.c.nc.d7 r120=\[r20\]
+ 1b9c: 00 00 04 00 nop.i 0x0
+ 1ba0: 08 c0 03 28 40 11 \[MMI\] ld1.c.clr.acq r120=\[r20\]
+ 1ba6: 80 07 50 84 22 00 ld1.c.clr.acq.nt1 r120=\[r20\]
+ 1bac: 00 00 04 00 nop.i 0x0
+ 1bb0: 08 c0 03 28 42 11 \[MMI\] ld1.c.clr.acq.nt1 r120=\[r20\]
+ 1bb6: 80 07 50 88 22 00 ld1.c.clr.acq.d2 r120=\[r20\]
+ 1bbc: 00 00 04 00 nop.i 0x0
+ 1bc0: 08 c0 03 28 44 11 \[MMI\] ld1.c.clr.acq.d2 r120=\[r20\]
+ 1bc6: 80 07 50 8c 22 00 ld1.c.clr.acq.nta r120=\[r20\]
+ 1bcc: 00 00 04 00 nop.i 0x0
+ 1bd0: 08 c0 03 28 46 11 \[MMI\] ld1.c.clr.acq.nta r120=\[r20\]
+ 1bd6: 80 07 52 80 22 00 ld1.c.clr.acq.d4 r120=\[r20\]
+ 1bdc: 00 00 04 00 nop.i 0x0
+ 1be0: 08 c0 03 29 42 11 \[MMI\] ld1.c.clr.acq.d5 r120=\[r20\]
+ 1be6: 80 07 52 88 22 00 ld1.c.clr.acq.d6 r120=\[r20\]
+ 1bec: 00 00 04 00 nop.i 0x0
+ 1bf0: 08 c0 03 29 46 11 \[MMI\] ld1.c.clr.acq.d7 r120=\[r20\]
+ 1bf6: 80 07 50 90 22 00 ld2.c.clr.acq r120=\[r20\]
+ 1bfc: 00 00 04 00 nop.i 0x0
+ 1c00: 08 c0 03 28 4a 11 \[MMI\] ld2.c.clr.acq.nt1 r120=\[r20\]
+ 1c06: 80 07 50 94 22 00 ld2.c.clr.acq.nt1 r120=\[r20\]
+ 1c0c: 00 00 04 00 nop.i 0x0
+ 1c10: 08 c0 03 28 4c 11 \[MMI\] ld2.c.clr.acq.d2 r120=\[r20\]
+ 1c16: 80 07 50 98 22 00 ld2.c.clr.acq.d2 r120=\[r20\]
+ 1c1c: 00 00 04 00 nop.i 0x0
+ 1c20: 08 c0 03 28 4e 11 \[MMI\] ld2.c.clr.acq.nta r120=\[r20\]
+ 1c26: 80 07 52 90 22 00 ld2.c.clr.acq.d4 r120=\[r20\]
+ 1c2c: 00 00 04 00 nop.i 0x0
+ 1c30: 08 c0 03 29 4a 11 \[MMI\] ld2.c.clr.acq.d5 r120=\[r20\]
+ 1c36: 80 07 52 98 22 00 ld2.c.clr.acq.d6 r120=\[r20\]
+ 1c3c: 00 00 04 00 nop.i 0x0
+ 1c40: 08 c0 03 29 4e 11 \[MMI\] ld2.c.clr.acq.d7 r120=\[r20\]
+ 1c46: 80 07 50 a0 22 00 ld4.c.clr.acq r120=\[r20\]
+ 1c4c: 00 00 04 00 nop.i 0x0
+ 1c50: 08 c0 03 28 52 11 \[MMI\] ld4.c.clr.acq.nt1 r120=\[r20\]
+ 1c56: 80 07 50 a4 22 00 ld4.c.clr.acq.nt1 r120=\[r20\]
+ 1c5c: 00 00 04 00 nop.i 0x0
+ 1c60: 08 c0 03 28 54 11 \[MMI\] ld4.c.clr.acq.d2 r120=\[r20\]
+ 1c66: 80 07 50 a8 22 00 ld4.c.clr.acq.d2 r120=\[r20\]
+ 1c6c: 00 00 04 00 nop.i 0x0
+ 1c70: 08 c0 03 28 56 11 \[MMI\] ld4.c.clr.acq.nta r120=\[r20\]
+ 1c76: 80 07 50 ac 22 00 ld4.c.clr.acq.nta r120=\[r20\]
+ 1c7c: 00 00 04 00 nop.i 0x0
+ 1c80: 08 c0 03 29 50 11 \[MMI\] ld4.c.clr.acq.d4 r120=\[r20\]
+ 1c86: 80 07 52 a4 22 00 ld4.c.clr.acq.d5 r120=\[r20\]
+ 1c8c: 00 00 04 00 nop.i 0x0
+ 1c90: 08 c0 03 29 54 11 \[MMI\] ld4.c.clr.acq.d6 r120=\[r20\]
+ 1c96: 80 07 52 ac 22 00 ld4.c.clr.acq.d7 r120=\[r20\]
+ 1c9c: 00 00 04 00 nop.i 0x0
+ 1ca0: 08 c0 03 28 58 11 \[MMI\] ld8.c.clr.acq r120=\[r20\]
+ 1ca6: 80 07 50 b4 22 00 ld8.c.clr.acq.nt1 r120=\[r20\]
+ 1cac: 00 00 04 00 nop.i 0x0
+ 1cb0: 08 c0 03 28 5a 11 \[MMI\] ld8.c.clr.acq.nt1 r120=\[r20\]
+ 1cb6: 80 07 50 b8 22 00 ld8.c.clr.acq.d2 r120=\[r20\]
+ 1cbc: 00 00 04 00 nop.i 0x0
+ 1cc0: 08 c0 03 28 5c 11 \[MMI\] ld8.c.clr.acq.d2 r120=\[r20\]
+ 1cc6: 80 07 50 bc 22 00 ld8.c.clr.acq.nta r120=\[r20\]
+ 1ccc: 00 00 04 00 nop.i 0x0
+ 1cd0: 08 c0 03 28 5e 11 \[MMI\] ld8.c.clr.acq.nta r120=\[r20\]
+ 1cd6: 80 07 52 b0 22 00 ld8.c.clr.acq.d4 r120=\[r20\]
+ 1cdc: 00 00 04 00 nop.i 0x0
+ 1ce0: 08 c0 03 29 5a 11 \[MMI\] ld8.c.clr.acq.d5 r120=\[r20\]
+ 1ce6: 80 07 52 b8 22 00 ld8.c.clr.acq.d6 r120=\[r20\]
+ 1cec: 00 00 04 00 nop.i 0x0
+ 1cf0: 08 c0 03 29 5e 11 \[MMI\] ld8.c.clr.acq.d7 r120=\[r20\]
+ 1cf6: 80 07 50 82 22 00 ld16 r120,ar.csd=\[r20\]
+ 1cfc: 00 00 04 00 nop.i 0x0
+ 1d00: 08 c0 03 28 41 11 \[MMI\] ld16 r120,ar.csd=\[r20\]
+ 1d06: 80 07 50 86 22 00 ld16.nt1 r120,ar.csd=\[r20\]
+ 1d0c: 00 00 04 00 nop.i 0x0
+ 1d10: 08 c0 03 28 43 11 \[MMI\] ld16.nt1 r120,ar.csd=\[r20\]
+ 1d16: 80 07 50 8a 22 00 ld16.d2 r120,ar.csd=\[r20\]
+ 1d1c: 00 00 04 00 nop.i 0x0
+ 1d20: 08 c0 03 28 45 11 \[MMI\] ld16.d2 r120,ar.csd=\[r20\]
+ 1d26: 80 07 50 86 22 00 ld16.nt1 r120,ar.csd=\[r20\]
+ 1d2c: 00 00 04 00 nop.i 0x0
+ 1d30: 08 c0 03 28 43 11 \[MMI\] ld16.nt1 r120,ar.csd=\[r20\]
+ 1d36: 80 07 50 8a 22 00 ld16.d2 r120,ar.csd=\[r20\]
+ 1d3c: 00 00 04 00 nop.i 0x0
+ 1d40: 08 c0 03 28 45 11 \[MMI\] ld16.d2 r120,ar.csd=\[r20\]
+ 1d46: 80 07 50 8e 22 00 ld16.nta r120,ar.csd=\[r20\]
+ 1d4c: 00 00 04 00 nop.i 0x0
+ 1d50: 08 c0 03 28 47 11 \[MMI\] ld16.nta r120,ar.csd=\[r20\]
+ 1d56: 80 07 52 82 22 00 ld16.d4 r120,ar.csd=\[r20\]
+ 1d5c: 00 00 04 00 nop.i 0x0
+ 1d60: 08 c0 03 29 43 11 \[MMI\] ld16.d5 r120,ar.csd=\[r20\]
+ 1d66: 80 07 52 8a 22 00 ld16.d6 r120,ar.csd=\[r20\]
+ 1d6c: 00 00 04 00 nop.i 0x0
+ 1d70: 08 c0 03 29 47 11 \[MMI\] ld16.d7 r120,ar.csd=\[r20\]
+ 1d76: 80 07 50 8e 22 00 ld16.nta r120,ar.csd=\[r20\]
+ 1d7c: 00 00 04 00 nop.i 0x0
+ 1d80: 08 c0 03 28 47 11 \[MMI\] ld16.nta r120,ar.csd=\[r20\]
+ 1d86: 80 07 52 82 22 00 ld16.d4 r120,ar.csd=\[r20\]
+ 1d8c: 00 00 04 00 nop.i 0x0
+ 1d90: 08 c0 03 29 43 11 \[MMI\] ld16.d5 r120,ar.csd=\[r20\]
+ 1d96: 80 07 52 8a 22 00 ld16.d6 r120,ar.csd=\[r20\]
+ 1d9c: 00 00 04 00 nop.i 0x0
+ 1da0: 08 c0 03 29 47 11 \[MMI\] ld16.d7 r120,ar.csd=\[r20\]
+ 1da6: 80 07 50 c2 22 00 ld16.acq r120,ar.csd=\[r20\]
+ 1dac: 00 00 04 00 nop.i 0x0
+ 1db0: 08 c0 03 28 61 11 \[MMI\] ld16.acq r120,ar.csd=\[r20\]
+ 1db6: 80 07 50 c6 22 00 ld16.acq.nt1 r120,ar.csd=\[r20\]
+ 1dbc: 00 00 04 00 nop.i 0x0
+ 1dc0: 08 c0 03 28 63 11 \[MMI\] ld16.acq.nt1 r120,ar.csd=\[r20\]
+ 1dc6: 80 07 50 ca 22 00 ld16.acq.d2 r120,ar.csd=\[r20\]
+ 1dcc: 00 00 04 00 nop.i 0x0
+ 1dd0: 08 c0 03 28 65 11 \[MMI\] ld16.acq.d2 r120,ar.csd=\[r20\]
+ 1dd6: 80 07 50 c6 22 00 ld16.acq.nt1 r120,ar.csd=\[r20\]
+ 1ddc: 00 00 04 00 nop.i 0x0
+ 1de0: 08 c0 03 28 63 11 \[MMI\] ld16.acq.nt1 r120,ar.csd=\[r20\]
+ 1de6: 80 07 50 ca 22 00 ld16.acq.d2 r120,ar.csd=\[r20\]
+ 1dec: 00 00 04 00 nop.i 0x0
+ 1df0: 08 c0 03 28 65 11 \[MMI\] ld16.acq.d2 r120,ar.csd=\[r20\]
+ 1df6: 80 07 50 ce 22 00 ld16.acq.nta r120,ar.csd=\[r20\]
+ 1dfc: 00 00 04 00 nop.i 0x0
+ 1e00: 08 c0 03 28 67 11 \[MMI\] ld16.acq.nta r120,ar.csd=\[r20\]
+ 1e06: 80 07 52 c2 22 00 ld16.acq.d4 r120,ar.csd=\[r20\]
+ 1e0c: 00 00 04 00 nop.i 0x0
+ 1e10: 08 c0 03 29 63 11 \[MMI\] ld16.acq.d5 r120,ar.csd=\[r20\]
+ 1e16: 80 07 52 ca 22 00 ld16.acq.d6 r120,ar.csd=\[r20\]
+ 1e1c: 00 00 04 00 nop.i 0x0
+ 1e20: 08 c0 03 29 67 11 \[MMI\] ld16.acq.d7 r120,ar.csd=\[r20\]
+ 1e26: 80 07 50 ce 22 00 ld16.acq.nta r120,ar.csd=\[r20\]
+ 1e2c: 00 00 04 00 nop.i 0x0
+ 1e30: 08 c0 03 28 67 11 \[MMI\] ld16.acq.nta r120,ar.csd=\[r20\]
+ 1e36: 80 07 52 c2 22 00 ld16.acq.d4 r120,ar.csd=\[r20\]
+ 1e3c: 00 00 04 00 nop.i 0x0
+ 1e40: 08 c0 03 29 63 11 \[MMI\] ld16.acq.d5 r120,ar.csd=\[r20\]
+ 1e46: 80 07 52 ca 22 00 ld16.acq.d6 r120,ar.csd=\[r20\]
+ 1e4c: 00 00 04 00 nop.i 0x0
+ 1e50: 09 c0 03 29 67 11 \[MMI\] ld16.acq.d7 r120,ar.csd=\[r20\]
+ 1e56: 80 07 50 30 20 00 ld8 r120=\[r20\]
+ 1e5c: 00 00 04 00 nop.i 0x0;;
--- /dev/null
+
+ lfetch.count [r2], 1, 64
+ lfetch.count.d0 [r22], 5, -64
+ lfetch.count.nt1 [r23], 9, 1024-64
+ lfetch.count.d1 [r122], 12, -1024
+ lfetch.count.nt2 [r5], 16, 0x80
+ lfetch.count.d2 [r15], 20, -0x100
+ lfetch.count.nta [r125], 24, 512
+ lfetch.count.d3 [r8], 29, 960
+ lfetch.count.d4 [r18], 34, -0x400
+ lfetch.count.d5 [r127], 62, 0x3bf
+ lfetch.count.d6 [r10], 63, -0x3ff
+ lfetch.count.d7 [r96], 64, 0
+
+
+
+ tf.z p1,p2 = 32;;
+ tf.nz p7,p2 = @clz;;
+ tf.z.unc p3,p2 = @clz
+ tf.nz p3,p4 = @mpy
+ tf.z.and p5,p4 = @datahints
+ tf.nz.and p5,p6 = 35
+ tf.nz.andcm p5,p6 = 35
+ tf.z.or p7,p6 = 63
+ tf.nz.or p5,p6 = 35
+ tf.z.or.andcm p7,p6 = @mpy
+ tf.nz.or.andcm p7,p6 = @datahints
+ tf.z.and.orcm p7,p6 = @clz
+ tf.nz.and.orcm p7,p6 = @mpy
+
+
+ { .mib
+ tf.nz.unc p6,p0=33
+ nop.b 0 ;;
+ }
+ lfetch.d4 [r18]
+ { .mmi
+ lfetch.fault.excl.d7 [r19] ;;
+ lfetch.count [r14], 2, 128
+ sxt4 r8=r10
+ }
+ { .mmi
+ lfetch.count.d4 [r11], 64, 256;;
+ lfetch.excl.d5 [r17]
+ nop.i 0
+ }
+ { .mmi
+ lfetch.fault.d6 [r16] ;;
+ mov dahr7=7
+ clz r3=r9 ;;
+ }
+
+ mov dahr6=6
+ mpy4 r2=r9,r8
+ mpyshl4 r2=r9,r8
+
+ { .mmi
+ mov dahr5=5 ;;
+ mov dahr4=4
+ nop.i 0 ;;
+ }
+ { .mib
+ mov dahr3=3
+ add r8=r2,r3
+ nop.b 0 ;;
+ }
+ { .mmi
+ mov dahr2=2 ;;
+ mov dahr1=1
+ nop.i 0 ;;
+ }
+ { .mib
+ mov dahr0=0
+ nop.i 0
+ }
+ mov r12 = dahr[r5]
+ mov r122 = dahr[r55]
+
+ st1 [ r65 ] = r93
+ st1.d1 [ r65 ] = r93
+ st1.nt1 [ r65 ] = r93
+ st1.d2 [ r65 ] = r93
+ st1.nt2 [ r65 ] = r93
+ st1.nta [ r65 ] = r93
+ st1.d3 [ r65 ] = r93
+ st1.d4 [ r65 ] = r93
+ st1.d5 [ r65 ] = r93
+ st1.d6 [ r65 ] = r93
+ st1.d7 [ r65 ] = r93
+ st2 [ r65 ] = r93
+ st2.d1 [ r65 ] = r93
+ st2.nt1 [ r65 ] = r93
+ st2.d2 [ r65 ] = r93
+ st2.nt2 [ r65 ] = r93
+ st2.nta [ r65 ] = r93
+ st2.d3 [ r65 ] = r93
+ st2.d4 [ r65 ] = r93
+ st2.d5 [ r65 ] = r93
+ st2.d6 [ r65 ] = r93
+ st2.d7 [ r65 ] = r93
+ st4 [ r65 ] = r93
+ st4.d1 [ r65 ] = r93
+ st4.nt1 [ r65 ] = r93
+ st4.d2 [ r65 ] = r93
+ st4.nt2 [ r65 ] = r93
+ st4.nta [ r65 ] = r93
+ st4.d3 [ r65 ] = r93
+ st4.d4 [ r65 ] = r93
+ st4.d5 [ r65 ] = r93
+ st4.d6 [ r65 ] = r93
+ st4.d7 [ r65 ] = r93
+ st8 [ r65 ] = r93
+ st8.d1 [ r65 ] = r93
+ st8.nt1 [ r65 ] = r93
+ st8.d2 [ r65 ] = r93
+ st8.nt2 [ r65 ] = r93
+ st8.nta [ r65 ] = r93
+ st8.d3 [ r65 ] = r93
+ st8.d4 [ r65 ] = r93
+ st8.d5 [ r65 ] = r93
+ st8.d6 [ r65 ] = r93
+ st8.d7 [ r65 ] = r93
+ st16 [ r65 ] = r93
+ st16 [ r65 ] = r93
+ st16.d1 [ r65 ] = r93
+ st16.nt1 [ r65 ] = r93
+ st16.d2 [ r65 ] = r93
+ st16.nt2 [ r65 ] = r93
+ st16.nta [ r65 ] = r93
+ st16.d3 [ r65 ] = r93
+ st16.d4 [ r65 ] = r93
+ st16.d5 [ r65 ] = r93
+ st16.d6 [ r65 ] = r93
+ st16.d7 [ r65 ] = r93
+ st16.nta [ r65 ] = r93
+ st16.d3 [ r65 ] = r93
+ st16.d4 [ r65 ] = r93
+ st16.d5 [ r65 ] = r93
+ st16.d6 [ r65 ] = r93
+ st16.d7 [ r65 ] = r93
+ st1.rel [ r65 ] = r93
+ st1.rel.d1 [ r65 ] = r93
+ st1.rel.nt1 [ r65 ] = r93
+ st1.rel.d2 [ r65 ] = r93
+ st1.rel.nt2 [ r65 ] = r93
+ st1.rel.nta [ r65 ] = r93
+ st1.rel.d3 [ r65 ] = r93
+ st1.rel.d4 [ r65 ] = r93
+ st1.rel.d5 [ r65 ] = r93
+ st1.rel.d6 [ r65 ] = r93
+ st1.rel.d7 [ r65 ] = r93
+ st2.rel [ r65 ] = r93
+ st2.rel.d1 [ r65 ] = r93
+ st2.rel.nt1 [ r65 ] = r93
+ st2.rel.d2 [ r65 ] = r93
+ st2.rel.nt2 [ r65 ] = r93
+ st2.rel.nta [ r65 ] = r93
+ st2.rel.d3 [ r65 ] = r93
+ st2.rel.d4 [ r65 ] = r93
+ st2.rel.d5 [ r65 ] = r93
+ st2.rel.d6 [ r65 ] = r93
+ st2.rel.d7 [ r65 ] = r93
+ st4.rel [ r65 ] = r93
+ st4.rel.d1 [ r65 ] = r93
+ st4.rel.nt1 [ r65 ] = r93
+ st4.rel.d2 [ r65 ] = r93
+ st4.rel.nt2 [ r65 ] = r93
+ st4.rel.nta [ r65 ] = r93
+ st4.rel.d3 [ r65 ] = r93
+ st4.rel.d4 [ r65 ] = r93
+ st4.rel.d5 [ r65 ] = r93
+ st4.rel.d6 [ r65 ] = r93
+ st4.rel.d7 [ r65 ] = r93
+ st8.rel [ r65 ] = r93
+ st8.rel.d1 [ r65 ] = r93
+ st8.rel.nt1 [ r65 ] = r93
+ st8.rel.d2 [ r65 ] = r93
+ st8.rel.nt2 [ r65 ] = r93
+ st8.rel.nta [ r65 ] = r93
+ st8.rel.d3 [ r65 ] = r93
+ st8.rel.d4 [ r65 ] = r93
+ st8.rel.d5 [ r65 ] = r93
+ st8.rel.d6 [ r65 ] = r93
+ st8.rel.d7 [ r65 ] = r93
+ st16.rel [ r65 ] = r93
+ st16.rel [ r65 ] = r93, ar.csd
+ st16.rel.d1 [ r65 ] = r93
+ st16.rel.d1 [ r65 ] = r93, ar.csd
+ st16.rel.nt1 [ r65 ] = r93
+ st16.rel.nt1 [ r65 ] = r93, ar.csd
+ st16.rel.d2 [ r65 ] = r93
+ st16.rel.d2 [ r65 ] = r93, ar.csd
+ st16.rel.nt2 [ r65 ] = r93
+ st16.rel.nt2 [ r65 ] = r93, ar.csd
+ st16.rel.nta [ r65 ] = r93
+ st16.rel.d3 [ r65 ] = r93
+ st16.rel.d4 [ r65 ] = r93
+ st16.rel.d5 [ r65 ] = r93
+ st16.rel.d6 [ r65 ] = r93
+ st16.rel.d7 [ r65 ] = r93
+ st16.rel.nta [ r65 ] = r93, ar.csd
+ st16.rel.d3 [ r65 ] = r93, ar.csd
+ st16.rel.d4 [ r65 ] = r93, ar.csd
+ st16.rel.d5 [ r65 ] = r93, ar.csd
+ st16.rel.d6 [ r65 ] = r93, ar.csd
+ st16.rel.d7 [ r65 ] = r93, ar.csd
+ st8.spill [ r65 ] = r93
+ st8.spill.d1 [ r65 ] = r93
+ st8.spill.nt1 [ r65 ] = r93
+ st8.spill.d2 [ r65 ] = r93
+ st8.spill.nt2 [ r65 ] = r93
+ st8.spill.nta [ r65 ] = r93
+ st8.spill.d3 [ r65 ] = r93
+ st8.spill.d4 [ r65 ] = r93
+ st8.spill.d5 [ r65 ] = r93
+ st8.spill.d6 [ r65 ] = r93
+ st8.spill.d7 [ r65 ] = r93
+
+ lfetch [ r60 ]
+ lfetch.d1 [ r60 ]
+ lfetch.nt1 [ r60 ]
+ lfetch.d2 [ r60 ]
+ lfetch.nt2 [ r60 ]
+ lfetch.nta [ r60 ]
+ lfetch.d3 [ r60 ]
+ lfetch.d4 [ r60 ]
+ lfetch.d5 [ r60 ]
+ lfetch.d6 [ r60 ]
+ lfetch.d7 [ r60 ]
+
+
+ stfs [ r60 ] = f90
+ stfs.d1 [ r60 ] = f90
+ stfs.nt1 [ r60 ] = f90
+ stfs.d2 [ r60 ] = f90
+ stfs.nt2 [ r60 ] = f90
+ stfs.nta [ r60 ] = f90
+ stfs.d3 [ r60 ] = f90
+ stfs.d4 [ r60 ] = f90
+ stfs.d5 [ r60 ] = f90
+ stfs.d6 [ r60 ] = f90
+ stfs.d7 [ r60 ] = f90
+ stfd [ r60 ] = f90
+ stfd.d1 [ r60 ] = f90
+ stfd.nt1 [ r60 ] = f90
+ stfd.d2 [ r60 ] = f90
+ stfd.nt2 [ r60 ] = f90
+ stfd.nta [ r60 ] = f90
+ stfd.d3 [ r60 ] = f90
+ stfd.d4 [ r60 ] = f90
+ stfd.d5 [ r60 ] = f90
+ stfd.d6 [ r60 ] = f90
+ stfd.d7 [ r60 ] = f90
+ stf8 [ r60 ] = f90
+ stf8.d1 [ r60 ] = f90
+ stf8.nt1 [ r60 ] = f90
+ stf8.d2 [ r60 ] = f90
+ stf8.nt2 [ r60 ] = f90
+ stf8.nta [ r60 ] = f90
+ stf8.d3 [ r60 ] = f90
+ stf8.d4 [ r60 ] = f90
+ stf8.d5 [ r60 ] = f90
+ stf8.d6 [ r60 ] = f90
+ stf8.d7 [ r60 ] = f90
+ stfe [ r60 ] = f90
+ stfe.d1 [ r60 ] = f90
+ stfe.nt1 [ r60 ] = f90
+ stfe.d2 [ r60 ] = f90
+ stfe.nt2 [ r60 ] = f90
+ stfe.nta [ r60 ] = f90
+ stfe.d3 [ r60 ] = f90
+ stfe.d4 [ r60 ] = f90
+ stfe.d5 [ r60 ] = f90
+ stfe.d6 [ r60 ] = f90
+ stfe.d7 [ r60 ] = f90
+ stf.spill [ r60 ] = f90
+ stf.spill.d1 [ r60 ] = f90
+ stf.spill.nt1 [ r60 ] = f90
+ stf.spill.d2 [ r60 ] = f90
+ stf.spill.nt2 [ r60 ] = f90
+ stf.spill.nta [ r60 ] = f90
+ stf.spill.d3 [ r60 ] = f90
+ stf.spill.d4 [ r60 ] = f90
+ stf.spill.d5 [ r60 ] = f90
+ stf.spill.d6 [ r60 ] = f90
+ stf.spill.d7 [ r60 ] = f90
+
+
+ /* Floating-point load. */
+ ldfs f121 = [ r125 ]
+ ldfs.nt1 f121 = [ r125 ]
+ ldfs.d1 f121 = [ r125 ]
+ ldfs.d2 f121 = [ r125 ]
+ ldfs.nt2 f121 = [ r125 ]
+ ldfs.nta f121 = [ r125 ]
+ ldfs.d3 f121 = [ r125 ]
+ ldfs.d4 f121 = [ r125 ]
+ ldfs.d5 f121 = [ r125 ]
+ ldfs.d6 f121 = [ r125 ]
+ ldfs.d7 f121 = [ r125 ]
+ ldfd f121 = [ r125 ]
+ ldfd.nt1 f121 = [ r125 ]
+ ldfd.d1 f121 = [ r125 ]
+ ldfd.d2 f121 = [ r125 ]
+ ldfd.nt2 f121 = [ r125 ]
+ ldfd.nta f121 = [ r125 ]
+ ldfd.d3 f121 = [ r125 ]
+ ldfd.d4 f121 = [ r125 ]
+ ldfd.d5 f121 = [ r125 ]
+ ldfd.d6 f121 = [ r125 ]
+ ldfd.d7 f121 = [ r125 ]
+ ldf8 f121 = [ r125 ]
+ ldf8.nt1 f121 = [ r125 ]
+ ldf8.d1 f121 = [ r125 ]
+ ldf8.d2 f121 = [ r125 ]
+ ldf8.nt2 f121 = [ r125 ]
+ ldf8.nta f121 = [ r125 ]
+ ldf8.d3 f121 = [ r125 ]
+ ldf8.d4 f121 = [ r125 ]
+ ldf8.d5 f121 = [ r125 ]
+ ldf8.d6 f121 = [ r125 ]
+ ldf8.d7 f121 = [ r125 ]
+ ldfe f121 = [ r125 ]
+ ldfe.nt1 f121 = [ r125 ]
+ ldfe.d1 f121 = [ r125 ]
+ ldfe.d2 f121 = [ r125 ]
+ ldfe.nt2 f121 = [ r125 ]
+ ldfe.nta f121 = [ r125 ]
+ ldfe.d3 f121 = [ r125 ]
+ ldfe.d4 f121 = [ r125 ]
+ ldfe.d5 f121 = [ r125 ]
+ ldfe.d6 f121 = [ r125 ]
+ ldfe.d7 f121 = [ r125 ]
+ ldfs.s f121 = [ r125 ]
+ ldfs.s.nt1 f121 = [ r125 ]
+ ldfs.s.d1 f121 = [ r125 ]
+ ldfs.s.d2 f121 = [ r125 ]
+ ldfs.s.nt2 f121 = [ r125 ]
+ ldfs.s.nta f121 = [ r125 ]
+ ldfs.s.d3 f121 = [ r125 ]
+ ldfs.s.d4 f121 = [ r125 ]
+ ldfs.s.d5 f121 = [ r125 ]
+ ldfs.s.d6 f121 = [ r125 ]
+ ldfs.s.d7 f121 = [ r125 ]
+ ldfd.s f121 = [ r125 ]
+ ldfd.s.nt1 f121 = [ r125 ]
+ ldfd.s.d1 f121 = [ r125 ]
+ ldfd.s.d2 f121 = [ r125 ]
+ ldfd.s.nt2 f121 = [ r125 ]
+ ldfd.s.nta f121 = [ r125 ]
+ ldfd.s.d3 f121 = [ r125 ]
+ ldfd.s.d4 f121 = [ r125 ]
+ ldfd.s.d5 f121 = [ r125 ]
+ ldfd.s.d6 f121 = [ r125 ]
+ ldfd.s.d7 f121 = [ r125 ]
+ ldf8.s f121 = [ r125 ]
+ ldf8.s.nt1 f121 = [ r125 ]
+ ldf8.s.d1 f121 = [ r125 ]
+ ldf8.s.d2 f121 = [ r125 ]
+ ldf8.s.nt2 f121 = [ r125 ]
+ ldf8.s.nta f121 = [ r125 ]
+ ldf8.s.d3 f121 = [ r125 ]
+ ldf8.s.d4 f121 = [ r125 ]
+ ldf8.s.d5 f121 = [ r125 ]
+ ldf8.s.d6 f121 = [ r125 ]
+ ldf8.s.d7 f121 = [ r125 ]
+ ldfe.s f121 = [ r125 ]
+ ldfe.s.nt1 f121 = [ r125 ]
+ ldfe.s.d1 f121 = [ r125 ]
+ ldfe.s.d2 f121 = [ r125 ]
+ ldfe.s.nt2 f121 = [ r125 ]
+ ldfe.s.nta f121 = [ r125 ]
+ ldfe.s.d3 f121 = [ r125 ]
+ ldfe.s.d4 f121 = [ r125 ]
+ ldfe.s.d5 f121 = [ r125 ]
+ ldfe.s.d6 f121 = [ r125 ]
+ ldfe.s.d7 f121 = [ r125 ]
+ ldfs.a f121 = [ r125 ]
+ ldfs.a.nt1 f121 = [ r125 ]
+ ldfs.a.d1 f121 = [ r125 ]
+ ldfs.a.d2 f121 = [ r125 ]
+ ldfs.a.nt2 f121 = [ r125 ]
+ ldfs.a.nta f121 = [ r125 ]
+ ldfs.a.d3 f121 = [ r125 ]
+ ldfs.a.d4 f121 = [ r125 ]
+ ldfs.a.d5 f121 = [ r125 ]
+ ldfs.a.d6 f121 = [ r125 ]
+ ldfs.a.d7 f121 = [ r125 ]
+ ldfd.a f121 = [ r125 ]
+ ldfd.a.nt1 f121 = [ r125 ]
+ ldfd.a.d1 f121 = [ r125 ]
+ ldfd.a.d2 f121 = [ r125 ]
+ ldfd.a.nt2 f121 = [ r125 ]
+ ldfd.a.nta f121 = [ r125 ]
+ ldfd.a.d3 f121 = [ r125 ]
+ ldfd.a.d4 f121 = [ r125 ]
+ ldfd.a.d5 f121 = [ r125 ]
+ ldfd.a.d6 f121 = [ r125 ]
+ ldfd.a.d7 f121 = [ r125 ]
+ ldf8.a f121 = [ r125 ]
+ ldf8.a.nt1 f121 = [ r125 ]
+ ldf8.a.d1 f121 = [ r125 ]
+ ldf8.a.d2 f121 = [ r125 ]
+ ldf8.a.nt2 f121 = [ r125 ]
+ ldf8.a.nta f121 = [ r125 ]
+ ldf8.a.d3 f121 = [ r125 ]
+ ldf8.a.d4 f121 = [ r125 ]
+ ldf8.a.d5 f121 = [ r125 ]
+ ldf8.a.d6 f121 = [ r125 ]
+ ldf8.a.d7 f121 = [ r125 ]
+ ldfe.a f121 = [ r125 ]
+ ldfe.a.nt1 f121 = [ r125 ]
+ ldfe.a.d1 f121 = [ r125 ]
+ ldfe.a.d2 f121 = [ r125 ]
+ ldfe.a.nt2 f121 = [ r125 ]
+ ldfe.a.nta f121 = [ r125 ]
+ ldfe.a.d3 f121 = [ r125 ]
+ ldfe.a.d4 f121 = [ r125 ]
+ ldfe.a.d5 f121 = [ r125 ]
+ ldfe.a.d6 f121 = [ r125 ]
+ ldfe.a.d7 f121 = [ r125 ]
+ ldfs.sa f121 = [ r125 ]
+ ldfs.sa.nt1 f121 = [ r125 ]
+ ldfs.sa.d1 f121 = [ r125 ]
+ ldfs.sa.d2 f121 = [ r125 ]
+ ldfs.sa.nt2 f121 = [ r125 ]
+ ldfs.sa.nta f121 = [ r125 ]
+ ldfs.sa.d3 f121 = [ r125 ]
+ ldfs.sa.d4 f121 = [ r125 ]
+ ldfs.sa.d5 f121 = [ r125 ]
+ ldfs.sa.d6 f121 = [ r125 ]
+ ldfs.sa.d7 f121 = [ r125 ]
+ ldfd.sa f121 = [ r125 ]
+ ldfd.sa.nt1 f121 = [ r125 ]
+ ldfd.sa.d1 f121 = [ r125 ]
+ ldfd.sa.d2 f121 = [ r125 ]
+ ldfd.sa.nt2 f121 = [ r125 ]
+ ldfd.sa.nta f121 = [ r125 ]
+ ldfd.sa.d3 f121 = [ r125 ]
+ ldfd.sa.d4 f121 = [ r125 ]
+ ldfd.sa.d5 f121 = [ r125 ]
+ ldfd.sa.d6 f121 = [ r125 ]
+ ldfd.sa.d7 f121 = [ r125 ]
+ ldf8.sa f121 = [ r125 ]
+ ldf8.sa.nt1 f121 = [ r125 ]
+ ldf8.sa.d1 f121 = [ r125 ]
+ ldf8.sa.d2 f121 = [ r125 ]
+ ldf8.sa.nt2 f121 = [ r125 ]
+ ldf8.sa.nta f121 = [ r125 ]
+ ldf8.sa.d3 f121 = [ r125 ]
+ ldf8.sa.d4 f121 = [ r125 ]
+ ldf8.sa.d5 f121 = [ r125 ]
+ ldf8.sa.d6 f121 = [ r125 ]
+ ldf8.sa.d7 f121 = [ r125 ]
+ ldfe.sa f121 = [ r125 ]
+ ldfe.sa.nt1 f121 = [ r125 ]
+ ldfe.sa.d1 f121 = [ r125 ]
+ ldfe.sa.d2 f121 = [ r125 ]
+ ldfe.sa.nt2 f121 = [ r125 ]
+ ldfe.sa.nta f121 = [ r125 ]
+ ldfe.sa.d3 f121 = [ r125 ]
+ ldfe.sa.d4 f121 = [ r125 ]
+ ldfe.sa.d5 f121 = [ r125 ]
+ ldfe.sa.d6 f121 = [ r125 ]
+ ldfe.sa.d7 f121 = [ r125 ]
+ ldf.fill f121 = [ r125 ]
+ ldf.fill.nt1 f121 = [ r125 ]
+ ldf.fill.d1 f121 = [ r125 ]
+ ldf.fill.d2 f121 = [ r125 ]
+ ldf.fill.nt2 f121 = [ r125 ]
+ ldf.fill.nta f121 = [ r125 ]
+ ldf.fill.d3 f121 = [ r125 ]
+ ldf.fill.d4 f121 = [ r125 ]
+ ldf.fill.d5 f121 = [ r125 ]
+ ldf.fill.d6 f121 = [ r125 ]
+ ldf.fill.d7 f121 = [ r125 ]
+ ldfs.c.clr f121 = [ r125 ]
+ ldfs.c.clr.nt1 f121 = [ r125 ]
+ ldfs.c.clr.d1 f121 = [ r125 ]
+ ldfs.c.clr.d2 f121 = [ r125 ]
+ ldfs.c.clr.nt2 f121 = [ r125 ]
+ ldfs.c.clr.nta f121 = [ r125 ]
+ ldfs.c.clr.d3 f121 = [ r125 ]
+ ldfs.c.clr.d4 f121 = [ r125 ]
+ ldfs.c.clr.d5 f121 = [ r125 ]
+ ldfs.c.clr.d6 f121 = [ r125 ]
+ ldfs.c.clr.d7 f121 = [ r125 ]
+ ldfd.c.clr f121 = [ r125 ]
+ ldfd.c.clr.nt1 f121 = [ r125 ]
+ ldfd.c.clr.d1 f121 = [ r125 ]
+ ldfd.c.clr.d2 f121 = [ r125 ]
+ ldfd.c.clr.nt2 f121 = [ r125 ]
+ ldfd.c.clr.nta f121 = [ r125 ]
+ ldfd.c.clr.d3 f121 = [ r125 ]
+ ldfd.c.clr.d4 f121 = [ r125 ]
+ ldfd.c.clr.d5 f121 = [ r125 ]
+ ldfd.c.clr.d6 f121 = [ r125 ]
+ ldfd.c.clr.d7 f121 = [ r125 ]
+ ldf8.c.clr f121 = [ r125 ]
+ ldf8.c.clr.nt1 f121 = [ r125 ]
+ ldf8.c.clr.d1 f121 = [ r125 ]
+ ldf8.c.clr.d2 f121 = [ r125 ]
+ ldf8.c.clr.nt2 f121 = [ r125 ]
+ ldf8.c.clr.nta f121 = [ r125 ]
+ ldf8.c.clr.d3 f121 = [ r125 ]
+ ldf8.c.clr.d4 f121 = [ r125 ]
+ ldf8.c.clr.d5 f121 = [ r125 ]
+ ldf8.c.clr.d6 f121 = [ r125 ]
+ ldf8.c.clr.d7 f121 = [ r125 ]
+ ldfe.c.clr f121 = [ r125 ]
+ ldfe.c.clr.nt1 f121 = [ r125 ]
+ ldfe.c.clr.d1 f121 = [ r125 ]
+ ldfe.c.clr.d2 f121 = [ r125 ]
+ ldfe.c.clr.nt2 f121 = [ r125 ]
+ ldfe.c.clr.nta f121 = [ r125 ]
+ ldfe.c.clr.d3 f121 = [ r125 ]
+ ldfe.c.clr.d4 f121 = [ r125 ]
+ ldfe.c.clr.d5 f121 = [ r125 ]
+ ldfe.c.clr.d6 f121 = [ r125 ]
+ ldfe.c.clr.d7 f121 = [ r125 ]
+ ldfs.c.nc f121 = [ r125 ]
+ ldfs.c.nc.nt1 f121 = [ r125 ]
+ ldfs.c.nc.d1 f121 = [ r125 ]
+ ldfs.c.nc.d2 f121 = [ r125 ]
+ ldfs.c.nc.nt2 f121 = [ r125 ]
+ ldfs.c.nc.nta f121 = [ r125 ]
+ ldfs.c.nc.d3 f121 = [ r125 ]
+ ldfs.c.nc.d4 f121 = [ r125 ]
+ ldfs.c.nc.d5 f121 = [ r125 ]
+ ldfs.c.nc.d6 f121 = [ r125 ]
+ ldfs.c.nc.d7 f121 = [ r125 ]
+ ldfd.c.nc f121 = [ r125 ]
+ ldfd.c.nc.nt1 f121 = [ r125 ]
+ ldfd.c.nc.d1 f121 = [ r125 ]
+ ldfd.c.nc.d2 f121 = [ r125 ]
+ ldfd.c.nc.nt2 f121 = [ r125 ]
+ ldfd.c.nc.nta f121 = [ r125 ]
+ ldfd.c.nc.d3 f121 = [ r125 ]
+ ldfd.c.nc.d4 f121 = [ r125 ]
+ ldfd.c.nc.d5 f121 = [ r125 ]
+ ldfd.c.nc.d6 f121 = [ r125 ]
+ ldfd.c.nc.d7 f121 = [ r125 ]
+ ldf8.c.nc f121 = [ r125 ]
+ ldf8.c.nc.nt1 f121 = [ r125 ]
+ ldf8.c.nc.d1 f121 = [ r125 ]
+ ldf8.c.nc.d2 f121 = [ r125 ]
+ ldf8.c.nc.nt2 f121 = [ r125 ]
+ ldf8.c.nc.nta f121 = [ r125 ]
+ ldf8.c.nc.d3 f121 = [ r125 ]
+ ldf8.c.nc.d4 f121 = [ r125 ]
+ ldf8.c.nc.d5 f121 = [ r125 ]
+ ldf8.c.nc.d6 f121 = [ r125 ]
+ ldf8.c.nc.d7 f121 = [ r125 ]
+ ldfe.c.nc f121 = [ r125 ]
+ ldfe.c.nc.nt1 f121 = [ r125 ]
+ ldfe.c.nc.d1 f121 = [ r125 ]
+ ldfe.c.nc.d2 f121 = [ r125 ]
+ ldfe.c.nc.nt2 f121 = [ r125 ]
+ ldfe.c.nc.nta f121 = [ r125 ]
+ ldfe.c.nc.d3 f121 = [ r125 ]
+ ldfe.c.nc.d4 f121 = [ r125 ]
+ ldfe.c.nc.d5 f121 = [ r125 ]
+ ldfe.c.nc.d6 f121 = [ r125 ]
+ ldfe.c.nc.d7 f121 = [ r125 ]
+
+
+
+
+ ld1 r120 = [ r20 ]
+ ld1.nt1 r120 = [ r20 ]
+ ld1.d1 r120 = [ r20 ]
+ ld1.d2 r120 = [ r20 ]
+ ld1.nt2 r120 = [ r20 ]
+ ld1.nta r120 = [ r20 ]
+ ld1.d3 r120 = [ r20 ]
+ ld1.d4 r120 = [ r20 ]
+ ld1.d5 r120 = [ r20 ]
+ ld1.d6 r120 = [ r20 ]
+ ld1.d7 r120 = [ r20 ]
+ ld2 r120 = [ r20 ]
+ ld2.nt1 r120 = [ r20 ]
+ ld2.d1 r120 = [ r20 ]
+ ld2.d2 r120 = [ r20 ]
+ ld2.nt2 r120 = [ r20 ]
+ ld2.nta r120 = [ r20 ]
+ ld2.d3 r120 = [ r20 ]
+ ld2.d4 r120 = [ r20 ]
+ ld2.d5 r120 = [ r20 ]
+ ld2.d6 r120 = [ r20 ]
+ ld2.d7 r120 = [ r20 ]
+ ld4 r120 = [ r20 ]
+ ld4.nt1 r120 = [ r20 ]
+ ld4.d1 r120 = [ r20 ]
+ ld4.d2 r120 = [ r20 ]
+ ld4.nt2 r120 = [ r20 ]
+ ld4.nta r120 = [ r20 ]
+ ld4.d3 r120 = [ r20 ]
+ ld4.d4 r120 = [ r20 ]
+ ld4.d5 r120 = [ r20 ]
+ ld4.d6 r120 = [ r20 ]
+ ld4.d7 r120 = [ r20 ]
+ ld8 r120 = [ r20 ]
+ ld8.nt1 r120 = [ r20 ]
+ ld8.d1 r120 = [ r20 ]
+ ld8.d2 r120 = [ r20 ]
+ ld8.nt2 r120 = [ r20 ]
+ ld8.nta r120 = [ r20 ]
+ ld8.d3 r120 = [ r20 ]
+ ld8.d4 r120 = [ r20 ]
+ ld8.d5 r120 = [ r20 ]
+ ld8.d6 r120 = [ r20 ]
+ ld8.d7 r120 = [ r20 ]
+ ld1.s r120 = [ r20 ]
+ ld1.s.nt1 r120 = [ r20 ]
+ ld1.s.d1 r120 = [ r20 ]
+ ld1.s.d2 r120 = [ r20 ]
+ ld1.s.nt2 r120 = [ r20 ]
+ ld1.s.nta r120 = [ r20 ]
+ ld1.s.d3 r120 = [ r20 ]
+ ld1.s.d4 r120 = [ r20 ]
+ ld1.s.d5 r120 = [ r20 ]
+ ld1.s.d6 r120 = [ r20 ]
+ ld1.s.d7 r120 = [ r20 ]
+ ld2.s r120 = [ r20 ]
+ ld2.s.nt1 r120 = [ r20 ]
+ ld2.s.d1 r120 = [ r20 ]
+ ld2.s.d2 r120 = [ r20 ]
+ ld2.s.nt2 r120 = [ r20 ]
+ ld2.s.nta r120 = [ r20 ]
+ ld2.s.d3 r120 = [ r20 ]
+ ld2.s.d4 r120 = [ r20 ]
+ ld2.s.d5 r120 = [ r20 ]
+ ld2.s.d6 r120 = [ r20 ]
+ ld2.s.d7 r120 = [ r20 ]
+ ld4.s r120 = [ r20 ]
+ ld4.s.nt1 r120 = [ r20 ]
+ ld4.s.d1 r120 = [ r20 ]
+ ld4.s.d2 r120 = [ r20 ]
+ ld4.s.nt2 r120 = [ r20 ]
+ ld4.s.nta r120 = [ r20 ]
+ ld4.s.d3 r120 = [ r20 ]
+ ld4.s.d4 r120 = [ r20 ]
+ ld4.s.d5 r120 = [ r20 ]
+ ld4.s.d6 r120 = [ r20 ]
+ ld4.s.d7 r120 = [ r20 ]
+ ld8.s r120 = [ r20 ]
+ ld8.s.nt1 r120 = [ r20 ]
+ ld8.s.d1 r120 = [ r20 ]
+ ld8.s.d2 r120 = [ r20 ]
+ ld8.s.nt2 r120 = [ r20 ]
+ ld8.s.nta r120 = [ r20 ]
+ ld8.s.d3 r120 = [ r20 ]
+ ld8.s.d4 r120 = [ r20 ]
+ ld8.s.d5 r120 = [ r20 ]
+ ld8.s.d6 r120 = [ r20 ]
+ ld8.s.d7 r120 = [ r20 ]
+ ld1.a r120 = [ r20 ]
+ ld1.a.nt1 r120 = [ r20 ]
+ ld1.a.d1 r120 = [ r20 ]
+ ld1.a.d2 r120 = [ r20 ]
+ ld1.a.nt2 r120 = [ r20 ]
+ ld1.a.nta r120 = [ r20 ]
+ ld1.a.d3 r120 = [ r20 ]
+ ld1.a.d4 r120 = [ r20 ]
+ ld1.a.d5 r120 = [ r20 ]
+ ld1.a.d6 r120 = [ r20 ]
+ ld1.a.d7 r120 = [ r20 ]
+ ld2.a r120 = [ r20 ]
+ ld2.a.nt1 r120 = [ r20 ]
+ ld2.a.d1 r120 = [ r20 ]
+ ld2.a.nt2 r120 = [ r20 ]
+ ld2.a.nta r120 = [ r20 ]
+ ld2.a.d3 r120 = [ r20 ]
+ ld2.a.d4 r120 = [ r20 ]
+ ld2.a.d5 r120 = [ r20 ]
+ ld2.a.d6 r120 = [ r20 ]
+ ld2.a.d7 r120 = [ r20 ]
+ ld4.a r120 = [ r20 ]
+ ld4.a.nt1 r120 = [ r20 ]
+ ld4.a.d1 r120 = [ r20 ]
+ ld4.a.d2 r120 = [ r20 ]
+ ld4.a.nt2 r120 = [ r20 ]
+ ld4.a.nta r120 = [ r20 ]
+ ld4.a.d3 r120 = [ r20 ]
+ ld4.a.d4 r120 = [ r20 ]
+ ld4.a.d5 r120 = [ r20 ]
+ ld4.a.d6 r120 = [ r20 ]
+ ld4.a.d7 r120 = [ r20 ]
+ ld8.a r120 = [ r20 ]
+ ld8.a.nt1 r120 = [ r20 ]
+ ld8.a.d1 r120 = [ r20 ]
+ ld8.a.d2 r120 = [ r20 ]
+ ld8.a.nt2 r120 = [ r20 ]
+ ld8.a.nta r120 = [ r20 ]
+ ld8.a.d3 r120 = [ r20 ]
+ ld8.a.d5 r120 = [ r20 ]
+ ld8.a.d6 r120 = [ r20 ]
+ ld8.a.d7 r120 = [ r20 ]
+ ld1.sa r120 = [ r20 ]
+ ld1.sa.nt1 r120 = [ r20 ]
+ ld1.sa.d1 r120 = [ r20 ]
+ ld1.sa.d2 r120 = [ r20 ]
+ ld1.sa.nt2 r120 = [ r20 ]
+ ld1.sa.nta r120 = [ r20 ]
+ ld1.sa.d3 r120 = [ r20 ]
+ ld1.sa.d4 r120 = [ r20 ]
+ ld1.sa.d5 r120 = [ r20 ]
+ ld1.sa.d6 r120 = [ r20 ]
+ ld1.sa.d7 r120 = [ r20 ]
+ ld2.sa r120 = [ r20 ]
+ ld2.sa.nt1 r120 = [ r20 ]
+ ld2.sa.d1 r120 = [ r20 ]
+ ld2.sa.d2 r120 = [ r20 ]
+ ld2.sa.nt2 r120 = [ r20 ]
+ ld2.sa.nta r120 = [ r20 ]
+ ld2.sa.d3 r120 = [ r20 ]
+ ld2.sa.d4 r120 = [ r20 ]
+ ld2.sa.d5 r120 = [ r20 ]
+ ld2.sa.d6 r120 = [ r20 ]
+ ld2.sa.d7 r120 = [ r20 ]
+ ld4.sa.nt1 r120 = [ r20 ]
+ ld4.sa.d1 r120 = [ r20 ]
+ ld4.sa.d2 r120 = [ r20 ]
+ ld4.sa.nt2 r120 = [ r20 ]
+ ld4.sa.nta r120 = [ r20 ]
+ ld4.sa.d3 r120 = [ r20 ]
+ ld4.sa.d4 r120 = [ r20 ]
+ ld4.sa.d5 r120 = [ r20 ]
+ ld4.sa.d6 r120 = [ r20 ]
+ ld4.sa.d7 r120 = [ r20 ]
+ ld8.sa r120 = [ r20 ]
+ ld8.sa.nt1 r120 = [ r20 ]
+ ld8.sa.d1 r120 = [ r20 ]
+ ld8.sa.d2 r120 = [ r20 ]
+ ld8.sa.nt2 r120 = [ r20 ]
+ ld8.sa.nta r120 = [ r20 ]
+ ld8.sa.d3 r120 = [ r20 ]
+ ld8.sa.d4 r120 = [ r20 ]
+ ld8.sa.d5 r120 = [ r20 ]
+ ld8.sa.d6 r120 = [ r20 ]
+ ld8.sa.d7 r120 = [ r20 ]
+ ld1.bias r120 = [ r20 ]
+ ld1.bias.nt1 r120 = [ r20 ]
+ ld1.bias.d1 r120 = [ r20 ]
+ ld1.bias.d2 r120 = [ r20 ]
+ ld1.bias.nt2 r120 = [ r20 ]
+ ld1.bias.nta r120 = [ r20 ]
+ ld1.bias.d3 r120 = [ r20 ]
+ ld1.bias.d4 r120 = [ r20 ]
+ ld1.bias.d5 r120 = [ r20 ]
+ ld1.bias.d6 r120 = [ r20 ]
+ ld1.bias.d7 r120 = [ r20 ]
+ ld2.bias r120 = [ r20 ]
+ ld2.bias.nt1 r120 = [ r20 ]
+ ld2.bias.d1 r120 = [ r20 ]
+ ld2.bias.d2 r120 = [ r20 ]
+ ld2.bias.nt2 r120 = [ r20 ]
+ ld2.bias.nta r120 = [ r20 ]
+ ld2.bias.d3 r120 = [ r20 ]
+ ld2.bias.d4 r120 = [ r20 ]
+ ld2.bias.d5 r120 = [ r20 ]
+ ld2.bias.d6 r120 = [ r20 ]
+ ld2.bias.d7 r120 = [ r20 ]
+ ld4.bias r120 = [ r20 ]
+ ld4.bias.nt1 r120 = [ r20 ]
+ ld4.bias.d1 r120 = [ r20 ]
+ ld4.bias.d2 r120 = [ r20 ]
+ ld4.bias.nt2 r120 = [ r20 ]
+ ld4.bias.nta r120 = [ r20 ]
+ ld4.bias.d3 r120 = [ r20 ]
+ ld4.bias.d4 r120 = [ r20 ]
+ ld4.bias.d5 r120 = [ r20 ]
+ ld4.bias.d6 r120 = [ r20 ]
+ ld4.bias.d7 r120 = [ r20 ]
+ ld8.bias r120 = [ r20 ]
+ ld8.bias.nt1 r120 = [ r20 ]
+ ld8.bias.d1 r120 = [ r20 ]
+ ld8.bias.d2 r120 = [ r20 ]
+ ld8.bias.nt2 r120 = [ r20 ]
+ ld8.bias.nta r120 = [ r20 ]
+ ld8.bias.d3 r120 = [ r20 ]
+ ld8.bias.d4 r120 = [ r20 ]
+ ld8.bias.d5 r120 = [ r20 ]
+ ld8.bias.d6 r120 = [ r20 ]
+ ld8.bias.d7 r120 = [ r20 ]
+ ld1.acq r120 = [ r20 ]
+ ld1.acq.nt1 r120 = [ r20 ]
+ ld1.acq.d1 r120 = [ r20 ]
+ ld1.acq.d2 r120 = [ r20 ]
+ ld1.acq.nt2 r120 = [ r20 ]
+ ld1.acq.nta r120 = [ r20 ]
+ ld1.acq.d3 r120 = [ r20 ]
+ ld1.acq.d4 r120 = [ r20 ]
+ ld1.acq.d5 r120 = [ r20 ]
+ ld1.acq.d6 r120 = [ r20 ]
+ ld2.acq r120 = [ r20 ]
+ ld2.acq.nt1 r120 = [ r20 ]
+ ld2.acq.d1 r120 = [ r20 ]
+ ld2.acq.d2 r120 = [ r20 ]
+ ld2.acq.nt2 r120 = [ r20 ]
+ ld2.acq.nta r120 = [ r20 ]
+ ld2.acq.d3 r120 = [ r20 ]
+ ld2.acq.d4 r120 = [ r20 ]
+ ld2.acq.d5 r120 = [ r20 ]
+ ld2.acq.d6 r120 = [ r20 ]
+ ld2.acq.d7 r120 = [ r20 ]
+ ld4.acq r120 = [ r20 ]
+ ld4.acq.nt1 r120 = [ r20 ]
+ ld4.acq.d1 r120 = [ r20 ]
+ ld4.acq.d2 r120 = [ r20 ]
+ ld4.acq.nt2 r120 = [ r20 ]
+ ld4.acq.nta r120 = [ r20 ]
+ ld4.acq.d3 r120 = [ r20 ]
+ ld4.acq.d4 r120 = [ r20 ]
+ ld4.acq.d5 r120 = [ r20 ]
+ ld4.acq.d6 r120 = [ r20 ]
+ ld4.acq.d7 r120 = [ r20 ]
+ ld8.acq r120 = [ r20 ]
+ ld8.acq.nt1 r120 = [ r20 ]
+ ld8.acq.d1 r120 = [ r20 ]
+ ld8.acq.d2 r120 = [ r20 ]
+ ld8.acq.nt2 r120 = [ r20 ]
+ ld8.acq.nta r120 = [ r20 ]
+ ld8.acq.d3 r120 = [ r20 ]
+ ld8.acq.d4 r120 = [ r20 ]
+ ld8.acq.d5 r120 = [ r20 ]
+ ld8.acq.d6 r120 = [ r20 ]
+ ld8.acq.d7 r120 = [ r20 ]
+ ld8.fill r120 = [ r20 ]
+ ld8.fill.nt1 r120 = [ r20 ]
+ ld8.fill.d1 r120 = [ r20 ]
+ ld8.fill.d2 r120 = [ r20 ]
+ ld8.fill.nt2 r120 = [ r20 ]
+ ld8.fill.nta r120 = [ r20 ]
+ ld8.fill.d3 r120 = [ r20 ]
+ ld8.fill.d4 r120 = [ r20 ]
+ ld8.fill.d5 r120 = [ r20 ]
+ ld8.fill.d6 r120 = [ r20 ]
+ ld8.fill.d7 r120 = [ r20 ]
+ ld1.c.clr r120 = [ r20 ]
+ ld1.c.clr.nt1 r120 = [ r20 ]
+ ld1.c.clr.d1 r120 = [ r20 ]
+ ld1.c.clr.d2 r120 = [ r20 ]
+ ld1.c.clr.nt2 r120 = [ r20 ]
+ ld1.c.clr.nta r120 = [ r20 ]
+ ld1.c.clr.d3 r120 = [ r20 ]
+ ld1.c.clr.d4 r120 = [ r20 ]
+ ld1.c.clr.d5 r120 = [ r20 ]
+ ld1.c.clr.d6 r120 = [ r20 ]
+ ld1.c.clr.d7 r120 = [ r20 ]
+ ld2.c.clr r120 = [ r20 ]
+ ld2.c.clr.nt1 r120 = [ r20 ]
+ ld2.c.clr.d1 r120 = [ r20 ]
+ ld2.c.clr.d2 r120 = [ r20 ]
+ ld2.c.clr.nt2 r120 = [ r20 ]
+ ld2.c.clr.nta r120 = [ r20 ]
+ ld2.c.clr.d3 r120 = [ r20 ]
+ ld2.c.clr.d4 r120 = [ r20 ]
+ ld2.c.clr.d5 r120 = [ r20 ]
+ ld2.c.clr.d6 r120 = [ r20 ]
+ ld2.c.clr.d7 r120 = [ r20 ]
+ ld4.c.clr r120 = [ r20 ]
+ ld4.c.clr.nt1 r120 = [ r20 ]
+ ld4.c.clr.d1 r120 = [ r20 ]
+ ld4.c.clr.d2 r120 = [ r20 ]
+ ld4.c.clr.nt2 r120 = [ r20 ]
+ ld4.c.clr.nta r120 = [ r20 ]
+ ld4.c.clr.d3 r120 = [ r20 ]
+ ld4.c.clr.d4 r120 = [ r20 ]
+ ld4.c.clr.d5 r120 = [ r20 ]
+ ld4.c.clr.d6 r120 = [ r20 ]
+ ld4.c.clr.d7 r120 = [ r20 ]
+ ld8.c.clr r120 = [ r20 ]
+ ld8.c.clr.nt1 r120 = [ r20 ]
+ ld8.c.clr.d1 r120 = [ r20 ]
+ ld8.c.clr.d2 r120 = [ r20 ]
+ ld8.c.clr.nt2 r120 = [ r20 ]
+ ld8.c.clr.nta r120 = [ r20 ]
+ ld8.c.clr.d3 r120 = [ r20 ]
+ ld8.c.clr.d4 r120 = [ r20 ]
+ ld8.c.clr.d5 r120 = [ r20 ]
+ ld8.c.clr.d6 r120 = [ r20 ]
+ ld8.c.clr.d7 r120 = [ r20 ]
+ ld1.c.nc r120 = [ r20 ]
+ ld1.c.nc.nt1 r120 = [ r20 ]
+ ld1.c.nc.d1 r120 = [ r20 ]
+ ld1.c.nc.d2 r120 = [ r20 ]
+ ld1.c.nc.nt2 r120 = [ r20 ]
+ ld1.c.nc.nta r120 = [ r20 ]
+ ld1.c.nc.d3 r120 = [ r20 ]
+ ld1.c.nc.d4 r120 = [ r20 ]
+ ld1.c.nc.d5 r120 = [ r20 ]
+ ld1.c.nc.d7 r120 = [ r20 ]
+ ld2.c.nc r120 = [ r20 ]
+ ld2.c.nc.nt1 r120 = [ r20 ]
+ ld2.c.nc.d1 r120 = [ r20 ]
+ ld2.c.nc.d2 r120 = [ r20 ]
+ ld2.c.nc.nt2 r120 = [ r20 ]
+ ld2.c.nc.nta r120 = [ r20 ]
+ ld2.c.nc.d3 r120 = [ r20 ]
+ ld2.c.nc.d4 r120 = [ r20 ]
+ ld2.c.nc.d5 r120 = [ r20 ]
+ ld2.c.nc.d6 r120 = [ r20 ]
+ ld2.c.nc.d7 r120 = [ r20 ]
+ ld4.c.nc r120 = [ r20 ]
+ ld4.c.nc.nt1 r120 = [ r20 ]
+ ld4.c.nc.d1 r120 = [ r20 ]
+ ld4.c.nc.d2 r120 = [ r20 ]
+ ld4.c.nc.nt2 r120 = [ r20 ]
+ ld4.c.nc.nta r120 = [ r20 ]
+ ld4.c.nc.d3 r120 = [ r20 ]
+ ld4.c.nc.d4 r120 = [ r20 ]
+ ld4.c.nc.d5 r120 = [ r20 ]
+ ld4.c.nc.d6 r120 = [ r20 ]
+ ld4.c.nc.d7 r120 = [ r20 ]
+ ld8.c.nc r120 = [ r20 ]
+ ld8.c.nc.nt1 r120 = [ r20 ]
+ ld8.c.nc.d1 r120 = [ r20 ]
+ ld8.c.nc.d2 r120 = [ r20 ]
+ ld8.c.nc.nt2 r120 = [ r20 ]
+ ld8.c.nc.nta r120 = [ r20 ]
+ ld8.c.nc.d3 r120 = [ r20 ]
+ ld8.c.nc.d4 r120 = [ r20 ]
+ ld8.c.nc.d5 r120 = [ r20 ]
+ ld8.c.nc.d6 r120 = [ r20 ]
+ ld8.c.nc.d7 r120 = [ r20 ]
+ ld1.c.clr.acq r120 = [ r20 ]
+ ld1.c.clr.acq.nt1 r120 = [ r20 ]
+ ld1.c.clr.acq.d1 r120 = [ r20 ]
+ ld1.c.clr.acq.d2 r120 = [ r20 ]
+ ld1.c.clr.acq.nt2 r120 = [ r20 ]
+ ld1.c.clr.acq.nta r120 = [ r20 ]
+ ld1.c.clr.acq.d3 r120 = [ r20 ]
+ ld1.c.clr.acq.d4 r120 = [ r20 ]
+ ld1.c.clr.acq.d5 r120 = [ r20 ]
+ ld1.c.clr.acq.d6 r120 = [ r20 ]
+ ld1.c.clr.acq.d7 r120 = [ r20 ]
+ ld2.c.clr.acq r120 = [ r20 ]
+ ld2.c.clr.acq.nt1 r120 = [ r20 ]
+ ld2.c.clr.acq.d1 r120 = [ r20 ]
+ ld2.c.clr.acq.d2 r120 = [ r20 ]
+ ld2.c.clr.acq.nt2 r120 = [ r20 ]
+ ld2.c.clr.acq.d3 r120 = [ r20 ]
+ ld2.c.clr.acq.d4 r120 = [ r20 ]
+ ld2.c.clr.acq.d5 r120 = [ r20 ]
+ ld2.c.clr.acq.d6 r120 = [ r20 ]
+ ld2.c.clr.acq.d7 r120 = [ r20 ]
+ ld4.c.clr.acq r120 = [ r20 ]
+ ld4.c.clr.acq.nt1 r120 = [ r20 ]
+ ld4.c.clr.acq.d1 r120 = [ r20 ]
+ ld4.c.clr.acq.d2 r120 = [ r20 ]
+ ld4.c.clr.acq.nt2 r120 = [ r20 ]
+ ld4.c.clr.acq.nta r120 = [ r20 ]
+ ld4.c.clr.acq.d3 r120 = [ r20 ]
+ ld4.c.clr.acq.d4 r120 = [ r20 ]
+ ld4.c.clr.acq.d5 r120 = [ r20 ]
+ ld4.c.clr.acq.d6 r120 = [ r20 ]
+ ld4.c.clr.acq.d7 r120 = [ r20 ]
+ ld8.c.clr.acq r120 = [ r20 ]
+ ld8.c.clr.acq.nt1 r120 = [ r20 ]
+ ld8.c.clr.acq.d1 r120 = [ r20 ]
+ ld8.c.clr.acq.d2 r120 = [ r20 ]
+ ld8.c.clr.acq.nt2 r120 = [ r20 ]
+ ld8.c.clr.acq.nta r120 = [ r20 ]
+ ld8.c.clr.acq.d3 r120 = [ r20 ]
+ ld8.c.clr.acq.d4 r120 = [ r20 ]
+ ld8.c.clr.acq.d5 r120 = [ r20 ]
+ ld8.c.clr.acq.d6 r120 = [ r20 ]
+ ld8.c.clr.acq.d7 r120 = [ r20 ]
+ ld16 r120 = [ r20 ]
+ ld16 r120 = [ r20 ]
+ ld16.nt1 r120 = [ r20 ]
+ ld16.d1 r120 = [ r20 ]
+ ld16.d2 r120 = [ r20 ]
+ ld16.nt2 r120 = [ r20 ]
+ ld16.nt1 r120 = [ r20 ]
+ ld16.d1 r120 = [ r20 ]
+ ld16.d2 r120 = [ r20 ]
+ ld16.nt2 r120 = [ r20 ]
+ ld16.nta r120 = [ r20 ]
+ ld16.d3 r120 = [ r20 ]
+ ld16.d4 r120 = [ r20 ]
+ ld16.d5 r120 = [ r20 ]
+ ld16.d6 r120 = [ r20 ]
+ ld16.d7 r120 = [ r20 ]
+ ld16.nta r120 = [ r20 ]
+ ld16.d3 r120 = [ r20 ]
+ ld16.d4 r120 = [ r20 ]
+ ld16.d5 r120 = [ r20 ]
+ ld16.d6 r120 = [ r20 ]
+ ld16.d7 r120 = [ r20 ]
+ ld16.acq r120 = [ r20 ]
+ ld16.acq r120, ar.csd = [ r20 ]
+ ld16.acq.nt1 r120 = [ r20 ]
+ ld16.acq.d1 r120 = [ r20 ]
+ ld16.acq.d2 r120, ar.csd = [ r20 ]
+ ld16.acq.nt2 r120 = [ r20 ]
+ ld16.acq.nt1 r120 = [ r20 ]
+ ld16.acq.d1 r120 = [ r20 ]
+ ld16.acq.d2 r120 = [ r20 ]
+ ld16.acq.nt2 r120 = [ r20 ]
+ ld16.acq.nta r120 = [ r20 ]
+ ld16.acq.d3 r120 = [ r20 ]
+ ld16.acq.d4 r120 = [ r20 ]
+ ld16.acq.d5 r120 = [ r20 ]
+ ld16.acq.d6 r120 = [ r20 ]
+ ld16.acq.d7 r120 = [ r20 ]
+ ld16.acq.nta r120, ar.csd = [ r20 ]
+ ld16.acq.d3 r120 = [ r20 ]
+ ld16.acq.d4 r120 = [ r20 ]
+ ld16.acq.d5 r120 = [ r20 ]
+ ld16.acq.d6 r120 = [ r20 ]
+ ld16.acq.d7 r120 = [ r20 ]
+
+ /* Pseudo-op that generates ldxmov relocation. */
+ ld8.mov r120 = [ r20 ], AAAAA
+AAAAA:
+
--- /dev/null
+# No warnings or errors expected!
--- /dev/null
+ .set micromips
+ .text
+foo:
+ .rept count
+ ori $2, $3, (. - foo) >> 2
+ .endr
+ addu $2, $3, $4
+ j ext
-#as: -64 -EB
+#as: -march=from-abi -64 -EB
#objdump: -sj.eh_frame
.*
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF got reloc n32
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
.*: +file format elf32-n.*mips.*
b .Lfn2
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
.end fn
.globl __start
__start:
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+
.data
.align 2
sp2:
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF got reloc n64
-#as: -64 -KPIC
+#as: -march=from-abi -64 -KPIC
.*: +file format elf64-.*mips.*
ld $5,dl2+34($5)
b .Lfn2
-# Force at least 8 (non-deddlay-slot) zero bytes, to make 'objdump' print ...
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
.end fn
.globl __start
__start:
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
.data
.align 3
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF xgot reloc n32
-#as: -n32 -KPIC -xgot
+#as: -march=from-abi -n32 -KPIC -xgot
#source: elf-rel-got-n32.s
.*: +file format elf32-n.*mips.*
000005f0 <fn\+0x5f0> 10000003 b 00000600 <fn2>
000005f4 <fn\+0x5f4> 00000000 nop
\.\.\.
+ \.\.\.
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF xgot reloc n64
-#as: -64 -KPIC -xgot
+#as: -march=from-abi -64 -KPIC -xgot
#source: elf-rel-got-n64.s
.*: +file format elf64-.*mips.*
00000000000005f0 <fn\+0x5f0> 10000003 b 0000000000000600 <fn2>
00000000000005f4 <fn\+0x5f4> 00000000 nop
\.\.\.
+ \.\.\.
#readelf: --relocs
-#as: -mabi=n32 -KPIC
+#as: -march=from-abi -mabi=n32 -KPIC
Relocation section '\.rela\.text' at offset .* contains 4 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
.*: R_MIPS_SUB \*ABS\*
.*: R_MIPS_LO16 \*ABS\*
.*: 0384e02d daddu \$28,\$28,\$4
+ \.\.\.
foo:
.cpsetup $4,$5,foo
.end foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
.*: R_MIPS_SUB \*ABS\*
.*: R_MIPS_LO16 \*ABS\*
.*: 0384e02d daddu \$28,\$28,\$4
+ \.\.\.
.*: R_MIPS_HI16 __gnu_local_gp
.*: 279c0000 addiu \$28,\$28,0
.*: R_MIPS_LO16 __gnu_local_gp
-.*: 00000000 nop
+ \.\.\.
#source: elf-rel28.s
-#as: -n32
+#as: -march=from-abi -n32
#objdump: -dr
#name: MIPS ELF reloc 28 (n32)
.*: R_MIPS_TLS_TPREL_LO16 bar
.*: fc840000 sd a0,0\(a0\)
.*: R_MIPS_TLS_GOTTPREL bar
- ...
+ \.\.\.
#source: elf-rel28.s
-#as: -64
+#as: -march=from-abi -64
#objdump: -dr
#name: MIPS ELF reloc 28 (n64)
sd $4,%tprel_lo(bar)($4)
sd $4,%gottprel(bar)($4)
.end foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS ELF NewABI jal
-#as: -n32 -KPIC -xgot
+#as: -march=from-abi -n32 -KPIC -xgot
.*: +file format elf32-n.*mips.*
#objdump: -d
-#as: -KPIC -64
+#as: -march=from-abi -KPIC -64
#name: MIPS ld-st-la constants (ABI n64, shared)
#source: ldstla-n64.s
#objdump: -dr
-#as: -64 -msym32 -G8 -EB
+#as: -march=from-abi -64 -msym32 -G8 -EB
#name: MIPS ld-st-la with sym32
#source: ldstla-sym32.s
#objdump: -d
-#as: -64
+#as: -march=from-abi -64
#name: MIPS ld-st-la constants (ABI n64)
#source: ldstla-n64.s
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
#source: macro-warn-1.s
#stderr: macro-warn-1-n32.l
#objdump: -p
-#as: -n32 -KPIC
+#as: -march=from-abi -n32 -KPIC
#source: macro-warn-2.s
#objdump: -p
#pass
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE for MIPS32
+#as: -mdsp -32
+#source: mips32-dsp.s
+
+# Check MIPS DSP ASE for MIPS32 Instruction Assembly (microMIPS)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 0041 000d addq\.ph zero,at,v0
+0+0004 <[^>]*> 0062 0c0d addq_s\.ph at,v0,v1
+0+0008 <[^>]*> 0083 1305 addq_s\.w v0,v1,a0
+0+000c <[^>]*> 00a4 18cd addu\.qb v1,a0,a1
+0+0010 <[^>]*> 00c5 24cd addu_s\.qb a0,a1,a2
+0+0014 <[^>]*> 00e6 2a0d subq\.ph a1,a2,a3
+0+0018 <[^>]*> 0107 360d subq_s\.ph a2,a3,t0
+0+001c <[^>]*> 0128 3b45 subq_s\.w a3,t0,t1
+0+0020 <[^>]*> 0149 42cd subu\.qb t0,t1,t2
+0+0024 <[^>]*> 016a 4ecd subu_s\.qb t1,t2,t3
+0+0028 <[^>]*> 018b 5385 addsc t2,t3,t4
+0+002c <[^>]*> 01ac 5bc5 addwc t3,t4,t5
+0+0030 <[^>]*> 01cd 6295 modsub t4,t5,t6
+0+0034 <[^>]*> 01ae f13c raddu\.w\.qb t5,t6
+0+0038 <[^>]*> 01cf 113c absq_s\.ph t6,t7
+0+003c <[^>]*> 01f0 213c absq_s\.w t7,s0
+0+0040 <[^>]*> 0251 80ad precrq\.qb\.ph s0,s1,s2
+0+0044 <[^>]*> 0272 88ed precrq\.ph\.w s1,s2,s3
+0+0048 <[^>]*> 0293 912d precrq_rs\.ph\.w s2,s3,s4
+0+004c <[^>]*> 02b4 996d precrqu_s\.qb\.ph s3,s4,s5
+0+0050 <[^>]*> 0295 513c preceq\.w\.phl s4,s5
+0+0054 <[^>]*> 02b6 613c preceq\.w\.phr s5,s6
+0+0058 <[^>]*> 02d7 713c precequ\.ph\.qbl s6,s7
+0+005c <[^>]*> 02f8 913c precequ\.ph\.qbr s7,t8
+0+0060 <[^>]*> 0319 733c precequ\.ph\.qbla t8,t9
+0+0064 <[^>]*> 033a 933c precequ\.ph\.qbra t9,k0
+0+0068 <[^>]*> 035b b13c preceu\.ph\.qbl k0,k1
+0+006c <[^>]*> 037c d13c preceu\.ph\.qbr k1,gp
+0+0070 <[^>]*> 039d b33c preceu\.ph\.qbla gp,sp
+0+0074 <[^>]*> 03be d33c preceu\.ph\.qbra sp,s8
+0+0078 <[^>]*> 03df 087c shll\.qb s8,ra,0x0
+0+007c <[^>]*> 03df e87c shll\.qb s8,ra,0x7
+0+0080 <[^>]*> 0001 fb95 shllv\.qb ra,zero,at
+0+0084 <[^>]*> 0001 03b5 shll\.ph zero,at,0x0
+0+0088 <[^>]*> 0001 f3b5 shll\.ph zero,at,0xf
+0+008c <[^>]*> 0043 0b8d shllv\.ph at,v0,v1
+0+0090 <[^>]*> 0043 0bb5 shll_s\.ph v0,v1,0x0
+0+0094 <[^>]*> 0043 fbb5 shll_s\.ph v0,v1,0xf
+0+0098 <[^>]*> 0085 1f8d shllv_s\.ph v1,a0,a1
+0+009c <[^>]*> 0085 03f5 shll_s\.w a0,a1,0x0
+0+00a0 <[^>]*> 0085 fbf5 shll_s\.w a0,a1,0x1f
+0+00a4 <[^>]*> 00c7 2bd5 shllv_s\.w a1,a2,a3
+0+00a8 <[^>]*> 00c7 187c shrl\.qb a2,a3,0x0
+0+00ac <[^>]*> 00c7 f87c shrl\.qb a2,a3,0x7
+0+00b0 <[^>]*> 0109 3b55 shrlv\.qb a3,t0,t1
+0+00b4 <[^>]*> 0109 0335 shra\.ph t0,t1,0x0
+0+00b8 <[^>]*> 0109 f335 shra\.ph t0,t1,0xf
+0+00bc <[^>]*> 014b 498d shrav\.ph t1,t2,t3
+0+00c0 <[^>]*> 014b 0735 shra_r\.ph t2,t3,0x0
+0+00c4 <[^>]*> 014b f735 shra_r\.ph t2,t3,0xf
+0+00c8 <[^>]*> 018d 5d8d shrav_r\.ph t3,t4,t5
+0+00cc <[^>]*> 018d 02f5 shra_r\.w t4,t5,0x0
+0+00d0 <[^>]*> 018d faf5 shra_r\.w t4,t5,0x1f
+0+00d4 <[^>]*> 01cf 6ad5 shrav_r\.w t5,t6,t7
+0+00d8 <[^>]*> 020f 7095 muleu_s\.ph\.qbl t6,t7,s0
+0+00dc <[^>]*> 0230 78d5 muleu_s\.ph\.qbr t7,s0,s1
+0+00e0 <[^>]*> 0251 8115 mulq_rs\.ph s0,s1,s2
+0+00e4 <[^>]*> 0272 8825 muleq_s\.w\.phl s1,s2,s3
+0+00e8 <[^>]*> 0293 9065 muleq_s\.w\.phr s2,s3,s4
+0+00ec <[^>]*> 0293 20bc dpau\.h\.qbl \$ac0,s3,s4
+0+00f0 <[^>]*> 02b4 70bc dpau\.h\.qbr \$ac1,s4,s5
+0+00f4 <[^>]*> 02d5 a4bc dpsu\.h\.qbl \$ac2,s5,s6
+0+00f8 <[^>]*> 02f6 f4bc dpsu\.h\.qbr \$ac3,s6,s7
+0+00fc <[^>]*> 0317 02bc dpaq_s\.w\.ph \$ac0,s7,t8
+0+0100 <[^>]*> 0338 46bc dpsq_s\.w\.ph \$ac1,t8,t9
+0+0104 <[^>]*> 0359 bcbc mulsaq_s\.w\.ph \$ac2,t9,k0
+0+0108 <[^>]*> 037a d2bc dpaq_sa.l\.w \$ac3,k0,k1
+0+010c <[^>]*> 039b 16bc dpsq_sa.l\.w \$ac0,k1,gp
+0+0110 <[^>]*> 03bc 5a7c maq_s\.w\.phl \$ac1,gp,sp
+0+0114 <[^>]*> 03dd 8a7c maq_s\.w\.phr \$ac2,sp,s8
+0+0118 <[^>]*> 03fe fa7c maq_sa\.w\.phl \$ac3,s8,ra
+0+011c <[^>]*> 001f 2a7c maq_sa\.w\.phr \$ac0,ra,zero
+0+0120 <[^>]*> 0001 313c bitrev zero,at
+0+0124 <[^>]*> 0022 413c insv at,v0
+0+0128 <[^>]*> 0040 05fc repl\.qb v0,0x0
+0+012c <[^>]*> 005f e5fc repl\.qb v0,0xff
+0+0130 <[^>]*> 0064 133c replv\.qb v1,a0
+0+0134 <[^>]*> 0200 203d repl\.ph a0,-512
+0+0138 <[^>]*> 01ff 203d repl\.ph a0,511
+0+013c <[^>]*> 00a6 033c replv\.ph a1,a2
+0+0140 <[^>]*> 00e6 0245 cmpu\.eq\.qb a2,a3
+0+0144 <[^>]*> 0107 0285 cmpu\.lt\.qb a3,t0
+0+0148 <[^>]*> 0128 02c5 cmpu\.le\.qb t0,t1
+0+014c <[^>]*> 016a 48c5 cmpgu\.eq\.qb t1,t2,t3
+0+0150 <[^>]*> 018b 5105 cmpgu\.lt\.qb t2,t3,t4
+0+0154 <[^>]*> 01ac 5945 cmpgu\.le\.qb t3,t4,t5
+0+0158 <[^>]*> 01ac 0005 cmp\.eq\.ph t4,t5
+0+015c <[^>]*> 01cd 0045 cmp\.lt\.ph t5,t6
+0+0160 <[^>]*> 01ee 0085 cmp\.le\.ph t6,t7
+0+0164 <[^>]*> 0230 79ed pick\.qb t7,s0,s1
+0+0168 <[^>]*> 0251 822d pick\.ph s0,s1,s2
+0+016c <[^>]*> 0272 89ad packrl\.ph s1,s2,s3
+0+0170 <[^>]*> 0240 4e7c extr\.w s2,\$ac1,0x0
+0+0174 <[^>]*> 025f 4e7c extr\.w s2,\$ac1,0x1f
+0+0178 <[^>]*> 0260 9e7c extr_r\.w s3,\$ac2,0x0
+0+017c <[^>]*> 027f 9e7c extr_r\.w s3,\$ac2,0x1f
+0+0180 <[^>]*> 0280 ee7c extr_rs\.w s4,\$ac3,0x0
+0+0184 <[^>]*> 029f ee7c extr_rs\.w s4,\$ac3,0x1f
+0+0188 <[^>]*> 02a0 3e7c extr_s\.h s5,\$ac0,0x0
+0+018c <[^>]*> 02bf 3e7c extr_s\.h s5,\$ac0,0x1f
+0+0190 <[^>]*> 02d7 7ebc extrv_s\.h s6,\$ac1,s7
+0+0194 <[^>]*> 02f8 8ebc extrv\.w s7,\$ac2,t8
+0+0198 <[^>]*> 0319 debc extrv_r\.w t8,\$ac3,t9
+0+019c <[^>]*> 033a 2ebc extrv_rs\.w t9,\$ac0,k0
+0+01a0 <[^>]*> 0340 667c extp k0,\$ac1,0x0
+0+01a4 <[^>]*> 035f 667c extp k0,\$ac1,0x1f
+0+01a8 <[^>]*> 037c a8bc extpv k1,\$ac2,gp
+0+01ac <[^>]*> 0380 f67c extpdp gp,\$ac3,0x0
+0+01b0 <[^>]*> 039f f67c extpdp gp,\$ac3,0x1f
+0+01b4 <[^>]*> 03be 38bc extpdpv sp,\$ac0,s8
+0+01b8 <[^>]*> 0020 401d shilo \$ac1,-32
+0+01bc <[^>]*> 001f 401d shilo \$ac1,31
+0+01c0 <[^>]*> 001e 927c shilov \$ac2,s8
+0+01c4 <[^>]*> 001f c27c mthlip ra,\$ac3
+0+01c8 <[^>]*> 0000 007c mfhi zero,\$ac0
+0+01cc <[^>]*> 0001 507c mflo at,\$ac1
+0+01d0 <[^>]*> 0002 a07c mthi v0,\$ac2
+0+01d4 <[^>]*> 0003 f07c mtlo v1,\$ac3
+0+01d8 <[^>]*> 0080 167c wrdsp a0,0x0
+0+01dc <[^>]*> 008f d67c wrdsp a0
+0+01e0 <[^>]*> 00af d67c wrdsp a1
+0+01e4 <[^>]*> 00c0 067c rddsp a2,0x0
+0+01e8 <[^>]*> 00cf c67c rddsp a2
+0+01ec <[^>]*> 00ef c67c rddsp a3
+0+01f0 <[^>]*> 012a 4225 lbux t0,t1\(t2\)
+0+01f4 <[^>]*> 014b 4965 lhx t1,t2\(t3\)
+0+01f8 <[^>]*> 016c 51a5 lwx t2,t3\(t4\)
+0+01fc <[^>]*> 4360 fffe bposge32 000001fc <text_label\+0x1fc>
+ 1fc: R_MICROMIPS_PC16_S1 text_label
+0+0200 <[^>]*> 0c00 nop
+0+0202 <[^>]*> 018b 8abc madd \$ac2,t3,t4
+0+0206 <[^>]*> 01ac dabc maddu \$ac3,t4,t5
+0+020a <[^>]*> 01cd 2abc msub \$ac0,t5,t6
+0+020e <[^>]*> 01ee 7abc msubu \$ac1,t6,t7
+0+0212 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6
+0+0216 <[^>]*> 02f6 1cbc multu \$ac0,s6,s7
+0+021a <[^>]*> 0c00 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev2 for MIPS32
+#as: -mdspr2 -32
+#source: mips32-dspr2.s
+
+# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly (microMIPS)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 0001 013c absq_s\.qb zero,at
+0+0004 <[^>]*> 0062 090d addu\.ph at,v0,v1
+0+0008 <[^>]*> 0083 150d addu_s\.ph v0,v1,a0
+0+000c <[^>]*> 00a4 194d adduh\.qb v1,a0,a1
+0+0010 <[^>]*> 00c5 254d adduh_r\.qb a0,a1,a2
+0+0014 <[^>]*> 00a6 0215 append a1,a2,0x0
+0+0018 <[^>]*> 00a6 fa15 append a1,a2,0x1f
+0+001c <[^>]*> 0c00 nop
+0+001e <[^>]*> 00c7 48bc balign a2,a3,0x1
+0+0022 <[^>]*> 00e6 31ad packrl\.ph a2,a2,a3
+0+0026 <[^>]*> 00c7 c8bc balign a2,a3,0x3
+0+002a <[^>]*> 0107 3185 cmpgdu\.eq\.qb a2,a3,t0
+0+002e <[^>]*> 0128 39c5 cmpgdu\.lt\.qb a3,t0,t1
+0+0032 <[^>]*> 0149 4205 cmpgdu\.le\.qb t0,t1,t2
+0+0036 <[^>]*> 0149 00bc dpa\.w\.ph \$ac0,t1,t2
+0+003a <[^>]*> 016a 44bc dps\.w\.ph \$ac1,t2,t3
+0+003e <[^>]*> 018b 8abc madd \$ac2,t3,t4
+0+0042 <[^>]*> 01ac dabc maddu \$ac3,t4,t5
+0+0046 <[^>]*> 01cd 2abc msub \$ac0,t5,t6
+0+004a <[^>]*> 01ee 7abc msubu \$ac1,t6,t7
+0+004e <[^>]*> 0230 782d mul\.ph t7,s0,s1
+0+0052 <[^>]*> 0251 842d mul_s\.ph s0,s1,s2
+0+0056 <[^>]*> 0272 8995 mulq_rs\.w s1,s2,s3
+0+005a <[^>]*> 0293 9155 mulq_s\.ph s2,s3,s4
+0+005e <[^>]*> 02b4 99d5 mulq_s\.w s3,s4,s5
+0+0062 <[^>]*> 02b4 acbc mulsa\.w\.ph \$ac2,s4,s5
+0+0066 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6
+0+006a <[^>]*> 02f6 1cbc multu \$ac0,s6,s7
+0+006e <[^>]*> 0338 b86d precr\.qb\.ph s7,t8,t9
+0+0072 <[^>]*> 0319 03cd precr_sra\.ph\.w t8,t9,0x0
+0+0076 <[^>]*> 0319 fbcd precr_sra\.ph\.w t8,t9,0x1f
+0+007a <[^>]*> 033a 07cd precr_sra_r\.ph\.w t9,k0,0x0
+0+007e <[^>]*> 033a ffcd precr_sra_r\.ph\.w t9,k0,0x1f
+0+0082 <[^>]*> 035b 0255 prepend k0,k1,0x0
+0+0086 <[^>]*> 035b fa55 prepend k0,k1,0x1f
+0+008a <[^>]*> 037c 01fc shra\.qb k1,gp,0x0
+0+008e <[^>]*> 037c e1fc shra\.qb k1,gp,0x7
+0+0092 <[^>]*> 039d 11fc shra_r\.qb gp,sp,0x0
+0+0096 <[^>]*> 039d f1fc shra_r\.qb gp,sp,0x7
+0+009a <[^>]*> 03df e9cd shrav\.qb sp,s8,ra
+0+009e <[^>]*> 03e0 f5cd shrav_r\.qb s8,ra,zero
+0+00a2 <[^>]*> 03e0 03fc shrl\.ph ra,zero,0x0
+0+00a6 <[^>]*> 03e0 f3fc shrl\.ph ra,zero,0xf
+0+00aa <[^>]*> 0022 0315 shrlv\.ph zero,at,v0
+0+00ae <[^>]*> 0062 0b0d subu\.ph at,v0,v1
+0+00b2 <[^>]*> 0083 170d subu_s\.ph v0,v1,a0
+0+00b6 <[^>]*> 00a4 1b4d subuh\.qb v1,a0,a1
+0+00ba <[^>]*> 00c5 274d subuh_r\.qb a0,a1,a2
+0+00be <[^>]*> 00e6 284d addqh\.ph a1,a2,a3
+0+00c2 <[^>]*> 0107 344d addqh_r\.ph a2,a3,t0
+0+00c6 <[^>]*> 0128 388d addqh\.w a3,t0,t1
+0+00ca <[^>]*> 0149 448d addqh_r\.w t0,t1,t2
+0+00ce <[^>]*> 016a 4a4d subqh\.ph t1,t2,t3
+0+00d2 <[^>]*> 018b 564d subqh_r\.ph t2,t3,t4
+0+00d6 <[^>]*> 01ac 5a8d subqh\.w t3,t4,t5
+0+00da <[^>]*> 01cd 668d subqh_r\.w t4,t5,t6
+0+00de <[^>]*> 01cd 50bc dpax\.w\.ph \$ac1,t5,t6
+0+00e2 <[^>]*> 01ee 94bc dpsx\.w\.ph \$ac2,t6,t7
+0+00e6 <[^>]*> 020f e2bc dpaqx_s\.w\.ph \$ac3,t7,s0
+0+00ea <[^>]*> 0230 32bc dpaqx_sa\.w\.ph \$ac0,s0,s1
+0+00ee <[^>]*> 0251 66bc dpsqx_s\.w\.ph \$ac1,s1,s2
+0+00f2 <[^>]*> 0272 b6bc dpsqx_sa\.w\.ph \$ac2,s2,s3
+0+00f6 <[^>]*> 0c00 nop
+ \.\.\.
set ecoff [expr [istarget *-*-ecoff*] || [istarget *-*-ultrix*] || [istarget *-*-irix\[1-4\]*] ]
set aout [expr [istarget *-*-bsd*] || [istarget *-*-openbsd*] ]
set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*] || [istarget mips*-*-ecoff]]
- set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
+ set has_newabi [expr [istarget *-*-irix6*] || [istarget mips*-*-linux*] || [istarget mips*-sde-elf*]]
set no_mips16 [expr !$elf]
set no_micromips [expr !$elf]
run_dump_test_arches "branch-misc-2pic-64" [mips_arch_list_matching mips3]
run_dump_test "branch-misc-3"
run_dump_test "branch-swap"
+
+ if $elf {
+ # Sweep a range of branch offsets so that it hits a position where
+ # it is at the beginning of a frag and then swapped with a 16-bit
+ # instruction from the preceding frag. The offset will be somewhere
+ # close below 4096 as this is the default obstack size limit that
+ # we use and some space will have been already consumed. The exact
+ # amount depends on the host's programming model.
+ for { set count 960 } { $count <= 1024 } { incr count } {
+ run_list_test "branch-swap-2" "--defsym count=$count" \
+ "MIPS branch swapping ($count)"
+ }
+ }
+
run_dump_test "div"
if { !$addr32 } {
-#as: -n32
+#as: -march=from-abi -n32
#objdump: -Dr --prefix-addresses
#name: n32 consecutive unrelated relocations
.text
.long .
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+
.data
.long .+4
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
+2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (mips_opcode): Add the exclusions field.
+ (OPCODE_IS_MEMBER): Remove macro.
+ (cpu_is_member): New inline function.
+ (opcode_is_member): Likewise.
+
2012-07-31 Chao-Ying Fu <fu@mips.com>
Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
#ifndef _MIPS_H_
#define _MIPS_H_
+#include "bfd.h"
+
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
+ /* A collection of bits describing the instruction sets of which this
+ instruction or macro is not a member. */
+ unsigned long exclusions;
};
/* These are the characters which may appear in the args field of an
#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */
+/* Return true if the given CPU is included in INSN_* mask MASK. */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+ switch (cpu)
+ {
+ case CPU_R4650:
+ case CPU_RM7000:
+ case CPU_RM9000:
+ return (mask & INSN_4650) != 0;
+
+ case CPU_R4010:
+ return (mask & INSN_4010) != 0;
+
+ case CPU_VR4100:
+ return (mask & INSN_4100) != 0;
+
+ case CPU_R3900:
+ return (mask & INSN_3900) != 0;
+
+ case CPU_R10000:
+ case CPU_R12000:
+ case CPU_R14000:
+ case CPU_R16000:
+ return (mask & INSN_10000) != 0;
+
+ case CPU_SB1:
+ return (mask & INSN_SB1) != 0;
+
+ case CPU_R4111:
+ return (mask & INSN_4111) != 0;
+
+ case CPU_VR4120:
+ return (mask & INSN_4120) != 0;
+
+ case CPU_VR5400:
+ return (mask & INSN_5400) != 0;
+
+ case CPU_VR5500:
+ return (mask & INSN_5500) != 0;
+
+ case CPU_LOONGSON_2E:
+ return (mask & INSN_LOONGSON_2E) != 0;
+
+ case CPU_LOONGSON_2F:
+ return (mask & INSN_LOONGSON_2F) != 0;
+
+ case CPU_LOONGSON_3A:
+ return (mask & INSN_LOONGSON_3A) != 0;
+
+ case CPU_OCTEON:
+ return (mask & INSN_OCTEON) != 0;
+
+ case CPU_OCTEONP:
+ return (mask & INSN_OCTEONP) != 0;
+
+ case CPU_OCTEON2:
+ return (mask & INSN_OCTEON2) != 0;
+
+ case CPU_XLR:
+ return (mask & INSN_XLR) != 0;
+
+ default:
+ return FALSE;
+ }
+}
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
- test, or zero if no CPU specific ISA test is desired. */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu) \
- (((isa & INSN_ISA_MASK) != 0 \
- && ((insn)->membership & INSN_ISA_MASK) != 0 \
- && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
- (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
- || ((isa & ~INSN_ISA_MASK) \
- & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
- || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
- || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
- || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
- || cpu == CPU_R16000) \
- && ((insn)->membership & INSN_10000) != 0) \
- || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
- || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
- || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
- || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
- || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || (cpu == CPU_LOONGSON_2E \
- && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
- || (cpu == CPU_LOONGSON_2F \
- && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
- || (cpu == CPU_LOONGSON_3A \
- && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
- || (cpu == CPU_OCTEON \
- && ((insn)->membership & INSN_OCTEON) != 0) \
- || (cpu == CPU_OCTEONP \
- && ((insn)->membership & INSN_OCTEONP) != 0) \
- || (cpu == CPU_OCTEON2 \
- && ((insn)->membership & INSN_OCTEON2) != 0) \
- || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
- || 0) /* Please keep this term for easier source merging. */
+ test, or zero if no CPU specific ISA test is desired. Return true
+ if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+{
+ if (!cpu_is_member (cpu, insn->exclusions))
+ {
+ /* Test for ISA level compatibility. */
+ if ((isa & INSN_ISA_MASK) != 0
+ && (insn->membership & INSN_ISA_MASK) != 0
+ && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+ >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+ return TRUE;
+
+ /* Test for ASE compatibility. */
+ if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+ return TRUE;
+
+ /* Test for processor-specific extensions. */
+ if (cpu_is_member (cpu, insn->membership))
+ return TRUE;
+ }
+ return FALSE;
+}
/* This is a list of macro expanded instructions.
+ * emulparams/elf32bmip.sh: Make _gp hidden.
+ * emulparams/elf32bmipn32-defs.sh: Likewise.
+ * emulparams/elf32mipswindiss.sh: Likewise.
+ * scripttempl/mips.sc: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ldexp.h (etree_union): Add defsym member to the assign member
+ structure.
+ (exp_assign): Add hidden argument to prototype.
+ * ldexp.c (exp_fold_tree_1): Use the defsym member to handle
+ --defsym symbols.
+ (exp_assop): Add defsym argument, initialize the defsym member
+ of the assign structure.
+ (exp_assign): Handle hidden symbols.
+ (exp_defsym): Update to use the defsym argument to exp_assop.
+ (exp_provide): Update to handle the defsym argument to exp_assop.
+ * ldlex.l (HIDDEN): New token.
+ * ldgram.y (HIDDEN): Likewise.
+ (assignment, section): Update calls to exp_assign.
+ * ldctor.c (ldctor_build_sets): Likewise.
+ * mri.c (mri_format): Likewise.
+ * ldlang.c (lang_insert_orphan, lang_leave_overlay): Likewise.
+ (open_input_bfds): Remove --defsym symbols special case.
+ * emultempl/beos.em (gld_${EMULATION_NAME}_set_symbols): Update
+ call to exp_assign.
+ * emultempl/pe.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
+ * emultempl/pep.em (gld_${EMULATION_NAME}_set_symbols): Likewise.
+ * emultempl/spuelf.em (spu_place_special_section): Likewise.
+ * emultempl/xtensaelf.em (ld_xtensa_insert_page_offsets):
+ Likewise.
+ * ld.texinfo (Assigning Values to Symbols): Add HIDDEN.
+ (HIDDEN): New subsection.
+
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
# of .got.
OTHER_GOT_SYMBOLS='
. = .;
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
'
# .got.plt is only used for the PLT psABI extension. It should not be
# included in the .sdata block with .got, as there is no need to access
# of .got.
OTHER_GOT_SYMBOLS='
. = .;
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
'
# .got.plt is only used for the PLT psABI extension. It should not be
# included in the .sdata block with .got, as there is no need to access
# the Diab linker.
TEXT_START_ADDR=0x100000
DATA_START_SYMBOLS='__DATA_ROM = .; __DATA_RAM = .;'
-SDATA_START_SYMBOLS='_SDA_BASE_ = .; _gp = . + 0x7ff0;'
+SDATA_START_SYMBOLS='_SDA_BASE_ = .; HIDDEN (_gp = . + 0x7ff0);'
SDATA2_START_SYMBOLS='_SDA2_BASE_ = .;'
EXECUTABLE_SYMBOLS='__HEAP_START = .; __SP_INIT = 0x800000; __SP_END = __SP_INIT - 0x20000; __HEAP_END = __SP_END; __DATA_END = _edata; __BSS_START = __bss_start; __BSS_END = _end; __HEAP_START = _end;'
for (j = 0; init[j].ptr; j++)
{
long val = init[j].value;
- lang_add_assignment (exp_assign (init[j].symbol, exp_intop (val)));
+ lang_add_assignment (exp_assign (init[j].symbol, exp_intop (val),
+ FALSE));
if (init[j].size == sizeof(short))
*(short *)init[j].ptr = val;
else if (init[j].size == sizeof(int))
lang_assignment_statement_type *rv;
rv = lang_add_assignment (exp_assign (GET_INIT_SYMBOL_NAME (j),
- exp_intop (val)));
+ exp_intop (val), FALSE));
if (init[j].size == sizeof (short))
*(short *) init[j].ptr = val;
else if (init[j].size == sizeof (int))
= pe_def_file->base_address;
init[IMAGEBASEOFF].inited = 1;
if (image_base_statement)
- image_base_statement->exp = exp_assign ("__image_base__",
- exp_intop (pe.ImageBase));
+ image_base_statement->exp
+ = exp_assign ("__image_base__", exp_intop (pe.ImageBase),
+ FALSE);
}
if (pe_def_file->stack_reserve != -1
lang_assignment_statement_type *rv;
rv = lang_add_assignment (exp_assign (GET_INIT_SYMBOL_NAME (j),
- exp_intop (val)));
+ exp_intop (val), FALSE));
if (init[j].size == sizeof (short))
*(short *) init[j].ptr = (short) val;
else if (init[j].size == sizeof (int))
= pep_def_file->base_address;
init[IMAGEBASEOFF].inited = 1;
if (image_base_statement)
- image_base_statement->exp = exp_assign ("__image_base__",
- exp_intop (pep.ImageBase));
+ image_base_statement->exp
+ = exp_assign ("__image_base__", exp_intop (pep.ImageBase),
+ FALSE);
}
if (pep_def_file->stack_reserve != -1
push_stat_ptr (&os->children);
e_size = exp_intop (params.line_size - s->size);
- lang_add_assignment (exp_assign (".", e_size));
+ lang_add_assignment (exp_assign (".", e_size, FALSE));
pop_stat_ptr ();
}
lang_add_section (&os->children, s, NULL, os);
etree_type *name_op = exp_nameop (NAME, ".");
etree_type *addend_op = exp_intop (1 << xtensa_page_power);
etree_type *add_op = exp_binop ('+', name_op, addend_op);
- etree_type *assign_op = exp_assign (".", add_op);
+ etree_type *assign_op = exp_assign (".", add_op, FALSE);
lang_assignment_statement_type *assign_stmt;
lang_statement_union_type *assign_union;
@menu
* Simple Assignments:: Simple Assignments
+* HIDDEN:: HIDDEN
* PROVIDE:: PROVIDE
* PROVIDE_HIDDEN:: PROVIDE_HIDDEN
* Source Code Reference:: How to use a linker script defined symbol in source code
defined as the address following the @samp{.text} output section aligned
upward to a 4 byte boundary.
+@node HIDDEN
+@subsection HIDDEN
+@cindex HIDDEN
+For ELF targeted ports, define a symbol that will be hidden and won't be
+exported. The syntax is @code{HIDDEN(@var{symbol} = @var{expression})}.
+
+Here is the example from @ref{Simple Assignments}, rewritten to use
+@code{HIDDEN}:
+
+@smallexample
+HIDDEN(floating_point = 0);
+SECTIONS
+@{
+ .text :
+ @{
+ *(.text)
+ HIDDEN(_etext = .);
+ @}
+ HIDDEN(_bdata = (. + 3) & ~ 3);
+ .data : @{ *(.data) @}
+@}
+@end smallexample
+@noindent
+In this case none of the three symbols will be visible outside this module.
+
@node PROVIDE
@subsection PROVIDE
@cindex PROVIDE
lang_add_assignment (exp_assign (".",
exp_unop (ALIGN_K,
- exp_intop (reloc_size))));
+ exp_intop (reloc_size)),
+ FALSE));
lang_add_assignment (exp_assign (p->h->root.string,
- exp_nameop (NAME, ".")));
+ exp_nameop (NAME, "."),
+ FALSE));
lang_add_data (size, exp_intop (p->count));
for (e = p->elements; e != NULL; e = e->next)
if (expld.result.valid_p
|| (expld.phase <= lang_mark_phase_enum
&& tree->type.node_class == etree_assign
- && tree->assign.hidden))
+ && tree->assign.defsym))
{
if (h == NULL)
{
exp_assop (const char *dst,
etree_type *src,
enum node_tree_enum class,
+ bfd_boolean defsym,
bfd_boolean hidden)
{
etree_type *n;
n->assign.type.node_class = class;
n->assign.src = src;
n->assign.dst = dst;
+ n->assign.defsym = defsym;
n->assign.hidden = hidden;
return n;
}
+/* Handle linker script assignments and HIDDEN. */
+
etree_type *
-exp_assign (const char *dst, etree_type *src)
+exp_assign (const char *dst, etree_type *src, bfd_boolean hidden)
{
- return exp_assop (dst, src, etree_assign, FALSE);
+ return exp_assop (dst, src, etree_assign, FALSE, hidden);
}
+/* Handle --defsym command-line option. */
+
etree_type *
exp_defsym (const char *dst, etree_type *src)
{
- return exp_assop (dst, src, etree_assign, TRUE);
+ return exp_assop (dst, src, etree_assign, TRUE, FALSE);
}
/* Handle PROVIDE. */
etree_type *
exp_provide (const char *dst, etree_type *src, bfd_boolean hidden)
{
- return exp_assop (dst, src, etree_provide, hidden);
+ return exp_assop (dst, src, etree_provide, FALSE, hidden);
}
/* Handle ASSERT. */
node_type type;
const char *dst;
union etree_union *src;
+ bfd_boolean defsym;
bfd_boolean hidden;
} assign;
struct {
etree_type *exp_nameop
(int, const char *);
etree_type *exp_assign
- (const char *, etree_type *);
+ (const char *, etree_type *, bfd_boolean);
etree_type *exp_defsym
(const char *, etree_type *);
etree_type *exp_provide
%token STARTUP HLL SYSLIB FLOAT NOFLOAT NOCROSSREFS
%token ORIGIN FILL
%token LENGTH CREATE_OBJECT_SYMBOLS INPUT GROUP OUTPUT CONSTRUCTORS
-%token ALIGNMOD AT SUBALIGN PROVIDE PROVIDE_HIDDEN AS_NEEDED
+%token ALIGNMOD AT SUBALIGN HIDDEN PROVIDE PROVIDE_HIDDEN AS_NEEDED
%type <token> assign_op atype attributes_opt sect_constraint
%type <name> filename
%token CHIP LIST SECT ABSOLUTE LOAD NEWLINE ENDWORD ORDER NAMEWORD ASSERT_K
assignment:
NAME '=' mustbe_exp
{
- lang_add_assignment (exp_assign ($1, $3));
+ lang_add_assignment (exp_assign ($1, $3, FALSE));
}
| NAME assign_op mustbe_exp
{
exp_binop ($2,
exp_nameop (NAME,
$1),
- $3)));
+ $3), FALSE));
+ }
+ | HIDDEN '(' NAME '=' mustbe_exp ')'
+ {
+ lang_add_assignment (exp_assign ($3, $5, TRUE));
}
| PROVIDE '(' NAME '=' mustbe_exp ')'
{
opt_exp_with_type
{
ldlex_popstate ();
- lang_add_assignment (exp_assign (".", $3));
+ lang_add_assignment (exp_assign (".", $3, FALSE));
}
'{' sec_or_group_p1 '}'
| INCLUDE filename
#endif
break;
case lang_assignment_statement_enum:
- if (s->assignment_statement.exp->assign.hidden)
+ if (s->assignment_statement.exp->assign.defsym)
/* This is from a --defsym on the command line. */
exp_fold_tree_no_dot (s->assignment_statement.exp);
break;
{
overlay_list->os->update_dot = 1;
overlay_list->os->update_dot_tree
- = exp_assign (".", exp_binop ('+', overlay_vma, overlay_max));
+ = exp_assign (".", exp_binop ('+', overlay_vma, overlay_max), FALSE);
}
l = overlay_list;
<BOTH,SCRIPT>"PHDRS" { RTOKEN (PHDRS); }
<EXPRESSION,BOTH,SCRIPT>"AT" { RTOKEN(AT);}
<EXPRESSION,BOTH,SCRIPT>"SUBALIGN" { RTOKEN(SUBALIGN);}
+<EXPRESSION,BOTH,SCRIPT>"HIDDEN" { RTOKEN(HIDDEN); }
<EXPRESSION,BOTH,SCRIPT>"PROVIDE" { RTOKEN(PROVIDE); }
<EXPRESSION,BOTH,SCRIPT>"PROVIDE_HIDDEN" { RTOKEN(PROVIDE_HIDDEN); }
<EXPRESSION,BOTH,SCRIPT>"KEEP" { RTOKEN(KEEP); }
void
mri_public (const char *name, etree_type *exp)
{
- lang_add_assignment (exp_assign (name, exp));
+ lang_add_assignment (exp_assign (name, exp, FALSE));
}
void
*(.data)
${CONSTRUCTING+CONSTRUCTORS}
}
- ${RELOCATING+ _gp = ALIGN(16) + 0x8000;}
+ ${RELOCATING+ HIDDEN (_gp = ALIGN (16) + 0x8000);}
.lit8 : {
*(.lit8)
}
+2012-08-28 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-elf/export-class.sd: New test.
+ * ld-elf/export-class.vd: New test.
+ * ld-elf/export-class-def.s: New test source.
+ * ld-elf/export-class-dep.s: New test source.
+ * ld-elf/export-class-lib.s: New test source.
+ * ld-elf/export-class-ref.s: New test source.
+ * ld-elf/export-class-lib.ver: New test version script.
+ * ld-elf/export-class.exp: New test script.
+ * ld-arm/arm-export-class.rd: New test.
+ * ld-arm/arm-export-class.xd: New test.
+ * ld-arm/export-class.exp: New test script.
+ * ld-i386/i386-export-class.rd: New test.
+ * ld-i386/i386-export-class.xd: New test.
+ * ld-i386/export-class.exp: New test script.
+ * ld-mips-elf/mips-32-export-class.rd: New test.
+ * ld-mips-elf/mips-32-export-class.xd: New test.
+ * ld-mips-elf/mips-64-export-class.rd: New test.
+ * ld-mips-elf/mips-64-export-class.xd: New test.
+ * ld-mips-elf/export-class.exp: New test script.
+ * ld-powerpc/powerpc-32-export-class.rd: New test.
+ * ld-powerpc/powerpc-32-export-class.xd: New test.
+ * ld-powerpc/powerpc-64-export-class.rd: New test.
+ * ld-powerpc/powerpc-64-export-class.xd: New test.
+ * ld-powerpc/export-class.exp: New test script.
+ * ld-x86-64/x86-64-64-export-class.rd: New test.
+ * ld-x86-64/x86-64-x32-export-class.rd: New test.
+ * ld-x86-64/export-class.exp: New test script.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/export-class-call16-o32.dd: New test.
+ * ld-mips-elf/export-class-call16-o32-irix.dd: New test.
+ * ld-mips-elf/export-class-call16-o32.gd: New test.
+ * ld-mips-elf/export-class-call16-n32.dd: New test.
+ * ld-mips-elf/export-class-call16-n32.gd: New test.
+ * ld-mips-elf/export-class-call16-n64.dd: New test.
+ * ld-mips-elf/export-class-call16-n64.gd: New test.
+ * ld-mips-elf/export-class-call16-def.s: New test source.
+ * ld-mips-elf/export-class-call16-o32.s: New test source.
+ * ld-mips-elf/export-class-call16-n32.s: New test source.
+ * ld-mips-elf/export-class-call16-n64.s: New test source.
+ * ld-mips-elf/export-class-call16.ld: New test linker script.
+ * ld-mips-elf/mips-elf.exp: Run the new tests.
+
+ * ld-mips-elf/dyn-sec64.ld: Use HIDDEN to define _gp.
+ * ld-mips-elf/eh-frame5.ld: Likewise.
+ * ld-mips-elf/got-dump-1.ld: Likewise.
+ * ld-mips-elf/got-dump-2.ld: Likewise.
+ * ld-mips-elf/got-page-1.ld: Likewise.
+ * ld-mips-elf/mips-dyn.ld: Likewise.
+ * ld-mips-elf/mips-lib.ld: Likewise.
+ * ld-mips-elf/mips16-pic-1.ld: Likewise.
+ * ld-mips-elf/no-shared-1.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-1.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3a.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.ld: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6.ld: Likewise.
+ * ld-mips-elf/reloc-2.ld: Likewise.
+ * ld-mips-elf/reloc-estimate-1.ld: Likewise.
+ * ld-mips-elf/stub-dynsym-1.ld: Likewise.
+ * ld-mips-elf/tls-hidden3.ld: Likewise.
+ * ld-mips-elf/mips16-pic-2.ad: Update accordingly.
+ * ld-mips-elf/pic-and-nonpic-3b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.ad: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.ad: Likewise.
+ * ld-mips-elf/eh-frame5.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-1.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-2.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+ * ld-mips-elf/tlsdyn-o32.d: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3a.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise.
+ * ld-mips-elf/tls-multi-got-1.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-1.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-2.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32-3.got: Likewise.
+ * ld-mips-elf/tlsdyn-o32.got: Likewise.
+ * ld-mips-elf/tlslib-o32-ver.got: Likewise.
+ * ld-mips-elf/tlslib-o32.got: Likewise.
+ * ld-mips-elf/mips16-pic-2.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-1.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-5b.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n32.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-n64.nd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-6-o32.nd: Likewise.
+ * ld-mips-elf/tls-multi-got-1.r: Likewise.
+ * ld-mips-elf/pic-and-nonpic-3b.rd: Likewise.
+ * ld-mips-elf/pic-and-nonpic-4b.rd: Likewise.
+ * ld-mips-elf/mips-elf.exp: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/gp-hidden.rd: New test.
+ * ld-mips-elf/gp-hidden.sd: New test.
+ * ld-mips-elf/gp-hidden-lib.rd: New test.
+ * ld-mips-elf/gp-hidden-ver.rd: New test.
+ * ld-mips-elf/gp-hidden-64.rd: New test.
+ * ld-mips-elf/gp-hidden-lib-64.rd: New test.
+ * ld-mips-elf/gp-hidden-ver-64.rd: New test.
+ * ld-mips-elf/gp-hidden.s: New test source.
+ * ld-mips-elf/gp-hidden-lib.s: New test source.
+ * ld-mips-elf/gp-hidden-ver.s: New test source.
+ * ld-mips-elf/gp-hidden-ver.ver: New test version script.
+ * ld-mips-elf/mips-elf.exp: Run the new tests.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/mips-elf.exp: Set has_newabi for all Linux targets.
+ Adjust abi_asflags for targets that do not infer the ISA from the
+ ABI.
+ * ld-mips-elf/eh-frame1-n32.d: Adjust for targets that do not
+ infer the ISA from the ABI.
+ * ld-mips-elf/eh-frame1-n64.d: Likewise.
+ * ld-mips-elf/eh-frame2-n32.d: Likewise.
+ * ld-mips-elf/eh-frame2-n64.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n32-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n32.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64-linux.d: Likewise.
+ * ld-mips-elf/elf-rel-got-n64.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+ * ld-mips-elf/elf-rel-xgot-n64.d: Likewise.
+ * ld-mips-elf/emit-relocs-1.d: Likewise.
+ * ld-mips-elf/got-page-2.d: Likewise.
+ * ld-mips-elf/no-shared-1-n32.d: Likewise.
+ * ld-mips-elf/no-shared-1-n64.d: Likewise.
+ * ld-mips-elf/rel32-n32.d: Likewise.
+ * ld-mips-elf/rel64.d: Likewise.
+ * ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
+ * ld-mips-elf/relax-jalr-n32.d: Likewise.
+ * ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
+ * ld-mips-elf/relax-jalr-n64.d: Likewise.
+ * ld-mips-elf/reloc-1-n32.d: Likewise.
+ * ld-mips-elf/reloc-1-n64.d: Likewise.
+ * ld-mips-elf/textrel-1.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/reloc-1-n32.d: Add -EB to GAS flags.
+ * ld-mips-elf/mips-elf.exp: Update GAS flags in reloc test 6.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * lib/ld-lib.exp (run_dump_test): Implement the EXTRA_OPTIONS
+ argument and the "dump" keyword.
+ * ld-mips-elf/emit-relocs-1a.s: Make section alignment uniform
+ across targets.
+ * ld-mips-elf/emit-relocs-1b.s: Likewise.
+ * ld-mips-elf/jalbal.s: Adjust padding.
+ * ld-mips-elf/elf-rel-got-n32-embed.d: New test.
+ * ld-mips-elf/elf-rel-got-n64-embed.d: New test.
+ * ld-mips-elf/elf-rel-xgot-n32-embed.d: New test.
+ * ld-mips-elf/elf-rel-xgot-n64-embed.d: New test.
+ * ld-mips-elf/elf-rel-got-n32.d: Remove -melf32btsmipn32.
+ * ld-mips-elf/elf-rel-got-n64.d: Remove -melf64btsmip. Adjust
+ output.
+ * ld-mips-elf/elf-rel-got-n64-linux.d: Remove -melf64btsmip.
+ * ld-mips-elf/elf-rel-xgot-n32.d: Remove -melf32btsmipn32.
+ Adjust output.
+ * ld-mips-elf/elf-rel-xgot-n64.d: Remove -melf64btsmip. Adjust
+ output.
+ * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+ * ld-mips-elf/reloc-1-n64.d: Remove -melf64btsmip.
+ * ld-mips-elf/mips-elf.exp: Set has_newabi for mips*-sde-elf*
+ too. Move tool flags from o32_as_flags and o32_ld_flags
+ variables into abi_asflags and abi_ldflags arrays. Adjust test
+ cases run to use them. Run the new tests.
+
+ * ld-mips-elf/rel32-o32.d: Adjust section VMAs after the removal
+ of _gp from the global scope.
+ * ld-mips-elf/rel32-n32.d: Likewise.
+ * ld-mips-elf/rel64.d: Likewise.
+
+2012-08-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * lib/ld-lib.exp (at_least_gcc_version): Accept more version
+ number formats; avoid throwing exceptions in any case.
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+2012-08-03 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * ld-mips-elf/mode-change-error-1.d: Update the error message.
+
2012-08-05 Maciej W. Rozycki <macro@linux-mips.org>
* ld-vax-elf: New directory.
--- /dev/null
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name
+12340010 00000017 R_ARM_RELATIVE *
+12340020 00000017 R_ARM_RELATIVE *
+12340060 00000017 R_ARM_RELATIVE *
+12340070 00000017 R_ARM_RELATIVE *
+12340080 00000017 R_ARM_RELATIVE *
+12340090 00000017 R_ARM_RELATIVE *
+12340000 [0-9a-f]+02 R_ARM_ABS32 123400a0 protected_baz
+12340040 [0-9a-f]+02 R_ARM_ABS32 123400a0 protected_foo
+12340050 [0-9a-f]+02 R_ARM_ABS32 123400a0 protected_bar
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 00000000 00000000 00000000 00000000 .*
+ 0x12340010 a0003412 00000000 00000000 00000000 .*
+ 0x12340020 a0003412 00000000 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 00000000 00000000 00000000 00000000 .*
+ 0x12340050 00000000 00000000 00000000 00000000 .*
+ 0x12340060 a0003412 00000000 00000000 00000000 .*
+ 0x12340070 a0003412 00000000 00000000 00000000 .*
+ 0x12340080 a0003412 00000000 00000000 00000000 .*
+ 0x12340090 a0003412 00000000 00000000 00000000 .*
--- /dev/null
+# Expect script for symbol export classes, ARM variation.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-Linux targets; feel free to include your favorite one
+# if you like.
+if { ![istarget arm*-*-linux*] } {
+ return
+}
+
+set testname "ARM symbol export class test"
+
+# Build an auxiliary shared object with conflicting versioned symbol
+# definitions.
+run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "-marmelf_linux_eabi -shared -version-script ../ld-elf/export-class-lib.ver" \
+ "-EL" \
+ { ../ld-elf/export-class-lib.s } \
+ {} \
+ "arm-export-class-lib.so" \
+ ] \
+]
+
+# Build a static object that pulls symbol definitions. It has to come
+# first before the auxiliary shared object and other static objects on
+# the linker's command line and hence we need to build it separately.
+run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "-marmelf_linux_eabi -r" \
+ "-EL" \
+ { ../ld-elf/export-class-ref.s } \
+ {} \
+ "arm-export-class-ref-r.o" \
+ ] \
+]
+
+# Build static objects that satisfy symbol dependencies and preempt
+# shared-object symbol definitions, and link all the objects built into
+# the final shared object. The command-line order of objects linked is
+# important to make sure the linker correctly preempts versioned symbols
+# from the auxiliary shared object and is as follows: ref, lib, dep, def.
+# Get a dump to make sure symbol dependencies are resolved internally.
+run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "-marmelf_linux_eabi -shared -Tdata=0x12340000 tmpdir/arm-export-class-ref-r.o tmpdir/arm-export-class-lib.so" \
+ "-EL" \
+ { ../ld-elf/export-class-dep.s ../ld-elf/export-class-def.s } \
+ { \
+ { readelf -r arm-export-class.rd } \
+ { readelf "-x .data" arm-export-class.xd } \
+ } \
+ "arm-export-class.so" \
+ ] \
+]
--- /dev/null
+ .data
+ .balign 32
+ .xdef protected_bar
+ .protected protected_bar
+protected_bar:
+ .balign 32
+ .xdef protected_foo
+ .protected protected_foo
+protected_foo:
+ .balign 32
+ .xdef hidden_bar
+ .hidden hidden_bar
+hidden_bar:
+ .balign 32
+ .xdef hidden_foo
+ .hidden hidden_foo
+hidden_foo:
+ .balign 32
+ .xdef internal_bar
+ .internal internal_bar
+internal_bar:
+ .balign 32
+ .xdef internal_foo
+ .internal internal_foo
+internal_foo:
--- /dev/null
+ .data
+ .balign 16
+ .dc.a protected_foo
+ .balign 16
+ .dc.a protected_bar
+ .balign 16
+ .dc.a hidden_foo
+ .balign 16
+ .dc.a hidden_bar
+ .balign 16
+ .dc.a internal_foo
+ .balign 16
+ .dc.a internal_bar
+ .balign 32
+ .xdef protected_baz
+ .protected protected_baz
+protected_baz:
+ .balign 32
+ .xdef hidden_baz
+ .hidden hidden_baz
+hidden_baz:
+ .balign 32
+ .xdef internal_baz
+ .internal internal_baz
+internal_baz:
--- /dev/null
+ .data
+ .balign 16
+ .xdef protected_foo
+protected_foo:
+ .balign 16
+ .xdef hidden_foo
+hidden_foo:
+ .balign 16
+ .xdef internal_foo
+internal_foo:
--- /dev/null
+GCC_3.0 { global: *_foo; };
--- /dev/null
+ .data
+ .balign 16
+ .dc.a protected_baz
+ .balign 16
+ .dc.a hidden_baz
+ .balign 16
+ .dc.a internal_baz
--- /dev/null
+# Expect script for symbol export classes.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-ELF targets.
+if { ![is_elf_format] } {
+ return
+}
+
+# Exclude some more targets; feel free to include your favorite one
+# if you like.
+if { ![istarget *-*-linux*]
+ && ![istarget *-*-nacl*]
+ && ![istarget *-*-gnu*] } {
+ return
+}
+
+set testname "Symbol export class test"
+
+# Build an auxiliary shared object with conflicting versioned symbol
+# definitions.
+run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "-shared -version-script export-class-lib.ver" \
+ "" \
+ { export-class-lib.s } \
+ {} \
+ "export-class-lib.so" \
+ ] \
+]
+
+# Build a static object that pulls symbol definitions. It has to come
+# first before the auxiliary shared object and other static objects on
+# the linker's command line and hence we need to build it separately.
+run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "-r" \
+ "" \
+ { export-class-ref.s } \
+ {} \
+ "export-class-ref-r.o" \
+ ] \
+]
+
+# Build static objects that satisfy symbol dependencies and preempt
+# shared-object symbol definitions, and link all the objects built into
+# the final shared object. The command-line order of objects linked is
+# important to make sure the linker correctly preempts versioned symbols
+# from the auxiliary shared object and is as follows: ref, lib, dep, def.
+# Get a dump to make sure symbol dependencies are resolved internally.
+run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "-shared -Tdata=0x12340000 tmpdir/export-class-ref-r.o tmpdir/export-class-lib.so" \
+ "" \
+ { export-class-dep.s export-class-def.s } \
+ { \
+ { readelf -s export-class.sd } \
+ { readelf -V export-class.vd } \
+ } \
+ "export-class.so" \
+ ] \
+]
--- /dev/null
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ * Num: * Value * Size * Type * Bind * Vis * Ndx * Name
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_foo
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_bar
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_baz
+#...
+Symbol table '\.symtab' contains [0-9]+ entries:
+ * Num: * Value * Size * Type * Bind * Vis * Ndx * Name
+#...
+ * [0-9a-f]+: * 0*12340000 * 0 * SECTION * LOCAL * DEFAULT * [0-9]+ *
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * hidden_foo
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * internal_baz
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * internal_bar
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * internal_foo
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * hidden_bar
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * LOCAL * DEFAULT * [0-9]+ * hidden_baz
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_foo
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_bar
+#...
+ * [0-9a-f]+: * 0*123400a0 * 0 * NOTYPE * GLOBAL * PROTECTED * [0-9]+ * protected_baz
+#pass
--- /dev/null
+No version information found in this file\.
--- /dev/null
+# Expect script for symbol export classes, i386 variation.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-ELF targets.
+if { ![is_elf_format] } {
+ return
+}
+
+# Exclude non-Linux targets; feel free to include your favorite one
+# if you like.
+if { ![istarget i?86-*-linux*] } {
+ return
+}
+
+set testname "i386 symbol export class test"
+
+# Build an auxiliary shared object with conflicting versioned symbol
+# definitions.
+run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "-shared -version-script ../ld-elf/export-class-lib.ver" \
+ "" \
+ { ../ld-elf/export-class-lib.s } \
+ {} \
+ "i386-export-class-lib.so" \
+ ] \
+]
+
+# Build a static object that pulls symbol definitions. It has to come
+# first before the auxiliary shared object and other static objects on
+# the linker's command line and hence we need to build it separately.
+run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "-r" \
+ "" \
+ { ../ld-elf/export-class-ref.s } \
+ {} \
+ "i386-export-class-ref-r.o" \
+ ] \
+]
+
+# Build static objects that satisfy symbol dependencies and preempt
+# shared-object symbol definitions, and link all the objects built into
+# the final shared object. The command-line order of objects linked is
+# important to make sure the linker correctly preempts versioned symbols
+# from the auxiliary shared object and is as follows: ref, lib, dep, def.
+# Get a dump to make sure symbol dependencies are resolved internally.
+run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "-shared -Tdata=0x12340000 tmpdir/i386-export-class-ref-r.o tmpdir/i386-export-class-lib.so" \
+ "" \
+ { ../ld-elf/export-class-dep.s ../ld-elf/export-class-def.s } \
+ { \
+ { readelf -r i386-export-class.rd } \
+ { readelf "-x .data" i386-export-class.xd } \
+ } \
+ "i386-export-class.so" \
+ ] \
+]
--- /dev/null
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name
+12340010 00000008 R_386_RELATIVE *
+12340020 00000008 R_386_RELATIVE *
+12340060 00000008 R_386_RELATIVE *
+12340070 00000008 R_386_RELATIVE *
+12340080 00000008 R_386_RELATIVE *
+12340090 00000008 R_386_RELATIVE *
+12340000 [0-9a-f]+01 R_386_32 123400a0 protected_baz
+12340040 [0-9a-f]+01 R_386_32 123400a0 protected_foo
+12340050 [0-9a-f]+01 R_386_32 123400a0 protected_bar
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 00000000 00000000 00000000 00000000 .*
+ 0x12340010 a0003412 00000000 00000000 00000000 .*
+ 0x12340020 a0003412 00000000 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 00000000 00000000 00000000 00000000 .*
+ 0x12340050 00000000 00000000 00000000 00000000 .*
+ 0x12340060 a0003412 00000000 00000000 00000000 .*
+ 0x12340070 a0003412 00000000 00000000 00000000 .*
+ 0x12340080 a0003412 00000000 00000000 00000000 .*
+ 0x12340090 a0003412 00000000 00000000 00000000 .*
.MIPS.stubs : { *(.MIPS.stubs) }
. = 0x1235000000000;
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
.data : { *(.data) }
}
#name: MIPS eh-frame 1, n32
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -n32 --defsym alignment=2 --defsym fill=0x40
+#as: -march=from-abi -EB -n32 --defsym alignment=2 --defsym fill=0x40
#readelf: --relocs -wf
#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 1, n64
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -64 --defsym alignment=3 --defsym fill=0x40
+#as: -march=from-abi -EB -64 --defsym alignment=3 --defsym fill=0x40
#readelf: --relocs -wf
#ld: -shared -melf64btsmip -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 2, n32
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -n32 --defsym alignment=2 --defsym fill=0
+#as: -march=from-abi -EB -n32 --defsym alignment=2 --defsym fill=0
#readelf: --relocs -wf
#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
#name: MIPS eh-frame 2, n64
#source: eh-frame1.s
#source: eh-frame1.s
-#as: -EB -64 --defsym alignment=3 --defsym fill=0
+#as: -march=from-abi -EB -64 --defsym alignment=3 --defsym fill=0
#readelf: --relocs -wf
#ld: -shared -melf64btsmip -Teh-frame1.ld
#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
-Relocation section '.rel.dyn' at offset 0x101f0 contains 8 entries:
+Relocation section '.rel.dyn' at offset 0x101dc contains 8 entries:
Offset Info Type Sym.Value Sym. Name
00000000 .* R_MIPS_NONE *
#
. = 0x10000;
.data : { *(.data) }
. = 0x10400;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
--- /dev/null
+#name: MIPS ELF got reloc n32
+#as: -march=from-abi -EB -n32 -KPIC
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
+#ld:
+#objdump: -D --show-raw-insn
+
+.*: +file format elf32-n.*mips.*
+
+Disassembly of section \.reginfo:
+
+10000078 <\.reginfo>:
+10000078: 92020022 .*
+ \.\.\.
+1000008c: 10018560 .*
+
+Disassembly of section \.text:
+
+10000074 <fn>:
+10000074: 8f858018 lw a1,-32744\(gp\)
+10000078: 8f858018 lw a1,-32744\(gp\)
+1000007c: 24a5000c addiu a1,a1,12
+10000080: 8f858018 lw a1,-32744\(gp\)
+10000084: 3c010001 lui at,0x1
+10000088: 3421e240 ori at,at,0xe240
+1000008c: 00a12821 addu a1,a1,at
+10000090: 8f858018 lw a1,-32744\(gp\)
+10000094: 00b12821 addu a1,a1,s1
+10000098: 8f858018 lw a1,-32744\(gp\)
+1000009c: 24a5000c addiu a1,a1,12
+100000a0: 00b12821 addu a1,a1,s1
+100000a4: 8f858018 lw a1,-32744\(gp\)
+100000a8: 3c010001 lui at,0x1
+100000ac: 3421e240 ori at,at,0xe240
+100000b0: 00a12821 addu a1,a1,at
+100000b4: 00b12821 addu a1,a1,s1
+100000b8: 8f85801c lw a1,-32740\(gp\)
+100000bc: 8ca504bc lw a1,1212\(a1\)
+100000c0: 8f85801c lw a1,-32740\(gp\)
+100000c4: 8ca504c8 lw a1,1224\(a1\)
+100000c8: 8f85801c lw a1,-32740\(gp\)
+100000cc: 00b12821 addu a1,a1,s1
+100000d0: 8ca504bc lw a1,1212\(a1\)
+100000d4: 8f85801c lw a1,-32740\(gp\)
+100000d8: 00b12821 addu a1,a1,s1
+100000dc: 8ca504c8 lw a1,1224\(a1\)
+100000e0: 8f81801c lw at,-32740\(gp\)
+100000e4: 00250821 addu at,at,a1
+100000e8: 8c2504de lw a1,1246\(at\)
+100000ec: 8f81801c lw at,-32740\(gp\)
+100000f0: 00250821 addu at,at,a1
+100000f4: ac2504f4 sw a1,1268\(at\)
+100000f8: 8f818018 lw at,-32744\(gp\)
+100000fc: 88250000 lwl a1,0\(at\)
+10000100: 98250003 lwr a1,3\(at\)
+10000104: 8f818018 lw at,-32744\(gp\)
+10000108: 2421000c addiu at,at,12
+1000010c: 88250000 lwl a1,0\(at\)
+10000110: 98250003 lwr a1,3\(at\)
+10000114: 8f818018 lw at,-32744\(gp\)
+10000118: 00310821 addu at,at,s1
+1000011c: 88250000 lwl a1,0\(at\)
+10000120: 98250003 lwr a1,3\(at\)
+10000124: 8f818018 lw at,-32744\(gp\)
+10000128: 2421000c addiu at,at,12
+1000012c: 00310821 addu at,at,s1
+10000130: 88250000 lwl a1,0\(at\)
+10000134: 98250003 lwr a1,3\(at\)
+10000138: 8f818018 lw at,-32744\(gp\)
+1000013c: 24210022 addiu at,at,34
+10000140: 00250821 addu at,at,a1
+10000144: 88250000 lwl a1,0\(at\)
+10000148: 98250003 lwr a1,3\(at\)
+1000014c: 8f818018 lw at,-32744\(gp\)
+10000150: 24210038 addiu at,at,56
+10000154: 00250821 addu at,at,a1
+10000158: a8250000 swl a1,0\(at\)
+1000015c: b8250003 swr a1,3\(at\)
+10000160: 8f858018 lw a1,-32744\(gp\)
+10000164: 8f858020 lw a1,-32736\(gp\)
+10000168: 8f858024 lw a1,-32732\(gp\)
+1000016c: 8f858018 lw a1,-32744\(gp\)
+10000170: 00b12821 addu a1,a1,s1
+10000174: 8f858020 lw a1,-32736\(gp\)
+10000178: 00b12821 addu a1,a1,s1
+1000017c: 8f858024 lw a1,-32732\(gp\)
+10000180: 00b12821 addu a1,a1,s1
+10000184: 8f85801c lw a1,-32740\(gp\)
+10000188: 8ca504bc lw a1,1212\(a1\)
+1000018c: 8f85801c lw a1,-32740\(gp\)
+10000190: 8ca504c8 lw a1,1224\(a1\)
+10000194: 8f85801c lw a1,-32740\(gp\)
+10000198: 00b12821 addu a1,a1,s1
+1000019c: 8ca504bc lw a1,1212\(a1\)
+100001a0: 8f85801c lw a1,-32740\(gp\)
+100001a4: 00b12821 addu a1,a1,s1
+100001a8: 8ca504c8 lw a1,1224\(a1\)
+100001ac: 8f81801c lw at,-32740\(gp\)
+100001b0: 00250821 addu at,at,a1
+100001b4: 8c2504de lw a1,1246\(at\)
+100001b8: 8f81801c lw at,-32740\(gp\)
+100001bc: 00250821 addu at,at,a1
+100001c0: ac2504f4 sw a1,1268\(at\)
+100001c4: 8f818018 lw at,-32744\(gp\)
+100001c8: 88250000 lwl a1,0\(at\)
+100001cc: 98250003 lwr a1,3\(at\)
+100001d0: 8f818020 lw at,-32736\(gp\)
+100001d4: 88250000 lwl a1,0\(at\)
+100001d8: 98250003 lwr a1,3\(at\)
+100001dc: 8f818018 lw at,-32744\(gp\)
+100001e0: 00310821 addu at,at,s1
+100001e4: 88250000 lwl a1,0\(at\)
+100001e8: 98250003 lwr a1,3\(at\)
+100001ec: 8f818020 lw at,-32736\(gp\)
+100001f0: 00310821 addu at,at,s1
+100001f4: 88250000 lwl a1,0\(at\)
+100001f8: 98250003 lwr a1,3\(at\)
+100001fc: 8f818028 lw at,-32728\(gp\)
+10000200: 00250821 addu at,at,a1
+10000204: 88250000 lwl a1,0\(at\)
+10000208: 98250003 lwr a1,3\(at\)
+1000020c: 8f81802c lw at,-32724\(gp\)
+10000210: 00250821 addu at,at,a1
+10000214: a8250000 swl a1,0\(at\)
+10000218: b8250003 swr a1,3\(at\)
+1000021c: 8f858030 lw a1,-32720\(gp\)
+10000220: 8f858030 lw a1,-32720\(gp\)
+10000224: 8f998030 lw t9,-32720\(gp\)
+10000228: 8f998030 lw t9,-32720\(gp\)
+1000022c: 8f998030 lw t9,-32720\(gp\)
+10000230: 0411ff90 bal 10000074 <fn>
+10000234: 00000000 nop
+10000238: 8f998030 lw t9,-32720\(gp\)
+1000023c: 0411ff8d bal 10000074 <fn>
+10000240: 00000000 nop
+10000244: 8f858034 lw a1,-32716\(gp\)
+10000248: 8f858034 lw a1,-32716\(gp\)
+1000024c: 24a5000c addiu a1,a1,12
+10000250: 8f858034 lw a1,-32716\(gp\)
+10000254: 3c010001 lui at,0x1
+10000258: 3421e240 ori at,at,0xe240
+1000025c: 00a12821 addu a1,a1,at
+10000260: 8f858034 lw a1,-32716\(gp\)
+10000264: 00b12821 addu a1,a1,s1
+10000268: 8f858034 lw a1,-32716\(gp\)
+1000026c: 24a5000c addiu a1,a1,12
+10000270: 00b12821 addu a1,a1,s1
+10000274: 8f858034 lw a1,-32716\(gp\)
+10000278: 3c010001 lui at,0x1
+1000027c: 3421e240 ori at,at,0xe240
+10000280: 00a12821 addu a1,a1,at
+10000284: 00b12821 addu a1,a1,s1
+10000288: 8f85801c lw a1,-32740\(gp\)
+1000028c: 8ca50534 lw a1,1332\(a1\)
+10000290: 8f85801c lw a1,-32740\(gp\)
+10000294: 8ca50540 lw a1,1344\(a1\)
+10000298: 8f85801c lw a1,-32740\(gp\)
+1000029c: 00b12821 addu a1,a1,s1
+100002a0: 8ca50534 lw a1,1332\(a1\)
+100002a4: 8f85801c lw a1,-32740\(gp\)
+100002a8: 00b12821 addu a1,a1,s1
+100002ac: 8ca50540 lw a1,1344\(a1\)
+100002b0: 8f81801c lw at,-32740\(gp\)
+100002b4: 00250821 addu at,at,a1
+100002b8: 8c250556 lw a1,1366\(at\)
+100002bc: 8f81801c lw at,-32740\(gp\)
+100002c0: 00250821 addu at,at,a1
+100002c4: ac25056c sw a1,1388\(at\)
+100002c8: 8f818034 lw at,-32716\(gp\)
+100002cc: 88250000 lwl a1,0\(at\)
+100002d0: 98250003 lwr a1,3\(at\)
+100002d4: 8f818034 lw at,-32716\(gp\)
+100002d8: 2421000c addiu at,at,12
+100002dc: 88250000 lwl a1,0\(at\)
+100002e0: 98250003 lwr a1,3\(at\)
+100002e4: 8f818034 lw at,-32716\(gp\)
+100002e8: 00310821 addu at,at,s1
+100002ec: 88250000 lwl a1,0\(at\)
+100002f0: 98250003 lwr a1,3\(at\)
+100002f4: 8f818034 lw at,-32716\(gp\)
+100002f8: 2421000c addiu at,at,12
+100002fc: 00310821 addu at,at,s1
+10000300: 88250000 lwl a1,0\(at\)
+10000304: 98250003 lwr a1,3\(at\)
+10000308: 8f818034 lw at,-32716\(gp\)
+1000030c: 24210022 addiu at,at,34
+10000310: 00250821 addu at,at,a1
+10000314: 88250000 lwl a1,0\(at\)
+10000318: 98250003 lwr a1,3\(at\)
+1000031c: 8f818034 lw at,-32716\(gp\)
+10000320: 24210038 addiu at,at,56
+10000324: 00250821 addu at,at,a1
+10000328: a8250000 swl a1,0\(at\)
+1000032c: b8250003 swr a1,3\(at\)
+10000330: 8f858034 lw a1,-32716\(gp\)
+10000334: 8f858038 lw a1,-32712\(gp\)
+10000338: 8f85803c lw a1,-32708\(gp\)
+1000033c: 8f858034 lw a1,-32716\(gp\)
+10000340: 00b12821 addu a1,a1,s1
+10000344: 8f858038 lw a1,-32712\(gp\)
+10000348: 00b12821 addu a1,a1,s1
+1000034c: 8f85803c lw a1,-32708\(gp\)
+10000350: 00b12821 addu a1,a1,s1
+10000354: 8f85801c lw a1,-32740\(gp\)
+10000358: 8ca50534 lw a1,1332\(a1\)
+1000035c: 8f85801c lw a1,-32740\(gp\)
+10000360: 8ca50540 lw a1,1344\(a1\)
+10000364: 8f85801c lw a1,-32740\(gp\)
+10000368: 00b12821 addu a1,a1,s1
+1000036c: 8ca50534 lw a1,1332\(a1\)
+10000370: 8f85801c lw a1,-32740\(gp\)
+10000374: 00b12821 addu a1,a1,s1
+10000378: 8ca50540 lw a1,1344\(a1\)
+1000037c: 8f81801c lw at,-32740\(gp\)
+10000380: 00250821 addu at,at,a1
+10000384: 8c250556 lw a1,1366\(at\)
+10000388: 8f81801c lw at,-32740\(gp\)
+1000038c: 00250821 addu at,at,a1
+10000390: ac25056c sw a1,1388\(at\)
+10000394: 8f818034 lw at,-32716\(gp\)
+10000398: 88250000 lwl a1,0\(at\)
+1000039c: 98250003 lwr a1,3\(at\)
+100003a0: 8f818038 lw at,-32712\(gp\)
+100003a4: 88250000 lwl a1,0\(at\)
+100003a8: 98250003 lwr a1,3\(at\)
+100003ac: 8f818034 lw at,-32716\(gp\)
+100003b0: 00310821 addu at,at,s1
+100003b4: 88250000 lwl a1,0\(at\)
+100003b8: 98250003 lwr a1,3\(at\)
+100003bc: 8f818038 lw at,-32712\(gp\)
+100003c0: 00310821 addu at,at,s1
+100003c4: 88250000 lwl a1,0\(at\)
+100003c8: 98250003 lwr a1,3\(at\)
+100003cc: 8f818040 lw at,-32704\(gp\)
+100003d0: 00250821 addu at,at,a1
+100003d4: 88250000 lwl a1,0\(at\)
+100003d8: 98250003 lwr a1,3\(at\)
+100003dc: 8f818044 lw at,-32700\(gp\)
+100003e0: 00250821 addu at,at,a1
+100003e4: a8250000 swl a1,0\(at\)
+100003e8: b8250003 swr a1,3\(at\)
+100003ec: 8f858048 lw a1,-32696\(gp\)
+100003f0: 8f858048 lw a1,-32696\(gp\)
+100003f4: 8f998048 lw t9,-32696\(gp\)
+100003f8: 8f998048 lw t9,-32696\(gp\)
+100003fc: 8f998048 lw t9,-32696\(gp\)
+10000400: 0411001d bal 10000478 <fn2>
+10000404: 00000000 nop
+10000408: 8f998048 lw t9,-32696\(gp\)
+1000040c: 0411001a bal 10000478 <fn2>
+10000410: 00000000 nop
+10000414: 1000ff17 b 10000074 <fn>
+10000418: 8f858018 lw a1,-32744\(gp\)
+1000041c: 8f85801c lw a1,-32740\(gp\)
+10000420: 10000015 b 10000478 <fn2>
+10000424: 8ca50534 lw a1,1332\(a1\)
+10000428: 1000ff12 b 10000074 <fn>
+1000042c: 8f858018 lw a1,-32744\(gp\)
+10000430: 8f858038 lw a1,-32712\(gp\)
+10000434: 10000010 b 10000478 <fn2>
+10000438: 00000000 nop
+1000043c: 8f858024 lw a1,-32732\(gp\)
+10000440: 1000ff0c b 10000074 <fn>
+10000444: 00000000 nop
+10000448: 8f85801c lw a1,-32740\(gp\)
+1000044c: 1000000a b 10000478 <fn2>
+10000450: 8ca50534 lw a1,1332\(a1\)
+10000454: 8f85801c lw a1,-32740\(gp\)
+10000458: 1000ff06 b 10000074 <fn>
+1000045c: 8ca504c8 lw a1,1224\(a1\)
+10000460: 8f81801c lw at,-32740\(gp\)
+10000464: 00250821 addu at,at,a1
+10000468: 10000003 b 10000478 <fn2>
+1000046c: 8c250556 lw a1,1366\(at\)
+ \.\.\.
+
+10000478 <fn2>:
+ \.\.\.
+Disassembly of section \.data:
+
+10010480 <_fdata>:
+ \.\.\.
+
+100104bc <dg1>:
+ \.\.\.
+
+100104f8 <sp2>:
+ \.\.\.
+
+10010534 <dg2>:
+ \.\.\.
+Disassembly of section \.got:
+
+10010570 <_GLOBAL_OFFSET_TABLE_>:
+10010570: 00000000 .*
+10010574: 80000000 .*
+10010578: 100104bc .*
+1001057c: 10010000 .*
+10010580: 100104c8 .*
+10010584: 1002e6fc .*
+10010588: 100104de .*
+1001058c: 100104f4 .*
+10010590: 10000074 .*
+10010594: 10010534 .*
+10010598: 10010540 .*
+1001059c: 1002e774 .*
+100105a0: 10010556 .*
+100105a4: 1001056c .*
+100105a8: 10000478 .*
+100105ac: 00000000 .*
+ \.\.\.
+#pass
#name: MIPS ELF got reloc n32
-#as: -EB -n32 -KPIC
+#as: -march=from-abi -EB -n32 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
-#ld: -melf32btsmipn32
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf32-n.*mips.*
--- /dev/null
+#name: MIPS ELF got reloc n64
+#as: -march=from-abi -EB -64 -KPIC
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld:
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000001200000b0 <\.MIPS\.options>:
+ 1200000b0: 01280000 .*
+ 1200000b4: 00000000 .*
+ 1200000b8: 92020022 .*
+ \.\.\.
+ 1200000d0: 00000001 .*
+ 1200000d4: 200185a0 .*
+Disassembly of section \.text:
+
+00000001200000b0 <fn>:
+ 1200000b0: df858020 ld a1,-32736\(gp\)
+ 1200000b4: df858020 ld a1,-32736\(gp\)
+ 1200000b8: 64a5000c daddiu a1,a1,12
+ 1200000bc: df858020 ld a1,-32736\(gp\)
+ 1200000c0: 3c010001 lui at,0x1
+ 1200000c4: 3421e240 ori at,at,0xe240
+ 1200000c8: 00a1282d daddu a1,a1,at
+ 1200000cc: df858020 ld a1,-32736\(gp\)
+ 1200000d0: 00b1282d daddu a1,a1,s1
+ 1200000d4: df858020 ld a1,-32736\(gp\)
+ 1200000d8: 64a5000c daddiu a1,a1,12
+ 1200000dc: 00b1282d daddu a1,a1,s1
+ 1200000e0: df858020 ld a1,-32736\(gp\)
+ 1200000e4: 3c010001 lui at,0x1
+ 1200000e8: 3421e240 ori at,at,0xe240
+ 1200000ec: 00a1282d daddu a1,a1,at
+ 1200000f0: 00b1282d daddu a1,a1,s1
+ 1200000f4: df858028 ld a1,-32728\(gp\)
+ 1200000f8: dca504fc ld a1,1276\(a1\)
+ 1200000fc: df858028 ld a1,-32728\(gp\)
+ 120000100: dca50508 ld a1,1288\(a1\)
+ 120000104: df858028 ld a1,-32728\(gp\)
+ 120000108: 00b1282d daddu a1,a1,s1
+ 12000010c: dca504fc ld a1,1276\(a1\)
+ 120000110: df858028 ld a1,-32728\(gp\)
+ 120000114: 00b1282d daddu a1,a1,s1
+ 120000118: dca50508 ld a1,1288\(a1\)
+ 12000011c: df818028 ld at,-32728\(gp\)
+ 120000120: 0025082d daddu at,at,a1
+ 120000124: dc25051e ld a1,1310\(at\)
+ 120000128: df818028 ld at,-32728\(gp\)
+ 12000012c: 0025082d daddu at,at,a1
+ 120000130: fc250534 sd a1,1332\(at\)
+ 120000134: df818020 ld at,-32736\(gp\)
+ 120000138: 88250000 lwl a1,0\(at\)
+ 12000013c: 98250003 lwr a1,3\(at\)
+ 120000140: df818020 ld at,-32736\(gp\)
+ 120000144: 6421000c daddiu at,at,12
+ 120000148: 88250000 lwl a1,0\(at\)
+ 12000014c: 98250003 lwr a1,3\(at\)
+ 120000150: df818020 ld at,-32736\(gp\)
+ 120000154: 0031082d daddu at,at,s1
+ 120000158: 88250000 lwl a1,0\(at\)
+ 12000015c: 98250003 lwr a1,3\(at\)
+ 120000160: df818020 ld at,-32736\(gp\)
+ 120000164: 6421000c daddiu at,at,12
+ 120000168: 0031082d daddu at,at,s1
+ 12000016c: 88250000 lwl a1,0\(at\)
+ 120000170: 98250003 lwr a1,3\(at\)
+ 120000174: df818020 ld at,-32736\(gp\)
+ 120000178: 64210022 daddiu at,at,34
+ 12000017c: 0025082d daddu at,at,a1
+ 120000180: 88250000 lwl a1,0\(at\)
+ 120000184: 98250003 lwr a1,3\(at\)
+ 120000188: df818020 ld at,-32736\(gp\)
+ 12000018c: 64210038 daddiu at,at,56
+ 120000190: 0025082d daddu at,at,a1
+ 120000194: a8250000 swl a1,0\(at\)
+ 120000198: b8250003 swr a1,3\(at\)
+ 12000019c: df858020 ld a1,-32736\(gp\)
+ 1200001a0: df858030 ld a1,-32720\(gp\)
+ 1200001a4: df858038 ld a1,-32712\(gp\)
+ 1200001a8: df858020 ld a1,-32736\(gp\)
+ 1200001ac: 00b1282d daddu a1,a1,s1
+ 1200001b0: df858030 ld a1,-32720\(gp\)
+ 1200001b4: 00b1282d daddu a1,a1,s1
+ 1200001b8: df858038 ld a1,-32712\(gp\)
+ 1200001bc: 00b1282d daddu a1,a1,s1
+ 1200001c0: df858028 ld a1,-32728\(gp\)
+ 1200001c4: dca504fc ld a1,1276\(a1\)
+ 1200001c8: df858028 ld a1,-32728\(gp\)
+ 1200001cc: dca50508 ld a1,1288\(a1\)
+ 1200001d0: df858028 ld a1,-32728\(gp\)
+ 1200001d4: 00b1282d daddu a1,a1,s1
+ 1200001d8: dca504fc ld a1,1276\(a1\)
+ 1200001dc: df858028 ld a1,-32728\(gp\)
+ 1200001e0: 00b1282d daddu a1,a1,s1
+ 1200001e4: dca50508 ld a1,1288\(a1\)
+ 1200001e8: df818028 ld at,-32728\(gp\)
+ 1200001ec: 0025082d daddu at,at,a1
+ 1200001f0: dc25051e ld a1,1310\(at\)
+ 1200001f4: df818028 ld at,-32728\(gp\)
+ 1200001f8: 0025082d daddu at,at,a1
+ 1200001fc: fc250534 sd a1,1332\(at\)
+ 120000200: df818020 ld at,-32736\(gp\)
+ 120000204: 88250000 lwl a1,0\(at\)
+ 120000208: 98250003 lwr a1,3\(at\)
+ 12000020c: df818030 ld at,-32720\(gp\)
+ 120000210: 88250000 lwl a1,0\(at\)
+ 120000214: 98250003 lwr a1,3\(at\)
+ 120000218: df818020 ld at,-32736\(gp\)
+ 12000021c: 0031082d daddu at,at,s1
+ 120000220: 88250000 lwl a1,0\(at\)
+ 120000224: 98250003 lwr a1,3\(at\)
+ 120000228: df818030 ld at,-32720\(gp\)
+ 12000022c: 0031082d daddu at,at,s1
+ 120000230: 88250000 lwl a1,0\(at\)
+ 120000234: 98250003 lwr a1,3\(at\)
+ 120000238: df818040 ld at,-32704\(gp\)
+ 12000023c: 0025082d daddu at,at,a1
+ 120000240: 88250000 lwl a1,0\(at\)
+ 120000244: 98250003 lwr a1,3\(at\)
+ 120000248: df818048 ld at,-32696\(gp\)
+ 12000024c: 0025082d daddu at,at,a1
+ 120000250: a8250000 swl a1,0\(at\)
+ 120000254: b8250003 swr a1,3\(at\)
+ 120000258: df858050 ld a1,-32688\(gp\)
+ 12000025c: df858050 ld a1,-32688\(gp\)
+ 120000260: df998050 ld t9,-32688\(gp\)
+ 120000264: df998050 ld t9,-32688\(gp\)
+ 120000268: df998050 ld t9,-32688\(gp\)
+ 12000026c: 0411ff90 bal 1200000b0 <fn>
+ 120000270: 00000000 nop
+ 120000274: df998050 ld t9,-32688\(gp\)
+ 120000278: 0411ff8d bal 1200000b0 <fn>
+ 12000027c: 00000000 nop
+ 120000280: df858058 ld a1,-32680\(gp\)
+ 120000284: df858058 ld a1,-32680\(gp\)
+ 120000288: 64a5000c daddiu a1,a1,12
+ 12000028c: df858058 ld a1,-32680\(gp\)
+ 120000290: 3c010001 lui at,0x1
+ 120000294: 3421e240 ori at,at,0xe240
+ 120000298: 00a1282d daddu a1,a1,at
+ 12000029c: df858058 ld a1,-32680\(gp\)
+ 1200002a0: 00b1282d daddu a1,a1,s1
+ 1200002a4: df858058 ld a1,-32680\(gp\)
+ 1200002a8: 64a5000c daddiu a1,a1,12
+ 1200002ac: 00b1282d daddu a1,a1,s1
+ 1200002b0: df858058 ld a1,-32680\(gp\)
+ 1200002b4: 3c010001 lui at,0x1
+ 1200002b8: 3421e240 ori at,at,0xe240
+ 1200002bc: 00a1282d daddu a1,a1,at
+ 1200002c0: 00b1282d daddu a1,a1,s1
+ 1200002c4: df858028 ld a1,-32728\(gp\)
+ 1200002c8: dca50574 ld a1,1396\(a1\)
+ 1200002cc: df858028 ld a1,-32728\(gp\)
+ 1200002d0: dca50580 ld a1,1408\(a1\)
+ 1200002d4: df858028 ld a1,-32728\(gp\)
+ 1200002d8: 00b1282d daddu a1,a1,s1
+ 1200002dc: dca50574 ld a1,1396\(a1\)
+ 1200002e0: df858028 ld a1,-32728\(gp\)
+ 1200002e4: 00b1282d daddu a1,a1,s1
+ 1200002e8: dca50580 ld a1,1408\(a1\)
+ 1200002ec: df818028 ld at,-32728\(gp\)
+ 1200002f0: 0025082d daddu at,at,a1
+ 1200002f4: dc250596 ld a1,1430\(at\)
+ 1200002f8: df818028 ld at,-32728\(gp\)
+ 1200002fc: 0025082d daddu at,at,a1
+ 120000300: fc2505ac sd a1,1452\(at\)
+ 120000304: df818058 ld at,-32680\(gp\)
+ 120000308: 88250000 lwl a1,0\(at\)
+ 12000030c: 98250003 lwr a1,3\(at\)
+ 120000310: df818058 ld at,-32680\(gp\)
+ 120000314: 6421000c daddiu at,at,12
+ 120000318: 88250000 lwl a1,0\(at\)
+ 12000031c: 98250003 lwr a1,3\(at\)
+ 120000320: df818058 ld at,-32680\(gp\)
+ 120000324: 0031082d daddu at,at,s1
+ 120000328: 88250000 lwl a1,0\(at\)
+ 12000032c: 98250003 lwr a1,3\(at\)
+ 120000330: df818058 ld at,-32680\(gp\)
+ 120000334: 6421000c daddiu at,at,12
+ 120000338: 0031082d daddu at,at,s1
+ 12000033c: 88250000 lwl a1,0\(at\)
+ 120000340: 98250003 lwr a1,3\(at\)
+ 120000344: df818058 ld at,-32680\(gp\)
+ 120000348: 64210022 daddiu at,at,34
+ 12000034c: 0025082d daddu at,at,a1
+ 120000350: 88250000 lwl a1,0\(at\)
+ 120000354: 98250003 lwr a1,3\(at\)
+ 120000358: df818058 ld at,-32680\(gp\)
+ 12000035c: 64210038 daddiu at,at,56
+ 120000360: 0025082d daddu at,at,a1
+ 120000364: a8250000 swl a1,0\(at\)
+ 120000368: b8250003 swr a1,3\(at\)
+ 12000036c: df858058 ld a1,-32680\(gp\)
+ 120000370: df858060 ld a1,-32672\(gp\)
+ 120000374: df858068 ld a1,-32664\(gp\)
+ 120000378: df858058 ld a1,-32680\(gp\)
+ 12000037c: 00b1282d daddu a1,a1,s1
+ 120000380: df858060 ld a1,-32672\(gp\)
+ 120000384: 00b1282d daddu a1,a1,s1
+ 120000388: df858068 ld a1,-32664\(gp\)
+ 12000038c: 00b1282d daddu a1,a1,s1
+ 120000390: df858028 ld a1,-32728\(gp\)
+ 120000394: dca50574 ld a1,1396\(a1\)
+ 120000398: df858028 ld a1,-32728\(gp\)
+ 12000039c: dca50580 ld a1,1408\(a1\)
+ 1200003a0: df858028 ld a1,-32728\(gp\)
+ 1200003a4: 00b1282d daddu a1,a1,s1
+ 1200003a8: dca50574 ld a1,1396\(a1\)
+ 1200003ac: df858028 ld a1,-32728\(gp\)
+ 1200003b0: 00b1282d daddu a1,a1,s1
+ 1200003b4: dca50580 ld a1,1408\(a1\)
+ 1200003b8: df818028 ld at,-32728\(gp\)
+ 1200003bc: 0025082d daddu at,at,a1
+ 1200003c0: dc250596 ld a1,1430\(at\)
+ 1200003c4: df818028 ld at,-32728\(gp\)
+ 1200003c8: 0025082d daddu at,at,a1
+ 1200003cc: fc2505ac sd a1,1452\(at\)
+ 1200003d0: df818058 ld at,-32680\(gp\)
+ 1200003d4: 88250000 lwl a1,0\(at\)
+ 1200003d8: 98250003 lwr a1,3\(at\)
+ 1200003dc: df818060 ld at,-32672\(gp\)
+ 1200003e0: 88250000 lwl a1,0\(at\)
+ 1200003e4: 98250003 lwr a1,3\(at\)
+ 1200003e8: df818058 ld at,-32680\(gp\)
+ 1200003ec: 0031082d daddu at,at,s1
+ 1200003f0: 88250000 lwl a1,0\(at\)
+ 1200003f4: 98250003 lwr a1,3\(at\)
+ 1200003f8: df818060 ld at,-32672\(gp\)
+ 1200003fc: 0031082d daddu at,at,s1
+ 120000400: 88250000 lwl a1,0\(at\)
+ 120000404: 98250003 lwr a1,3\(at\)
+ 120000408: df818070 ld at,-32656\(gp\)
+ 12000040c: 0025082d daddu at,at,a1
+ 120000410: 88250000 lwl a1,0\(at\)
+ 120000414: 98250003 lwr a1,3\(at\)
+ 120000418: df818078 ld at,-32648\(gp\)
+ 12000041c: 0025082d daddu at,at,a1
+ 120000420: a8250000 swl a1,0\(at\)
+ 120000424: b8250003 swr a1,3\(at\)
+ 120000428: df858080 ld a1,-32640\(gp\)
+ 12000042c: df858080 ld a1,-32640\(gp\)
+ 120000430: df998080 ld t9,-32640\(gp\)
+ 120000434: df998080 ld t9,-32640\(gp\)
+ 120000438: df998080 ld t9,-32640\(gp\)
+ 12000043c: 0411001d bal 1200004b4 <fn2>
+ 120000440: 00000000 nop
+ 120000444: df998080 ld t9,-32640\(gp\)
+ 120000448: 0411001a bal 1200004b4 <fn2>
+ 12000044c: 00000000 nop
+ 120000450: 1000ff17 b 1200000b0 <fn>
+ 120000454: df858020 ld a1,-32736\(gp\)
+ 120000458: df858028 ld a1,-32728\(gp\)
+ 12000045c: 10000015 b 1200004b4 <fn2>
+ 120000460: dca50574 ld a1,1396\(a1\)
+ 120000464: 1000ff12 b 1200000b0 <fn>
+ 120000468: df858020 ld a1,-32736\(gp\)
+ 12000046c: df858060 ld a1,-32672\(gp\)
+ 120000470: 10000010 b 1200004b4 <fn2>
+ 120000474: 00000000 nop
+ 120000478: df858038 ld a1,-32712\(gp\)
+ 12000047c: 1000ff0c b 1200000b0 <fn>
+ 120000480: 00000000 nop
+ 120000484: df858028 ld a1,-32728\(gp\)
+ 120000488: 1000000a b 1200004b4 <fn2>
+ 12000048c: dca50574 ld a1,1396\(a1\)
+ 120000490: df858028 ld a1,-32728\(gp\)
+ 120000494: 1000ff06 b 1200000b0 <fn>
+ 120000498: dca50508 ld a1,1288\(a1\)
+ 12000049c: df818028 ld at,-32728\(gp\)
+ 1200004a0: 0025082d daddu at,at,a1
+ 1200004a4: 10000003 b 1200004b4 <fn2>
+ 1200004a8: dc250596 ld a1,1430\(at\)
+ \.\.\.
+
+00000001200004b4 <fn2>:
+ \.\.\.
+Disassembly of section \.data:
+
+00000001200104c0 <_fdata>:
+ \.\.\.
+
+00000001200104fc <dg1>:
+ \.\.\.
+
+0000000120010538 <sp2>:
+ \.\.\.
+
+0000000120010574 <dg2>:
+ \.\.\.
+Disassembly of section \.got:
+
+00000001200105b0 <_GLOBAL_OFFSET_TABLE_>:
+ \.\.\.
+ 1200105b8: 80000000 .*
+ 1200105bc: 00000000 .*
+ 1200105c0: 00000001 .*
+ 1200105c4: 200104fc .*
+ 1200105c8: 00000001 .*
+ 1200105cc: 20010000 .*
+ 1200105d0: 00000001 .*
+ 1200105d4: 20010508 .*
+ 1200105d8: 00000001 .*
+ 1200105dc: 2002e73c .*
+ 1200105e0: 00000001 .*
+ 1200105e4: 2001051e .*
+ 1200105e8: 00000001 .*
+ 1200105ec: 20010534 .*
+ 1200105f0: 00000001 .*
+ 1200105f4: 200000b0 .*
+ 1200105f8: 00000001 .*
+ 1200105fc: 20010574 .*
+ 120010600: 00000001 .*
+ 120010604: 20010580 .*
+ 120010608: 00000001 .*
+ 12001060c: 2002e7b4 .*
+ 120010610: 00000001 .*
+ 120010614: 20010596 .*
+ 120010618: 00000001 .*
+ 12001061c: 200105ac .*
+ 120010620: 00000001 .*
+ 120010624: 200004b4 .*
+ \.\.\.
+#pass
#name: MIPS ELF got reloc n64
-#as: -EB -64 -KPIC
+#as: -march=from-abi -EB -64 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
#name: MIPS ELF got reloc n64
-#as: -EB -64 -KPIC
+#as: -march=from-abi -EB -64 -KPIC
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
Disassembly of section \.MIPS\.options:
-00000000100000b0 <\.MIPS\.options>:
- 100000b0: 01280000 .*
- 100000b4: 00000000 .*
- 100000b8: 92020022 .*
+00000000100000e8 <\.MIPS\.options>:
+ 100000e8: 01280000 .*
+ 100000ec: 00000000 .*
+ 100000f0: 92020022 .*
\.\.\.
- 100000d4: 101085d0 .*
+ 1000010c: 10018600 .*
Disassembly of section \.text:
-00000000100000e0 <fn>:
- 100000e0: df8580b8 ld a1,-32584\(gp\)
- 100000e4: df8580b8 ld a1,-32584\(gp\)
- 100000e8: 64a5000c daddiu a1,a1,12
- 100000ec: df8580b8 ld a1,-32584\(gp\)
- 100000f0: 3c010002 lui at,0x2
- 100000f4: 6421e240 daddiu at,at,-7616
- 100000f8: 00a1282d daddu a1,a1,at
- 100000fc: df8580b8 ld a1,-32584\(gp\)
- 10000100: 00b1282d daddu a1,a1,s1
- 10000104: df8580b8 ld a1,-32584\(gp\)
- 10000108: 64a5000c daddiu a1,a1,12
- 1000010c: 00b1282d daddu a1,a1,s1
- 10000110: df8580b8 ld a1,-32584\(gp\)
- 10000114: 3c010002 lui at,0x2
- 10000118: 6421e240 daddiu at,at,-7616
- 1000011c: 00a1282d daddu a1,a1,at
- 10000120: 00b1282d daddu a1,a1,s1
- 10000124: df8580b8 ld a1,-32584\(gp\)
- 10000128: dca50000 ld a1,0\(a1\)
- 1000012c: df8580b8 ld a1,-32584\(gp\)
- 10000130: dca5000c ld a1,12\(a1\)
- 10000134: df8580b8 ld a1,-32584\(gp\)
- 10000138: 00b1282d daddu a1,a1,s1
- 1000013c: dca50000 ld a1,0\(a1\)
- 10000140: df8580b8 ld a1,-32584\(gp\)
- 10000144: 00b1282d daddu a1,a1,s1
- 10000148: dca5000c ld a1,12\(a1\)
- 1000014c: df8180b8 ld at,-32584\(gp\)
- 10000150: 0025082d daddu at,at,a1
- 10000154: dc250022 ld a1,34\(at\)
- 10000158: df8180b8 ld at,-32584\(gp\)
- 1000015c: 0025082d daddu at,at,a1
- 10000160: fc250038 sd a1,56\(at\)
- 10000164: df8180b8 ld at,-32584\(gp\)
- 10000168: 88250000 lwl a1,0\(at\)
- 1000016c: 98250003 lwr a1,3\(at\)
- 10000170: df8180b8 ld at,-32584\(gp\)
- 10000174: 6421000c daddiu at,at,12
- 10000178: 88250000 lwl a1,0\(at\)
- 1000017c: 98250003 lwr a1,3\(at\)
- 10000180: df8180b8 ld at,-32584\(gp\)
- 10000184: 0031082d daddu at,at,s1
- 10000188: 88250000 lwl a1,0\(at\)
- 1000018c: 98250003 lwr a1,3\(at\)
- 10000190: df8180b8 ld at,-32584\(gp\)
- 10000194: 6421000c daddiu at,at,12
- 10000198: 0031082d daddu at,at,s1
- 1000019c: 88250000 lwl a1,0\(at\)
- 100001a0: 98250003 lwr a1,3\(at\)
- 100001a4: df8180b8 ld at,-32584\(gp\)
- 100001a8: 64210022 daddiu at,at,34
- 100001ac: 0025082d daddu at,at,a1
- 100001b0: 88250000 lwl a1,0\(at\)
- 100001b4: 98250003 lwr a1,3\(at\)
- 100001b8: df8180b8 ld at,-32584\(gp\)
- 100001bc: 64210038 daddiu at,at,56
- 100001c0: 0025082d daddu at,at,a1
- 100001c4: a8250000 swl a1,0\(at\)
- 100001c8: b8250003 swr a1,3\(at\)
- 100001cc: df858020 ld a1,-32736\(gp\)
- 100001d0: df858028 ld a1,-32728\(gp\)
- 100001d4: df858030 ld a1,-32720\(gp\)
- 100001d8: df858020 ld a1,-32736\(gp\)
- 100001dc: 00b1282d daddu a1,a1,s1
- 100001e0: df858028 ld a1,-32728\(gp\)
- 100001e4: 00b1282d daddu a1,a1,s1
- 100001e8: df858030 ld a1,-32720\(gp\)
- 100001ec: 00b1282d daddu a1,a1,s1
- 100001f0: df858038 ld a1,-32712\(gp\)
- 100001f4: dca5052c ld a1,1324\(a1\)
- 100001f8: df858038 ld a1,-32712\(gp\)
- 100001fc: dca50538 ld a1,1336\(a1\)
- 10000200: df858038 ld a1,-32712\(gp\)
- 10000204: 00b1282d daddu a1,a1,s1
- 10000208: dca5052c ld a1,1324\(a1\)
- 1000020c: df858038 ld a1,-32712\(gp\)
- 10000210: 00b1282d daddu a1,a1,s1
- 10000214: dca50538 ld a1,1336\(a1\)
- 10000218: df818038 ld at,-32712\(gp\)
- 1000021c: 0025082d daddu at,at,a1
- 10000220: dc25054e ld a1,1358\(at\)
- 10000224: df818038 ld at,-32712\(gp\)
- 10000228: 0025082d daddu at,at,a1
- 1000022c: fc250564 sd a1,1380\(at\)
- 10000230: df818020 ld at,-32736\(gp\)
- 10000234: 88250000 lwl a1,0\(at\)
- 10000238: 98250003 lwr a1,3\(at\)
- 1000023c: df818028 ld at,-32728\(gp\)
- 10000240: 88250000 lwl a1,0\(at\)
- 10000244: 98250003 lwr a1,3\(at\)
- 10000248: df818020 ld at,-32736\(gp\)
- 1000024c: 0031082d daddu at,at,s1
- 10000250: 88250000 lwl a1,0\(at\)
- 10000254: 98250003 lwr a1,3\(at\)
- 10000258: df818028 ld at,-32728\(gp\)
- 1000025c: 0031082d daddu at,at,s1
- 10000260: 88250000 lwl a1,0\(at\)
- 10000264: 98250003 lwr a1,3\(at\)
- 10000268: df818040 ld at,-32704\(gp\)
- 1000026c: 0025082d daddu at,at,a1
+0000000010000110 <fn>:
+ 10000110: df858020 ld a1,-32736\(gp\)
+ 10000114: df858020 ld a1,-32736\(gp\)
+ 10000118: 64a5000c daddiu a1,a1,12
+ 1000011c: df858020 ld a1,-32736\(gp\)
+ 10000120: 3c010001 lui at,0x1
+ 10000124: 3421e240 ori at,at,0xe240
+ 10000128: 00a1282d daddu a1,a1,at
+ 1000012c: df858020 ld a1,-32736\(gp\)
+ 10000130: 00b1282d daddu a1,a1,s1
+ 10000134: df858020 ld a1,-32736\(gp\)
+ 10000138: 64a5000c daddiu a1,a1,12
+ 1000013c: 00b1282d daddu a1,a1,s1
+ 10000140: df858020 ld a1,-32736\(gp\)
+ 10000144: 3c010001 lui at,0x1
+ 10000148: 3421e240 ori at,at,0xe240
+ 1000014c: 00a1282d daddu a1,a1,at
+ 10000150: 00b1282d daddu a1,a1,s1
+ 10000154: df858028 ld a1,-32728\(gp\)
+ 10000158: dca5055c ld a1,1372\(a1\)
+ 1000015c: df858028 ld a1,-32728\(gp\)
+ 10000160: dca50568 ld a1,1384\(a1\)
+ 10000164: df858028 ld a1,-32728\(gp\)
+ 10000168: 00b1282d daddu a1,a1,s1
+ 1000016c: dca5055c ld a1,1372\(a1\)
+ 10000170: df858028 ld a1,-32728\(gp\)
+ 10000174: 00b1282d daddu a1,a1,s1
+ 10000178: dca50568 ld a1,1384\(a1\)
+ 1000017c: df818028 ld at,-32728\(gp\)
+ 10000180: 0025082d daddu at,at,a1
+ 10000184: dc25057e ld a1,1406\(at\)
+ 10000188: df818028 ld at,-32728\(gp\)
+ 1000018c: 0025082d daddu at,at,a1
+ 10000190: fc250594 sd a1,1428\(at\)
+ 10000194: df818020 ld at,-32736\(gp\)
+ 10000198: 88250000 lwl a1,0\(at\)
+ 1000019c: 98250003 lwr a1,3\(at\)
+ 100001a0: df818020 ld at,-32736\(gp\)
+ 100001a4: 6421000c daddiu at,at,12
+ 100001a8: 88250000 lwl a1,0\(at\)
+ 100001ac: 98250003 lwr a1,3\(at\)
+ 100001b0: df818020 ld at,-32736\(gp\)
+ 100001b4: 0031082d daddu at,at,s1
+ 100001b8: 88250000 lwl a1,0\(at\)
+ 100001bc: 98250003 lwr a1,3\(at\)
+ 100001c0: df818020 ld at,-32736\(gp\)
+ 100001c4: 6421000c daddiu at,at,12
+ 100001c8: 0031082d daddu at,at,s1
+ 100001cc: 88250000 lwl a1,0\(at\)
+ 100001d0: 98250003 lwr a1,3\(at\)
+ 100001d4: df818020 ld at,-32736\(gp\)
+ 100001d8: 64210022 daddiu at,at,34
+ 100001dc: 0025082d daddu at,at,a1
+ 100001e0: 88250000 lwl a1,0\(at\)
+ 100001e4: 98250003 lwr a1,3\(at\)
+ 100001e8: df818020 ld at,-32736\(gp\)
+ 100001ec: 64210038 daddiu at,at,56
+ 100001f0: 0025082d daddu at,at,a1
+ 100001f4: a8250000 swl a1,0\(at\)
+ 100001f8: b8250003 swr a1,3\(at\)
+ 100001fc: df858020 ld a1,-32736\(gp\)
+ 10000200: df858030 ld a1,-32720\(gp\)
+ 10000204: df858038 ld a1,-32712\(gp\)
+ 10000208: df858020 ld a1,-32736\(gp\)
+ 1000020c: 00b1282d daddu a1,a1,s1
+ 10000210: df858030 ld a1,-32720\(gp\)
+ 10000214: 00b1282d daddu a1,a1,s1
+ 10000218: df858038 ld a1,-32712\(gp\)
+ 1000021c: 00b1282d daddu a1,a1,s1
+ 10000220: df858028 ld a1,-32728\(gp\)
+ 10000224: dca5055c ld a1,1372\(a1\)
+ 10000228: df858028 ld a1,-32728\(gp\)
+ 1000022c: dca50568 ld a1,1384\(a1\)
+ 10000230: df858028 ld a1,-32728\(gp\)
+ 10000234: 00b1282d daddu a1,a1,s1
+ 10000238: dca5055c ld a1,1372\(a1\)
+ 1000023c: df858028 ld a1,-32728\(gp\)
+ 10000240: 00b1282d daddu a1,a1,s1
+ 10000244: dca50568 ld a1,1384\(a1\)
+ 10000248: df818028 ld at,-32728\(gp\)
+ 1000024c: 0025082d daddu at,at,a1
+ 10000250: dc25057e ld a1,1406\(at\)
+ 10000254: df818028 ld at,-32728\(gp\)
+ 10000258: 0025082d daddu at,at,a1
+ 1000025c: fc250594 sd a1,1428\(at\)
+ 10000260: df818020 ld at,-32736\(gp\)
+ 10000264: 88250000 lwl a1,0\(at\)
+ 10000268: 98250003 lwr a1,3\(at\)
+ 1000026c: df818030 ld at,-32720\(gp\)
10000270: 88250000 lwl a1,0\(at\)
10000274: 98250003 lwr a1,3\(at\)
- 10000278: df818048 ld at,-32696\(gp\)
- 1000027c: 0025082d daddu at,at,a1
- 10000280: a8250000 swl a1,0\(at\)
- 10000284: b8250003 swr a1,3\(at\)
- 10000288: df8580a8 ld a1,-32600\(gp\)
- 1000028c: df858050 ld a1,-32688\(gp\)
- 10000290: df9980a8 ld t9,-32600\(gp\)
- 10000294: df998050 ld t9,-32688\(gp\)
- 10000298: df9980a8 ld t9,-32600\(gp\)
- 1000029c: 0320f809 jalr t9
- 100002a0: 00000000 nop
- 100002a4: df998050 ld t9,-32688\(gp\)
- 100002a8: 0320f809 jalr t9
- 100002ac: 00000000 nop
- 100002b0: df8580c0 ld a1,-32576\(gp\)
- 100002b4: df8580c0 ld a1,-32576\(gp\)
- 100002b8: 64a5000c daddiu a1,a1,12
- 100002bc: df8580c0 ld a1,-32576\(gp\)
- 100002c0: 3c010002 lui at,0x2
- 100002c4: 6421e240 daddiu at,at,-7616
- 100002c8: 00a1282d daddu a1,a1,at
- 100002cc: df8580c0 ld a1,-32576\(gp\)
- 100002d0: 00b1282d daddu a1,a1,s1
- 100002d4: df8580c0 ld a1,-32576\(gp\)
- 100002d8: 64a5000c daddiu a1,a1,12
- 100002dc: 00b1282d daddu a1,a1,s1
- 100002e0: df8580c0 ld a1,-32576\(gp\)
- 100002e4: 3c010002 lui at,0x2
- 100002e8: 6421e240 daddiu at,at,-7616
- 100002ec: 00a1282d daddu a1,a1,at
- 100002f0: 00b1282d daddu a1,a1,s1
- 100002f4: df8580c0 ld a1,-32576\(gp\)
- 100002f8: dca50000 ld a1,0\(a1\)
- 100002fc: df8580c0 ld a1,-32576\(gp\)
- 10000300: dca5000c ld a1,12\(a1\)
- 10000304: df8580c0 ld a1,-32576\(gp\)
- 10000308: 00b1282d daddu a1,a1,s1
- 1000030c: dca50000 ld a1,0\(a1\)
- 10000310: df8580c0 ld a1,-32576\(gp\)
- 10000314: 00b1282d daddu a1,a1,s1
- 10000318: dca5000c ld a1,12\(a1\)
- 1000031c: df8180c0 ld at,-32576\(gp\)
- 10000320: 0025082d daddu at,at,a1
- 10000324: dc250022 ld a1,34\(at\)
- 10000328: df8180c0 ld at,-32576\(gp\)
- 1000032c: 0025082d daddu at,at,a1
- 10000330: fc250038 sd a1,56\(at\)
- 10000334: df8180c0 ld at,-32576\(gp\)
- 10000338: 88250000 lwl a1,0\(at\)
- 1000033c: 98250003 lwr a1,3\(at\)
- 10000340: df8180c0 ld at,-32576\(gp\)
- 10000344: 6421000c daddiu at,at,12
- 10000348: 88250000 lwl a1,0\(at\)
- 1000034c: 98250003 lwr a1,3\(at\)
- 10000350: df8180c0 ld at,-32576\(gp\)
- 10000354: 0031082d daddu at,at,s1
- 10000358: 88250000 lwl a1,0\(at\)
- 1000035c: 98250003 lwr a1,3\(at\)
- 10000360: df8180c0 ld at,-32576\(gp\)
- 10000364: 6421000c daddiu at,at,12
- 10000368: 0031082d daddu at,at,s1
- 1000036c: 88250000 lwl a1,0\(at\)
- 10000370: 98250003 lwr a1,3\(at\)
- 10000374: df8180c0 ld at,-32576\(gp\)
- 10000378: 64210022 daddiu at,at,34
- 1000037c: 0025082d daddu at,at,a1
- 10000380: 88250000 lwl a1,0\(at\)
- 10000384: 98250003 lwr a1,3\(at\)
- 10000388: df8180c0 ld at,-32576\(gp\)
- 1000038c: 64210038 daddiu at,at,56
- 10000390: 0025082d daddu at,at,a1
- 10000394: a8250000 swl a1,0\(at\)
- 10000398: b8250003 swr a1,3\(at\)
- 1000039c: df858058 ld a1,-32680\(gp\)
- 100003a0: df858060 ld a1,-32672\(gp\)
- 100003a4: df858068 ld a1,-32664\(gp\)
- 100003a8: df858058 ld a1,-32680\(gp\)
- 100003ac: 00b1282d daddu a1,a1,s1
- 100003b0: df858060 ld a1,-32672\(gp\)
- 100003b4: 00b1282d daddu a1,a1,s1
- 100003b8: df858068 ld a1,-32664\(gp\)
- 100003bc: 00b1282d daddu a1,a1,s1
- 100003c0: df858038 ld a1,-32712\(gp\)
- 100003c4: dca505a4 ld a1,1444\(a1\)
- 100003c8: df858038 ld a1,-32712\(gp\)
- 100003cc: dca505b0 ld a1,1456\(a1\)
- 100003d0: df858038 ld a1,-32712\(gp\)
- 100003d4: 00b1282d daddu a1,a1,s1
- 100003d8: dca505a4 ld a1,1444\(a1\)
- 100003dc: df858038 ld a1,-32712\(gp\)
- 100003e0: 00b1282d daddu a1,a1,s1
- 100003e4: dca505b0 ld a1,1456\(a1\)
- 100003e8: df818038 ld at,-32712\(gp\)
- 100003ec: 0025082d daddu at,at,a1
- 100003f0: dc2505c6 ld a1,1478\(at\)
- 100003f4: df818038 ld at,-32712\(gp\)
- 100003f8: 0025082d daddu at,at,a1
- 100003fc: fc2505dc sd a1,1500\(at\)
- 10000400: df818058 ld at,-32680\(gp\)
- 10000404: 88250000 lwl a1,0\(at\)
- 10000408: 98250003 lwr a1,3\(at\)
- 1000040c: df818060 ld at,-32672\(gp\)
- 10000410: 88250000 lwl a1,0\(at\)
- 10000414: 98250003 lwr a1,3\(at\)
- 10000418: df818058 ld at,-32680\(gp\)
- 1000041c: 0031082d daddu at,at,s1
- 10000420: 88250000 lwl a1,0\(at\)
- 10000424: 98250003 lwr a1,3\(at\)
- 10000428: df818060 ld at,-32672\(gp\)
- 1000042c: 0031082d daddu at,at,s1
- 10000430: 88250000 lwl a1,0\(at\)
- 10000434: 98250003 lwr a1,3\(at\)
- 10000438: df818070 ld at,-32656\(gp\)
- 1000043c: 0025082d daddu at,at,a1
+ 10000278: df818020 ld at,-32736\(gp\)
+ 1000027c: 0031082d daddu at,at,s1
+ 10000280: 88250000 lwl a1,0\(at\)
+ 10000284: 98250003 lwr a1,3\(at\)
+ 10000288: df818030 ld at,-32720\(gp\)
+ 1000028c: 0031082d daddu at,at,s1
+ 10000290: 88250000 lwl a1,0\(at\)
+ 10000294: 98250003 lwr a1,3\(at\)
+ 10000298: df818040 ld at,-32704\(gp\)
+ 1000029c: 0025082d daddu at,at,a1
+ 100002a0: 88250000 lwl a1,0\(at\)
+ 100002a4: 98250003 lwr a1,3\(at\)
+ 100002a8: df818048 ld at,-32696\(gp\)
+ 100002ac: 0025082d daddu at,at,a1
+ 100002b0: a8250000 swl a1,0\(at\)
+ 100002b4: b8250003 swr a1,3\(at\)
+ 100002b8: df858050 ld a1,-32688\(gp\)
+ 100002bc: df858050 ld a1,-32688\(gp\)
+ 100002c0: df998050 ld t9,-32688\(gp\)
+ 100002c4: df998050 ld t9,-32688\(gp\)
+ 100002c8: df998050 ld t9,-32688\(gp\)
+ 100002cc: 0411ff90 bal 10000110 <fn>
+ 100002d0: 00000000 nop
+ 100002d4: df998050 ld t9,-32688\(gp\)
+ 100002d8: 0411ff8d bal 10000110 <fn>
+ 100002dc: 00000000 nop
+ 100002e0: df858058 ld a1,-32680\(gp\)
+ 100002e4: df858058 ld a1,-32680\(gp\)
+ 100002e8: 64a5000c daddiu a1,a1,12
+ 100002ec: df858058 ld a1,-32680\(gp\)
+ 100002f0: 3c010001 lui at,0x1
+ 100002f4: 3421e240 ori at,at,0xe240
+ 100002f8: 00a1282d daddu a1,a1,at
+ 100002fc: df858058 ld a1,-32680\(gp\)
+ 10000300: 00b1282d daddu a1,a1,s1
+ 10000304: df858058 ld a1,-32680\(gp\)
+ 10000308: 64a5000c daddiu a1,a1,12
+ 1000030c: 00b1282d daddu a1,a1,s1
+ 10000310: df858058 ld a1,-32680\(gp\)
+ 10000314: 3c010001 lui at,0x1
+ 10000318: 3421e240 ori at,at,0xe240
+ 1000031c: 00a1282d daddu a1,a1,at
+ 10000320: 00b1282d daddu a1,a1,s1
+ 10000324: df858028 ld a1,-32728\(gp\)
+ 10000328: dca505d4 ld a1,1492\(a1\)
+ 1000032c: df858028 ld a1,-32728\(gp\)
+ 10000330: dca505e0 ld a1,1504\(a1\)
+ 10000334: df858028 ld a1,-32728\(gp\)
+ 10000338: 00b1282d daddu a1,a1,s1
+ 1000033c: dca505d4 ld a1,1492\(a1\)
+ 10000340: df858028 ld a1,-32728\(gp\)
+ 10000344: 00b1282d daddu a1,a1,s1
+ 10000348: dca505e0 ld a1,1504\(a1\)
+ 1000034c: df818028 ld at,-32728\(gp\)
+ 10000350: 0025082d daddu at,at,a1
+ 10000354: dc2505f6 ld a1,1526\(at\)
+ 10000358: df818028 ld at,-32728\(gp\)
+ 1000035c: 0025082d daddu at,at,a1
+ 10000360: fc25060c sd a1,1548\(at\)
+ 10000364: df818058 ld at,-32680\(gp\)
+ 10000368: 88250000 lwl a1,0\(at\)
+ 1000036c: 98250003 lwr a1,3\(at\)
+ 10000370: df818058 ld at,-32680\(gp\)
+ 10000374: 6421000c daddiu at,at,12
+ 10000378: 88250000 lwl a1,0\(at\)
+ 1000037c: 98250003 lwr a1,3\(at\)
+ 10000380: df818058 ld at,-32680\(gp\)
+ 10000384: 0031082d daddu at,at,s1
+ 10000388: 88250000 lwl a1,0\(at\)
+ 1000038c: 98250003 lwr a1,3\(at\)
+ 10000390: df818058 ld at,-32680\(gp\)
+ 10000394: 6421000c daddiu at,at,12
+ 10000398: 0031082d daddu at,at,s1
+ 1000039c: 88250000 lwl a1,0\(at\)
+ 100003a0: 98250003 lwr a1,3\(at\)
+ 100003a4: df818058 ld at,-32680\(gp\)
+ 100003a8: 64210022 daddiu at,at,34
+ 100003ac: 0025082d daddu at,at,a1
+ 100003b0: 88250000 lwl a1,0\(at\)
+ 100003b4: 98250003 lwr a1,3\(at\)
+ 100003b8: df818058 ld at,-32680\(gp\)
+ 100003bc: 64210038 daddiu at,at,56
+ 100003c0: 0025082d daddu at,at,a1
+ 100003c4: a8250000 swl a1,0\(at\)
+ 100003c8: b8250003 swr a1,3\(at\)
+ 100003cc: df858058 ld a1,-32680\(gp\)
+ 100003d0: df858060 ld a1,-32672\(gp\)
+ 100003d4: df858068 ld a1,-32664\(gp\)
+ 100003d8: df858058 ld a1,-32680\(gp\)
+ 100003dc: 00b1282d daddu a1,a1,s1
+ 100003e0: df858060 ld a1,-32672\(gp\)
+ 100003e4: 00b1282d daddu a1,a1,s1
+ 100003e8: df858068 ld a1,-32664\(gp\)
+ 100003ec: 00b1282d daddu a1,a1,s1
+ 100003f0: df858028 ld a1,-32728\(gp\)
+ 100003f4: dca505d4 ld a1,1492\(a1\)
+ 100003f8: df858028 ld a1,-32728\(gp\)
+ 100003fc: dca505e0 ld a1,1504\(a1\)
+ 10000400: df858028 ld a1,-32728\(gp\)
+ 10000404: 00b1282d daddu a1,a1,s1
+ 10000408: dca505d4 ld a1,1492\(a1\)
+ 1000040c: df858028 ld a1,-32728\(gp\)
+ 10000410: 00b1282d daddu a1,a1,s1
+ 10000414: dca505e0 ld a1,1504\(a1\)
+ 10000418: df818028 ld at,-32728\(gp\)
+ 1000041c: 0025082d daddu at,at,a1
+ 10000420: dc2505f6 ld a1,1526\(at\)
+ 10000424: df818028 ld at,-32728\(gp\)
+ 10000428: 0025082d daddu at,at,a1
+ 1000042c: fc25060c sd a1,1548\(at\)
+ 10000430: df818058 ld at,-32680\(gp\)
+ 10000434: 88250000 lwl a1,0\(at\)
+ 10000438: 98250003 lwr a1,3\(at\)
+ 1000043c: df818060 ld at,-32672\(gp\)
10000440: 88250000 lwl a1,0\(at\)
10000444: 98250003 lwr a1,3\(at\)
- 10000448: df818078 ld at,-32648\(gp\)
- 1000044c: 0025082d daddu at,at,a1
- 10000450: a8250000 swl a1,0\(at\)
- 10000454: b8250003 swr a1,3\(at\)
- 10000458: df8580b0 ld a1,-32592\(gp\)
- 1000045c: df858080 ld a1,-32640\(gp\)
- 10000460: df9980b0 ld t9,-32592\(gp\)
- 10000464: df998080 ld t9,-32640\(gp\)
- 10000468: df9980b0 ld t9,-32592\(gp\)
- 1000046c: 0320f809 jalr t9
- 10000470: 00000000 nop
- 10000474: df998080 ld t9,-32640\(gp\)
- 10000478: 0320f809 jalr t9
- 1000047c: 00000000 nop
- 10000480: 1000ff17 b 100000e0 <fn>
- 10000484: df8580b8 ld a1,-32584\(gp\)
- 10000488: df8580c0 ld a1,-32576\(gp\)
- 1000048c: 10000015 b 100004e4 <fn2>
- 10000490: dca50000 ld a1,0\(a1\)
- 10000494: 1000ff12 b 100000e0 <fn>
- 10000498: df858020 ld a1,-32736\(gp\)
- 1000049c: df858060 ld a1,-32672\(gp\)
- 100004a0: 10000010 b 100004e4 <fn2>
- 100004a4: 00000000 nop
- 100004a8: df858030 ld a1,-32720\(gp\)
- 100004ac: 1000ff0c b 100000e0 <fn>
- 100004b0: 00000000 nop
- 100004b4: df858038 ld a1,-32712\(gp\)
- 100004b8: 1000000a b 100004e4 <fn2>
- 100004bc: dca505a4 ld a1,1444\(a1\)
- 100004c0: df858038 ld a1,-32712\(gp\)
- 100004c4: 1000ff06 b 100000e0 <fn>
- 100004c8: dca50538 ld a1,1336\(a1\)
- 100004cc: df818038 ld at,-32712\(gp\)
- 100004d0: 0025082d daddu at,at,a1
- 100004d4: 10000003 b 100004e4 <fn2>
- 100004d8: dc2505c6 ld a1,1478\(at\)
+ 10000448: df818058 ld at,-32680\(gp\)
+ 1000044c: 0031082d daddu at,at,s1
+ 10000450: 88250000 lwl a1,0\(at\)
+ 10000454: 98250003 lwr a1,3\(at\)
+ 10000458: df818060 ld at,-32672\(gp\)
+ 1000045c: 0031082d daddu at,at,s1
+ 10000460: 88250000 lwl a1,0\(at\)
+ 10000464: 98250003 lwr a1,3\(at\)
+ 10000468: df818070 ld at,-32656\(gp\)
+ 1000046c: 0025082d daddu at,at,a1
+ 10000470: 88250000 lwl a1,0\(at\)
+ 10000474: 98250003 lwr a1,3\(at\)
+ 10000478: df818078 ld at,-32648\(gp\)
+ 1000047c: 0025082d daddu at,at,a1
+ 10000480: a8250000 swl a1,0\(at\)
+ 10000484: b8250003 swr a1,3\(at\)
+ 10000488: df858080 ld a1,-32640\(gp\)
+ 1000048c: df858080 ld a1,-32640\(gp\)
+ 10000490: df998080 ld t9,-32640\(gp\)
+ 10000494: df998080 ld t9,-32640\(gp\)
+ 10000498: df998080 ld t9,-32640\(gp\)
+ 1000049c: 0411001d bal 10000514 <fn2>
+ 100004a0: 00000000 nop
+ 100004a4: df998080 ld t9,-32640\(gp\)
+ 100004a8: 0411001a bal 10000514 <fn2>
+ 100004ac: 00000000 nop
+ 100004b0: 1000ff17 b 10000110 <fn>
+ 100004b4: df858020 ld a1,-32736\(gp\)
+ 100004b8: df858028 ld a1,-32728\(gp\)
+ 100004bc: 10000015 b 10000514 <fn2>
+ 100004c0: dca505d4 ld a1,1492\(a1\)
+ 100004c4: 1000ff12 b 10000110 <fn>
+ 100004c8: df858020 ld a1,-32736\(gp\)
+ 100004cc: df858060 ld a1,-32672\(gp\)
+ 100004d0: 10000010 b 10000514 <fn2>
+ 100004d4: 00000000 nop
+ 100004d8: df858038 ld a1,-32712\(gp\)
+ 100004dc: 1000ff0c b 10000110 <fn>
+ 100004e0: 00000000 nop
+ 100004e4: df858028 ld a1,-32728\(gp\)
+ 100004e8: 1000000a b 10000514 <fn2>
+ 100004ec: dca505d4 ld a1,1492\(a1\)
+ 100004f0: df858028 ld a1,-32728\(gp\)
+ 100004f4: 1000ff06 b 10000110 <fn>
+ 100004f8: dca50568 ld a1,1384\(a1\)
+ 100004fc: df818028 ld at,-32728\(gp\)
+ 10000500: 0025082d daddu at,at,a1
+ 10000504: 10000003 b 10000514 <fn2>
+ 10000508: dc2505f6 ld a1,1526\(at\)
\.\.\.
-00000000100004e4 <fn2>:
+0000000010000514 <fn2>:
\.\.\.
Disassembly of section \.data:
-00000000101004f0 <_fdata>:
+0000000010010520 <_fdata>:
\.\.\.
-000000001010052c <dg1>:
+000000001001055c <dg1>:
\.\.\.
-0000000010100568 <sp2>:
+0000000010010598 <sp2>:
\.\.\.
-00000000101005a4 <dg2>:
+00000000100105d4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000000101005e0 <_GLOBAL_OFFSET_TABLE_>:
+0000000010010610 <_GLOBAL_OFFSET_TABLE_>:
\.\.\.
- 101005e8: 80000000 .*
- 101005ec: 00000000 .*
- 101005f0: 00000000 .*
- 101005f4: 1010052c .*
- 101005f8: 00000000 .*
- 101005fc: 10100538 .*
- 10100600: 00000000 .*
- 10100604: 1011e76c .*
- 10100608: 00000000 .*
- 1010060c: 10100000 .*
- 10100610: 00000000 .*
- 10100614: 1010054e .*
- 10100618: 00000000 .*
- 1010061c: 10100564 .*
- 10100620: 00000000 .*
- 10100624: 100000e0 .*
- 10100628: 00000000 .*
- 1010062c: 101005a4 .*
- 10100630: 00000000 .*
- 10100634: 101005b0 .*
- 10100638: 00000000 .*
- 1010063c: 1011e7e4 .*
- 10100640: 00000000 .*
- 10100644: 101005c6 .*
- 10100648: 00000000 .*
- 1010064c: 101005dc .*
- 10100650: 00000000 .*
- 10100654: 100004e4 .*
- 10100658: 00000000 .*
+ 10010618: 80000000 .*
+ \.\.\.
+ 10010624: 1001055c .*
+ 10010628: 00000000 .*
+ 1001062c: 10010000 .*
+ 10010630: 00000000 .*
+ 10010634: 10010568 .*
+ 10010638: 00000000 .*
+ 1001063c: 1002e79c .*
+ 10010640: 00000000 .*
+ 10010644: 1001057e .*
+ 10010648: 00000000 .*
+ 1001064c: 10010594 .*
+ 10010650: 00000000 .*
+ 10010654: 10000110 .*
+ 10010658: 00000000 .*
+ 1001065c: 100105d4 .*
+ 10010660: 00000000 .*
+ 10010664: 100105e0 .*
+ 10010668: 00000000 .*
+ 1001066c: 1002e814 .*
+ 10010670: 00000000 .*
+ 10010674: 100105f6 .*
+ 10010678: 00000000 .*
+ 1001067c: 1001060c .*
+ 10010680: 00000000 .*
+ 10010684: 10000514 .*
+ 10010688: 00000000 .*
\.\.\.
- 1010067c: 100000e0 .*
- 10100680: 00000000 .*
- 10100684: 100004e4 .*
- 10100688: 00000000 .*
- 1010068c: 1010052c .*
- 10100690: 00000000 .*
- 10100694: 101005a4 .*
--- /dev/null
+#name: MIPS ELF xgot reloc n32
+#as: -march=from-abi -EB -n32 -KPIC -xgot
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
+#ld:
+#objdump: -D --show-raw-insn
+
+.*: +file format elf32-n.*mips.*
+
+Disassembly of section \.reginfo:
+
+10000078 <\.reginfo>:
+10000078: 92020022 .*
+ \.\.\.
+1000008c: 10018760 .*
+
+Disassembly of section \.text:
+
+10000074 <fn>:
+10000074: 3c050000 lui a1,0x0
+10000078: 00bc2821 addu a1,a1,gp
+1000007c: 8ca58018 lw a1,-32744\(a1\)
+10000080: 3c050000 lui a1,0x0
+10000084: 00bc2821 addu a1,a1,gp
+10000088: 8ca58018 lw a1,-32744\(a1\)
+1000008c: 24a5000c addiu a1,a1,12
+10000090: 3c050000 lui a1,0x0
+10000094: 00bc2821 addu a1,a1,gp
+10000098: 8ca58018 lw a1,-32744\(a1\)
+1000009c: 3c010001 lui at,0x1
+100000a0: 3421e240 ori at,at,0xe240
+100000a4: 00a12821 addu a1,a1,at
+100000a8: 3c050000 lui a1,0x0
+100000ac: 00bc2821 addu a1,a1,gp
+100000b0: 8ca58018 lw a1,-32744\(a1\)
+100000b4: 00b12821 addu a1,a1,s1
+100000b8: 3c050000 lui a1,0x0
+100000bc: 00bc2821 addu a1,a1,gp
+100000c0: 8ca58018 lw a1,-32744\(a1\)
+100000c4: 24a5000c addiu a1,a1,12
+100000c8: 00b12821 addu a1,a1,s1
+100000cc: 3c050000 lui a1,0x0
+100000d0: 00bc2821 addu a1,a1,gp
+100000d4: 8ca58018 lw a1,-32744\(a1\)
+100000d8: 3c010001 lui at,0x1
+100000dc: 3421e240 ori at,at,0xe240
+100000e0: 00a12821 addu a1,a1,at
+100000e4: 00b12821 addu a1,a1,s1
+100000e8: 3c050000 lui a1,0x0
+100000ec: 00bc2821 addu a1,a1,gp
+100000f0: 8ca58018 lw a1,-32744\(a1\)
+100000f4: 8ca50000 lw a1,0\(a1\)
+100000f8: 3c050000 lui a1,0x0
+100000fc: 00bc2821 addu a1,a1,gp
+10000100: 8ca58018 lw a1,-32744\(a1\)
+10000104: 8ca5000c lw a1,12\(a1\)
+10000108: 3c050000 lui a1,0x0
+1000010c: 00bc2821 addu a1,a1,gp
+10000110: 8ca58018 lw a1,-32744\(a1\)
+10000114: 00b12821 addu a1,a1,s1
+10000118: 8ca50000 lw a1,0\(a1\)
+1000011c: 3c050000 lui a1,0x0
+10000120: 00bc2821 addu a1,a1,gp
+10000124: 8ca58018 lw a1,-32744\(a1\)
+10000128: 00b12821 addu a1,a1,s1
+1000012c: 8ca5000c lw a1,12\(a1\)
+10000130: 3c010000 lui at,0x0
+10000134: 003c0821 addu at,at,gp
+10000138: 8c218018 lw at,-32744\(at\)
+1000013c: 00250821 addu at,at,a1
+10000140: 8c250022 lw a1,34\(at\)
+10000144: 3c010000 lui at,0x0
+10000148: 003c0821 addu at,at,gp
+1000014c: 8c218018 lw at,-32744\(at\)
+10000150: 00250821 addu at,at,a1
+10000154: ac250038 sw a1,56\(at\)
+10000158: 3c010000 lui at,0x0
+1000015c: 003c0821 addu at,at,gp
+10000160: 8c218018 lw at,-32744\(at\)
+10000164: 88250000 lwl a1,0\(at\)
+10000168: 98250003 lwr a1,3\(at\)
+1000016c: 3c010000 lui at,0x0
+10000170: 003c0821 addu at,at,gp
+10000174: 8c218018 lw at,-32744\(at\)
+10000178: 2421000c addiu at,at,12
+1000017c: 88250000 lwl a1,0\(at\)
+10000180: 98250003 lwr a1,3\(at\)
+10000184: 3c010000 lui at,0x0
+10000188: 003c0821 addu at,at,gp
+1000018c: 8c218018 lw at,-32744\(at\)
+10000190: 00310821 addu at,at,s1
+10000194: 88250000 lwl a1,0\(at\)
+10000198: 98250003 lwr a1,3\(at\)
+1000019c: 3c010000 lui at,0x0
+100001a0: 003c0821 addu at,at,gp
+100001a4: 8c218018 lw at,-32744\(at\)
+100001a8: 2421000c addiu at,at,12
+100001ac: 00310821 addu at,at,s1
+100001b0: 88250000 lwl a1,0\(at\)
+100001b4: 98250003 lwr a1,3\(at\)
+100001b8: 3c010000 lui at,0x0
+100001bc: 003c0821 addu at,at,gp
+100001c0: 8c218018 lw at,-32744\(at\)
+100001c4: 24210022 addiu at,at,34
+100001c8: 00250821 addu at,at,a1
+100001cc: 88250000 lwl a1,0\(at\)
+100001d0: 98250003 lwr a1,3\(at\)
+100001d4: 3c010000 lui at,0x0
+100001d8: 003c0821 addu at,at,gp
+100001dc: 8c218018 lw at,-32744\(at\)
+100001e0: 24210038 addiu at,at,56
+100001e4: 00250821 addu at,at,a1
+100001e8: a8250000 swl a1,0\(at\)
+100001ec: b8250003 swr a1,3\(at\)
+100001f0: 8f85801c lw a1,-32740\(gp\)
+100001f4: 24a506b8 addiu a1,a1,1720
+100001f8: 8f85801c lw a1,-32740\(gp\)
+100001fc: 24a506c4 addiu a1,a1,1732
+10000200: 8f858020 lw a1,-32736\(gp\)
+10000204: 24a5e8f8 addiu a1,a1,-5896
+10000208: 8f85801c lw a1,-32740\(gp\)
+1000020c: 24a506b8 addiu a1,a1,1720
+10000210: 00b12821 addu a1,a1,s1
+10000214: 8f85801c lw a1,-32740\(gp\)
+10000218: 24a506c4 addiu a1,a1,1732
+1000021c: 00b12821 addu a1,a1,s1
+10000220: 8f858020 lw a1,-32736\(gp\)
+10000224: 24a5e8f8 addiu a1,a1,-5896
+10000228: 00b12821 addu a1,a1,s1
+1000022c: 8f85801c lw a1,-32740\(gp\)
+10000230: 8ca506b8 lw a1,1720\(a1\)
+10000234: 8f85801c lw a1,-32740\(gp\)
+10000238: 8ca506c4 lw a1,1732\(a1\)
+1000023c: 8f85801c lw a1,-32740\(gp\)
+10000240: 00b12821 addu a1,a1,s1
+10000244: 8ca506b8 lw a1,1720\(a1\)
+10000248: 8f85801c lw a1,-32740\(gp\)
+1000024c: 00b12821 addu a1,a1,s1
+10000250: 8ca506c4 lw a1,1732\(a1\)
+10000254: 8f81801c lw at,-32740\(gp\)
+10000258: 00250821 addu at,at,a1
+1000025c: 8c2506da lw a1,1754\(at\)
+10000260: 8f81801c lw at,-32740\(gp\)
+10000264: 00250821 addu at,at,a1
+10000268: ac2506f0 sw a1,1776\(at\)
+1000026c: 8f81801c lw at,-32740\(gp\)
+10000270: 242106b8 addiu at,at,1720
+10000274: 88250000 lwl a1,0\(at\)
+10000278: 98250003 lwr a1,3\(at\)
+1000027c: 8f81801c lw at,-32740\(gp\)
+10000280: 242106c4 addiu at,at,1732
+10000284: 88250000 lwl a1,0\(at\)
+10000288: 98250003 lwr a1,3\(at\)
+1000028c: 8f81801c lw at,-32740\(gp\)
+10000290: 242106b8 addiu at,at,1720
+10000294: 00310821 addu at,at,s1
+10000298: 88250000 lwl a1,0\(at\)
+1000029c: 98250003 lwr a1,3\(at\)
+100002a0: 8f81801c lw at,-32740\(gp\)
+100002a4: 242106c4 addiu at,at,1732
+100002a8: 00310821 addu at,at,s1
+100002ac: 88250000 lwl a1,0\(at\)
+100002b0: 98250003 lwr a1,3\(at\)
+100002b4: 8f81801c lw at,-32740\(gp\)
+100002b8: 242106da addiu at,at,1754
+100002bc: 00250821 addu at,at,a1
+100002c0: 88250000 lwl a1,0\(at\)
+100002c4: 98250003 lwr a1,3\(at\)
+100002c8: 8f81801c lw at,-32740\(gp\)
+100002cc: 242106f0 addiu at,at,1776
+100002d0: 00250821 addu at,at,a1
+100002d4: a8250000 swl a1,0\(at\)
+100002d8: b8250003 swr a1,3\(at\)
+100002dc: 3c050000 lui a1,0x0
+100002e0: 00bc2821 addu a1,a1,gp
+100002e4: 8ca58024 lw a1,-32732\(a1\)
+100002e8: 8f858028 lw a1,-32728\(gp\)
+100002ec: 24a50074 addiu a1,a1,116
+100002f0: 3c190000 lui t9,0x0
+100002f4: 033cc821 addu t9,t9,gp
+100002f8: 8f398024 lw t9,-32732\(t9\)
+100002fc: 8f998028 lw t9,-32728\(gp\)
+10000300: 27390074 addiu t9,t9,116
+10000304: 3c190000 lui t9,0x0
+10000308: 033cc821 addu t9,t9,gp
+1000030c: 8f398024 lw t9,-32732\(t9\)
+10000310: 0411ff58 bal 10000074 <fn>
+10000314: 00000000 nop
+10000318: 8f998028 lw t9,-32728\(gp\)
+1000031c: 27390074 addiu t9,t9,116
+10000320: 0411ff54 bal 10000074 <fn>
+10000324: 00000000 nop
+10000328: 3c050000 lui a1,0x0
+1000032c: 00bc2821 addu a1,a1,gp
+10000330: 8ca5802c lw a1,-32724\(a1\)
+10000334: 3c050000 lui a1,0x0
+10000338: 00bc2821 addu a1,a1,gp
+1000033c: 8ca5802c lw a1,-32724\(a1\)
+10000340: 24a5000c addiu a1,a1,12
+10000344: 3c050000 lui a1,0x0
+10000348: 00bc2821 addu a1,a1,gp
+1000034c: 8ca5802c lw a1,-32724\(a1\)
+10000350: 3c010001 lui at,0x1
+10000354: 3421e240 ori at,at,0xe240
+10000358: 00a12821 addu a1,a1,at
+1000035c: 3c050000 lui a1,0x0
+10000360: 00bc2821 addu a1,a1,gp
+10000364: 8ca5802c lw a1,-32724\(a1\)
+10000368: 00b12821 addu a1,a1,s1
+1000036c: 3c050000 lui a1,0x0
+10000370: 00bc2821 addu a1,a1,gp
+10000374: 8ca5802c lw a1,-32724\(a1\)
+10000378: 24a5000c addiu a1,a1,12
+1000037c: 00b12821 addu a1,a1,s1
+10000380: 3c050000 lui a1,0x0
+10000384: 00bc2821 addu a1,a1,gp
+10000388: 8ca5802c lw a1,-32724\(a1\)
+1000038c: 3c010001 lui at,0x1
+10000390: 3421e240 ori at,at,0xe240
+10000394: 00a12821 addu a1,a1,at
+10000398: 00b12821 addu a1,a1,s1
+1000039c: 3c050000 lui a1,0x0
+100003a0: 00bc2821 addu a1,a1,gp
+100003a4: 8ca5802c lw a1,-32724\(a1\)
+100003a8: 8ca50000 lw a1,0\(a1\)
+100003ac: 3c050000 lui a1,0x0
+100003b0: 00bc2821 addu a1,a1,gp
+100003b4: 8ca5802c lw a1,-32724\(a1\)
+100003b8: 8ca5000c lw a1,12\(a1\)
+100003bc: 3c050000 lui a1,0x0
+100003c0: 00bc2821 addu a1,a1,gp
+100003c4: 8ca5802c lw a1,-32724\(a1\)
+100003c8: 00b12821 addu a1,a1,s1
+100003cc: 8ca50000 lw a1,0\(a1\)
+100003d0: 3c050000 lui a1,0x0
+100003d4: 00bc2821 addu a1,a1,gp
+100003d8: 8ca5802c lw a1,-32724\(a1\)
+100003dc: 00b12821 addu a1,a1,s1
+100003e0: 8ca5000c lw a1,12\(a1\)
+100003e4: 3c010000 lui at,0x0
+100003e8: 003c0821 addu at,at,gp
+100003ec: 8c21802c lw at,-32724\(at\)
+100003f0: 00250821 addu at,at,a1
+100003f4: 8c250022 lw a1,34\(at\)
+100003f8: 3c010000 lui at,0x0
+100003fc: 003c0821 addu at,at,gp
+10000400: 8c21802c lw at,-32724\(at\)
+10000404: 00250821 addu at,at,a1
+10000408: ac250038 sw a1,56\(at\)
+1000040c: 3c010000 lui at,0x0
+10000410: 003c0821 addu at,at,gp
+10000414: 8c21802c lw at,-32724\(at\)
+10000418: 88250000 lwl a1,0\(at\)
+1000041c: 98250003 lwr a1,3\(at\)
+10000420: 3c010000 lui at,0x0
+10000424: 003c0821 addu at,at,gp
+10000428: 8c21802c lw at,-32724\(at\)
+1000042c: 2421000c addiu at,at,12
+10000430: 88250000 lwl a1,0\(at\)
+10000434: 98250003 lwr a1,3\(at\)
+10000438: 3c010000 lui at,0x0
+1000043c: 003c0821 addu at,at,gp
+10000440: 8c21802c lw at,-32724\(at\)
+10000444: 00310821 addu at,at,s1
+10000448: 88250000 lwl a1,0\(at\)
+1000044c: 98250003 lwr a1,3\(at\)
+10000450: 3c010000 lui at,0x0
+10000454: 003c0821 addu at,at,gp
+10000458: 8c21802c lw at,-32724\(at\)
+1000045c: 2421000c addiu at,at,12
+10000460: 00310821 addu at,at,s1
+10000464: 88250000 lwl a1,0\(at\)
+10000468: 98250003 lwr a1,3\(at\)
+1000046c: 3c010000 lui at,0x0
+10000470: 003c0821 addu at,at,gp
+10000474: 8c21802c lw at,-32724\(at\)
+10000478: 24210022 addiu at,at,34
+1000047c: 00250821 addu at,at,a1
+10000480: 88250000 lwl a1,0\(at\)
+10000484: 98250003 lwr a1,3\(at\)
+10000488: 3c010000 lui at,0x0
+1000048c: 003c0821 addu at,at,gp
+10000490: 8c21802c lw at,-32724\(at\)
+10000494: 24210038 addiu at,at,56
+10000498: 00250821 addu at,at,a1
+1000049c: a8250000 swl a1,0\(at\)
+100004a0: b8250003 swr a1,3\(at\)
+100004a4: 8f85801c lw a1,-32740\(gp\)
+100004a8: 24a50730 addiu a1,a1,1840
+100004ac: 8f85801c lw a1,-32740\(gp\)
+100004b0: 24a5073c addiu a1,a1,1852
+100004b4: 8f858020 lw a1,-32736\(gp\)
+100004b8: 24a5e970 addiu a1,a1,-5776
+100004bc: 8f85801c lw a1,-32740\(gp\)
+100004c0: 24a50730 addiu a1,a1,1840
+100004c4: 00b12821 addu a1,a1,s1
+100004c8: 8f85801c lw a1,-32740\(gp\)
+100004cc: 24a5073c addiu a1,a1,1852
+100004d0: 00b12821 addu a1,a1,s1
+100004d4: 8f858020 lw a1,-32736\(gp\)
+100004d8: 24a5e970 addiu a1,a1,-5776
+100004dc: 00b12821 addu a1,a1,s1
+100004e0: 8f85801c lw a1,-32740\(gp\)
+100004e4: 8ca50730 lw a1,1840\(a1\)
+100004e8: 8f85801c lw a1,-32740\(gp\)
+100004ec: 8ca5073c lw a1,1852\(a1\)
+100004f0: 8f85801c lw a1,-32740\(gp\)
+100004f4: 00b12821 addu a1,a1,s1
+100004f8: 8ca50730 lw a1,1840\(a1\)
+100004fc: 8f85801c lw a1,-32740\(gp\)
+10000500: 00b12821 addu a1,a1,s1
+10000504: 8ca5073c lw a1,1852\(a1\)
+10000508: 8f81801c lw at,-32740\(gp\)
+1000050c: 00250821 addu at,at,a1
+10000510: 8c250752 lw a1,1874\(at\)
+10000514: 8f81801c lw at,-32740\(gp\)
+10000518: 00250821 addu at,at,a1
+1000051c: ac250768 sw a1,1896\(at\)
+10000520: 8f81801c lw at,-32740\(gp\)
+10000524: 24210730 addiu at,at,1840
+10000528: 88250000 lwl a1,0\(at\)
+1000052c: 98250003 lwr a1,3\(at\)
+10000530: 8f81801c lw at,-32740\(gp\)
+10000534: 2421073c addiu at,at,1852
+10000538: 88250000 lwl a1,0\(at\)
+1000053c: 98250003 lwr a1,3\(at\)
+10000540: 8f81801c lw at,-32740\(gp\)
+10000544: 24210730 addiu at,at,1840
+10000548: 00310821 addu at,at,s1
+1000054c: 88250000 lwl a1,0\(at\)
+10000550: 98250003 lwr a1,3\(at\)
+10000554: 8f81801c lw at,-32740\(gp\)
+10000558: 2421073c addiu at,at,1852
+1000055c: 00310821 addu at,at,s1
+10000560: 88250000 lwl a1,0\(at\)
+10000564: 98250003 lwr a1,3\(at\)
+10000568: 8f81801c lw at,-32740\(gp\)
+1000056c: 24210752 addiu at,at,1874
+10000570: 00250821 addu at,at,a1
+10000574: 88250000 lwl a1,0\(at\)
+10000578: 98250003 lwr a1,3\(at\)
+1000057c: 8f81801c lw at,-32740\(gp\)
+10000580: 24210768 addiu at,at,1896
+10000584: 00250821 addu at,at,a1
+10000588: a8250000 swl a1,0\(at\)
+1000058c: b8250003 swr a1,3\(at\)
+10000590: 3c050000 lui a1,0x0
+10000594: 00bc2821 addu a1,a1,gp
+10000598: 8ca58030 lw a1,-32720\(a1\)
+1000059c: 8f858028 lw a1,-32728\(gp\)
+100005a0: 24a50674 addiu a1,a1,1652
+100005a4: 3c190000 lui t9,0x0
+100005a8: 033cc821 addu t9,t9,gp
+100005ac: 8f398030 lw t9,-32720\(t9\)
+100005b0: 8f998028 lw t9,-32728\(gp\)
+100005b4: 27390674 addiu t9,t9,1652
+100005b8: 3c190000 lui t9,0x0
+100005bc: 033cc821 addu t9,t9,gp
+100005c0: 8f398030 lw t9,-32720\(t9\)
+100005c4: 0411002b bal 10000674 <fn2>
+100005c8: 00000000 nop
+100005cc: 8f998028 lw t9,-32728\(gp\)
+100005d0: 27390674 addiu t9,t9,1652
+100005d4: 04110027 bal 10000674 <fn2>
+100005d8: 00000000 nop
+100005dc: 3c050000 lui a1,0x0
+100005e0: 00bc2821 addu a1,a1,gp
+100005e4: 8ca58018 lw a1,-32744\(a1\)
+100005e8: 1000fea2 b 10000074 <fn>
+100005ec: 00000000 nop
+100005f0: 3c050000 lui a1,0x0
+100005f4: 00bc2821 addu a1,a1,gp
+100005f8: 8ca5802c lw a1,-32724\(a1\)
+100005fc: 8ca50000 lw a1,0\(a1\)
+10000600: 1000001c b 10000674 <fn2>
+10000604: 00000000 nop
+10000608: 8f85801c lw a1,-32740\(gp\)
+1000060c: 24a506b8 addiu a1,a1,1720
+10000610: 1000fe98 b 10000074 <fn>
+10000614: 00000000 nop
+10000618: 8f85801c lw a1,-32740\(gp\)
+1000061c: 24a5073c addiu a1,a1,1852
+10000620: 10000014 b 10000674 <fn2>
+10000624: 00000000 nop
+10000628: 8f858020 lw a1,-32736\(gp\)
+1000062c: 24a5e8f8 addiu a1,a1,-5896
+10000630: 1000fe90 b 10000074 <fn>
+10000634: 00000000 nop
+10000638: 8f85801c lw a1,-32740\(gp\)
+1000063c: 8ca50730 lw a1,1840\(a1\)
+10000640: 1000000c b 10000674 <fn2>
+10000644: 00000000 nop
+10000648: 8f85801c lw a1,-32740\(gp\)
+1000064c: 8ca506c4 lw a1,1732\(a1\)
+10000650: 1000fe88 b 10000074 <fn>
+10000654: 00000000 nop
+10000658: 8f81801c lw at,-32740\(gp\)
+1000065c: 00250821 addu at,at,a1
+10000660: 8c250752 lw a1,1874\(at\)
+10000664: 10000003 b 10000674 <fn2>
+10000668: 00000000 nop
+ \.\.\.
+
+10000674 <fn2>:
+ \.\.\.
+
+Disassembly of section \.data:
+
+1001067c <_fdata>:
+ \.\.\.
+
+100106b8 <dg1>:
+ \.\.\.
+
+100106f4 <sp2>:
+ \.\.\.
+
+10010730 <dg2>:
+ \.\.\.
+
+Disassembly of section \.got:
+
+10010770 <_GLOBAL_OFFSET_TABLE_>:
+10010770: 00000000 .*
+10010774: 80000000 .*
+10010778: 100106b8 .*
+1001077c: 10010000 .*
+10010780: 10030000 .*
+10010784: 10000074 .*
+10010788: 10000000 .*
+1001078c: 10010730 .*
+10010790: 10000674 .*
+10010794: 00000000 .*
+10010798: 00000000 .*
+#pass
#name: MIPS ELF xgot reloc n32
-#as: -EB -n32 -KPIC -xgot
+#as: -march=from-abi -EB -n32 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
-#ld: -melf32btsmipn32
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf32-n.*mips.*
10000098 <\.reginfo>:
10000098: 92020022 .*
\.\.\.
-100000ac: 10018790 .*
+100000ac: 100187a0 .*
Disassembly of section \.text:
10000224: a8250000 swl a1,0\(at\)
10000228: b8250003 swr a1,3\(at\)
1000022c: 8f85801c lw a1,-32740\(gp\)
-10000230: 24a506ec addiu a1,a1,1772
+10000230: 24a506fc addiu a1,a1,1788
10000234: 8f85801c lw a1,-32740\(gp\)
-10000238: 24a506f8 addiu a1,a1,1784
+10000238: 24a50708 addiu a1,a1,1800
1000023c: 8f858020 lw a1,-32736\(gp\)
-10000240: 24a5e92c addiu a1,a1,-5844
+10000240: 24a5e93c addiu a1,a1,-5828
10000244: 8f85801c lw a1,-32740\(gp\)
-10000248: 24a506ec addiu a1,a1,1772
+10000248: 24a506fc addiu a1,a1,1788
1000024c: 00b12821 addu a1,a1,s1
10000250: 8f85801c lw a1,-32740\(gp\)
-10000254: 24a506f8 addiu a1,a1,1784
+10000254: 24a50708 addiu a1,a1,1800
10000258: 00b12821 addu a1,a1,s1
1000025c: 8f858020 lw a1,-32736\(gp\)
-10000260: 24a5e92c addiu a1,a1,-5844
+10000260: 24a5e93c addiu a1,a1,-5828
10000264: 00b12821 addu a1,a1,s1
10000268: 8f85801c lw a1,-32740\(gp\)
-1000026c: 8ca506ec lw a1,1772\(a1\)
+1000026c: 8ca506fc lw a1,1788\(a1\)
10000270: 8f85801c lw a1,-32740\(gp\)
-10000274: 8ca506f8 lw a1,1784\(a1\)
+10000274: 8ca50708 lw a1,1800\(a1\)
10000278: 8f85801c lw a1,-32740\(gp\)
1000027c: 00b12821 addu a1,a1,s1
-10000280: 8ca506ec lw a1,1772\(a1\)
+10000280: 8ca506fc lw a1,1788\(a1\)
10000284: 8f85801c lw a1,-32740\(gp\)
10000288: 00b12821 addu a1,a1,s1
-1000028c: 8ca506f8 lw a1,1784\(a1\)
+1000028c: 8ca50708 lw a1,1800\(a1\)
10000290: 8f81801c lw at,-32740\(gp\)
10000294: 00250821 addu at,at,a1
-10000298: 8c25070e lw a1,1806\(at\)
+10000298: 8c25071e lw a1,1822\(at\)
1000029c: 8f81801c lw at,-32740\(gp\)
100002a0: 00250821 addu at,at,a1
-100002a4: ac250724 sw a1,1828\(at\)
+100002a4: ac250734 sw a1,1844\(at\)
100002a8: 8f81801c lw at,-32740\(gp\)
-100002ac: 242106ec addiu at,at,1772
+100002ac: 242106fc addiu at,at,1788
100002b0: 88250000 lwl a1,0\(at\)
100002b4: 98250003 lwr a1,3\(at\)
100002b8: 8f81801c lw at,-32740\(gp\)
-100002bc: 242106f8 addiu at,at,1784
+100002bc: 24210708 addiu at,at,1800
100002c0: 88250000 lwl a1,0\(at\)
100002c4: 98250003 lwr a1,3\(at\)
100002c8: 8f81801c lw at,-32740\(gp\)
-100002cc: 242106ec addiu at,at,1772
+100002cc: 242106fc addiu at,at,1788
100002d0: 00310821 addu at,at,s1
100002d4: 88250000 lwl a1,0\(at\)
100002d8: 98250003 lwr a1,3\(at\)
100002dc: 8f81801c lw at,-32740\(gp\)
-100002e0: 242106f8 addiu at,at,1784
+100002e0: 24210708 addiu at,at,1800
100002e4: 00310821 addu at,at,s1
100002e8: 88250000 lwl a1,0\(at\)
100002ec: 98250003 lwr a1,3\(at\)
100002f0: 8f81801c lw at,-32740\(gp\)
-100002f4: 2421070e addiu at,at,1806
+100002f4: 2421071e addiu at,at,1822
100002f8: 00250821 addu at,at,a1
100002fc: 88250000 lwl a1,0\(at\)
10000300: 98250003 lwr a1,3\(at\)
10000304: 8f81801c lw at,-32740\(gp\)
-10000308: 24210724 addiu at,at,1828
+10000308: 24210734 addiu at,at,1844
1000030c: 00250821 addu at,at,a1
10000310: a8250000 swl a1,0\(at\)
10000314: b8250003 swr a1,3\(at\)
100004d8: a8250000 swl a1,0\(at\)
100004dc: b8250003 swr a1,3\(at\)
100004e0: 8f85801c lw a1,-32740\(gp\)
-100004e4: 24a50764 addiu a1,a1,1892
+100004e4: 24a50774 addiu a1,a1,1908
100004e8: 8f85801c lw a1,-32740\(gp\)
-100004ec: 24a50770 addiu a1,a1,1904
+100004ec: 24a50780 addiu a1,a1,1920
100004f0: 8f858020 lw a1,-32736\(gp\)
-100004f4: 24a5e9a4 addiu a1,a1,-5724
+100004f4: 24a5e9b4 addiu a1,a1,-5708
100004f8: 8f85801c lw a1,-32740\(gp\)
-100004fc: 24a50764 addiu a1,a1,1892
+100004fc: 24a50774 addiu a1,a1,1908
10000500: 00b12821 addu a1,a1,s1
10000504: 8f85801c lw a1,-32740\(gp\)
-10000508: 24a50770 addiu a1,a1,1904
+10000508: 24a50780 addiu a1,a1,1920
1000050c: 00b12821 addu a1,a1,s1
10000510: 8f858020 lw a1,-32736\(gp\)
-10000514: 24a5e9a4 addiu a1,a1,-5724
+10000514: 24a5e9b4 addiu a1,a1,-5708
10000518: 00b12821 addu a1,a1,s1
1000051c: 8f85801c lw a1,-32740\(gp\)
-10000520: 8ca50764 lw a1,1892\(a1\)
+10000520: 8ca50774 lw a1,1908\(a1\)
10000524: 8f85801c lw a1,-32740\(gp\)
-10000528: 8ca50770 lw a1,1904\(a1\)
+10000528: 8ca50780 lw a1,1920\(a1\)
1000052c: 8f85801c lw a1,-32740\(gp\)
10000530: 00b12821 addu a1,a1,s1
-10000534: 8ca50764 lw a1,1892\(a1\)
+10000534: 8ca50774 lw a1,1908\(a1\)
10000538: 8f85801c lw a1,-32740\(gp\)
1000053c: 00b12821 addu a1,a1,s1
-10000540: 8ca50770 lw a1,1904\(a1\)
+10000540: 8ca50780 lw a1,1920\(a1\)
10000544: 8f81801c lw at,-32740\(gp\)
10000548: 00250821 addu at,at,a1
-1000054c: 8c250786 lw a1,1926\(at\)
+1000054c: 8c250796 lw a1,1942\(at\)
10000550: 8f81801c lw at,-32740\(gp\)
10000554: 00250821 addu at,at,a1
-10000558: ac25079c sw a1,1948\(at\)
+10000558: ac2507ac sw a1,1964\(at\)
1000055c: 8f81801c lw at,-32740\(gp\)
-10000560: 24210764 addiu at,at,1892
+10000560: 24210774 addiu at,at,1908
10000564: 88250000 lwl a1,0\(at\)
10000568: 98250003 lwr a1,3\(at\)
1000056c: 8f81801c lw at,-32740\(gp\)
-10000570: 24210770 addiu at,at,1904
+10000570: 24210780 addiu at,at,1920
10000574: 88250000 lwl a1,0\(at\)
10000578: 98250003 lwr a1,3\(at\)
1000057c: 8f81801c lw at,-32740\(gp\)
-10000580: 24210764 addiu at,at,1892
+10000580: 24210774 addiu at,at,1908
10000584: 00310821 addu at,at,s1
10000588: 88250000 lwl a1,0\(at\)
1000058c: 98250003 lwr a1,3\(at\)
10000590: 8f81801c lw at,-32740\(gp\)
-10000594: 24210770 addiu at,at,1904
+10000594: 24210780 addiu at,at,1920
10000598: 00310821 addu at,at,s1
1000059c: 88250000 lwl a1,0\(at\)
100005a0: 98250003 lwr a1,3\(at\)
100005a4: 8f81801c lw at,-32740\(gp\)
-100005a8: 24210786 addiu at,at,1926
+100005a8: 24210796 addiu at,at,1942
100005ac: 00250821 addu at,at,a1
100005b0: 88250000 lwl a1,0\(at\)
100005b4: 98250003 lwr a1,3\(at\)
100005b8: 8f81801c lw at,-32740\(gp\)
-100005bc: 2421079c addiu at,at,1948
+100005bc: 242107ac addiu at,at,1964
100005c0: 00250821 addu at,at,a1
100005c4: a8250000 swl a1,0\(at\)
100005c8: b8250003 swr a1,3\(at\)
1000063c: 1000001c b 100006b0 <fn2>
10000640: 00000000 nop
10000644: 8f85801c lw a1,-32740\(gp\)
-10000648: 24a506ec addiu a1,a1,1772
+10000648: 24a506fc addiu a1,a1,1788
1000064c: 1000fe98 b 100000b0 <fn>
10000650: 00000000 nop
10000654: 8f85801c lw a1,-32740\(gp\)
-10000658: 24a50770 addiu a1,a1,1904
+10000658: 24a50780 addiu a1,a1,1920
1000065c: 10000014 b 100006b0 <fn2>
10000660: 00000000 nop
10000664: 8f858020 lw a1,-32736\(gp\)
-10000668: 24a5e92c addiu a1,a1,-5844
+10000668: 24a5e93c addiu a1,a1,-5828
1000066c: 1000fe90 b 100000b0 <fn>
10000670: 00000000 nop
10000674: 8f85801c lw a1,-32740\(gp\)
-10000678: 8ca50764 lw a1,1892\(a1\)
+10000678: 8ca50774 lw a1,1908\(a1\)
1000067c: 1000000c b 100006b0 <fn2>
10000680: 00000000 nop
10000684: 8f85801c lw a1,-32740\(gp\)
-10000688: 8ca506f8 lw a1,1784\(a1\)
+10000688: 8ca50708 lw a1,1800\(a1\)
1000068c: 1000fe88 b 100000b0 <fn>
10000690: 00000000 nop
10000694: 8f81801c lw at,-32740\(gp\)
10000698: 00250821 addu at,at,a1
-1000069c: 8c250786 lw a1,1926\(at\)
+1000069c: 8c250796 lw a1,1942\(at\)
100006a0: 10000003 b 100006b0 <fn2>
100006a4: 00000000 nop
\.\.\.
+100006b0 <fn2>:
+ \.\.\.
+
Disassembly of section \.data:
-100106b0 <_fdata>:
+100106c0 <_fdata>:
\.\.\.
-100106ec <dg1>:
+100106fc <dg1>:
\.\.\.
-10010728 <sp2>:
+10010738 <sp2>:
\.\.\.
-10010764 <dg2>:
+10010774 <dg2>:
\.\.\.
Disassembly of section \.got:
-100107a0 <_GLOBAL_OFFSET_TABLE_>:
-100107a0: 00000000 .*
-100107a4: 80000000 .*
-100107a8: 100106ec .*
-100107ac: 10010000 .*
-100107b0: 10030000 .*
-100107b4: 100000b0 .*
-100107b8: 10000000 .*
-100107bc: 10010764 .*
-100107c0: 100006b0 .*
-100107c4: 00000000 .*
-100107c8: 00000000 .*
+100107b0 <_GLOBAL_OFFSET_TABLE_>:
+100107b0: 00000000 .*
+100107b4: 80000000 .*
+100107b8: 100106fc .*
+100107bc: 10010000 .*
+100107c0: 10030000 .*
+100107c4: 100000b0 .*
+100107c8: 10000000 .*
+100107cc: 10010774 .*
+100107d0: 100006b0 .*
+100107d4: 00000000 .*
+100107d8: 00000000 .*
#pass
--- /dev/null
+#name: MIPS ELF xgot reloc n64
+#as: -march=from-abi -EB -64 -KPIC -xgot
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld:
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000001200000b0 <\.MIPS\.options>:
+ 1200000b0: 01280000 .*
+ 1200000b4: 00000000 .*
+ 1200000b8: 92020022 .*
+ \.\.\.
+ 1200000d0: 00000001 .*
+ 1200000d4: 200187a0 .*
+
+Disassembly of section \.text:
+
+00000001200000b0 <fn>:
+ 1200000b0: 3c050000 lui a1,0x0
+ 1200000b4: 00bc282d daddu a1,a1,gp
+ 1200000b8: dca58020 ld a1,-32736\(a1\)
+ 1200000bc: 3c050000 lui a1,0x0
+ 1200000c0: 00bc282d daddu a1,a1,gp
+ 1200000c4: dca58020 ld a1,-32736\(a1\)
+ 1200000c8: 64a5000c daddiu a1,a1,12
+ 1200000cc: 3c050000 lui a1,0x0
+ 1200000d0: 00bc282d daddu a1,a1,gp
+ 1200000d4: dca58020 ld a1,-32736\(a1\)
+ 1200000d8: 3c010001 lui at,0x1
+ 1200000dc: 3421e240 ori at,at,0xe240
+ 1200000e0: 00a1282d daddu a1,a1,at
+ 1200000e4: 3c050000 lui a1,0x0
+ 1200000e8: 00bc282d daddu a1,a1,gp
+ 1200000ec: dca58020 ld a1,-32736\(a1\)
+ 1200000f0: 00b1282d daddu a1,a1,s1
+ 1200000f4: 3c050000 lui a1,0x0
+ 1200000f8: 00bc282d daddu a1,a1,gp
+ 1200000fc: dca58020 ld a1,-32736\(a1\)
+ 120000100: 64a5000c daddiu a1,a1,12
+ 120000104: 00b1282d daddu a1,a1,s1
+ 120000108: 3c050000 lui a1,0x0
+ 12000010c: 00bc282d daddu a1,a1,gp
+ 120000110: dca58020 ld a1,-32736\(a1\)
+ 120000114: 3c010001 lui at,0x1
+ 120000118: 3421e240 ori at,at,0xe240
+ 12000011c: 00a1282d daddu a1,a1,at
+ 120000120: 00b1282d daddu a1,a1,s1
+ 120000124: 3c050000 lui a1,0x0
+ 120000128: 00bc282d daddu a1,a1,gp
+ 12000012c: dca58020 ld a1,-32736\(a1\)
+ 120000130: dca50000 ld a1,0\(a1\)
+ 120000134: 3c050000 lui a1,0x0
+ 120000138: 00bc282d daddu a1,a1,gp
+ 12000013c: dca58020 ld a1,-32736\(a1\)
+ 120000140: dca5000c ld a1,12\(a1\)
+ 120000144: 3c050000 lui a1,0x0
+ 120000148: 00bc282d daddu a1,a1,gp
+ 12000014c: dca58020 ld a1,-32736\(a1\)
+ 120000150: 00b1282d daddu a1,a1,s1
+ 120000154: dca50000 ld a1,0\(a1\)
+ 120000158: 3c050000 lui a1,0x0
+ 12000015c: 00bc282d daddu a1,a1,gp
+ 120000160: dca58020 ld a1,-32736\(a1\)
+ 120000164: 00b1282d daddu a1,a1,s1
+ 120000168: dca5000c ld a1,12\(a1\)
+ 12000016c: 3c010000 lui at,0x0
+ 120000170: 003c082d daddu at,at,gp
+ 120000174: dc218020 ld at,-32736\(at\)
+ 120000178: 0025082d daddu at,at,a1
+ 12000017c: dc250022 ld a1,34\(at\)
+ 120000180: 3c010000 lui at,0x0
+ 120000184: 003c082d daddu at,at,gp
+ 120000188: dc218020 ld at,-32736\(at\)
+ 12000018c: 0025082d daddu at,at,a1
+ 120000190: fc250038 sd a1,56\(at\)
+ 120000194: 3c010000 lui at,0x0
+ 120000198: 003c082d daddu at,at,gp
+ 12000019c: dc218020 ld at,-32736\(at\)
+ 1200001a0: 88250000 lwl a1,0\(at\)
+ 1200001a4: 98250003 lwr a1,3\(at\)
+ 1200001a8: 3c010000 lui at,0x0
+ 1200001ac: 003c082d daddu at,at,gp
+ 1200001b0: dc218020 ld at,-32736\(at\)
+ 1200001b4: 6421000c daddiu at,at,12
+ 1200001b8: 88250000 lwl a1,0\(at\)
+ 1200001bc: 98250003 lwr a1,3\(at\)
+ 1200001c0: 3c010000 lui at,0x0
+ 1200001c4: 003c082d daddu at,at,gp
+ 1200001c8: dc218020 ld at,-32736\(at\)
+ 1200001cc: 0031082d daddu at,at,s1
+ 1200001d0: 88250000 lwl a1,0\(at\)
+ 1200001d4: 98250003 lwr a1,3\(at\)
+ 1200001d8: 3c010000 lui at,0x0
+ 1200001dc: 003c082d daddu at,at,gp
+ 1200001e0: dc218020 ld at,-32736\(at\)
+ 1200001e4: 6421000c daddiu at,at,12
+ 1200001e8: 0031082d daddu at,at,s1
+ 1200001ec: 88250000 lwl a1,0\(at\)
+ 1200001f0: 98250003 lwr a1,3\(at\)
+ 1200001f4: 3c010000 lui at,0x0
+ 1200001f8: 003c082d daddu at,at,gp
+ 1200001fc: dc218020 ld at,-32736\(at\)
+ 120000200: 64210022 daddiu at,at,34
+ 120000204: 0025082d daddu at,at,a1
+ 120000208: 88250000 lwl a1,0\(at\)
+ 12000020c: 98250003 lwr a1,3\(at\)
+ 120000210: 3c010000 lui at,0x0
+ 120000214: 003c082d daddu at,at,gp
+ 120000218: dc218020 ld at,-32736\(at\)
+ 12000021c: 64210038 daddiu at,at,56
+ 120000220: 0025082d daddu at,at,a1
+ 120000224: a8250000 swl a1,0\(at\)
+ 120000228: b8250003 swr a1,3\(at\)
+ 12000022c: df858028 ld a1,-32728\(gp\)
+ 120000230: 64a506f4 daddiu a1,a1,1780
+ 120000234: df858028 ld a1,-32728\(gp\)
+ 120000238: 64a50700 daddiu a1,a1,1792
+ 12000023c: df858030 ld a1,-32720\(gp\)
+ 120000240: 64a5e934 daddiu a1,a1,-5836
+ 120000244: df858028 ld a1,-32728\(gp\)
+ 120000248: 64a506f4 daddiu a1,a1,1780
+ 12000024c: 00b1282d daddu a1,a1,s1
+ 120000250: df858028 ld a1,-32728\(gp\)
+ 120000254: 64a50700 daddiu a1,a1,1792
+ 120000258: 00b1282d daddu a1,a1,s1
+ 12000025c: df858030 ld a1,-32720\(gp\)
+ 120000260: 64a5e934 daddiu a1,a1,-5836
+ 120000264: 00b1282d daddu a1,a1,s1
+ 120000268: df858028 ld a1,-32728\(gp\)
+ 12000026c: dca506f4 ld a1,1780\(a1\)
+ 120000270: df858028 ld a1,-32728\(gp\)
+ 120000274: dca50700 ld a1,1792\(a1\)
+ 120000278: df858028 ld a1,-32728\(gp\)
+ 12000027c: 00b1282d daddu a1,a1,s1
+ 120000280: dca506f4 ld a1,1780\(a1\)
+ 120000284: df858028 ld a1,-32728\(gp\)
+ 120000288: 00b1282d daddu a1,a1,s1
+ 12000028c: dca50700 ld a1,1792\(a1\)
+ 120000290: df818028 ld at,-32728\(gp\)
+ 120000294: 0025082d daddu at,at,a1
+ 120000298: dc250716 ld a1,1814\(at\)
+ 12000029c: df818028 ld at,-32728\(gp\)
+ 1200002a0: 0025082d daddu at,at,a1
+ 1200002a4: fc25072c sd a1,1836\(at\)
+ 1200002a8: df818028 ld at,-32728\(gp\)
+ 1200002ac: 642106f4 daddiu at,at,1780
+ 1200002b0: 88250000 lwl a1,0\(at\)
+ 1200002b4: 98250003 lwr a1,3\(at\)
+ 1200002b8: df818028 ld at,-32728\(gp\)
+ 1200002bc: 64210700 daddiu at,at,1792
+ 1200002c0: 88250000 lwl a1,0\(at\)
+ 1200002c4: 98250003 lwr a1,3\(at\)
+ 1200002c8: df818028 ld at,-32728\(gp\)
+ 1200002cc: 642106f4 daddiu at,at,1780
+ 1200002d0: 0031082d daddu at,at,s1
+ 1200002d4: 88250000 lwl a1,0\(at\)
+ 1200002d8: 98250003 lwr a1,3\(at\)
+ 1200002dc: df818028 ld at,-32728\(gp\)
+ 1200002e0: 64210700 daddiu at,at,1792
+ 1200002e4: 0031082d daddu at,at,s1
+ 1200002e8: 88250000 lwl a1,0\(at\)
+ 1200002ec: 98250003 lwr a1,3\(at\)
+ 1200002f0: df818028 ld at,-32728\(gp\)
+ 1200002f4: 64210716 daddiu at,at,1814
+ 1200002f8: 0025082d daddu at,at,a1
+ 1200002fc: 88250000 lwl a1,0\(at\)
+ 120000300: 98250003 lwr a1,3\(at\)
+ 120000304: df818028 ld at,-32728\(gp\)
+ 120000308: 6421072c daddiu at,at,1836
+ 12000030c: 0025082d daddu at,at,a1
+ 120000310: a8250000 swl a1,0\(at\)
+ 120000314: b8250003 swr a1,3\(at\)
+ 120000318: 3c050000 lui a1,0x0
+ 12000031c: 00bc282d daddu a1,a1,gp
+ 120000320: dca58038 ld a1,-32712\(a1\)
+ 120000324: df858040 ld a1,-32704\(gp\)
+ 120000328: 64a500b0 daddiu a1,a1,176
+ 12000032c: 3c190000 lui t9,0x0
+ 120000330: 033cc82d daddu t9,t9,gp
+ 120000334: df398038 ld t9,-32712\(t9\)
+ 120000338: df998040 ld t9,-32704\(gp\)
+ 12000033c: 673900b0 daddiu t9,t9,176
+ 120000340: 3c190000 lui t9,0x0
+ 120000344: 033cc82d daddu t9,t9,gp
+ 120000348: df398038 ld t9,-32712\(t9\)
+ 12000034c: 0411ff58 bal 1200000b0 <fn>
+ 120000350: 00000000 nop
+ 120000354: df998040 ld t9,-32704\(gp\)
+ 120000358: 673900b0 daddiu t9,t9,176
+ 12000035c: 0411ff54 bal 1200000b0 <fn>
+ 120000360: 00000000 nop
+ 120000364: 3c050000 lui a1,0x0
+ 120000368: 00bc282d daddu a1,a1,gp
+ 12000036c: dca58048 ld a1,-32696\(a1\)
+ 120000370: 3c050000 lui a1,0x0
+ 120000374: 00bc282d daddu a1,a1,gp
+ 120000378: dca58048 ld a1,-32696\(a1\)
+ 12000037c: 64a5000c daddiu a1,a1,12
+ 120000380: 3c050000 lui a1,0x0
+ 120000384: 00bc282d daddu a1,a1,gp
+ 120000388: dca58048 ld a1,-32696\(a1\)
+ 12000038c: 3c010001 lui at,0x1
+ 120000390: 3421e240 ori at,at,0xe240
+ 120000394: 00a1282d daddu a1,a1,at
+ 120000398: 3c050000 lui a1,0x0
+ 12000039c: 00bc282d daddu a1,a1,gp
+ 1200003a0: dca58048 ld a1,-32696\(a1\)
+ 1200003a4: 00b1282d daddu a1,a1,s1
+ 1200003a8: 3c050000 lui a1,0x0
+ 1200003ac: 00bc282d daddu a1,a1,gp
+ 1200003b0: dca58048 ld a1,-32696\(a1\)
+ 1200003b4: 64a5000c daddiu a1,a1,12
+ 1200003b8: 00b1282d daddu a1,a1,s1
+ 1200003bc: 3c050000 lui a1,0x0
+ 1200003c0: 00bc282d daddu a1,a1,gp
+ 1200003c4: dca58048 ld a1,-32696\(a1\)
+ 1200003c8: 3c010001 lui at,0x1
+ 1200003cc: 3421e240 ori at,at,0xe240
+ 1200003d0: 00a1282d daddu a1,a1,at
+ 1200003d4: 00b1282d daddu a1,a1,s1
+ 1200003d8: 3c050000 lui a1,0x0
+ 1200003dc: 00bc282d daddu a1,a1,gp
+ 1200003e0: dca58048 ld a1,-32696\(a1\)
+ 1200003e4: dca50000 ld a1,0\(a1\)
+ 1200003e8: 3c050000 lui a1,0x0
+ 1200003ec: 00bc282d daddu a1,a1,gp
+ 1200003f0: dca58048 ld a1,-32696\(a1\)
+ 1200003f4: dca5000c ld a1,12\(a1\)
+ 1200003f8: 3c050000 lui a1,0x0
+ 1200003fc: 00bc282d daddu a1,a1,gp
+ 120000400: dca58048 ld a1,-32696\(a1\)
+ 120000404: 00b1282d daddu a1,a1,s1
+ 120000408: dca50000 ld a1,0\(a1\)
+ 12000040c: 3c050000 lui a1,0x0
+ 120000410: 00bc282d daddu a1,a1,gp
+ 120000414: dca58048 ld a1,-32696\(a1\)
+ 120000418: 00b1282d daddu a1,a1,s1
+ 12000041c: dca5000c ld a1,12\(a1\)
+ 120000420: 3c010000 lui at,0x0
+ 120000424: 003c082d daddu at,at,gp
+ 120000428: dc218048 ld at,-32696\(at\)
+ 12000042c: 0025082d daddu at,at,a1
+ 120000430: dc250022 ld a1,34\(at\)
+ 120000434: 3c010000 lui at,0x0
+ 120000438: 003c082d daddu at,at,gp
+ 12000043c: dc218048 ld at,-32696\(at\)
+ 120000440: 0025082d daddu at,at,a1
+ 120000444: fc250038 sd a1,56\(at\)
+ 120000448: 3c010000 lui at,0x0
+ 12000044c: 003c082d daddu at,at,gp
+ 120000450: dc218048 ld at,-32696\(at\)
+ 120000454: 88250000 lwl a1,0\(at\)
+ 120000458: 98250003 lwr a1,3\(at\)
+ 12000045c: 3c010000 lui at,0x0
+ 120000460: 003c082d daddu at,at,gp
+ 120000464: dc218048 ld at,-32696\(at\)
+ 120000468: 6421000c daddiu at,at,12
+ 12000046c: 88250000 lwl a1,0\(at\)
+ 120000470: 98250003 lwr a1,3\(at\)
+ 120000474: 3c010000 lui at,0x0
+ 120000478: 003c082d daddu at,at,gp
+ 12000047c: dc218048 ld at,-32696\(at\)
+ 120000480: 0031082d daddu at,at,s1
+ 120000484: 88250000 lwl a1,0\(at\)
+ 120000488: 98250003 lwr a1,3\(at\)
+ 12000048c: 3c010000 lui at,0x0
+ 120000490: 003c082d daddu at,at,gp
+ 120000494: dc218048 ld at,-32696\(at\)
+ 120000498: 6421000c daddiu at,at,12
+ 12000049c: 0031082d daddu at,at,s1
+ 1200004a0: 88250000 lwl a1,0\(at\)
+ 1200004a4: 98250003 lwr a1,3\(at\)
+ 1200004a8: 3c010000 lui at,0x0
+ 1200004ac: 003c082d daddu at,at,gp
+ 1200004b0: dc218048 ld at,-32696\(at\)
+ 1200004b4: 64210022 daddiu at,at,34
+ 1200004b8: 0025082d daddu at,at,a1
+ 1200004bc: 88250000 lwl a1,0\(at\)
+ 1200004c0: 98250003 lwr a1,3\(at\)
+ 1200004c4: 3c010000 lui at,0x0
+ 1200004c8: 003c082d daddu at,at,gp
+ 1200004cc: dc218048 ld at,-32696\(at\)
+ 1200004d0: 64210038 daddiu at,at,56
+ 1200004d4: 0025082d daddu at,at,a1
+ 1200004d8: a8250000 swl a1,0\(at\)
+ 1200004dc: b8250003 swr a1,3\(at\)
+ 1200004e0: df858028 ld a1,-32728\(gp\)
+ 1200004e4: 64a5076c daddiu a1,a1,1900
+ 1200004e8: df858028 ld a1,-32728\(gp\)
+ 1200004ec: 64a50778 daddiu a1,a1,1912
+ 1200004f0: df858030 ld a1,-32720\(gp\)
+ 1200004f4: 64a5e9ac daddiu a1,a1,-5716
+ 1200004f8: df858028 ld a1,-32728\(gp\)
+ 1200004fc: 64a5076c daddiu a1,a1,1900
+ 120000500: 00b1282d daddu a1,a1,s1
+ 120000504: df858028 ld a1,-32728\(gp\)
+ 120000508: 64a50778 daddiu a1,a1,1912
+ 12000050c: 00b1282d daddu a1,a1,s1
+ 120000510: df858030 ld a1,-32720\(gp\)
+ 120000514: 64a5e9ac daddiu a1,a1,-5716
+ 120000518: 00b1282d daddu a1,a1,s1
+ 12000051c: df858028 ld a1,-32728\(gp\)
+ 120000520: dca5076c ld a1,1900\(a1\)
+ 120000524: df858028 ld a1,-32728\(gp\)
+ 120000528: dca50778 ld a1,1912\(a1\)
+ 12000052c: df858028 ld a1,-32728\(gp\)
+ 120000530: 00b1282d daddu a1,a1,s1
+ 120000534: dca5076c ld a1,1900\(a1\)
+ 120000538: df858028 ld a1,-32728\(gp\)
+ 12000053c: 00b1282d daddu a1,a1,s1
+ 120000540: dca50778 ld a1,1912\(a1\)
+ 120000544: df818028 ld at,-32728\(gp\)
+ 120000548: 0025082d daddu at,at,a1
+ 12000054c: dc25078e ld a1,1934\(at\)
+ 120000550: df818028 ld at,-32728\(gp\)
+ 120000554: 0025082d daddu at,at,a1
+ 120000558: fc2507a4 sd a1,1956\(at\)
+ 12000055c: df818028 ld at,-32728\(gp\)
+ 120000560: 6421076c daddiu at,at,1900
+ 120000564: 88250000 lwl a1,0\(at\)
+ 120000568: 98250003 lwr a1,3\(at\)
+ 12000056c: df818028 ld at,-32728\(gp\)
+ 120000570: 64210778 daddiu at,at,1912
+ 120000574: 88250000 lwl a1,0\(at\)
+ 120000578: 98250003 lwr a1,3\(at\)
+ 12000057c: df818028 ld at,-32728\(gp\)
+ 120000580: 6421076c daddiu at,at,1900
+ 120000584: 0031082d daddu at,at,s1
+ 120000588: 88250000 lwl a1,0\(at\)
+ 12000058c: 98250003 lwr a1,3\(at\)
+ 120000590: df818028 ld at,-32728\(gp\)
+ 120000594: 64210778 daddiu at,at,1912
+ 120000598: 0031082d daddu at,at,s1
+ 12000059c: 88250000 lwl a1,0\(at\)
+ 1200005a0: 98250003 lwr a1,3\(at\)
+ 1200005a4: df818028 ld at,-32728\(gp\)
+ 1200005a8: 6421078e daddiu at,at,1934
+ 1200005ac: 0025082d daddu at,at,a1
+ 1200005b0: 88250000 lwl a1,0\(at\)
+ 1200005b4: 98250003 lwr a1,3\(at\)
+ 1200005b8: df818028 ld at,-32728\(gp\)
+ 1200005bc: 642107a4 daddiu at,at,1956
+ 1200005c0: 0025082d daddu at,at,a1
+ 1200005c4: a8250000 swl a1,0\(at\)
+ 1200005c8: b8250003 swr a1,3\(at\)
+ 1200005cc: 3c050000 lui a1,0x0
+ 1200005d0: 00bc282d daddu a1,a1,gp
+ 1200005d4: dca58050 ld a1,-32688\(a1\)
+ 1200005d8: df858040 ld a1,-32704\(gp\)
+ 1200005dc: 64a506b0 daddiu a1,a1,1712
+ 1200005e0: 3c190000 lui t9,0x0
+ 1200005e4: 033cc82d daddu t9,t9,gp
+ 1200005e8: df398050 ld t9,-32688\(t9\)
+ 1200005ec: df998040 ld t9,-32704\(gp\)
+ 1200005f0: 673906b0 daddiu t9,t9,1712
+ 1200005f4: 3c190000 lui t9,0x0
+ 1200005f8: 033cc82d daddu t9,t9,gp
+ 1200005fc: df398050 ld t9,-32688\(t9\)
+ 120000600: 0411002b bal 1200006b0 <fn2>
+ 120000604: 00000000 nop
+ 120000608: df998040 ld t9,-32704\(gp\)
+ 12000060c: 673906b0 daddiu t9,t9,1712
+ 120000610: 04110027 bal 1200006b0 <fn2>
+ 120000614: 00000000 nop
+ 120000618: 3c050000 lui a1,0x0
+ 12000061c: 00bc282d daddu a1,a1,gp
+ 120000620: dca58020 ld a1,-32736\(a1\)
+ 120000624: 1000fea2 b 1200000b0 <fn>
+ 120000628: 00000000 nop
+ 12000062c: 3c050000 lui a1,0x0
+ 120000630: 00bc282d daddu a1,a1,gp
+ 120000634: dca58048 ld a1,-32696\(a1\)
+ 120000638: dca50000 ld a1,0\(a1\)
+ 12000063c: 1000001c b 1200006b0 <fn2>
+ 120000640: 00000000 nop
+ 120000644: df858028 ld a1,-32728\(gp\)
+ 120000648: 64a506f4 daddiu a1,a1,1780
+ 12000064c: 1000fe98 b 1200000b0 <fn>
+ 120000650: 00000000 nop
+ 120000654: df858028 ld a1,-32728\(gp\)
+ 120000658: 64a50778 daddiu a1,a1,1912
+ 12000065c: 10000014 b 1200006b0 <fn2>
+ 120000660: 00000000 nop
+ 120000664: df858030 ld a1,-32720\(gp\)
+ 120000668: 64a5e934 daddiu a1,a1,-5836
+ 12000066c: 1000fe90 b 1200000b0 <fn>
+ 120000670: 00000000 nop
+ 120000674: df858028 ld a1,-32728\(gp\)
+ 120000678: dca5076c ld a1,1900\(a1\)
+ 12000067c: 1000000c b 1200006b0 <fn2>
+ 120000680: 00000000 nop
+ 120000684: df858028 ld a1,-32728\(gp\)
+ 120000688: dca50700 ld a1,1792\(a1\)
+ 12000068c: 1000fe88 b 1200000b0 <fn>
+ 120000690: 00000000 nop
+ 120000694: df818028 ld at,-32728\(gp\)
+ 120000698: 0025082d daddu at,at,a1
+ 12000069c: dc25078e ld a1,1934\(at\)
+ 1200006a0: 10000003 b 1200006b0 <fn2>
+ 1200006a4: 00000000 nop
+ \.\.\.
+
+00000001200006b0 <fn2>:
+ \.\.\.
+
+Disassembly of section \.data:
+
+00000001200106b8 <_fdata>:
+ \.\.\.
+
+00000001200106f4 <dg1>:
+ \.\.\.
+
+0000000120010730 <sp2>:
+ \.\.\.
+
+000000012001076c <dg2>:
+ \.\.\.
+
+Disassembly of section \.got:
+
+00000001200107b0 <_GLOBAL_OFFSET_TABLE_>:
+ \.\.\.
+ 1200107b8: 80000000 .*
+ 1200107bc: 00000000 .*
+ 1200107c0: 00000001 .*
+ 1200107c4: 200106f4 .*
+ 1200107c8: 00000001 .*
+ 1200107cc: 20010000 .*
+ 1200107d0: 00000001 .*
+ 1200107d4: 20030000 .*
+ 1200107d8: 00000001 .*
+ 1200107dc: 200000b0 .*
+ 1200107e0: 00000001 .*
+ 1200107e4: 20000000 .*
+ 1200107e8: 00000001 .*
+ 1200107ec: 2001076c .*
+ 1200107f0: 00000001 .*
+ 1200107f4: 200006b0 .*
+ \.\.\.
+#pass
#name: MIPS ELF xgot reloc n64
-#as: -EB -64 -KPIC -xgot
+#as: -march=from-abi -EB -64 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
1200000b8: 92020022 .*
\.\.\.
1200000d0: 00000001 .*
- 1200000d4: 200187c0 .*
+ 1200000d4: 200187d0 .*
Disassembly of section \.text:
120000254: a8250000 swl a1,0\(at\)
120000258: b8250003 swr a1,3\(at\)
12000025c: df858028 ld a1,-32728\(gp\)
- 120000260: 64a5071c daddiu a1,a1,1820
+ 120000260: 64a5072c daddiu a1,a1,1836
120000264: df858028 ld a1,-32728\(gp\)
- 120000268: 64a50728 daddiu a1,a1,1832
+ 120000268: 64a50738 daddiu a1,a1,1848
12000026c: df858030 ld a1,-32720\(gp\)
- 120000270: 64a5e95c daddiu a1,a1,-5796
+ 120000270: 64a5e96c daddiu a1,a1,-5780
120000274: df858028 ld a1,-32728\(gp\)
- 120000278: 64a5071c daddiu a1,a1,1820
+ 120000278: 64a5072c daddiu a1,a1,1836
12000027c: 00b1282d daddu a1,a1,s1
120000280: df858028 ld a1,-32728\(gp\)
- 120000284: 64a50728 daddiu a1,a1,1832
+ 120000284: 64a50738 daddiu a1,a1,1848
120000288: 00b1282d daddu a1,a1,s1
12000028c: df858030 ld a1,-32720\(gp\)
- 120000290: 64a5e95c daddiu a1,a1,-5796
+ 120000290: 64a5e96c daddiu a1,a1,-5780
120000294: 00b1282d daddu a1,a1,s1
120000298: df858028 ld a1,-32728\(gp\)
- 12000029c: dca5071c ld a1,1820\(a1\)
+ 12000029c: dca5072c ld a1,1836\(a1\)
1200002a0: df858028 ld a1,-32728\(gp\)
- 1200002a4: dca50728 ld a1,1832\(a1\)
+ 1200002a4: dca50738 ld a1,1848\(a1\)
1200002a8: df858028 ld a1,-32728\(gp\)
1200002ac: 00b1282d daddu a1,a1,s1
- 1200002b0: dca5071c ld a1,1820\(a1\)
+ 1200002b0: dca5072c ld a1,1836\(a1\)
1200002b4: df858028 ld a1,-32728\(gp\)
1200002b8: 00b1282d daddu a1,a1,s1
- 1200002bc: dca50728 ld a1,1832\(a1\)
+ 1200002bc: dca50738 ld a1,1848\(a1\)
1200002c0: df818028 ld at,-32728\(gp\)
1200002c4: 0025082d daddu at,at,a1
- 1200002c8: dc25073e ld a1,1854\(at\)
+ 1200002c8: dc25074e ld a1,1870\(at\)
1200002cc: df818028 ld at,-32728\(gp\)
1200002d0: 0025082d daddu at,at,a1
- 1200002d4: fc250754 sd a1,1876\(at\)
+ 1200002d4: fc250764 sd a1,1892\(at\)
1200002d8: df818028 ld at,-32728\(gp\)
- 1200002dc: 6421071c daddiu at,at,1820
+ 1200002dc: 6421072c daddiu at,at,1836
1200002e0: 88250000 lwl a1,0\(at\)
1200002e4: 98250003 lwr a1,3\(at\)
1200002e8: df818028 ld at,-32728\(gp\)
- 1200002ec: 64210728 daddiu at,at,1832
+ 1200002ec: 64210738 daddiu at,at,1848
1200002f0: 88250000 lwl a1,0\(at\)
1200002f4: 98250003 lwr a1,3\(at\)
1200002f8: df818028 ld at,-32728\(gp\)
- 1200002fc: 6421071c daddiu at,at,1820
+ 1200002fc: 6421072c daddiu at,at,1836
120000300: 0031082d daddu at,at,s1
120000304: 88250000 lwl a1,0\(at\)
120000308: 98250003 lwr a1,3\(at\)
12000030c: df818028 ld at,-32728\(gp\)
- 120000310: 64210728 daddiu at,at,1832
+ 120000310: 64210738 daddiu at,at,1848
120000314: 0031082d daddu at,at,s1
120000318: 88250000 lwl a1,0\(at\)
12000031c: 98250003 lwr a1,3\(at\)
120000320: df818028 ld at,-32728\(gp\)
- 120000324: 6421073e daddiu at,at,1854
+ 120000324: 6421074e daddiu at,at,1870
120000328: 0025082d daddu at,at,a1
12000032c: 88250000 lwl a1,0\(at\)
120000330: 98250003 lwr a1,3\(at\)
120000334: df818028 ld at,-32728\(gp\)
- 120000338: 64210754 daddiu at,at,1876
+ 120000338: 64210764 daddiu at,at,1892
12000033c: 0025082d daddu at,at,a1
120000340: a8250000 swl a1,0\(at\)
120000344: b8250003 swr a1,3\(at\)
120000508: a8250000 swl a1,0\(at\)
12000050c: b8250003 swr a1,3\(at\)
120000510: df858028 ld a1,-32728\(gp\)
- 120000514: 64a50794 daddiu a1,a1,1940
+ 120000514: 64a507a4 daddiu a1,a1,1956
120000518: df858028 ld a1,-32728\(gp\)
- 12000051c: 64a507a0 daddiu a1,a1,1952
+ 12000051c: 64a507b0 daddiu a1,a1,1968
120000520: df858030 ld a1,-32720\(gp\)
- 120000524: 64a5e9d4 daddiu a1,a1,-5676
+ 120000524: 64a5e9e4 daddiu a1,a1,-5660
120000528: df858028 ld a1,-32728\(gp\)
- 12000052c: 64a50794 daddiu a1,a1,1940
+ 12000052c: 64a507a4 daddiu a1,a1,1956
120000530: 00b1282d daddu a1,a1,s1
120000534: df858028 ld a1,-32728\(gp\)
- 120000538: 64a507a0 daddiu a1,a1,1952
+ 120000538: 64a507b0 daddiu a1,a1,1968
12000053c: 00b1282d daddu a1,a1,s1
120000540: df858030 ld a1,-32720\(gp\)
- 120000544: 64a5e9d4 daddiu a1,a1,-5676
+ 120000544: 64a5e9e4 daddiu a1,a1,-5660
120000548: 00b1282d daddu a1,a1,s1
12000054c: df858028 ld a1,-32728\(gp\)
- 120000550: dca50794 ld a1,1940\(a1\)
+ 120000550: dca507a4 ld a1,1956\(a1\)
120000554: df858028 ld a1,-32728\(gp\)
- 120000558: dca507a0 ld a1,1952\(a1\)
+ 120000558: dca507b0 ld a1,1968\(a1\)
12000055c: df858028 ld a1,-32728\(gp\)
120000560: 00b1282d daddu a1,a1,s1
- 120000564: dca50794 ld a1,1940\(a1\)
+ 120000564: dca507a4 ld a1,1956\(a1\)
120000568: df858028 ld a1,-32728\(gp\)
12000056c: 00b1282d daddu a1,a1,s1
- 120000570: dca507a0 ld a1,1952\(a1\)
+ 120000570: dca507b0 ld a1,1968\(a1\)
120000574: df818028 ld at,-32728\(gp\)
120000578: 0025082d daddu at,at,a1
- 12000057c: dc2507b6 ld a1,1974\(at\)
+ 12000057c: dc2507c6 ld a1,1990\(at\)
120000580: df818028 ld at,-32728\(gp\)
120000584: 0025082d daddu at,at,a1
- 120000588: fc2507cc sd a1,1996\(at\)
+ 120000588: fc2507dc sd a1,2012\(at\)
12000058c: df818028 ld at,-32728\(gp\)
- 120000590: 64210794 daddiu at,at,1940
+ 120000590: 642107a4 daddiu at,at,1956
120000594: 88250000 lwl a1,0\(at\)
120000598: 98250003 lwr a1,3\(at\)
12000059c: df818028 ld at,-32728\(gp\)
- 1200005a0: 642107a0 daddiu at,at,1952
+ 1200005a0: 642107b0 daddiu at,at,1968
1200005a4: 88250000 lwl a1,0\(at\)
1200005a8: 98250003 lwr a1,3\(at\)
1200005ac: df818028 ld at,-32728\(gp\)
- 1200005b0: 64210794 daddiu at,at,1940
+ 1200005b0: 642107a4 daddiu at,at,1956
1200005b4: 0031082d daddu at,at,s1
1200005b8: 88250000 lwl a1,0\(at\)
1200005bc: 98250003 lwr a1,3\(at\)
1200005c0: df818028 ld at,-32728\(gp\)
- 1200005c4: 642107a0 daddiu at,at,1952
+ 1200005c4: 642107b0 daddiu at,at,1968
1200005c8: 0031082d daddu at,at,s1
1200005cc: 88250000 lwl a1,0\(at\)
1200005d0: 98250003 lwr a1,3\(at\)
1200005d4: df818028 ld at,-32728\(gp\)
- 1200005d8: 642107b6 daddiu at,at,1974
+ 1200005d8: 642107c6 daddiu at,at,1990
1200005dc: 0025082d daddu at,at,a1
1200005e0: 88250000 lwl a1,0\(at\)
1200005e4: 98250003 lwr a1,3\(at\)
1200005e8: df818028 ld at,-32728\(gp\)
- 1200005ec: 642107cc daddiu at,at,1996
+ 1200005ec: 642107dc daddiu at,at,2012
1200005f0: 0025082d daddu at,at,a1
1200005f4: a8250000 swl a1,0\(at\)
1200005f8: b8250003 swr a1,3\(at\)
12000066c: 1000001c b 1200006e0 <fn2>
120000670: 00000000 nop
120000674: df858028 ld a1,-32728\(gp\)
- 120000678: 64a5071c daddiu a1,a1,1820
+ 120000678: 64a5072c daddiu a1,a1,1836
12000067c: 1000fe98 b 1200000e0 <fn>
120000680: 00000000 nop
120000684: df858028 ld a1,-32728\(gp\)
- 120000688: 64a507a0 daddiu a1,a1,1952
+ 120000688: 64a507b0 daddiu a1,a1,1968
12000068c: 10000014 b 1200006e0 <fn2>
120000690: 00000000 nop
120000694: df858030 ld a1,-32720\(gp\)
- 120000698: 64a5e95c daddiu a1,a1,-5796
+ 120000698: 64a5e96c daddiu a1,a1,-5780
12000069c: 1000fe90 b 1200000e0 <fn>
1200006a0: 00000000 nop
1200006a4: df858028 ld a1,-32728\(gp\)
- 1200006a8: dca50794 ld a1,1940\(a1\)
+ 1200006a8: dca507a4 ld a1,1956\(a1\)
1200006ac: 1000000c b 1200006e0 <fn2>
1200006b0: 00000000 nop
1200006b4: df858028 ld a1,-32728\(gp\)
- 1200006b8: dca50728 ld a1,1832\(a1\)
+ 1200006b8: dca50738 ld a1,1848\(a1\)
1200006bc: 1000fe88 b 1200000e0 <fn>
1200006c0: 00000000 nop
1200006c4: df818028 ld at,-32728\(gp\)
1200006c8: 0025082d daddu at,at,a1
- 1200006cc: dc2507b6 ld a1,1974\(at\)
+ 1200006cc: dc2507c6 ld a1,1990\(at\)
1200006d0: 10000003 b 1200006e0 <fn2>
1200006d4: 00000000 nop
\.\.\.
+00000001200006e0 <fn2>:
+ \.\.\.
+
Disassembly of section \.data:
-00000001200106e0 <_fdata>:
+00000001200106f0 <_fdata>:
\.\.\.
-000000012001071c <dg1>:
+000000012001072c <dg1>:
\.\.\.
-0000000120010758 <sp2>:
+0000000120010768 <sp2>:
\.\.\.
-0000000120010794 <dg2>:
+00000001200107a4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000001200107d0 <_GLOBAL_OFFSET_TABLE_>:
+00000001200107e0 <_GLOBAL_OFFSET_TABLE_>:
\.\.\.
- 1200107d8: 80000000 .*
- 1200107dc: 00000000 .*
- 1200107e0: 00000001 .*
- 1200107e4: 2001071c .*
- 1200107e8: 00000001 .*
- 1200107ec: 20010000 .*
+ 1200107e8: 80000000 .*
+ 1200107ec: 00000000 .*
1200107f0: 00000001 .*
- 1200107f4: 20030000 .*
+ 1200107f4: 2001072c .*
1200107f8: 00000001 .*
- 1200107fc: 200000e0 .*
+ 1200107fc: 20010000 .*
120010800: 00000001 .*
- 120010804: 20000000 .*
+ 120010804: 20030000 .*
120010808: 00000001 .*
- 12001080c: 20010794 .*
+ 12001080c: 200000e0 .*
120010810: 00000001 .*
- 120010814: 200006e0 .*
+ 120010814: 20000000 .*
+ 120010818: 00000001 .*
+ 12001081c: 200107a4 .*
+ 120010820: 00000001 .*
+ 120010824: 200006e0 .*
\.\.\.
#pass
#name: MIPS ELF xgot reloc n64
-#as: -EB -64 -KPIC -xgot
+#as: -march=from-abi -EB -64 -KPIC -xgot
#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
-#ld: -melf64btsmip
+#ld:
#objdump: -D --show-raw-insn
.*: +file format elf64-.*mips.*
Disassembly of section \.MIPS\.options:
-00000000100000b0 <\.MIPS\.options>:
- 100000b0: 01280000 .*
- 100000b4: 00000000 .*
- 100000b8: 92020022 .*
+00000000100000e8 <\.MIPS\.options>:
+ 100000e8: 01280000 .*
+ 100000ec: 00000000 .*
+ 100000f0: 92020022 .*
\.\.\.
- 100000d4: 101087c0 .*
+ 1000010c: 10018800 .*
Disassembly of section \.text:
-00000000100000e0 <fn>:
- 100000e0: 3c050000 lui a1,0x0
- 100000e4: 00bc282d daddu a1,a1,gp
- 100000e8: dca58058 ld a1,-32680\(a1\)
- 100000ec: 3c050000 lui a1,0x0
- 100000f0: 00bc282d daddu a1,a1,gp
- 100000f4: dca58058 ld a1,-32680\(a1\)
- 100000f8: 64a5000c daddiu a1,a1,12
- 100000fc: 3c050000 lui a1,0x0
- 10000100: 00bc282d daddu a1,a1,gp
- 10000104: dca58058 ld a1,-32680\(a1\)
- 10000108: 3c010002 lui at,0x2
- 1000010c: 6421e240 daddiu at,at,-7616
- 10000110: 00a1282d daddu a1,a1,at
- 10000114: 3c050000 lui a1,0x0
- 10000118: 00bc282d daddu a1,a1,gp
- 1000011c: dca58058 ld a1,-32680\(a1\)
- 10000120: 00b1282d daddu a1,a1,s1
- 10000124: 3c050000 lui a1,0x0
- 10000128: 00bc282d daddu a1,a1,gp
- 1000012c: dca58058 ld a1,-32680\(a1\)
- 10000130: 64a5000c daddiu a1,a1,12
- 10000134: 00b1282d daddu a1,a1,s1
- 10000138: 3c050000 lui a1,0x0
- 1000013c: 00bc282d daddu a1,a1,gp
- 10000140: dca58058 ld a1,-32680\(a1\)
- 10000144: 3c010002 lui at,0x2
- 10000148: 6421e240 daddiu at,at,-7616
- 1000014c: 00a1282d daddu a1,a1,at
+0000000010000110 <fn>:
+ 10000110: 3c050000 lui a1,0x0
+ 10000114: 00bc282d daddu a1,a1,gp
+ 10000118: dca58020 ld a1,-32736\(a1\)
+ 1000011c: 3c050000 lui a1,0x0
+ 10000120: 00bc282d daddu a1,a1,gp
+ 10000124: dca58020 ld a1,-32736\(a1\)
+ 10000128: 64a5000c daddiu a1,a1,12
+ 1000012c: 3c050000 lui a1,0x0
+ 10000130: 00bc282d daddu a1,a1,gp
+ 10000134: dca58020 ld a1,-32736\(a1\)
+ 10000138: 3c010001 lui at,0x1
+ 1000013c: 3421e240 ori at,at,0xe240
+ 10000140: 00a1282d daddu a1,a1,at
+ 10000144: 3c050000 lui a1,0x0
+ 10000148: 00bc282d daddu a1,a1,gp
+ 1000014c: dca58020 ld a1,-32736\(a1\)
10000150: 00b1282d daddu a1,a1,s1
10000154: 3c050000 lui a1,0x0
10000158: 00bc282d daddu a1,a1,gp
- 1000015c: dca58058 ld a1,-32680\(a1\)
- 10000160: dca50000 ld a1,0\(a1\)
- 10000164: 3c050000 lui a1,0x0
- 10000168: 00bc282d daddu a1,a1,gp
- 1000016c: dca58058 ld a1,-32680\(a1\)
- 10000170: dca5000c ld a1,12\(a1\)
- 10000174: 3c050000 lui a1,0x0
- 10000178: 00bc282d daddu a1,a1,gp
- 1000017c: dca58058 ld a1,-32680\(a1\)
+ 1000015c: dca58020 ld a1,-32736\(a1\)
+ 10000160: 64a5000c daddiu a1,a1,12
+ 10000164: 00b1282d daddu a1,a1,s1
+ 10000168: 3c050000 lui a1,0x0
+ 1000016c: 00bc282d daddu a1,a1,gp
+ 10000170: dca58020 ld a1,-32736\(a1\)
+ 10000174: 3c010001 lui at,0x1
+ 10000178: 3421e240 ori at,at,0xe240
+ 1000017c: 00a1282d daddu a1,a1,at
10000180: 00b1282d daddu a1,a1,s1
- 10000184: dca50000 ld a1,0\(a1\)
- 10000188: 3c050000 lui a1,0x0
- 1000018c: 00bc282d daddu a1,a1,gp
- 10000190: dca58058 ld a1,-32680\(a1\)
- 10000194: 00b1282d daddu a1,a1,s1
- 10000198: dca5000c ld a1,12\(a1\)
- 1000019c: 3c010000 lui at,0x0
- 100001a0: 003c082d daddu at,at,gp
- 100001a4: dc218058 ld at,-32680\(at\)
- 100001a8: 0025082d daddu at,at,a1
- 100001ac: dc250022 ld a1,34\(at\)
- 100001b0: 3c010000 lui at,0x0
- 100001b4: 003c082d daddu at,at,gp
- 100001b8: dc218058 ld at,-32680\(at\)
- 100001bc: 0025082d daddu at,at,a1
- 100001c0: fc250038 sd a1,56\(at\)
- 100001c4: 3c010000 lui at,0x0
- 100001c8: 003c082d daddu at,at,gp
- 100001cc: dc218058 ld at,-32680\(at\)
- 100001d0: 88250000 lwl a1,0\(at\)
- 100001d4: 98250003 lwr a1,3\(at\)
- 100001d8: 3c010000 lui at,0x0
- 100001dc: 003c082d daddu at,at,gp
- 100001e0: dc218058 ld at,-32680\(at\)
- 100001e4: 6421000c daddiu at,at,12
- 100001e8: 88250000 lwl a1,0\(at\)
- 100001ec: 98250003 lwr a1,3\(at\)
- 100001f0: 3c010000 lui at,0x0
- 100001f4: 003c082d daddu at,at,gp
- 100001f8: dc218058 ld at,-32680\(at\)
- 100001fc: 0031082d daddu at,at,s1
+ 10000184: 3c050000 lui a1,0x0
+ 10000188: 00bc282d daddu a1,a1,gp
+ 1000018c: dca58020 ld a1,-32736\(a1\)
+ 10000190: dca50000 ld a1,0\(a1\)
+ 10000194: 3c050000 lui a1,0x0
+ 10000198: 00bc282d daddu a1,a1,gp
+ 1000019c: dca58020 ld a1,-32736\(a1\)
+ 100001a0: dca5000c ld a1,12\(a1\)
+ 100001a4: 3c050000 lui a1,0x0
+ 100001a8: 00bc282d daddu a1,a1,gp
+ 100001ac: dca58020 ld a1,-32736\(a1\)
+ 100001b0: 00b1282d daddu a1,a1,s1
+ 100001b4: dca50000 ld a1,0\(a1\)
+ 100001b8: 3c050000 lui a1,0x0
+ 100001bc: 00bc282d daddu a1,a1,gp
+ 100001c0: dca58020 ld a1,-32736\(a1\)
+ 100001c4: 00b1282d daddu a1,a1,s1
+ 100001c8: dca5000c ld a1,12\(a1\)
+ 100001cc: 3c010000 lui at,0x0
+ 100001d0: 003c082d daddu at,at,gp
+ 100001d4: dc218020 ld at,-32736\(at\)
+ 100001d8: 0025082d daddu at,at,a1
+ 100001dc: dc250022 ld a1,34\(at\)
+ 100001e0: 3c010000 lui at,0x0
+ 100001e4: 003c082d daddu at,at,gp
+ 100001e8: dc218020 ld at,-32736\(at\)
+ 100001ec: 0025082d daddu at,at,a1
+ 100001f0: fc250038 sd a1,56\(at\)
+ 100001f4: 3c010000 lui at,0x0
+ 100001f8: 003c082d daddu at,at,gp
+ 100001fc: dc218020 ld at,-32736\(at\)
10000200: 88250000 lwl a1,0\(at\)
10000204: 98250003 lwr a1,3\(at\)
10000208: 3c010000 lui at,0x0
1000020c: 003c082d daddu at,at,gp
- 10000210: dc218058 ld at,-32680\(at\)
+ 10000210: dc218020 ld at,-32736\(at\)
10000214: 6421000c daddiu at,at,12
- 10000218: 0031082d daddu at,at,s1
- 1000021c: 88250000 lwl a1,0\(at\)
- 10000220: 98250003 lwr a1,3\(at\)
- 10000224: 3c010000 lui at,0x0
- 10000228: 003c082d daddu at,at,gp
- 1000022c: dc218058 ld at,-32680\(at\)
- 10000230: 64210022 daddiu at,at,34
- 10000234: 0025082d daddu at,at,a1
- 10000238: 88250000 lwl a1,0\(at\)
- 1000023c: 98250003 lwr a1,3\(at\)
- 10000240: 3c010000 lui at,0x0
- 10000244: 003c082d daddu at,at,gp
- 10000248: dc218058 ld at,-32680\(at\)
- 1000024c: 64210038 daddiu at,at,56
- 10000250: 0025082d daddu at,at,a1
- 10000254: a8250000 swl a1,0\(at\)
- 10000258: b8250003 swr a1,3\(at\)
- 1000025c: df858020 ld a1,-32736\(gp\)
- 10000260: 64a5071c daddiu a1,a1,1820
- 10000264: df858020 ld a1,-32736\(gp\)
- 10000268: 64a50728 daddiu a1,a1,1832
- 1000026c: df858028 ld a1,-32728\(gp\)
- 10000270: 64a5e95c daddiu a1,a1,-5796
- 10000274: df858020 ld a1,-32736\(gp\)
- 10000278: 64a5071c daddiu a1,a1,1820
- 1000027c: 00b1282d daddu a1,a1,s1
- 10000280: df858020 ld a1,-32736\(gp\)
- 10000284: 64a50728 daddiu a1,a1,1832
- 10000288: 00b1282d daddu a1,a1,s1
+ 10000218: 88250000 lwl a1,0\(at\)
+ 1000021c: 98250003 lwr a1,3\(at\)
+ 10000220: 3c010000 lui at,0x0
+ 10000224: 003c082d daddu at,at,gp
+ 10000228: dc218020 ld at,-32736\(at\)
+ 1000022c: 0031082d daddu at,at,s1
+ 10000230: 88250000 lwl a1,0\(at\)
+ 10000234: 98250003 lwr a1,3\(at\)
+ 10000238: 3c010000 lui at,0x0
+ 1000023c: 003c082d daddu at,at,gp
+ 10000240: dc218020 ld at,-32736\(at\)
+ 10000244: 6421000c daddiu at,at,12
+ 10000248: 0031082d daddu at,at,s1
+ 1000024c: 88250000 lwl a1,0\(at\)
+ 10000250: 98250003 lwr a1,3\(at\)
+ 10000254: 3c010000 lui at,0x0
+ 10000258: 003c082d daddu at,at,gp
+ 1000025c: dc218020 ld at,-32736\(at\)
+ 10000260: 64210022 daddiu at,at,34
+ 10000264: 0025082d daddu at,at,a1
+ 10000268: 88250000 lwl a1,0\(at\)
+ 1000026c: 98250003 lwr a1,3\(at\)
+ 10000270: 3c010000 lui at,0x0
+ 10000274: 003c082d daddu at,at,gp
+ 10000278: dc218020 ld at,-32736\(at\)
+ 1000027c: 64210038 daddiu at,at,56
+ 10000280: 0025082d daddu at,at,a1
+ 10000284: a8250000 swl a1,0\(at\)
+ 10000288: b8250003 swr a1,3\(at\)
1000028c: df858028 ld a1,-32728\(gp\)
- 10000290: 64a5e95c daddiu a1,a1,-5796
- 10000294: 00b1282d daddu a1,a1,s1
- 10000298: df858020 ld a1,-32736\(gp\)
- 1000029c: dca5071c ld a1,1820\(a1\)
- 100002a0: df858020 ld a1,-32736\(gp\)
- 100002a4: dca50728 ld a1,1832\(a1\)
- 100002a8: df858020 ld a1,-32736\(gp\)
+ 10000290: 64a5075c daddiu a1,a1,1884
+ 10000294: df858028 ld a1,-32728\(gp\)
+ 10000298: 64a50768 daddiu a1,a1,1896
+ 1000029c: df858030 ld a1,-32720\(gp\)
+ 100002a0: 64a5e99c daddiu a1,a1,-5732
+ 100002a4: df858028 ld a1,-32728\(gp\)
+ 100002a8: 64a5075c daddiu a1,a1,1884
100002ac: 00b1282d daddu a1,a1,s1
- 100002b0: dca5071c ld a1,1820\(a1\)
- 100002b4: df858020 ld a1,-32736\(gp\)
+ 100002b0: df858028 ld a1,-32728\(gp\)
+ 100002b4: 64a50768 daddiu a1,a1,1896
100002b8: 00b1282d daddu a1,a1,s1
- 100002bc: dca50728 ld a1,1832\(a1\)
- 100002c0: df818020 ld at,-32736\(gp\)
- 100002c4: 0025082d daddu at,at,a1
- 100002c8: dc25073e ld a1,1854\(at\)
- 100002cc: df818020 ld at,-32736\(gp\)
- 100002d0: 0025082d daddu at,at,a1
- 100002d4: fc250754 sd a1,1876\(at\)
- 100002d8: df818020 ld at,-32736\(gp\)
- 100002dc: 6421071c daddiu at,at,1820
- 100002e0: 88250000 lwl a1,0\(at\)
- 100002e4: 98250003 lwr a1,3\(at\)
- 100002e8: df818020 ld at,-32736\(gp\)
- 100002ec: 64210728 daddiu at,at,1832
- 100002f0: 88250000 lwl a1,0\(at\)
- 100002f4: 98250003 lwr a1,3\(at\)
- 100002f8: df818020 ld at,-32736\(gp\)
- 100002fc: 6421071c daddiu at,at,1820
- 10000300: 0031082d daddu at,at,s1
- 10000304: 88250000 lwl a1,0\(at\)
- 10000308: 98250003 lwr a1,3\(at\)
- 1000030c: df818020 ld at,-32736\(gp\)
- 10000310: 64210728 daddiu at,at,1832
- 10000314: 0031082d daddu at,at,s1
- 10000318: 88250000 lwl a1,0\(at\)
- 1000031c: 98250003 lwr a1,3\(at\)
- 10000320: df818020 ld at,-32736\(gp\)
- 10000324: 6421073e daddiu at,at,1854
- 10000328: 0025082d daddu at,at,a1
- 1000032c: 88250000 lwl a1,0\(at\)
- 10000330: 98250003 lwr a1,3\(at\)
- 10000334: df818020 ld at,-32736\(gp\)
- 10000338: 64210754 daddiu at,at,1876
- 1000033c: 0025082d daddu at,at,a1
- 10000340: a8250000 swl a1,0\(at\)
- 10000344: b8250003 swr a1,3\(at\)
- 10000348: 3c050000 lui a1,0x0
- 1000034c: 00bc282d daddu a1,a1,gp
- 10000350: dca58048 ld a1,-32696\(a1\)
- 10000354: df858030 ld a1,-32720\(gp\)
- 10000358: 64a500e0 daddiu a1,a1,224
- 1000035c: 3c190000 lui t9,0x0
- 10000360: 033cc82d daddu t9,t9,gp
- 10000364: df398048 ld t9,-32696\(t9\)
- 10000368: df998030 ld t9,-32720\(gp\)
- 1000036c: 673900e0 daddiu t9,t9,224
- 10000370: 3c190000 lui t9,0x0
- 10000374: 033cc82d daddu t9,t9,gp
- 10000378: df398048 ld t9,-32696\(t9\)
- 1000037c: 0320f809 jalr t9
- 10000380: 00000000 nop
- 10000384: df998030 ld t9,-32720\(gp\)
- 10000388: 673900e0 daddiu t9,t9,224
- 1000038c: 0320f809 jalr t9
- 10000390: 00000000 nop
- 10000394: 3c050000 lui a1,0x0
- 10000398: 00bc282d daddu a1,a1,gp
- 1000039c: dca58060 ld a1,-32672\(a1\)
- 100003a0: 3c050000 lui a1,0x0
- 100003a4: 00bc282d daddu a1,a1,gp
- 100003a8: dca58060 ld a1,-32672\(a1\)
- 100003ac: 64a5000c daddiu a1,a1,12
- 100003b0: 3c050000 lui a1,0x0
- 100003b4: 00bc282d daddu a1,a1,gp
- 100003b8: dca58060 ld a1,-32672\(a1\)
- 100003bc: 3c010002 lui at,0x2
- 100003c0: 6421e240 daddiu at,at,-7616
- 100003c4: 00a1282d daddu a1,a1,at
- 100003c8: 3c050000 lui a1,0x0
- 100003cc: 00bc282d daddu a1,a1,gp
- 100003d0: dca58060 ld a1,-32672\(a1\)
- 100003d4: 00b1282d daddu a1,a1,s1
- 100003d8: 3c050000 lui a1,0x0
- 100003dc: 00bc282d daddu a1,a1,gp
- 100003e0: dca58060 ld a1,-32672\(a1\)
- 100003e4: 64a5000c daddiu a1,a1,12
- 100003e8: 00b1282d daddu a1,a1,s1
- 100003ec: 3c050000 lui a1,0x0
- 100003f0: 00bc282d daddu a1,a1,gp
- 100003f4: dca58060 ld a1,-32672\(a1\)
- 100003f8: 3c010002 lui at,0x2
- 100003fc: 6421e240 daddiu at,at,-7616
- 10000400: 00a1282d daddu a1,a1,at
+ 100002bc: df858030 ld a1,-32720\(gp\)
+ 100002c0: 64a5e99c daddiu a1,a1,-5732
+ 100002c4: 00b1282d daddu a1,a1,s1
+ 100002c8: df858028 ld a1,-32728\(gp\)
+ 100002cc: dca5075c ld a1,1884\(a1\)
+ 100002d0: df858028 ld a1,-32728\(gp\)
+ 100002d4: dca50768 ld a1,1896\(a1\)
+ 100002d8: df858028 ld a1,-32728\(gp\)
+ 100002dc: 00b1282d daddu a1,a1,s1
+ 100002e0: dca5075c ld a1,1884\(a1\)
+ 100002e4: df858028 ld a1,-32728\(gp\)
+ 100002e8: 00b1282d daddu a1,a1,s1
+ 100002ec: dca50768 ld a1,1896\(a1\)
+ 100002f0: df818028 ld at,-32728\(gp\)
+ 100002f4: 0025082d daddu at,at,a1
+ 100002f8: dc25077e ld a1,1918\(at\)
+ 100002fc: df818028 ld at,-32728\(gp\)
+ 10000300: 0025082d daddu at,at,a1
+ 10000304: fc250794 sd a1,1940\(at\)
+ 10000308: df818028 ld at,-32728\(gp\)
+ 1000030c: 6421075c daddiu at,at,1884
+ 10000310: 88250000 lwl a1,0\(at\)
+ 10000314: 98250003 lwr a1,3\(at\)
+ 10000318: df818028 ld at,-32728\(gp\)
+ 1000031c: 64210768 daddiu at,at,1896
+ 10000320: 88250000 lwl a1,0\(at\)
+ 10000324: 98250003 lwr a1,3\(at\)
+ 10000328: df818028 ld at,-32728\(gp\)
+ 1000032c: 6421075c daddiu at,at,1884
+ 10000330: 0031082d daddu at,at,s1
+ 10000334: 88250000 lwl a1,0\(at\)
+ 10000338: 98250003 lwr a1,3\(at\)
+ 1000033c: df818028 ld at,-32728\(gp\)
+ 10000340: 64210768 daddiu at,at,1896
+ 10000344: 0031082d daddu at,at,s1
+ 10000348: 88250000 lwl a1,0\(at\)
+ 1000034c: 98250003 lwr a1,3\(at\)
+ 10000350: df818028 ld at,-32728\(gp\)
+ 10000354: 6421077e daddiu at,at,1918
+ 10000358: 0025082d daddu at,at,a1
+ 1000035c: 88250000 lwl a1,0\(at\)
+ 10000360: 98250003 lwr a1,3\(at\)
+ 10000364: df818028 ld at,-32728\(gp\)
+ 10000368: 64210794 daddiu at,at,1940
+ 1000036c: 0025082d daddu at,at,a1
+ 10000370: a8250000 swl a1,0\(at\)
+ 10000374: b8250003 swr a1,3\(at\)
+ 10000378: 3c050000 lui a1,0x0
+ 1000037c: 00bc282d daddu a1,a1,gp
+ 10000380: dca58038 ld a1,-32712\(a1\)
+ 10000384: df858040 ld a1,-32704\(gp\)
+ 10000388: 64a50110 daddiu a1,a1,272
+ 1000038c: 3c190000 lui t9,0x0
+ 10000390: 033cc82d daddu t9,t9,gp
+ 10000394: df398038 ld t9,-32712\(t9\)
+ 10000398: df998040 ld t9,-32704\(gp\)
+ 1000039c: 67390110 daddiu t9,t9,272
+ 100003a0: 3c190000 lui t9,0x0
+ 100003a4: 033cc82d daddu t9,t9,gp
+ 100003a8: df398038 ld t9,-32712\(t9\)
+ 100003ac: 0411ff58 bal 10000110 <fn>
+ 100003b0: 00000000 nop
+ 100003b4: df998040 ld t9,-32704\(gp\)
+ 100003b8: 67390110 daddiu t9,t9,272
+ 100003bc: 0411ff54 bal 10000110 <fn>
+ 100003c0: 00000000 nop
+ 100003c4: 3c050000 lui a1,0x0
+ 100003c8: 00bc282d daddu a1,a1,gp
+ 100003cc: dca58048 ld a1,-32696\(a1\)
+ 100003d0: 3c050000 lui a1,0x0
+ 100003d4: 00bc282d daddu a1,a1,gp
+ 100003d8: dca58048 ld a1,-32696\(a1\)
+ 100003dc: 64a5000c daddiu a1,a1,12
+ 100003e0: 3c050000 lui a1,0x0
+ 100003e4: 00bc282d daddu a1,a1,gp
+ 100003e8: dca58048 ld a1,-32696\(a1\)
+ 100003ec: 3c010001 lui at,0x1
+ 100003f0: 3421e240 ori at,at,0xe240
+ 100003f4: 00a1282d daddu a1,a1,at
+ 100003f8: 3c050000 lui a1,0x0
+ 100003fc: 00bc282d daddu a1,a1,gp
+ 10000400: dca58048 ld a1,-32696\(a1\)
10000404: 00b1282d daddu a1,a1,s1
10000408: 3c050000 lui a1,0x0
1000040c: 00bc282d daddu a1,a1,gp
- 10000410: dca58060 ld a1,-32672\(a1\)
- 10000414: dca50000 ld a1,0\(a1\)
- 10000418: 3c050000 lui a1,0x0
- 1000041c: 00bc282d daddu a1,a1,gp
- 10000420: dca58060 ld a1,-32672\(a1\)
- 10000424: dca5000c ld a1,12\(a1\)
- 10000428: 3c050000 lui a1,0x0
- 1000042c: 00bc282d daddu a1,a1,gp
- 10000430: dca58060 ld a1,-32672\(a1\)
+ 10000410: dca58048 ld a1,-32696\(a1\)
+ 10000414: 64a5000c daddiu a1,a1,12
+ 10000418: 00b1282d daddu a1,a1,s1
+ 1000041c: 3c050000 lui a1,0x0
+ 10000420: 00bc282d daddu a1,a1,gp
+ 10000424: dca58048 ld a1,-32696\(a1\)
+ 10000428: 3c010001 lui at,0x1
+ 1000042c: 3421e240 ori at,at,0xe240
+ 10000430: 00a1282d daddu a1,a1,at
10000434: 00b1282d daddu a1,a1,s1
- 10000438: dca50000 ld a1,0\(a1\)
- 1000043c: 3c050000 lui a1,0x0
- 10000440: 00bc282d daddu a1,a1,gp
- 10000444: dca58060 ld a1,-32672\(a1\)
- 10000448: 00b1282d daddu a1,a1,s1
- 1000044c: dca5000c ld a1,12\(a1\)
- 10000450: 3c010000 lui at,0x0
- 10000454: 003c082d daddu at,at,gp
- 10000458: dc218060 ld at,-32672\(at\)
- 1000045c: 0025082d daddu at,at,a1
- 10000460: dc250022 ld a1,34\(at\)
- 10000464: 3c010000 lui at,0x0
- 10000468: 003c082d daddu at,at,gp
- 1000046c: dc218060 ld at,-32672\(at\)
- 10000470: 0025082d daddu at,at,a1
- 10000474: fc250038 sd a1,56\(at\)
- 10000478: 3c010000 lui at,0x0
- 1000047c: 003c082d daddu at,at,gp
- 10000480: dc218060 ld at,-32672\(at\)
- 10000484: 88250000 lwl a1,0\(at\)
- 10000488: 98250003 lwr a1,3\(at\)
- 1000048c: 3c010000 lui at,0x0
- 10000490: 003c082d daddu at,at,gp
- 10000494: dc218060 ld at,-32672\(at\)
- 10000498: 6421000c daddiu at,at,12
- 1000049c: 88250000 lwl a1,0\(at\)
- 100004a0: 98250003 lwr a1,3\(at\)
- 100004a4: 3c010000 lui at,0x0
- 100004a8: 003c082d daddu at,at,gp
- 100004ac: dc218060 ld at,-32672\(at\)
- 100004b0: 0031082d daddu at,at,s1
+ 10000438: 3c050000 lui a1,0x0
+ 1000043c: 00bc282d daddu a1,a1,gp
+ 10000440: dca58048 ld a1,-32696\(a1\)
+ 10000444: dca50000 ld a1,0\(a1\)
+ 10000448: 3c050000 lui a1,0x0
+ 1000044c: 00bc282d daddu a1,a1,gp
+ 10000450: dca58048 ld a1,-32696\(a1\)
+ 10000454: dca5000c ld a1,12\(a1\)
+ 10000458: 3c050000 lui a1,0x0
+ 1000045c: 00bc282d daddu a1,a1,gp
+ 10000460: dca58048 ld a1,-32696\(a1\)
+ 10000464: 00b1282d daddu a1,a1,s1
+ 10000468: dca50000 ld a1,0\(a1\)
+ 1000046c: 3c050000 lui a1,0x0
+ 10000470: 00bc282d daddu a1,a1,gp
+ 10000474: dca58048 ld a1,-32696\(a1\)
+ 10000478: 00b1282d daddu a1,a1,s1
+ 1000047c: dca5000c ld a1,12\(a1\)
+ 10000480: 3c010000 lui at,0x0
+ 10000484: 003c082d daddu at,at,gp
+ 10000488: dc218048 ld at,-32696\(at\)
+ 1000048c: 0025082d daddu at,at,a1
+ 10000490: dc250022 ld a1,34\(at\)
+ 10000494: 3c010000 lui at,0x0
+ 10000498: 003c082d daddu at,at,gp
+ 1000049c: dc218048 ld at,-32696\(at\)
+ 100004a0: 0025082d daddu at,at,a1
+ 100004a4: fc250038 sd a1,56\(at\)
+ 100004a8: 3c010000 lui at,0x0
+ 100004ac: 003c082d daddu at,at,gp
+ 100004b0: dc218048 ld at,-32696\(at\)
100004b4: 88250000 lwl a1,0\(at\)
100004b8: 98250003 lwr a1,3\(at\)
100004bc: 3c010000 lui at,0x0
100004c0: 003c082d daddu at,at,gp
- 100004c4: dc218060 ld at,-32672\(at\)
+ 100004c4: dc218048 ld at,-32696\(at\)
100004c8: 6421000c daddiu at,at,12
- 100004cc: 0031082d daddu at,at,s1
- 100004d0: 88250000 lwl a1,0\(at\)
- 100004d4: 98250003 lwr a1,3\(at\)
- 100004d8: 3c010000 lui at,0x0
- 100004dc: 003c082d daddu at,at,gp
- 100004e0: dc218060 ld at,-32672\(at\)
- 100004e4: 64210022 daddiu at,at,34
- 100004e8: 0025082d daddu at,at,a1
- 100004ec: 88250000 lwl a1,0\(at\)
- 100004f0: 98250003 lwr a1,3\(at\)
- 100004f4: 3c010000 lui at,0x0
- 100004f8: 003c082d daddu at,at,gp
- 100004fc: dc218060 ld at,-32672\(at\)
- 10000500: 64210038 daddiu at,at,56
- 10000504: 0025082d daddu at,at,a1
- 10000508: a8250000 swl a1,0\(at\)
- 1000050c: b8250003 swr a1,3\(at\)
- 10000510: df858020 ld a1,-32736\(gp\)
- 10000514: 64a50794 daddiu a1,a1,1940
- 10000518: df858020 ld a1,-32736\(gp\)
- 1000051c: 64a507a0 daddiu a1,a1,1952
- 10000520: df858028 ld a1,-32728\(gp\)
- 10000524: 64a5e9d4 daddiu a1,a1,-5676
- 10000528: df858020 ld a1,-32736\(gp\)
- 1000052c: 64a50794 daddiu a1,a1,1940
- 10000530: 00b1282d daddu a1,a1,s1
- 10000534: df858020 ld a1,-32736\(gp\)
- 10000538: 64a507a0 daddiu a1,a1,1952
- 1000053c: 00b1282d daddu a1,a1,s1
+ 100004cc: 88250000 lwl a1,0\(at\)
+ 100004d0: 98250003 lwr a1,3\(at\)
+ 100004d4: 3c010000 lui at,0x0
+ 100004d8: 003c082d daddu at,at,gp
+ 100004dc: dc218048 ld at,-32696\(at\)
+ 100004e0: 0031082d daddu at,at,s1
+ 100004e4: 88250000 lwl a1,0\(at\)
+ 100004e8: 98250003 lwr a1,3\(at\)
+ 100004ec: 3c010000 lui at,0x0
+ 100004f0: 003c082d daddu at,at,gp
+ 100004f4: dc218048 ld at,-32696\(at\)
+ 100004f8: 6421000c daddiu at,at,12
+ 100004fc: 0031082d daddu at,at,s1
+ 10000500: 88250000 lwl a1,0\(at\)
+ 10000504: 98250003 lwr a1,3\(at\)
+ 10000508: 3c010000 lui at,0x0
+ 1000050c: 003c082d daddu at,at,gp
+ 10000510: dc218048 ld at,-32696\(at\)
+ 10000514: 64210022 daddiu at,at,34
+ 10000518: 0025082d daddu at,at,a1
+ 1000051c: 88250000 lwl a1,0\(at\)
+ 10000520: 98250003 lwr a1,3\(at\)
+ 10000524: 3c010000 lui at,0x0
+ 10000528: 003c082d daddu at,at,gp
+ 1000052c: dc218048 ld at,-32696\(at\)
+ 10000530: 64210038 daddiu at,at,56
+ 10000534: 0025082d daddu at,at,a1
+ 10000538: a8250000 swl a1,0\(at\)
+ 1000053c: b8250003 swr a1,3\(at\)
10000540: df858028 ld a1,-32728\(gp\)
- 10000544: 64a5e9d4 daddiu a1,a1,-5676
- 10000548: 00b1282d daddu a1,a1,s1
- 1000054c: df858020 ld a1,-32736\(gp\)
- 10000550: dca50794 ld a1,1940\(a1\)
- 10000554: df858020 ld a1,-32736\(gp\)
- 10000558: dca507a0 ld a1,1952\(a1\)
- 1000055c: df858020 ld a1,-32736\(gp\)
+ 10000544: 64a507d4 daddiu a1,a1,2004
+ 10000548: df858028 ld a1,-32728\(gp\)
+ 1000054c: 64a507e0 daddiu a1,a1,2016
+ 10000550: df858030 ld a1,-32720\(gp\)
+ 10000554: 64a5ea14 daddiu a1,a1,-5612
+ 10000558: df858028 ld a1,-32728\(gp\)
+ 1000055c: 64a507d4 daddiu a1,a1,2004
10000560: 00b1282d daddu a1,a1,s1
- 10000564: dca50794 ld a1,1940\(a1\)
- 10000568: df858020 ld a1,-32736\(gp\)
+ 10000564: df858028 ld a1,-32728\(gp\)
+ 10000568: 64a507e0 daddiu a1,a1,2016
1000056c: 00b1282d daddu a1,a1,s1
- 10000570: dca507a0 ld a1,1952\(a1\)
- 10000574: df818020 ld at,-32736\(gp\)
- 10000578: 0025082d daddu at,at,a1
- 1000057c: dc250794 ld a1,1940\(at\)
- 10000580: df818020 ld at,-32736\(gp\)
- 10000584: 0025082d daddu at,at,a1
- 10000588: fc2507cc sd a1,1996\(at\)
- 1000058c: df818020 ld at,-32736\(gp\)
- 10000590: 64210794 daddiu at,at,1940
- 10000594: 88250000 lwl a1,0\(at\)
- 10000598: 98250003 lwr a1,3\(at\)
- 1000059c: df818020 ld at,-32736\(gp\)
- 100005a0: 642107a0 daddiu at,at,1952
- 100005a4: 88250000 lwl a1,0\(at\)
- 100005a8: 98250003 lwr a1,3\(at\)
- 100005ac: df818020 ld at,-32736\(gp\)
- 100005b0: 64210794 daddiu at,at,1940
- 100005b4: 0031082d daddu at,at,s1
- 100005b8: 88250000 lwl a1,0\(at\)
- 100005bc: 98250003 lwr a1,3\(at\)
- 100005c0: df818020 ld at,-32736\(gp\)
- 100005c4: 642107a0 daddiu at,at,1952
- 100005c8: 0031082d daddu at,at,s1
- 100005cc: 88250000 lwl a1,0\(at\)
- 100005d0: 98250003 lwr a1,3\(at\)
- 100005d4: df818020 ld at,-32736\(gp\)
- 100005d8: 642107b6 daddiu at,at,1974
- 100005dc: 0025082d daddu at,at,a1
- 100005e0: 88250000 lwl a1,0\(at\)
- 100005e4: 98250003 lwr a1,3\(at\)
- 100005e8: df818020 ld at,-32736\(gp\)
- 100005ec: 642107cc daddiu at,at,1996
- 100005f0: 0025082d daddu at,at,a1
- 100005f4: a8250000 swl a1,0\(at\)
- 100005f8: b8250003 swr a1,3\(at\)
- 100005fc: 3c050000 lui a1,0x0
- 10000600: 00bc282d daddu a1,a1,gp
- 10000604: dca58050 ld a1,-32688\(a1\)
- 10000608: df858030 ld a1,-32720\(gp\)
- 1000060c: 64a506e0 daddiu a1,a1,1760
- 10000610: 3c190000 lui t9,0x0
- 10000614: 033cc82d daddu t9,t9,gp
- 10000618: df398050 ld t9,-32688\(t9\)
- 1000061c: df998030 ld t9,-32720\(gp\)
- 10000620: 673906e0 daddiu t9,t9,1760
- 10000624: 3c190000 lui t9,0x0
- 10000628: 033cc82d daddu t9,t9,gp
- 1000062c: df398050 ld t9,-32688\(t9\)
- 10000630: 0320f809 jalr t9
- 10000634: 00000000 nop
- 10000638: df998030 ld t9,-32720\(gp\)
- 1000063c: 673906e0 daddiu t9,t9,1760
- 10000640: 0320f809 jalr t9
- 10000644: 00000000 nop
- 10000648: 3c050000 lui a1,0x0
- 1000064c: 00bc282d daddu a1,a1,gp
- 10000650: dca58058 ld a1,-32680\(a1\)
- 10000654: 1000fea2 b 100000e0 <fn>
- 10000658: 00000000 nop
- 1000065c: 3c050000 lui a1,0x0
- 10000660: 00bc282d daddu a1,a1,gp
- 10000664: dca58060 ld a1,-32672\(a1\)
- 10000668: dca50000 ld a1,0\(a1\)
- 1000066c: 1000001c b 100006e0 <fn2>
- 10000670: 00000000 nop
- 10000674: df858020 ld a1,-32736\(gp\)
- 10000678: 64a5071c daddiu a1,a1,1820
- 1000067c: 1000fe98 b 100000e0 <fn>
- 10000680: 00000000 nop
- 10000684: df858020 ld a1,-32736\(gp\)
- 10000688: 64a507a0 daddiu a1,a1,1952
- 1000068c: 10000014 b 100006e0 <fn2>
- 10000690: 00000000 nop
- 10000694: df858028 ld a1,-32728\(gp\)
- 10000698: 64a5e95c daddiu a1,a1,-5796
- 1000069c: 1000fe90 b 100000e0 <fn>
+ 10000570: df858030 ld a1,-32720\(gp\)
+ 10000574: 64a5ea14 daddiu a1,a1,-5612
+ 10000578: 00b1282d daddu a1,a1,s1
+ 1000057c: df858028 ld a1,-32728\(gp\)
+ 10000580: dca507d4 ld a1,2004\(a1\)
+ 10000584: df858028 ld a1,-32728\(gp\)
+ 10000588: dca507e0 ld a1,2016\(a1\)
+ 1000058c: df858028 ld a1,-32728\(gp\)
+ 10000590: 00b1282d daddu a1,a1,s1
+ 10000594: dca507d4 ld a1,2004\(a1\)
+ 10000598: df858028 ld a1,-32728\(gp\)
+ 1000059c: 00b1282d daddu a1,a1,s1
+ 100005a0: dca507e0 ld a1,2016\(a1\)
+ 100005a4: df818028 ld at,-32728\(gp\)
+ 100005a8: 0025082d daddu at,at,a1
+ 100005ac: dc2507f6 ld a1,2038\(at\)
+ 100005b0: df818028 ld at,-32728\(gp\)
+ 100005b4: 0025082d daddu at,at,a1
+ 100005b8: fc25080c sd a1,2060\(at\)
+ 100005bc: df818028 ld at,-32728\(gp\)
+ 100005c0: 642107d4 daddiu at,at,2004
+ 100005c4: 88250000 lwl a1,0\(at\)
+ 100005c8: 98250003 lwr a1,3\(at\)
+ 100005cc: df818028 ld at,-32728\(gp\)
+ 100005d0: 642107e0 daddiu at,at,2016
+ 100005d4: 88250000 lwl a1,0\(at\)
+ 100005d8: 98250003 lwr a1,3\(at\)
+ 100005dc: df818028 ld at,-32728\(gp\)
+ 100005e0: 642107d4 daddiu at,at,2004
+ 100005e4: 0031082d daddu at,at,s1
+ 100005e8: 88250000 lwl a1,0\(at\)
+ 100005ec: 98250003 lwr a1,3\(at\)
+ 100005f0: df818028 ld at,-32728\(gp\)
+ 100005f4: 642107e0 daddiu at,at,2016
+ 100005f8: 0031082d daddu at,at,s1
+ 100005fc: 88250000 lwl a1,0\(at\)
+ 10000600: 98250003 lwr a1,3\(at\)
+ 10000604: df818028 ld at,-32728\(gp\)
+ 10000608: 642107f6 daddiu at,at,2038
+ 1000060c: 0025082d daddu at,at,a1
+ 10000610: 88250000 lwl a1,0\(at\)
+ 10000614: 98250003 lwr a1,3\(at\)
+ 10000618: df818028 ld at,-32728\(gp\)
+ 1000061c: 6421080c daddiu at,at,2060
+ 10000620: 0025082d daddu at,at,a1
+ 10000624: a8250000 swl a1,0\(at\)
+ 10000628: b8250003 swr a1,3\(at\)
+ 1000062c: 3c050000 lui a1,0x0
+ 10000630: 00bc282d daddu a1,a1,gp
+ 10000634: dca58050 ld a1,-32688\(a1\)
+ 10000638: df858040 ld a1,-32704\(gp\)
+ 1000063c: 64a50710 daddiu a1,a1,1808
+ 10000640: 3c190000 lui t9,0x0
+ 10000644: 033cc82d daddu t9,t9,gp
+ 10000648: df398050 ld t9,-32688\(t9\)
+ 1000064c: df998040 ld t9,-32704\(gp\)
+ 10000650: 67390710 daddiu t9,t9,1808
+ 10000654: 3c190000 lui t9,0x0
+ 10000658: 033cc82d daddu t9,t9,gp
+ 1000065c: df398050 ld t9,-32688\(t9\)
+ 10000660: 0411002b bal 10000710 <fn2>
+ 10000664: 00000000 nop
+ 10000668: df998040 ld t9,-32704\(gp\)
+ 1000066c: 67390710 daddiu t9,t9,1808
+ 10000670: 04110027 bal 10000710 <fn2>
+ 10000674: 00000000 nop
+ 10000678: 3c050000 lui a1,0x0
+ 1000067c: 00bc282d daddu a1,a1,gp
+ 10000680: dca58020 ld a1,-32736\(a1\)
+ 10000684: 1000fea2 b 10000110 <fn>
+ 10000688: 00000000 nop
+ 1000068c: 3c050000 lui a1,0x0
+ 10000690: 00bc282d daddu a1,a1,gp
+ 10000694: dca58048 ld a1,-32696\(a1\)
+ 10000698: dca50000 ld a1,0\(a1\)
+ 1000069c: 1000001c b 10000710 <fn2>
100006a0: 00000000 nop
- 100006a4: df858020 ld a1,-32736\(gp\)
- 100006a8: dca50794 ld a1,1940\(a1\)
- 100006ac: 1000000c b 100006e0 <fn2>
+ 100006a4: df858028 ld a1,-32728\(gp\)
+ 100006a8: 64a5075c daddiu a1,a1,1884
+ 100006ac: 1000fe98 b 10000110 <fn>
100006b0: 00000000 nop
- 100006b4: df858020 ld a1,-32736\(gp\)
- 100006b8: dca50728 ld a1,1832\(a1\)
- 100006bc: 1000fe88 b 100000e0 <fn>
+ 100006b4: df858028 ld a1,-32728\(gp\)
+ 100006b8: 64a507e0 daddiu a1,a1,2016
+ 100006bc: 10000014 b 10000710 <fn2>
100006c0: 00000000 nop
- 100006c4: df818020 ld at,-32736\(gp\)
- 100006c8: 0025082d daddu at,at,a1
- 100006cc: dc2507b6 ld a1,1974\(at\)
- 100006d0: 10000003 b 100006e0 <fn2>
- 100006d4: 00000000 nop
+ 100006c4: df858030 ld a1,-32720\(gp\)
+ 100006c8: 64a5e99c daddiu a1,a1,-5732
+ 100006cc: 1000fe90 b 10000110 <fn>
+ 100006d0: 00000000 nop
+ 100006d4: df858028 ld a1,-32728\(gp\)
+ 100006d8: dca507d4 ld a1,2004\(a1\)
+ 100006dc: 1000000c b 10000710 <fn2>
+ 100006e0: 00000000 nop
+ 100006e4: df858028 ld a1,-32728\(gp\)
+ 100006e8: dca50768 ld a1,1896\(a1\)
+ 100006ec: 1000fe88 b 10000110 <fn>
+ 100006f0: 00000000 nop
+ 100006f4: df818028 ld at,-32728\(gp\)
+ 100006f8: 0025082d daddu at,at,a1
+ 100006fc: dc2507f6 ld a1,2038\(at\)
+ 10000700: 10000003 b 10000710 <fn2>
+ 10000704: 00000000 nop
+ \.\.\.
+
+0000000010000710 <fn2>:
\.\.\.
Disassembly of section \.data:
-00000000101006e0 <_fdata>:
+0000000010010720 <_fdata>:
\.\.\.
-000000001010071c <dg1>:
+000000001001075c <dg1>:
\.\.\.
-0000000010100758 <sp2>:
+0000000010010798 <sp2>:
\.\.\.
-0000000010100794 <dg2>:
+00000000100107d4 <dg2>:
\.\.\.
Disassembly of section \.got:
-00000000101007d0 <_GLOBAL_OFFSET_TABLE_>:
+0000000010010810 <_GLOBAL_OFFSET_TABLE_>:
+ \.\.\.
+ 10010818: 80000000 .*
\.\.\.
- 101007d8: 80000000 .*
- 101007dc: 00000000 .*
- 101007e0: 00000000 .*
- 101007e4: 10100000 .*
- 101007e8: 00000000 .*
- 101007ec: 10120000 .*
- 101007f0: 00000000 .*
- 101007f4: 10000000 .*
- 101007f8: 00000000 .*
+ 10010824: 1001075c .*
+ 10010828: 00000000 .*
+ 1001082c: 10010000 .*
+ 10010830: 00000000 .*
+ 10010834: 10030000 .*
+ 10010838: 00000000 .*
+ 1001083c: 10000110 .*
+ 10010840: 00000000 .*
+ 10010844: 10000000 .*
+ 10010848: 00000000 .*
+ 1001084c: 100107d4 .*
+ 10010850: 00000000 .*
+ 10010854: 10000710 .*
+ 10010858: 00000000 .*
\.\.\.
- 1010080c: 100000e0 .*
- 10100810: 00000000 .*
- 10100814: 100006e0 .*
- 10100818: 00000000 .*
- 1010081c: 1010071c .*
- 10100820: 00000000 .*
- 10100824: 10100794 .*
#name: Emit relocs 1
-#source: emit-relocs-1a.s -mabi=n32 -EB
-#source: emit-relocs-1b.s -mabi=n32 -EB
+#source: emit-relocs-1a.s -march=from-abi -mabi=n32 -EB
+#source: emit-relocs-1b.s -march=from-abi -mabi=n32 -EB
#ld: -q -T emit-relocs-1.ld -melf32btsmipn32
#objdump: -sr
.text
+ .align 4
.globl _start
_start:
jr $31
D: .4byte 0x200
.data
+ .align 4
E: .4byte E
.4byte E + 0x1000
.4byte A
D: .4byte 0x200
.data
+ .align 4
E: .4byte E
.4byte E + 0x1000
.4byte A
--- /dev/null
+ .text
+ .balign 16
+ .xdef protected_foo
+ .protected protected_foo
+ .ent protected_foo
+protected_foo:
+ jr $31
+ .end protected_foo
+ .balign 16
+ .xdef hidden_foo
+ .hidden hidden_foo
+ .ent hidden_foo
+hidden_foo:
+ jr $31
+ .end hidden_foo
+ .balign 16
+ .xdef internal_foo
+ .internal internal_foo
+ .ent internal_foo
+internal_foo:
+ jr $31
+ .end internal_foo
--- /dev/null
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+12340000 <foo>:
+12340000: 27bdfff0 addiu sp,sp,-16
+12340004: ffbf0008 sd ra,8\(sp\)
+12340008: ffbc0000 sd gp,0\(sp\)
+1234000c: 3c1c0001 lui gp,0x1
+12340010: 279c8080 addiu gp,gp,-32640
+12340014: 0399e021 addu gp,gp,t9
+12340018: 8f998018 lw t9,-32744\(gp\)
+1234001c: 04110010 bal 12340060 <protected_foo>
+12340020: 00000000 nop
+12340024: 8f99801c lw t9,-32740\(gp\)
+12340028: 04110011 bal 12340070 <hidden_foo>
+1234002c: 00000000 nop
+12340030: 8f998020 lw t9,-32736\(gp\)
+12340034: 04110012 bal 12340080 <internal_foo>
+12340038: 00000000 nop
+1234003c: dfbc0000 ld gp,0\(sp\)
+12340040: dfbf0008 ld ra,8\(sp\)
+12340044: 03e00008 jr ra
+12340048: 27bd0010 addiu sp,sp,16
+ \.\.\.
+
+12340060 <protected_foo>:
+12340060: 03e00008 jr ra
+12340064: 00000000 nop
+ \.\.\.
+
+12340070 <hidden_foo>:
+12340070: 03e00008 jr ra
+12340074: 00000000 nop
+ \.\.\.
+
+12340080 <internal_foo>:
+12340080: 03e00008 jr ra
+12340084: 00000000 nop
+ \.\.\.
--- /dev/null
+
+Primary GOT:
+ Canonical gp value: 12348080
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 12340090 -32752\(gp\) 00000000 Lazy resolver
+ 12340094 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+ Address Access Initial
+ 12340098 -32744\(gp\) 12340060
+ 1234009c -32740\(gp\) 12340070
+ 123400a0 -32736\(gp\) 12340080
--- /dev/null
+ .text
+ .balign 16
+ .xdef foo
+ .ent foo
+foo:
+ .frame $29, 16, $31
+ .mask 0x90000000, -8
+ addiu $29, -16
+ sd $31, 8($29)
+ .cpsetup $25, 0, foo
+ jal protected_foo
+ jal hidden_foo
+ jal internal_foo
+ .cpreturn
+ ld $31, 8($29)
+ addiu $29, 16
+ jr $31
+ .end foo
+ .balign 4
+ .space 8
--- /dev/null
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+123456789abc0000 <foo>:
+123456789abc0000: 67bdfff0 daddiu sp,sp,-16
+123456789abc0004: ffbf0008 sd ra,8\(sp\)
+123456789abc0008: ffbc0000 sd gp,0\(sp\)
+123456789abc000c: 3c1c0001 lui gp,0x1
+123456789abc0010: 279c8080 addiu gp,gp,-32640
+123456789abc0014: 0399e02d daddu gp,gp,t9
+123456789abc0018: df998020 ld t9,-32736\(gp\)
+123456789abc001c: 04110010 bal 123456789abc0060 <protected_foo>
+123456789abc0020: 00000000 nop
+123456789abc0024: df998028 ld t9,-32728\(gp\)
+123456789abc0028: 04110011 bal 123456789abc0070 <hidden_foo>
+123456789abc002c: 00000000 nop
+123456789abc0030: df998030 ld t9,-32720\(gp\)
+123456789abc0034: 04110012 bal 123456789abc0080 <internal_foo>
+123456789abc0038: 00000000 nop
+123456789abc003c: dfbc0000 ld gp,0\(sp\)
+123456789abc0040: dfbf0008 ld ra,8\(sp\)
+123456789abc0044: 03e00008 jr ra
+123456789abc0048: 67bd0010 daddiu sp,sp,16
+ \.\.\.
+
+123456789abc0060 <protected_foo>:
+123456789abc0060: 03e00008 jr ra
+123456789abc0064: 00000000 nop
+ \.\.\.
+
+123456789abc0070 <hidden_foo>:
+123456789abc0070: 03e00008 jr ra
+123456789abc0074: 00000000 nop
+ \.\.\.
+
+123456789abc0080 <internal_foo>:
+123456789abc0080: 03e00008 jr ra
+123456789abc0084: 00000000 nop
+ \.\.\.
--- /dev/null
+
+Primary GOT:
+ Canonical gp value: 123456789abc8080
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 123456789abc0090 -32752\(gp\) 0000000000000000 Lazy resolver
+ 123456789abc0098 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\)
+
+ Local entries:
+ Address Access Initial
+ 123456789abc00a0 -32736\(gp\) 123456789abc0060
+ 123456789abc00a8 -32728\(gp\) 123456789abc0070
+ 123456789abc00b0 -32720\(gp\) 123456789abc0080
--- /dev/null
+ .text
+ .balign 16
+ .xdef foo
+ .ent foo
+foo:
+ .frame $29, 16, $31
+ .mask 0x90000000, -8
+ daddiu $29, -16
+ sd $31, 8($29)
+ .cpsetup $25, 0, foo
+ jal protected_foo
+ jal hidden_foo
+ jal internal_foo
+ .cpreturn
+ ld $31, 8($29)
+ daddiu $29, 16
+ jr $31
+ .end foo
+ .balign 4
+ .space 8
--- /dev/null
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+12340000 <foo>:
+12340000: 3c1c0001 lui gp,0x1
+12340004: 279c8080 addiu gp,gp,-32640
+12340008: 0399e021 addu gp,gp,t9
+1234000c: 27bdfff8 addiu sp,sp,-8
+12340010: afbf0004 sw ra,4\(sp\)
+12340014: afbc0000 sw gp,0\(sp\)
+12340018: 8f998018 lw t9,-32744\(gp\)
+1234001c: 0320f809 jalr t9
+12340020: 00000000 nop
+12340024: 8fbc0000 lw gp,0\(sp\)
+12340028: 8f99801c lw t9,-32740\(gp\)
+1234002c: 0320f809 jalr t9
+12340030: 00000000 nop
+12340034: 8fbc0000 lw gp,0\(sp\)
+12340038: 8f998020 lw t9,-32736\(gp\)
+1234003c: 0320f809 jalr t9
+12340040: 00000000 nop
+12340044: 8fbc0000 lw gp,0\(sp\)
+12340048: 8fbf0004 lw ra,4\(sp\)
+1234004c: 03e00008 jr ra
+12340050: 27bd0008 addiu sp,sp,8
+ \.\.\.
+
+12340060 <protected_foo>:
+12340060: 03e00008 jr ra
+12340064: 00000000 nop
+ \.\.\.
+
+12340070 <hidden_foo>:
+12340070: 03e00008 jr ra
+12340074: 00000000 nop
+ \.\.\.
+
+12340080 <internal_foo>:
+12340080: 03e00008 jr ra
+12340084: 00000000 nop
+ \.\.\.
--- /dev/null
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+12340000 <foo>:
+12340000: 3c1c0001 lui gp,0x1
+12340004: 279c8080 addiu gp,gp,-32640
+12340008: 0399e021 addu gp,gp,t9
+1234000c: 27bdfff8 addiu sp,sp,-8
+12340010: afbf0004 sw ra,4\(sp\)
+12340014: afbc0000 sw gp,0\(sp\)
+12340018: 8f998018 lw t9,-32744\(gp\)
+1234001c: 04110010 bal 12340060 <protected_foo>
+12340020: 00000000 nop
+12340024: 8fbc0000 lw gp,0\(sp\)
+12340028: 8f99801c lw t9,-32740\(gp\)
+1234002c: 04110010 bal 12340070 <hidden_foo>
+12340030: 00000000 nop
+12340034: 8fbc0000 lw gp,0\(sp\)
+12340038: 8f998020 lw t9,-32736\(gp\)
+1234003c: 04110010 bal 12340080 <internal_foo>
+12340040: 00000000 nop
+12340044: 8fbc0000 lw gp,0\(sp\)
+12340048: 8fbf0004 lw ra,4\(sp\)
+1234004c: 03e00008 jr ra
+12340050: 27bd0008 addiu sp,sp,8
+ \.\.\.
+
+12340060 <protected_foo>:
+12340060: 03e00008 jr ra
+12340064: 00000000 nop
+ \.\.\.
+
+12340070 <hidden_foo>:
+12340070: 03e00008 jr ra
+12340074: 00000000 nop
+ \.\.\.
+
+12340080 <internal_foo>:
+12340080: 03e00008 jr ra
+12340084: 00000000 nop
+ \.\.\.
--- /dev/null
+
+Primary GOT:
+ Canonical gp value: 12348080
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 12340090 -32752\(gp\) 00000000 Lazy resolver
+ 12340094 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+ Address Access Initial
+ 12340098 -32744\(gp\) 12340060
+ 1234009c -32740\(gp\) 12340070
+ 123400a0 -32736\(gp\) 12340080
--- /dev/null
+ .text
+ .balign 16
+ .xdef foo
+ .ent foo
+foo:
+ .frame $29, 8, $31
+ .mask 0x80000000, -4
+ .set noreorder
+ .cpload $25
+ .set reorder
+ addiu $29, -8
+ sw $31, 4($29)
+ .cprestore 0
+ jal protected_foo
+ jal hidden_foo
+ jal internal_foo
+ lw $31, 4($29)
+ addiu $29, 8
+ jr $31
+ .end foo
+ .balign 4
+ .space 8
--- /dev/null
+ENTRY (foo);
+SECTIONS
+{
+ .text : { *(.text) }
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
+ .got : { *(.got) }
+ .dynamic : { *(.dynamic) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .pdr : { *(.pdr) }
+ .shstrtab : { *(.shstrtab) }
+ .symtab : { *(.symtab) }
+ .strtab : { *(.strtab) }
+ /DISCARD/ : { *(*) }
+}
--- /dev/null
+# Expect script for symbol export classes, MIPS variation.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-Linux targets; feel free to include your favorite one
+# if you like.
+if { ![istarget mips*-*-linux*] } {
+ return
+}
+
+proc mips_export_class_test { abi flag emul } {
+
+ set testname "MIPS $abi symbol export class test"
+
+ set dump [string map {o32 32 n32 32 n64 64} $abi]
+
+ set AFLAGS "$flag -EB"
+ set LDFLAGS "-m$emul"
+
+ # Build an auxiliary shared object with conflicting versioned symbol
+ # definitions.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "$LDFLAGS -shared -version-script ../ld-elf/export-class-lib.ver" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-lib.s } \
+ {} \
+ "mips-$abi-export-class-lib.so" \
+ ] \
+ ]
+
+ # Build a static object that pulls symbol definitions. It has to come
+ # first before the auxiliary shared object and other static objects on
+ # the linker's command line and hence we need to build it separately.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "$LDFLAGS -r" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-ref.s } \
+ {} \
+ "mips-$abi-export-class-ref-r.o" \
+ ] \
+ ]
+
+ # Build static objects that satisfy symbol dependencies and preempt
+ # shared-object symbol definitions, and link all the objects built into
+ # the final shared object. The command-line order of objects linked is
+ # important to make sure the linker correctly preempts versioned symbols
+ # from the auxiliary shared object and is as follows: ref, lib, dep, def.
+ # Get a dump to make sure symbol dependencies are resolved internally.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "$LDFLAGS -shared -Tdata=0x12340000 tmpdir/mips-$abi-export-class-ref-r.o tmpdir/mips-$abi-export-class-lib.so" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-dep.s ../ld-elf/export-class-def.s } \
+ [list \
+ [list readelf -r mips-$dump-export-class.rd] \
+ [list readelf "-x .data" mips-$dump-export-class.xd] \
+ ] \
+ "mips-$abi-export-class.so" \
+ ] \
+ ]
+}
+
+# For targets that default to a specific ISA (instead of "from-abi"),
+# the 64-bit -march option is required to override it, like for
+# "mipsisa32r2el-*-*".
+set abis { o32 -32 elf32btsmip n32 "-n32 -march=mips3" elf32btsmipn32 n64 "-64 -march=mips3" elf64btsmip }
+foreach { abi flag emul } $abis {
+ mips_export_class_test $abi $flag $emul
+}
. = 0x60000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
. = 0x1236000000000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = ALIGN (0x400);
#name: GOT page test 2
#source: got-page-2.s
-#as: -EB -n32
+#as: -march=from-abi -EB -n32
#ld: -T got-page-1.ld -shared -melf32btsmipn32
#readelf: -d
#
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00000000 * R_MIPS_NONE *
+ * Type2: R_MIPS_NONE *
+ * Type3: R_MIPS_NONE *
+[0-9a-f]+ * [0-9a-f]+00001203 * R_MIPS_REL32 * [0-9a-f]+ * foo
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00000000 * R_MIPS_NONE *
+ * Type2: R_MIPS_NONE *
+ * Type3: R_MIPS_NONE *
+# This must be an absolute relocation, there must not be a _gp reference.
+[0-9a-f]+ * 0+00001203 * R_MIPS_REL32 *
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00 * R_MIPS_NONE *
+# This must be an absolute relocation, there must not be a _gp reference.
+[0-9a-f]+ * 0+03 * R_MIPS_REL32 *
--- /dev/null
+ .data
+ .globl bar
+ .type bar, @object
+bar:
+ .dc.a _gp
+ .size bar, . - bar
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 3 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00000000 * R_MIPS_NONE *
+ * Type2: R_MIPS_NONE *
+ * Type3: R_MIPS_NONE *
+# This must be an absolute relocation, there must not be a _gp reference.
+[0-9a-f]+ * 0+00001203 * R_MIPS_REL32 *
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
+[0-9a-f]+ * [0-9a-f]+00001203 * R_MIPS_REL32 * [0-9a-f]+ * bar
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 3 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00 * R_MIPS_NONE *
+# This must be an absolute relocation, there must not be a _gp reference.
+[0-9a-f]+ * 0+03 * R_MIPS_REL32 *
+[0-9a-f]+ * [0-9a-f]+03 * R_MIPS_REL32 * [0-9a-f]+ * bar
--- /dev/null
+ .data
+ .globl foo
+ .type foo, @object
+foo:
+ .dc.a bar
+ .dc.a _gp
+ .size foo, . - foo
--- /dev/null
+{ global: foo; local: *; };
--- /dev/null
+
+Relocation section '\.rel\.dyn' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name
+[0-9a-f]+ * 0+00 * R_MIPS_NONE *
+[0-9a-f]+ * [0-9a-f]+03 * R_MIPS_REL32 * [0-9a-f]+ * foo
--- /dev/null
+ .data
+ .globl blah
+ .type blah, @object
+blah:
+ .dc.a foo
+ .dc.a _gp
+ .size blah, . - blah
--- /dev/null
+
+Symbol table '.dynsym' contains [0-9]+ entries:
+ * Num: * Value * Size * Type * Bind * Vis * Ndx * Name
+#...
+Symbol table '.symtab' contains [0-9]+ entries:
+ * Num: * Value * Size * Type * Bind * Vis * Ndx * Name
+#...
+ * [0-9a-f]+: * [0-9a-f]+ * 0 * NOTYPE * LOCAL * DEFAULT * ABS * _gp
+#pass
nop
jal s2
nop
- nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name
+00000000 00000000 R_MIPS_NONE *
+12340000 00000003 R_MIPS_REL32 *
+12340010 00000003 R_MIPS_REL32 *
+12340020 00000003 R_MIPS_REL32 *
+12340040 00000003 R_MIPS_REL32 *
+12340050 00000003 R_MIPS_REL32 *
+12340060 00000003 R_MIPS_REL32 *
+12340070 00000003 R_MIPS_REL32 *
+12340080 00000003 R_MIPS_REL32 *
+12340090 00000003 R_MIPS_REL32 *
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 123400a0 00000000 00000000 00000000 .*
+ 0x12340010 123400a0 00000000 00000000 00000000 .*
+ 0x12340020 123400a0 00000000 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 123400a0 00000000 00000000 00000000 .*
+ 0x12340050 123400a0 00000000 00000000 00000000 .*
+ 0x12340060 123400a0 00000000 00000000 00000000 .*
+ 0x12340070 123400a0 00000000 00000000 00000000 .*
+ 0x12340080 123400a0 00000000 00000000 00000000 .*
+ 0x12340090 123400a0 00000000 00000000 00000000 .*
--- /dev/null
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name
+000000000000 000000000000 R_MIPS_NONE *
+ Type2: R_MIPS_NONE *
+ Type3: R_MIPS_NONE *
+000012340000 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340010 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340020 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340040 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340050 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340060 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340070 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340080 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
+000012340090 000000001203 R_MIPS_REL32 *
+ Type2: R_MIPS_64 *
+ Type3: R_MIPS_NONE *
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 00000000 123400a0 00000000 00000000 .*
+ 0x12340010 00000000 123400a0 00000000 00000000 .*
+ 0x12340020 00000000 123400a0 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 00000000 123400a0 00000000 00000000 .*
+ 0x12340050 00000000 123400a0 00000000 00000000 .*
+ 0x12340060 00000000 123400a0 00000000 00000000 .*
+ 0x12340070 00000000 123400a0 00000000 00000000 .*
+ 0x12340080 00000000 123400a0 00000000 00000000 .*
+ 0x12340090 00000000 123400a0 00000000 00000000 .*
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
.got : { *(.got.plt) *(.got) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
return
}
-set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
+set has_newabi [expr [istarget *-*-irix6*] \
+ || [istarget mips*-*-linux*] \
+ || [istarget mips*-sde-elf*]]
set linux_gnu [expr [istarget mips*-*-linux*]]
set embedded_elf [expr [istarget mips*-*-elf]]
+# Set defaults.
+set abi_asflags(o32) ""
+set abi_asflags(n32) "-march=from-abi -n32 -EB"
+set abi_asflags(n64) "-march=from-abi -64 -EB"
+set abi_ldflags(o32) ""
+set abi_ldflags(n32) -melf32bmipn32
+set abi_ldflags(n64) -melf64bmip
+
+# Override as needed.
+if { [istarget *-*-irix6*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32bsmip
+} elseif { [istarget mips64*-linux*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32btsmip
+} elseif { [istarget mips64*-*freebsd*] } {
+ set abi_asflags(o32) "-32 -EB"
+ set abi_ldflags(o32) -melf32btsmip_fbsd
+}
+if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] } {
+ set abi_ldflags(n32) -melf32btsmipn32
+ set abi_ldflags(n64) -melf64btsmip
+} elseif { [istarget mips64*-*freebsd*] } {
+ set abi_ldflags(n32) -melf32btsmipn32_fbsd
+ set abi_ldflags(n64) -melf64btsmip_fbsd
+}
+
if { $linux_gnu } {
run_ld_link_tests [list \
[list "Dummy shared library for MIPS16 PIC test 1" \
"mips16-pic-4"]]
}
-if { [istarget mips64*-linux-gnu] } {
- set o32_as_flags "-32 -EB"
- set o32_ld_flags "-melf32btsmip"
-} elseif { [istarget mips64*-*freebsd*] } {
- set o32_as_flags "-32 -EB"
- set o32_ld_flags "-melf32btsmip_fbsd"
-} else {
- set o32_as_flags ""
- set o32_ld_flags ""
-}
-
# Check MIPS16 markings being passed through link.
run_dump_test "mips16-1"
}
if $has_newabi {
- run_dump_test "elf-rel-got-n32"
- run_dump_test "elf-rel-xgot-n32"
+ if { $embedded_elf } {
+ run_dump_test "elf-rel-got-n32-embed" \
+ [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "elf-rel-xgot-n32-embed" \
+ [list [list ld $abi_ldflags(n32)]]
+ } else {
+ run_dump_test "elf-rel-got-n32" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "elf-rel-xgot-n32" [list [list ld $abi_ldflags(n32)]]
+ }
if { $linux_gnu } {
- run_dump_test "elf-rel-got-n64-linux"
- run_dump_test "elf-rel-xgot-n64-linux"
+ run_dump_test "elf-rel-got-n64-linux" \
+ [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64-linux" \
+ [list [list ld $abi_ldflags(n64)]]
+ } elseif { $embedded_elf } {
+ run_dump_test "elf-rel-got-n64-embed" \
+ [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64-embed" \
+ [list [list ld $abi_ldflags(n64)]]
} else {
- run_dump_test "elf-rel-got-n64"
- run_dump_test "elf-rel-xgot-n64"
+ run_dump_test "elf-rel-got-n64" [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "elf-rel-xgot-n64" [list [list ld $abi_ldflags(n64)]]
}
run_dump_test "relax-jalr-n32"
"readelf --symbols pic-and-nonpic-6-${abi}.nd" \
"readelf -d pic-and-nonpic-6-${abi}.ad"] \
"pic-and-nonpic-6-${abi}"]]
+
+ # This checks whether our linker scripts get the scope of _gp right,
+ # and must therefore use default scripts. If they don't, then -- in
+ # addition to dumps failing to match -- the final link fails with:
+ #
+ # ld: gp-hidden.o: undefined reference to symbol '_gp'
+ # ld: note: '_gp' is defined in DSO ./tmpdir/gp-hidden-lib-${abi}.so
+ # so try adding it to the linker command line
+ #
+ set suff64 [string map {o32 "" n32 "" n64 -64} $abi]
+ run_ld_link_tests [list \
+ [list \
+ "_gp scope test ($abi shared library)" \
+ "$abi_ldflags($abi) -shared" \
+ "$abi_asflags($abi) -KPIC" \
+ { gp-hidden-lib.s } \
+ [list \
+ "readelf --relocs gp-hidden-lib${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-lib-${abi}.so"] \
+ [list \
+ "_gp scope test ($abi versioned library)" \
+ "$abi_ldflags($abi) -shared -version-script gp-hidden-ver.ver tmpdir/gp-hidden-lib-${abi}.so" \
+ "$abi_asflags($abi) -KPIC" \
+ { gp-hidden-ver.s } \
+ [list \
+ "readelf --relocs gp-hidden-ver${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-ver-${abi}.so"] \
+ [list \
+ "_gp scope test ($abi executable)" \
+ "$abi_ldflags($abi) -e 0 -rpath-link . tmpdir/gp-hidden-ver-${abi}.so" \
+ "$abi_asflags($abi) -call_nonpic" \
+ { gp-hidden.s } \
+ [list \
+ "readelf --relocs gp-hidden${suff64}.rd" \
+ "readelf --syms gp-hidden.sd"] \
+ "gp-hidden-${abi}"]]
}
}
run_dump_test "reloc-1-rel"
}
if $has_newabi {
- run_dump_test "reloc-1-n32"
- if $linux_gnu {
- # Uses a linux-specific ld -m switch
- run_dump_test "reloc-1-n64"
- }
+ run_dump_test "reloc-1-n32" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "reloc-1-n64" [list [list ld $abi_ldflags(n64)]]
}
run_dump_test "reloc-2"
run_dump_test "reloc-merge-lo16"
run_dump_test "reloc-4"
run_dump_test "reloc-5"
if { $has_newabi } {
- run_ld_link_tests {
- {"reloc test 6a" "-shared"
- "-n32" "reloc-6a.s"
- {}
- "reloc-6a.so"}
- {"reloc test 6b" "tmpdir/reloc-6a.so"
- "-n32" "reloc-6b.s"
- {}
- "reloc-6b"}
- }
+ run_ld_link_tests [list \
+ [list \
+ "reloc test 6a" \
+ "-shared $abi_ldflags(n32)" \
+ "$abi_asflags(n32)" \
+ "reloc-6a.s" \
+ {} \
+ "reloc-6a.so"] \
+ [list \
+ "reloc test 6b" \
+ "$abi_ldflags(n32) tmpdir/reloc-6a.so" \
+ "$abi_asflags(n32)" \
+ "reloc-6b.s" \
+ {} \
+ "reloc-6b"]]
}
if {$has_newabi && $linux_gnu} {
run_dump_test "jaloverflow"
run_dump_test "jaloverflow-2"
if {$has_newabi} {
- run_dump_test "jalbal"
+ run_dump_test "jalbal" [list [list ld $abi_ldflags(n32)]]
}
run_dump_test "mode-change-error-1"
#
# the null symbol entry
# the .MIPS.stubs section symbol
- # _gp
# _GLOBAL_OFFSET_TABLE_
- set base_syms 4
+ set base_syms 3
foreach dynsym { 7fff 8000 fff0 10000 2fe80 } {
run_ld_link_tests \
[list [list \
set mips16_call_global_test [list \
[list "Global calls from mips16" \
- "$o32_ld_flags -T no-shared-1.ld" \
- "$o32_as_flags -mips32r2" \
+ "$abi_ldflags(o32) -T no-shared-1.ld" \
+ "$abi_asflags(o32) -mips32r2" \
{mips16-call-global-1.s mips16-call-global-2.s mips16-call-global-3.s} \
{{objdump -dr mips16-call-global.d}} \
"mips16-call-global"]]
set mips16_intermix_test [list \
[list "Intermixing mips32 and mips16 functions" \
- "$o32_ld_flags" \
- "$o32_as_flags -mips32r2" \
+ "$abi_ldflags(o32)" \
+ "$abi_asflags(o32) -mips32r2" \
{mips16-intermix-1.s mips16-intermix-2.s} \
{{objdump -t mips16-intermix.d}} \
"mips16-intermix"]]
# MIPS16 and microMIPS interlinking test.
run_dump_test "mips16-and-micromips"
+
+# Export class call relocation tests.
+set abis [concat o32 [expr {$has_newabi ? "n32 n64" : ""}]]
+foreach { abi } $abis {
+ set loadaddr [string map \
+ {o32 0x12340000 n32 0x12340000 n64 0x123456789abc0000} $abi]
+ set suff [subst \
+ [expr { [istarget *-*-irix*] \
+ ? [string map {o32 o32-irix n32 n32 n64 n64} $abi] \
+ : $abi }]]
+ run_ld_link_tests [list \
+ [list \
+ "MIPS export class call relocation test ($abi)" \
+ "$abi_ldflags($abi) -shared -Ttext $loadaddr -T export-class-call16.ld" \
+ "$abi_asflags($abi) -mips3 -KPIC" \
+ [list export-class-call16-${abi}.s export-class-call16-def.s] \
+ [list \
+ "objdump -d export-class-call16-${suff}.dd" \
+ "readelf -A export-class-call16-${abi}.gd"] \
+ "export-class-call16-${abi}.so"]]
+}
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
- _gp = ALIGN(16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN(16) + 0x7ff0);
.got : { *(.got.plt) *(.got) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.rel.plt : { *(.rel.plt) }
.rel.dyn : { *(.rel.dyn) }
. = 0x50000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0x50400;
.data : { *(.data) }
# [MIPS_GOTSYM, MIPS_SYMTABNO) covers used4...used7.
#...
- .* \(MIPS_SYMTABNO\) * 10
+ .* \(MIPS_SYMTABNO\) * 9
#...
- .* \(MIPS_GOTSYM\) * 0x6
+ .* \(MIPS_GOTSYM\) * 0x5
#pass
# used8 should come before MIPS_GOTSYM.
#...
- +4: 000405bc +36 +FUNC +GLOBAL +DEFAULT .* used8
- +5: .* _GLOBAL_OFFSET_TABLE_
- +6: 00040574 +36 +FUNC +GLOBAL +DEFAULT .* used6
- +7: 00040598 +36 +FUNC +GLOBAL +DEFAULT .* used7
- +8: 00040550 +36 +FUNC +GLOBAL +DEFAULT .* used5
- +9: 0004052c +36 +FUNC +GLOBAL +DEFAULT .* used4
+ +3: 000405bc +36 +FUNC +GLOBAL +DEFAULT .* used8
+ +4: .* _GLOBAL_OFFSET_TABLE_
+ +5: 00040574 +36 +FUNC +GLOBAL +DEFAULT .* used6
+ +6: 00040598 +36 +FUNC +GLOBAL +DEFAULT .* used7
+ +7: 00040550 +36 +FUNC +GLOBAL +DEFAULT .* used5
+ +8: 0004052c +36 +FUNC +GLOBAL +DEFAULT .* used4
#pass
#source: mode-change-error-1a.s
#source: mode-change-error-1b.s
#ld: -e 0x8000000
-#error: .*: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled.
+#error: .*: Unsupported jump between ISA modes; consider recompiling with interlinking enabled.
-#as: -mabi=n32 -EB
+#as: -march=from-abi -mabi=n32 -EB
#source: no-shared-1-o32.s
#ld: -melf32btsmipn32 -T no-shared-1.ld
#objdump: -dr -j.text -j.data -j.got
-#as: -mabi=64 -EB
+#as: -march=from-abi -mabi=64 -EB
#ld: -melf64btsmip -T no-shared-1.ld
#objdump: -dr -j.text -j.data -j.got
. = 0x60000;
.data : { *(.data) }
- _gp = ALIGN (16) + 0x7ff0;
+ HIDDEN (_gp = ALIGN (16) + 0x7ff0);
.got : { *(.got) }
}
.pdr : { *(.pdr) }
. = 0x41000;
.text : { *(.text) }
- _gp = 0x68000;
+ HIDDEN (_gp = 0x68000);
}
#...
+.*: 00068000 +0 +NOTYPE +LOCAL +DEFAULT +ABS _gp
.*: 00041018 +8 +FUNC +LOCAL +DEFAULT .* .pic.f1
.*: 00041000 +16 +FUNC +LOCAL +DEFAULT .* .pic.f2
.*: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +UND _gp_disp
-.*: 00068000 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _gp
.*: 00041050 +14 +FUNC +GLOBAL +DEFAULT +\[MIPS16\] .* f3
.*: 00041060 +24 +FUNC +GLOBAL +DEFAULT .* __start
.*: 0004103c +20 +FUNC +GLOBAL +DEFAULT .* f2
c00: 8f998010 lw t9,-32752\(gp\)
c04: 03e07821 move t7,ra
c08: 0320f809 jalr t9
- c0c: 24180007 li t8,7
+ c0c: 24180006 li t8,6
\.\.\.
.data : { *(.data) }
. = ALIGN (0x400);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
# This must be the number of GOT entries - 1, the last entry being for "bar".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 3
# This must be MIPS_GOTSYM + 1.
- 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000011 \(MIPS_SYMTABNO\) * 7
0x70000012 \(MIPS_UNREFEXTNO\) .*
# This must be the index of "bar".
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43000
0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
.*: 8f998010 lw t9,-32752\(gp\)
.*: 03e07821 move t7,ra
.*: 0320f809 jalr t9
-.*: 24180007 li t8,7
+.*: 24180006 li t8,6
\.\.\.
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +foo
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *7: 00044030 +0 +FUNC +GLOBAL +DEFAULT +UND +bar
+ *6: 00044030 +0 +FUNC +GLOBAL +DEFAULT +UND +bar
#pass
Relocation section '\.rel\.plt' at offset .* contains .*:
* Offset * Info * Type * Sym\.Value * Sym\. Name
-00081008 * 0000057f * R_MIPS_JUMP_SLOT * 00000000 * foo
+00081008 * 0000047f * R_MIPS_JUMP_SLOT * 00000000 * foo
# This must be the number of GOT entries - 1, the last entry being for "obj3".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
# This must be MIPS_GOTSYM + 1.
- 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000011 \(MIPS_SYMTABNO\) * 7
0x70000012 \(MIPS_UNREFEXTNO\) .*
# This must be the index of "obj3".
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000000 \(NULL\) * 0x0
.rld_map : { *(.rld_map) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 000a2008 +4 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +obj2
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *7: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj3
+ *6: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj3
#pass
* Offset * Info * Type * Sym\.Value * Sym\. Name
00000000 * 00000000 * R_MIPS_NONE *
000a2000 * 0000017e * R_MIPS_COPY * 000a2000 * obj1
-000a2008 * 0000047e * R_MIPS_COPY * 000a2008 * obj2
-000a1004 * 00000703 * R_MIPS_REL32 * 00000000 * obj3
+000a2008 * 0000037e * R_MIPS_COPY * 000a2008 * obj2
+000a1004 * 00000603 * R_MIPS_REL32 * 00000000 * obj3
# for "bar" and "obj2".
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
# This must be MIPS_GOTSYM + 2.
- 0x70000011 \(MIPS_SYMTABNO\) * 10
+ 0x70000011 \(MIPS_SYMTABNO\) * 9
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x8
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43030
0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
.*: 00043060 +0 +FUNC +GLOBAL +DEFAULT +\[MIPS PLT\] +UND +foo
# The index on the next line should correspond to MIPS_GOTSYM.
#...
- *8: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj2
- *9: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +bar
+ *7: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +obj2
+ *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +bar
#pass
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000011 \(MIPS_SYMTABNO\) * 13
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43028
0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
440a0: 8f998010 lw t9,-32752\(gp\)
440a4: 03e07821 move t3,ra
440a8: 0320f809 jalr t9
- 440ac: 2418000a li t8,10
+ 440ac: 24180009 li t8,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
0x0+70000005 \(MIPS_FLAGS\) * NOTPOT
0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x0+70000011 \(MIPS_SYMTABNO\) * 14
+ 0x0+70000011 \(MIPS_SYMTABNO\) * 13
0x0+70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x0+70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x0+70000013 \(MIPS_GOTSYM\) * 0x6
0x0+00000014 \(PLTREL\) * REL
0x0+00000017 \(JMPREL\) * 0x43050
0x0+00000002 \(PLTRELSZ\) * 48 \(bytes\)
440a0: df998010 ld t9,-32752\(gp\)
440a4: 03e0782d move t3,ra
440a8: 0320f809 jalr t9
- 440ac: 6418000a daddiu t8,zero,10
+ 440ac: 64180009 daddiu t8,zero,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000011 \(MIPS_SYMTABNO\) * 13
0x70000012 \(MIPS_UNREFEXTNO\) * .*
- 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x70000013 \(MIPS_GOTSYM\) * 0x6
0x00000014 \(PLTREL\) * REL
0x00000017 \(JMPREL\) * 0x43028
0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
440a0: 8f998010 lw t9,-32752\(gp\)
440a4: 03e07821 move t7,ra
440a8: 0320f809 jalr t9
- 440ac: 2418000a li t8,10
+ 440ac: 24180009 li t8,9
\.\.\.
# and the remaining symbols should have the same order as the
# GOT layout given in the *.dd dump.
#...
- *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
- *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
- *9: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
- *10: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
- *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
- *12: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
- *13: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
+ *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2
+ *7: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3
+ *8: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2
+ *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1
+ *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1
+ *11: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4
+ *12: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4
#pass
.got.plt : { *(.got.plt) }
. = 0xa0000;
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = 0xa1000;
#name: MIPS rel32 n32
#source: rel32.s
-#as: -KPIC -EB -n32
+#as: -march=from-abi -KPIC -EB -n32
#readelf: -x .text -r
#ld: -shared -melf32btsmipn32
[0-9a-f ]+R_MIPS_REL32
Hex dump of section '.text':
- 0x000002e0 00000000 00000000 00000000 00000000 ................
- 0x000002f0 000002f0 00000000 00000000 00000000 ................
- 0x00000300 00000000 00000000 00000000 00000000 ................
+ 0x000002d0 00000000 00000000 00000000 00000000 ................
+ 0x000002e0 000002e0 00000000 00000000 00000000 ................
+ 0x000002f0 00000000 00000000 00000000 00000000 ................
[0-9a-f ]+R_MIPS_REL32
Hex dump of section '.text':
+ 0x000002c0 00000000 00000000 00000000 00000000 ................
+ 0x000002d0 000002d0 00000000 00000000 00000000 ................
0x000002e0 00000000 00000000 00000000 00000000 ................
- 0x000002f0 000002f0 00000000 00000000 00000000 ................
- 0x00000300 00000000 00000000 00000000 00000000 ................
#name: MIPS rel64 n64
#source: rel64.s
-#as: -KPIC -EB -64
+#as: -march=from-abi -KPIC -EB -64
#readelf: -x .text -r
#ld: -shared -melf64btsmip
+Type3: R_MIPS_NONE
Hex dump of section '.text':
+ 0x00000430 00000000 00000000 00000000 00000000 ................
+ 0x00000440 00000000 00000440 00000000 00000000 ................
0x00000450 00000000 00000000 00000000 00000000 ................
- 0x00000460 00000000 00000460 00000000 00000000 ................
- 0x00000470 00000000 00000000 00000000 00000000 ................
#name: MIPS relax-jalr-shared n32
#source: relax-jalr.s
-#as: -KPIC -n32 -EB
+#as: -march=from-abi -KPIC -n32 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -shared -melf32btsmipn32
#name: MIPS relax-jalr n32
#source: relax-jalr.s
-#as: -KPIC -n32 -EB
+#as: -march=from-abi -KPIC -n32 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -melf32btsmipn32
#name: MIPS relax-jalr-shared n64
#source: relax-jalr.s
-#as: -KPIC -64 -EB
+#as: -march=from-abi -KPIC -64 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -shared -melf64btsmip
#name: MIPS relax-jalr n64
#source: relax-jalr.s
-#as: -KPIC -64 -EB
+#as: -march=from-abi -KPIC -64 -EB
#objdump: --prefix-addresses -d --show-raw-insn
#ld: --relax -melf64btsmip
-#source: reloc-1a.s -mabi=n32
-#source: reloc-1b.s -mabi=n32
+#source: reloc-1a.s -march=from-abi -mabi=n32 -EB
+#source: reloc-1b.s -march=from-abi -mabi=n32 -EB
#ld: -r
#readelf: --relocs
-#source: reloc-1a.s -mabi=64 -EB
-#source: reloc-1b.s -mabi=64 -EB
-#ld: -melf64btsmip -r
+#source: reloc-1a.s -march=from-abi -mabi=64 -EB
+#source: reloc-1b.s -march=from-abi -mabi=64 -EB
+#ld: -r
#readelf: --relocs
Relocation section '\.rela\.text' .*
. = 0x208000;
.text : { *(.text) }
. = 0x400000;
- _gp = 0x401234;
+ HIDDEN (_gp = 0x401234);
.sdata : { *(.sdata) }
/DISCARD/ : { *(*) }
}
.data : { *(.data) }
. = ALIGN (0x400);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
}
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
/DISCARD/ : { *(.reginfo) }
#name: MIPS textrel-1
#source: textrel-1.s
-#as: -EB -n32
+#as: -march=from-abi -EB -n32
#ld: -shared -melf32btsmipn32
#readelf: -d
.text : { *(.text) }
. = ALIGN (0x10000);
- _gp = . + 0x7ff0;
+ HIDDEN (_gp = . + 0x7ff0);
.got : { *(.got) }
. = ALIGN (0x400);
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-0013f830 R_MIPS_TLS_DTPMOD32 \*ABS\*
-0014948c R_MIPS_TLS_DTPMOD32 \*ABS\*
-0013f83c R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0013f840 R_MIPS_TLS_DTPREL32 tlsvar_gd
-00149498 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0014949c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0013f838 R_MIPS_TLS_TPREL32 tlsvar_ie
-00149494 R_MIPS_TLS_TPREL32 tlsvar_ie
-00143e38 R_MIPS_REL32 sym_1_9526
+0013f820 R_MIPS_TLS_DTPMOD32 \*ABS\*
+0014947c R_MIPS_TLS_DTPMOD32 \*ABS\*
+0013f82c R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0013f830 R_MIPS_TLS_DTPREL32 tlsvar_gd
+00149488 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0014948c R_MIPS_TLS_DTPREL32 tlsvar_gd
+0013f828 R_MIPS_TLS_TPREL32 tlsvar_ie
+00149484 R_MIPS_TLS_TPREL32 tlsvar_ie
+00143e28 R_MIPS_REL32 sym_1_9526
#...
-00139ab8 R_MIPS_REL32 sym_2_8654
+00139aa8 R_MIPS_REL32 sym_2_8654
Contents of section .got:
- 122360 00000000 80000000 000d7f98 000d65f4 .*
- 122370 000d1fa4 000d6010 000d5a48 000d19c0 .*
+ 122350 00000000 80000000 000d7f88 000d65e4 .*
+ 122360 000d1f94 000d6000 000d5a38 000d19b0 .*
#...
- 135be0 000cf204 000e0e48 00000000 80000000 .*
- 135bf0 00000000 00000000 00000000 00000000 .*
+ 135bd0 000cf1f4 000e0e38 00000000 80000000 .*
+ 135be0 00000000 00000000 00000000 00000000 .*
#...
+ 13f810 00000000 00000000 00000000 00000000 .*
13f820 00000000 00000000 00000000 00000000 .*
- 13f830 00000000 00000000 00000000 00000000 .*
- 13f840 00000000 00000000 80000000 00000000 .*
+ 13f830 00000000 00000000 80000000 00000000 .*
#...
+ 149440 00000000 00000000 00000000 00000000 .*
149450 00000000 00000000 00000000 00000000 .*
149460 00000000 00000000 00000000 00000000 .*
149470 00000000 00000000 00000000 00000000 .*
149480 00000000 00000000 00000000 00000000 .*
- 149490 00000000 00000000 00000000 00000000 .*
#pass
0x00000004 \(HASH\) 0x1c4
0x00000005 \(STRTAB\).*
0x00000006 \(SYMTAB\).*
- 0x0000000a \(STRSZ\) 220091 \(bytes\)
+ 0x0000000a \(STRSZ\) 220087 \(bytes\)
0x0000000b \(SYMENT\) 16 \(bytes\)
- 0x00000003 \(PLTGOT\) 0x122360
- 0x00000011 \(REL\) 0xa7978
+ 0x00000003 \(PLTGOT\) 0x122350
+ 0x00000011 \(REL\) 0xa7960
0x00000012 \(RELSZ\) 160072 \(bytes\)
0x00000013 \(RELENT\) 8 \(bytes\)
0x70000001 \(MIPS_RLD_VERSION\) 1
0x70000005 \(MIPS_FLAGS\) NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) 0x0
0x7000000a \(MIPS_LOCAL_GOTNO\) 2
- 0x70000011 \(MIPS_SYMTABNO\) 20013
+ 0x70000011 \(MIPS_SYMTABNO\) 20012
0x70000012 \(MIPS_UNREFEXTNO\) 10
- 0x70000013 \(MIPS_GOTSYM\) 0xd
+ 0x70000013 \(MIPS_GOTSYM\) 0xc
0x0000001e \(FLAGS\) STATIC_TLS
0x00000000 \(NULL\) 0x0
[0-9a-f ]+R_MIPS_TLS_DTPREL 00000000 tlsvar_gd
[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004 tlsvar_ie
[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004 tlsvar_ie
-[0-9a-f ]+R_MIPS_REL32 000d7f98 sym_1_9526
-[0-9a-f ]+R_MIPS_REL32 000d65f4 sym_1_7885
+[0-9a-f ]+R_MIPS_REL32 000d7f88 sym_1_9526
+[0-9a-f ]+R_MIPS_REL32 000d65e4 sym_1_7885
#...
-[0-9a-f ]+R_MIPS_REL32 000cf204 sym_1_0465
-[0-9a-f ]+R_MIPS_REL32 000e0e48 sym_2_8654
+[0-9a-f ]+R_MIPS_REL32 000cf1f4 sym_1_0465
+[0-9a-f ]+R_MIPS_REL32 000e0e38 sym_2_8654
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b30 addiu gp,gp,31536
+ .*: 279c7b50 addiu gp,gp,31568
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 004004cc 00000001 .........@......
+ 10000020 00000000 80000000 004004ac 00000001 .........@......
10000030 00000000 00000000 00000000 00000000 ................
10000040 00000000 00000000 00000000 ............
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b30 addiu gp,gp,31536
+ .*: 279c7b50 addiu gp,gp,31568
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 004004cc 00000000 .*
+ 10000020 00000000 80000000 004004ac 00000000 .*
10000030 00000000 00000000 00000000 00000000 .*
10000040 00000001 00000000 00000000 00000000 .*
10000050 00000000 00000000 .*
.* <other>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7bf0 addiu gp,gp,31728
+ .*: 279c7c10 addiu gp,gp,31760
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7b40 addiu gp,gp,31552
+ .*: 279c7b60 addiu gp,gp,31584
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 0040057c 00000000 .*
+ 10000020 00000000 80000000 0040055c 00000000 .*
10000030 00000000 00000000 00000000 00000000 .*
10000040 00000001 00000000 00000000 00000000 .*
10000050 00000000 00000000 .*
.* <__start>:
.*: 3c1c0fc0 lui gp,0xfc0
- .*: 279c7ba0 addiu gp,gp,31648
+ .*: 279c7bc0 addiu gp,gp,31680
.*: 0399e021 addu gp,gp,t9
.*: 27bdfff0 addiu sp,sp,-16
.*: afbe0008 sw s8,8\(sp\)
Contents of section .got:
- 10000020 00000000 80000000 0040051c 00000001 ................
+ 10000020 00000000 80000000 004004fc 00000001 ................
10000030 00000000 00000000 00000000 00000000 ................
10000040 00000000 00000000 00000000 ............
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-00040520 R_MIPS_TLS_DTPMOD32 \*ABS\*
-00040528 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0004052c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0004051c R_MIPS_TLS_TPREL32 tlsvar_ie
+00040500 R_MIPS_TLS_DTPMOD32 \*ABS\*
+00040508 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0004050c R_MIPS_TLS_DTPREL32 tlsvar_gd
+000404fc R_MIPS_TLS_TPREL32 tlsvar_ie
Contents of section .got:
- 40510 00000000 80000000 000004e0 00000000 ................
- 40520 00000000 00000000 00000000 00000000 ................
+ 404f0 00000000 80000000 000004c0 00000000 ................
+ 40500 00000000 00000000 00000000 00000000 ................
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
00000000 R_MIPS_NONE \*ABS\*
-00040480 R_MIPS_TLS_DTPMOD32 \*ABS\*
-00040488 R_MIPS_TLS_DTPMOD32 tlsvar_gd
-0004048c R_MIPS_TLS_DTPREL32 tlsvar_gd
-0004047c R_MIPS_TLS_TPREL32 tlsvar_ie
+00040460 R_MIPS_TLS_DTPMOD32 \*ABS\*
+00040468 R_MIPS_TLS_DTPMOD32 tlsvar_gd
+0004046c R_MIPS_TLS_DTPREL32 tlsvar_gd
+0004045c R_MIPS_TLS_TPREL32 tlsvar_ie
Contents of section .got:
- 40470 00000000 80000000 00000440 00000000 ................
- 40480 00000000 00000000 00000000 00000000 ................
+ 40450 00000000 80000000 00000420 00000000 ................
+ 40460 00000000 00000000 00000000 00000000 ................
--- /dev/null
+# Expect script for symbol export classes, PowerPC variation.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-Linux targets; feel free to include your favorite one
+# if you like.
+if { ![istarget powerpc*-*-linux*] } {
+ return
+}
+
+proc supports_ppc64 { } {
+ global ld
+
+ catch "exec $ld --help | grep emulations" tmp
+ if [string match "*elf64ppc*" $tmp] then {
+ return 1
+ } else {
+ return 0
+ }
+}
+
+proc powerpc_export_class_test { abi emul } {
+
+ set testname "PowerPC $abi symbol export class test"
+
+ set AFLAGS "-a$abi -be"
+ set LDFLAGS "-m$emul"
+
+ # Build an auxiliary shared object with conflicting versioned symbol
+ # definitions.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "$LDFLAGS -shared -version-script ../ld-elf/export-class-lib.ver" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-lib.s } \
+ {} \
+ "powerpc-$abi-export-class-lib.so" \
+ ] \
+ ]
+
+ # Build a static object that pulls symbol definitions. It has to come
+ # first before the auxiliary shared object and other static objects on
+ # the linker's command line and hence we need to build it separately.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "$LDFLAGS -r" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-ref.s } \
+ {} \
+ "powerpc-$abi-export-class-ref-r.o" \
+ ] \
+ ]
+
+ # Build static objects that satisfy symbol dependencies and preempt
+ # shared-object symbol definitions, and link all the objects built into
+ # the final shared object. The command-line order of objects linked is
+ # important to make sure the linker correctly preempts versioned symbols
+ # from the auxiliary shared object and is as follows: ref, lib, dep, def.
+ # Get a dump to make sure symbol dependencies are resolved internally.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "$LDFLAGS -shared -Tdata=0x12340000 tmpdir/powerpc-$abi-export-class-ref-r.o tmpdir/powerpc-$abi-export-class-lib.so" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-dep.s ../ld-elf/export-class-def.s } \
+ [list \
+ [list readelf -r powerpc-$abi-export-class.rd] \
+ [list readelf "-x .data" powerpc-$abi-export-class.xd] \
+ ] \
+ "powerpc-$abi-export-class.so" \
+ ] \
+ ]
+}
+
+if { [supports_ppc64] } {
+ set abis { 32 elf32ppclinux 64 elf64ppc }
+} else {
+ set abis { 32 elf32ppclinux }
+}
+foreach { abi emul } $abis {
+ powerpc_export_class_test $abi $emul
+}
--- /dev/null
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name * \+ * Addend
+12340000 00000016 R_PPC_RELATIVE * 123400a0
+12340010 00000016 R_PPC_RELATIVE * 123400a0
+12340020 00000016 R_PPC_RELATIVE * 123400a0
+12340040 00000016 R_PPC_RELATIVE * 123400a0
+12340050 00000016 R_PPC_RELATIVE * 123400a0
+12340060 00000016 R_PPC_RELATIVE * 123400a0
+12340070 00000016 R_PPC_RELATIVE * 123400a0
+12340080 00000016 R_PPC_RELATIVE * 123400a0
+12340090 00000016 R_PPC_RELATIVE * 123400a0
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 00000000 00000000 00000000 00000000 .*
+ 0x12340010 00000000 00000000 00000000 00000000 .*
+ 0x12340020 00000000 00000000 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 00000000 00000000 00000000 00000000 .*
+ 0x12340050 00000000 00000000 00000000 00000000 .*
+ 0x12340060 00000000 00000000 00000000 00000000 .*
+ 0x12340070 00000000 00000000 00000000 00000000 .*
+ 0x12340080 00000000 00000000 00000000 00000000 .*
+ 0x12340090 00000000 00000000 00000000 00000000 .*
--- /dev/null
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name * \+ * Addend
+000012340000 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340010 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340020 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340040 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340050 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340060 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340070 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340080 000000000016 R_PPC64_RELATIVE * 123400a0
+000012340090 000000000016 R_PPC64_RELATIVE * 123400a0
--- /dev/null
+Hex dump of section '\.data':
+ 0x12340000 00000000 123400a0 00000000 00000000 .*
+ 0x12340010 00000000 123400a0 00000000 00000000 .*
+ 0x12340020 00000000 123400a0 00000000 00000000 .*
+ 0x12340030 00000000 00000000 00000000 00000000 .*
+ 0x12340040 00000000 123400a0 00000000 00000000 .*
+ 0x12340050 00000000 123400a0 00000000 00000000 .*
+ 0x12340060 00000000 123400a0 00000000 00000000 .*
+ 0x12340070 00000000 123400a0 00000000 00000000 .*
+ 0x12340080 00000000 123400a0 00000000 00000000 .*
+ 0x12340090 00000000 123400a0 00000000 00000000 .*
--- /dev/null
+ .text
+
+ .hidden foo_hidden
+ .globl foo_hidden
+ .type foo_hidden, @function
+foo_hidden:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_hidden, . - foo_hidden
--- /dev/null
+.*: +file format .*vax.*
+
+Disassembly of section \.plt:
+
+00001000 <foo_local@plt-0xc>:
+ 1000: dd ef 76 20 pushl 307c <_GLOBAL_OFFSET_TABLE_\+0x4>
+ 1004: 00 00
+ 1006: 17 ff 74 20 jmp \*3080 <_GLOBAL_OFFSET_TABLE_\+0x8>
+ 100a: 00 00
+
+0000100c <foo_local@plt>:
+ 100c: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+ 100e: 16 ef ec ff jsb 1000 <foo_local@plt-0xc>
+ 1012: ff ff
+ 1014: 00 00 00 00 \.long 0x00000000
+
+00001018 <foo_extern@plt>:
+ 1018: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+ 101a: 16 ef e0 ff jsb 1000 <foo_local@plt-0xc>
+ 101e: ff ff
+ 1020: 0c 00 00 00 \.long 0x0000000c
+
+00001024 <foo_rehidden@plt>:
+ 1024: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+ 1026: 16 ef d4 ff jsb 1000 <foo_local@plt-0xc>
+ 102a: ff ff
+ 102c: 18 00 00 00 \.long 0x00000018
+
+00001030 <foo_global@plt>:
+ 1030: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+ 1032: 16 ef c8 ff jsb 1000 <foo_local@plt-0xc>
+ 1036: ff ff
+ 1038: 24 00 00 00 \.long 0x00000024
+
+Disassembly of section \.text:
+
+00002000 <foo_extern>:
+ 2000: 00 00 \.word 0x0000 # Entry mask: < >
+ 2002: fb 00 ff 7f calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ 2006: 10 00 00
+ 2009: fb 00 ff 80 calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
+ 200d: 10 00 00
+ 2010: fb 00 ff 6d calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2014: 10 00 00
+ 2017: fb 00 ef 2e calls \$0x0,204c <foo_hidden>
+ 201b: 00 00 00
+ 201e: fb 00 ff 67 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
+ 2022: 10 00 00
+ 2025: 04 ret
+
+00002026 <foo_local>:
+ 2026: 00 00 \.word 0x0000 # Entry mask: < >
+ 2028: fb 00 ff 59 calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ 202c: 10 00 00
+ 202f: fb 00 ff 5a calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
+ 2033: 10 00 00
+ 2036: fb 00 ff 47 calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 203a: 10 00 00
+ 203d: fb 00 ef 08 calls \$0x0,204c <foo_hidden>
+ 2041: 00 00 00
+ 2044: fb 00 ff 41 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
+ 2048: 10 00 00
+ 204b: 04 ret
+
+0000204c <foo_hidden>:
+ 204c: 00 00 \.word 0x0000 # Entry mask: < >
+ 204e: fb 00 ff 33 calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ 2052: 10 00 00
+ 2055: fb 00 ff 34 calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
+ 2059: 10 00 00
+ 205c: fb 00 ff 21 calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2060: 10 00 00
+ 2063: fb 00 ef e2 calls \$0x0,204c <foo_hidden>
+ 2067: ff ff ff
+ 206a: fb 00 ff 1b calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
+ 206e: 10 00 00
+ 2071: 04 ret
+
+00002072 <foo_rehidden>:
+ 2072: 00 00 \.word 0x0000 # Entry mask: < >
+ 2074: fb 00 ff 0d calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ 2078: 10 00 00
+ 207b: fb 00 ff 0e calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
+ 207f: 10 00 00
+ 2082: fb 00 ff fb calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2086: 0f 00 00
+ 2089: fb 00 ef bc calls \$0x0,204c <foo_hidden>
+ 208d: ff ff ff
+ 2090: fb 00 ff f5 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
+ 2094: 0f 00 00
+ 2097: 04 ret
--- /dev/null
+SECTIONS
+{
+ . = 0;
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rela.plt : { *(.rela.plt) }
+
+ . = 0x1000;
+ .plt : { *(.plt) }
+
+ . = 0x2000;
+ .text : { *(.text) }
+
+ . = 0x3000;
+ .dynamic : { *(.dynamic) }
+ .got : { *(.got.plt) }
+}
--- /dev/null
+ .text
+
+ .globl foo_extern
+ .type foo_extern, @function
+foo_extern:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_extern, . - foo_extern
+
+ .globl foo_local
+ .type foo_local, @function
+foo_local:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_local, . - foo_local
+
+ .hidden foo_hidden
+ .globl foo_hidden
+ .type foo_hidden, @function
+foo_hidden:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_hidden, . - foo_hidden
+
+ .globl foo_rehidden
+ .type foo_rehidden, @function
+foo_rehidden:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_rehidden, . - foo_rehidden
--- /dev/null
+ .text
+
+ .hidden foo_rehidden
+ .globl foo_rehidden
+ .type foo_rehidden, @function
+foo_rehidden:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_rehidden, . - foo_rehidden
--- /dev/null
+.*: +file format .*vax.*
+
+Disassembly of section \.plt:
+
+00001000 <foo_extern@plt-0xc>:
+ 1000: dd ef 86 20 pushl 308c <_GLOBAL_OFFSET_TABLE_\+0x4>
+ 1004: 00 00
+ 1006: 17 ff 84 20 jmp \*3090 <_GLOBAL_OFFSET_TABLE_\+0x8>
+ 100a: 00 00
+
+0000100c <foo_extern@plt>:
+ 100c: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+ 100e: 16 ef ec ff jsb 1000 <foo_extern@plt-0xc>
+ 1012: ff ff
+ 1014: 00 00 00 00 \.long 0x00000000
+
+Disassembly of section \.text:
+
+00002000 <foo_hidden>:
+ 2000: 00 00 \.word 0x0000 # Entry mask: < >
+ 2002: fb 00 ff 8b calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2006: 10 00 00
+ 2009: fb 00 ef 3c calls \$0x0,204c <foo_global>
+ 200d: 00 00 00
+ 2010: fb 00 ef 5b calls \$0x0,2072 <foo_local>
+ 2014: 00 00 00
+ 2017: fb 00 ef e2 calls \$0x0,2000 <foo_hidden>
+ 201b: ff ff ff
+ 201e: fb 00 ef 01 calls \$0x0,2026 <foo_rehidden>
+ 2022: 00 00 00
+ 2025: 04 ret
+
+00002026 <foo_rehidden>:
+ 2026: 00 00 \.word 0x0000 # Entry mask: < >
+ 2028: fb 00 ff 65 calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 202c: 10 00 00
+ 202f: fb 00 ef 16 calls \$0x0,204c <foo_global>
+ 2033: 00 00 00
+ 2036: fb 00 ef 35 calls \$0x0,2072 <foo_local>
+ 203a: 00 00 00
+ 203d: fb 00 ef bc calls \$0x0,2000 <foo_hidden>
+ 2041: ff ff ff
+ 2044: fb 00 ef db calls \$0x0,2026 <foo_rehidden>
+ 2048: ff ff ff
+ 204b: 04 ret
+
+0000204c <foo_global>:
+ 204c: 00 00 \.word 0x0000 # Entry mask: < >
+ 204e: fb 00 ff 3f calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2052: 10 00 00
+ 2055: fb 00 ef f0 calls \$0x0,204c <foo_global>
+ 2059: ff ff ff
+ 205c: fb 00 ef 0f calls \$0x0,2072 <foo_local>
+ 2060: 00 00 00
+ 2063: fb 00 ef 96 calls \$0x0,2000 <foo_hidden>
+ 2067: ff ff ff
+ 206a: fb 00 ef b5 calls \$0x0,2026 <foo_rehidden>
+ 206e: ff ff ff
+ 2071: 04 ret
+
+00002072 <foo_local>:
+ 2072: 00 00 \.word 0x0000 # Entry mask: < >
+ 2074: fb 00 ff 19 calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
+ 2078: 10 00 00
+ 207b: fb 00 ef ca calls \$0x0,204c <foo_global>
+ 207f: ff ff ff
+ 2082: fb 00 ef e9 calls \$0x0,2072 <foo_local>
+ 2086: ff ff ff
+ 2089: fb 00 ef 70 calls \$0x0,2000 <foo_hidden>
+ 208d: ff ff ff
+ 2090: fb 00 ef 8f calls \$0x0,2026 <foo_rehidden>
+ 2094: ff ff ff
+ 2097: 04 ret
--- /dev/null
+ENTRY (foo_global)
+SECTIONS
+{
+ . = 0;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .rela.plt : { *(.rela.plt) }
+
+ . = 0x1000;
+ .plt : { *(.plt) }
+
+ . = 0x2000;
+ .text : { *(.text) }
+
+ . = 0x3000;
+ .dynamic : { *(.dynamic) }
+ .got : { *(.got.plt) }
+};
+VERSION
+{
+ {
+ global:
+ foo_extern;
+ foo_global;
+ foo_hidden;
+ foo_rehidden;
+ local:
+ foo_local;
+ };
+}
--- /dev/null
+ .text
+
+ .globl foo_global
+ .type foo_global, @function
+foo_global:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_global, . - foo_global
+
+ .globl foo_local
+ .type foo_local, @function
+foo_local:
+ .word 0
+ calls $0, foo_extern
+ calls $0, foo_global
+ calls $0, foo_local
+ calls $0, foo_hidden
+ calls $0, foo_rehidden
+ ret
+ .size foo_local, . - foo_local
--- /dev/null
+# Expect script for VAX ELF linker tests
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget vax-*-*] || ![is_elf_format] } {
+ return
+}
+
+run_ld_link_tests [list \
+ [list "PLT test (shared library)" \
+ "-shared -T plt-local-lib.ld" \
+ "-k" \
+ { plt-local-lib.s } \
+ { { objdump -d plt-local-lib.dd } } \
+ "plt-local-lib.so"] \
+ [list "PLT test (object 1)" \
+ "-r" \
+ "-k" \
+ { plt-local-hidden-pic.s } \
+ {} \
+ "plt-local-hidden-pic-r.o"] \
+ [list "PLT test (object 2)" \
+ "-r" \
+ "-k" \
+ { plt-local-rehidden-pic.s } \
+ {} \
+ "plt-local-rehidden-pic-r.o"] \
+ [list "PLT test (executable)" \
+ "-T plt-local.ld tmpdir/plt-local-hidden-pic-r.o tmpdir/plt-local-rehidden-pic-r.o tmpdir/plt-local-lib.so" \
+ "" \
+ { plt-local.s } \
+ { { objdump -d plt-local.dd } } \
+ "plt-local"]]
--- /dev/null
+# Expect script for symbol export classes, x86-64 variation.
+#
+# Copyright 2012 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Maciej W. Rozycki <macro@codesourcery.com>
+#
+
+# Exclude non-Linux targets; feel free to include your favorite one
+# if you like.
+if { ![istarget x86_64*-*-linux*] } {
+ return
+}
+
+proc x86_64_export_class_test { abi flag emul } {
+
+ set testname "x86-64 $abi symbol export class test"
+
+ set dump [string map {32 ../ld-i386/i386 x32 x86-64-x32 64 x86-64-64} $abi]
+
+ set AFLAGS "$flag"
+ set LDFLAGS "-m$emul"
+
+ # Build an auxiliary shared object with conflicting versioned symbol
+ # definitions.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (auxiliary shared object)" \
+ "$LDFLAGS -shared -version-script ../ld-elf/export-class-lib.ver" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-lib.s } \
+ {} \
+ "x86-64-$abi-export-class-lib.so" \
+ ] \
+ ]
+
+ # Build a static object that pulls symbol definitions. It has to come
+ # first before the auxiliary shared object and other static objects on
+ # the linker's command line and hence we need to build it separately.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (initial static object)" \
+ "$LDFLAGS -r" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-ref.s } \
+ {} \
+ "x86-64-$abi-export-class-ref-r.o" \
+ ] \
+ ]
+
+ # Build static objects that satisfy symbol dependencies and preempt
+ # shared-object symbol definitions, and link all the objects built into
+ # the final shared object. The command-line order of objects linked is
+ # important to make sure the linker correctly preempts versioned symbols
+ # from the auxiliary shared object and is as follows: ref, lib, dep, def.
+ # Get a dump to make sure symbol dependencies are resolved internally.
+ run_ld_link_tests [list \
+ [list \
+ "$testname (final shared object)" \
+ "$LDFLAGS -shared -Tdata=0x12340000 tmpdir/x86-64-$abi-export-class-ref-r.o tmpdir/x86-64-$abi-export-class-lib.so" \
+ "$AFLAGS" \
+ { ../ld-elf/export-class-dep.s ../ld-elf/export-class-def.s } \
+ [list \
+ [list readelf -r $dump-export-class.rd] \
+ [list readelf "-x .data" ../ld-i386/i386-export-class.xd] \
+ ] \
+ "x86-64-$abi-export-class.so" \
+ ] \
+ ]
+}
+
+set abis { 32 --32 elf_i386 x32 --x32 elf32_x86_64 64 --64 elf_x86_64 }
+foreach { abi flag emul } $abis {
+ x86_64_export_class_test $abi $flag $emul
+}
--- /dev/null
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name * \+ * Addend
+000012340010 000000000008 R_X86_64_RELATIVE 123400a0
+000012340020 000000000008 R_X86_64_RELATIVE 123400a0
+000012340060 000000000008 R_X86_64_RELATIVE 123400a0
+000012340070 000000000008 R_X86_64_RELATIVE 123400a0
+000012340080 000000000008 R_X86_64_RELATIVE 123400a0
+000012340090 000000000008 R_X86_64_RELATIVE 123400a0
+000012340000 [0-9a-f]+00000001 R_X86_64_64 00000000123400a0 protected_baz \+ 0
+000012340040 [0-9a-f]+00000001 R_X86_64_64 00000000123400a0 protected_foo \+ 0
+000012340050 [0-9a-f]+00000001 R_X86_64_64 00000000123400a0 protected_bar \+ 0
--- /dev/null
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
+ * Offset * Info * Type * Sym\. *Value * Sym\. * Name * \+ * Addend
+12340010 00000008 R_X86_64_RELATIVE 123400a0
+12340020 00000008 R_X86_64_RELATIVE 123400a0
+12340060 00000008 R_X86_64_RELATIVE 123400a0
+12340070 00000008 R_X86_64_RELATIVE 123400a0
+12340080 00000008 R_X86_64_RELATIVE 123400a0
+12340090 00000008 R_X86_64_RELATIVE 123400a0
+12340000 [0-9a-f]+0a R_X86_64_32 123400a0 protected_baz \+ 0
+12340040 [0-9a-f]+0a R_X86_64_32 123400a0 protected_foo \+ 0
+12340050 [0-9a-f]+0a R_X86_64_32 123400a0 protected_bar \+ 0
set state [remote_exec host $CC --version]
set tmp "[lindex $state 1]\n"
# Look for (eg) 4.6.1 in the version output.
- regexp " .* (\[1-9\])\\.(\[0-9\])\\.\[0-9\]* .*" "$tmp" fred maj min
+ set ver_re "\[^\\.0-9\]+(\[1-9\]\[0-9\]*)\\.(\[0-9\]+)(?:\\.\[0-9\]+)?"
+ regexp $ver_re $tmp fred maj min
verbose "gcc version: $tmp"
+ if { ![info exists maj] || ![info exists min] } then {
+ perror "can't decipher gcc version number, fix the framework!"
+ return 0
+ }
verbose "major gcc version is $maj, want at least $major"
if { $maj == $major } then {
verbose "minor gcc version is $min, want at least $minor"
- return [expr $min >= $minor ]
+ return [expr $min >= $minor]
} else {
- return [expr $maj > $major ]
+ return [expr $maj > $major]
}
}
return $flags
}
-# run_dump_test FILE
+# run_dump_test FILE (optional:) EXTRA_OPTIONS
# Copied from gas testsuite, tweaked and further extended.
#
# Assemble a .s file, then run some utility on it and check the output.
# list ends with the first line that doesn't match the above syntax
# (hmm, not great for error detection).
#
+# The optional EXTRA_OPTIONS argument to `run_dump_test' is a list of
+# two-element lists. The first element of each is an option name, and
+# the second additional arguments to be added on to the end of the
+# option list as given in FILE.d. (If omitted, no additional options
+# are added.)
+#
# The interesting options are:
#
# name: TEST-NAME
# More than one "source" directive can be given, which is useful
# when testing linking.
#
+# dump: DUMP
+# Match against DUMP.d. If omitted, this defaults to FILE.d. This
+# is useful if several .d files differ by options only. Options are
+# always read from FILE.d.
+#
# xfail: TARGET
# The test is expected to fail on TARGET. This may occur more than
# once.
# regexps in FILE.d. `regexp_diff' is defined in binutils-common.exp;
# see further comments there.
#
-proc run_dump_test { name } {
+proc run_dump_test { name {extra_options {}} } {
global subdir srcdir
global OBJDUMP NM AS OBJCOPY READELF LD
global OBJDUMPFLAGS NMFLAGS ASFLAGS OBJCOPYFLAGS READELFFLAGS LDFLAGS
set opts(name) {}
set opts(PROG) {}
set opts(source) {}
+ set opts(dump) {}
set opts(error) {}
set opts(warning) {}
set opts(objcopy_linked_file) {}
}
}
}
+
+ foreach i $extra_options {
+ set opt_name [lindex $i 0]
+ set opt_val [lindex $i 1]
+ if ![info exists opts($opt_name)] {
+ perror "unknown option $opt_name given in extra_opts"
+ unresolved $subdir/$name
+ return
+ }
+ # Add extra option to end of existing option, adding space
+ # if necessary.
+ if { ![regexp "warning|error" $opt_name]
+ && [string length $opts($opt_name)] } {
+ append opts($opt_name) " "
+ }
+ append opts($opt_name) $opt_val
+ }
+
foreach opt { as ld } {
regsub {\[big_or_little_endian\]} $opts($opt) \
[big_or_little_endian] opts($opt)
}
}
+ if { $opts(dump) == "" } {
+ set dfile ${file}.d
+ } else {
+ set dfile $srcdir/$subdir/$opts(dump)
+ }
+
# Time to setup xfailures.
foreach targ $opts(xfail) {
setup_xfail $targ
}
if { $verbose > 2 } then { verbose "output is [file_contents $dumpfile]" 3 }
- if { [regexp_diff $dumpfile "${file}.d"] } then {
+ if { [regexp_diff $dumpfile "${dfile}"] } then {
fail $testname
if { $verbose == 2 } then { verbose "output is [file_contents $dumpfile]" 2 }
return
+2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
+ macros, use local variables for info struct member accesses,
+ update the type of the variable used to hold the instruction
+ word.
+ (print_insn_mips, print_mips16_insn_arg): Likewise.
+ (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
+ local variables for info struct member accesses.
+ (print_insn_micromips): Add GET_OP_S local macro.
+ (_print_insn_mips): Update the type of the variable used to hold
+ the instruction word.
+
+2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (micromips_opcodes): Update comment.
+ * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
+ instructions for IOCT as appropriate.
+ * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
+ opcode_is_member.
+ * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
+ the result of a check for the -Wno-missing-field-initializers
+ GCC option.
+ * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
+ (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
+ compilation.
+ (mips16-opc.lo): Likewise.
+ (micromips-opc.lo): Likewise.
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+ * Makefile.in: Regenerate.
+
2012-08-01 Alan Modra <amodra@gmail.com>
* h8300-dis.c: Fix printf arg warnings.
WARN_CFLAGS = @WARN_CFLAGS@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
AM_CFLAGS = $(WARN_CFLAGS)
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
$(top_srcdir)/../config/override.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
+ $(top_srcdir)/../config/warnings.m4 \
$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.in
NM = @NM@
NMEDIT = @NMEDIT@
NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+micromips-opc.lo: micromips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
m4_include([../config/override.m4])
m4_include([../config/po.m4])
m4_include([../config/progtest.m4])
+m4_include([../config/warnings.m4])
m4_include([../libtool.m4])
m4_include([../ltoptions.m4])
m4_include([../ltsugar.m4])
MAINT
MAINTAINER_MODE_FALSE
MAINTAINER_MODE_TRUE
+NO_WMISSING_FIELD_INITIALIZERS
NO_WERROR
WARN_CFLAGS
OTOOL64
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11137 "configure"
+#line 11138 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11243 "configure"
+#line 11244 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
+NO_WMISSING_FIELD_INITIALIZERS=
+save_CFLAGS="$CFLAGS"
+for real_option in -Wno-missing-field-initializers; do
+ # Do the check with the no- prefix removed since gcc silently
+ # accepts any -Wno-* option on purpose
+ case $real_option in
+ -Wno-*) option=-W`expr x$real_option : 'x-Wno-\(.*\)'` ;;
+ *) option=$real_option ;;
+ esac
+ as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh`
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5
+$as_echo_n "checking whether $CC supports $option... " >&6; }
+if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ CFLAGS="$option"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ eval "$as_acx_Woption=yes"
+else
+ eval "$as_acx_Woption=no"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+eval ac_res=\$$as_acx_Woption
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+ if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then :
+ NO_WMISSING_FIELD_INITIALIZERS="$NO_WMISSING_FIELD_INITIALIZERS${NO_WMISSING_FIELD_INITIALIZERS:+ }$real_option"
+fi
+ done
+CFLAGS="$save_CFLAGS"
+
ac_config_headers="$ac_config_headers config.h:config.in"
esac])dnl
AM_BINUTILS_WARNINGS
+ACX_PROG_CC_WARNING_OPTS([-Wno-missing-field-initializers],
+ [NO_WMISSING_FIELD_INITIALIZERS])
AC_CONFIG_HEADERS(config.h:config.in)
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
static void
print_insn_args (const char *d,
- register unsigned long int l,
+ int l,
bfd_vma pc,
struct disassemble_info *info,
const struct mips_opcode *opp)
{
- int op, delta;
+ const fprintf_ftype infprintf = info->fprintf_func;
unsigned int lsb, msb, msbd;
+ void *is = info->stream;
+ int op;
lsb = 0;
+#define GET_OP(insn, field) \
+ (((insn) >> OP_SH_##field) & OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
+ - ((OP_MASK_##field >> 1) + 1))
for (; *d != '\0'; d++)
{
switch (*d)
case ')':
case '[':
case ']':
- (*info->fprintf_func) (info->stream, "%c", *d);
+ infprintf (is, "%c", *d);
break;
case '+':
{
case '\0':
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, incomplete extension sequence (+)"));
+ infprintf (is,
+ _("# internal error, "
+ "incomplete extension sequence (+)"));
return;
case 'A':
- lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT);
+ infprintf (is, "0x%x", lsb);
break;
case 'B':
- msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB);
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI1) & OP_MASK_UDI1);
+ infprintf (is, "0x%x", GET_OP (l, UDI1));
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI2) & OP_MASK_UDI2);
+ infprintf (is, "0x%x", GET_OP (l, UDI2));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI3) & OP_MASK_UDI3);
+ infprintf (is, "0x%x", GET_OP (l, UDI3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI4) & OP_MASK_UDI4);
+ infprintf (is, "0x%x", GET_OP (l, UDI4));
break;
case 'C':
case 'H':
- msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD);
+ infprintf (is, "0x%x", msbd + 1);
break;
case 'D':
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RD);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mtcN (et al.), to be
printed textually if known. If not known, print both
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'E':
- lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
+ lsb = GET_OP (l, SHAMT) + 32;
+ infprintf (is, "0x%x", lsb);
break;
case 'F':
- msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
+ msb = GET_OP (l, INSMSB) + 32;
+ infprintf (is, "0x%x", msb - lsb + 1);
break;
case 'G':
- msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
+ msbd = GET_OP (l, EXTMSBD) + 32;
+ infprintf (is, "0x%x", msbd + 1);
break;
case 't': /* Coprocessor 0 reg name */
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RT) &
- OP_MASK_RT]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
break;
case 'T': /* Coprocessor 0 reg name */
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
- cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+ cp0reg = GET_OP (l, RT);
+ sel = GET_OP (l, SEL);
/* CP0 register including 'sel' code for mftc0, to be
printed textually if known. If not known, print both
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
+ infprintf (is, "%s", n->name);
else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+ infprintf (is, "$%d,%d", cp0reg, sel);
break;
}
case 'x': /* bbit bit index */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
+ infprintf (is, "0x%x", GET_OP (l, BBITIND));
break;
case 'p': /* cins, cins32, exts and exts32 position */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
+ infprintf (is, "0x%x", GET_OP (l, CINSPOS));
break;
case 's': /* cins and exts length-minus-one */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'S': /* cins32 and exts32 length-minus-one field */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
+ infprintf (is, "0x%x", GET_OP (l, CINSLM1));
break;
case 'Q': /* seqi/snei immediate field */
- op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
- /* Sign-extend it. */
- op = (op ^ 512) - 512;
- (*info->fprintf_func) (info->stream, "%d", op);
+ infprintf (is, "%d", GET_OP_S (l, SEQI));
break;
case 'a': /* 8-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_A;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
break;
case 'b': /* 8-bit signed offset in bit 3 */
- delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_B;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
break;
case 'c': /* 9-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
- if (delta & 0x100)
- delta |= ~OP_MASK_OFFSET_C;
/* Left shift 4 bits to print the real offset. */
- (*info->fprintf_func) (info->stream, "%d", delta << 4);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined extension sequence (+%c)"),
- *d);
+ infprintf (is,
+ _("# internal error, "
+ "undefined extension sequence (+%c)"),
+ *d);
return;
}
break;
case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BP) & OP_MASK_BP);
+ infprintf (is, "0x%x", GET_OP (l, BP));
break;
case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA3) & OP_MASK_SA3);
+ infprintf (is, "0x%x", GET_OP (l, SA3));
break;
case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA4) & OP_MASK_SA4);
+ infprintf (is, "0x%x", GET_OP (l, SA4));
break;
case '5':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMM8) & OP_MASK_IMM8);
+ infprintf (is, "0x%x", GET_OP (l, IMM8));
break;
case '6':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RS) & OP_MASK_RS);
+ infprintf (is, "0x%x", GET_OP (l, RS));
break;
case '7':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC));
break;
case '8':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
+ infprintf (is, "0x%x", GET_OP (l, WRDSP));
break;
case '9':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
+ infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
break;
case '0': /* dsp 6-bit signed immediate in bit 20 */
- delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
- if (delta & 0x20) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT));
break;
case ':': /* dsp 7-bit signed immediate in bit 19 */
- delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
- if (delta & 0x40) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT_7;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
break;
case '~':
- delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
- if (delta & 0x800)
- delta |= ~0x7ff;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, OFFSET12));
break;
case '\\':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
+ infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
break;
case '\'':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
+ infprintf (is, "0x%x", GET_OP (l, RDDSP));
break;
case '@': /* dsp 10-bit signed immediate in bit 16 */
- delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
- if (delta & 0x200) /* test sign bit */
- delta |= ~OP_MASK_IMM10;
- (*info->fprintf_func) (info->stream, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (l, IMM10));
break;
case '!':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_U) & OP_MASK_MT_U);
+ infprintf (is, "%d", GET_OP (l, MT_U));
break;
case '$':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_H) & OP_MASK_MT_H);
+ infprintf (is, "%d", GET_OP (l, MT_H));
break;
case '*':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
break;
case '&':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
+ infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
break;
case 'g':
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 's':
case 'b':
case 'r':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
break;
case 't':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
break;
case 'i':
case 'u':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
+ infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
break;
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- (*info->fprintf_func) (info->stream, "%d",
- delta);
+ infprintf (is, "%d", GET_OP_S (l, DELTA));
break;
case 'h':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_PREFX)
- & OP_MASK_PREFX));
+ infprintf (is, "0x%x", GET_OP (l, PREFX));
break;
case 'k':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_CACHE)
- & OP_MASK_CACHE));
+ infprintf (is, "0x%x", GET_OP (l, CACHE));
break;
case 'a':
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
- | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
+ | (GET_OP (l, TARGET) << 2));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (opp->name, "jalx") == 0)
case 'p':
/* Sign extend the displacement. */
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- info->target = (delta << 2) + pc + INSNLEN;
+ info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
(*info->print_address_func) (info->target, info);
break;
case 'd':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
break;
case 'U':
{
/* First check for both rd and rt being equal. */
- unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
- if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ unsigned int reg = GET_OP (l, RD);
+ if (reg == GET_OP (l, RT))
+ infprintf (is, "%s", mips_gpr_names[reg]);
else
{
/* If one is zero use the other. */
if (reg == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
+ else if (GET_OP (l, RT) == 0)
+ infprintf (is, "%s", mips_gpr_names[reg]);
else /* Bogus, result depends on processor. */
- (*info->fprintf_func) (info->stream, "%s or %s",
- mips_gpr_names[reg],
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ infprintf (is, "%s or %s",
+ mips_gpr_names[reg],
+ mips_gpr_names[GET_OP (l, RT)]);
}
}
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case '<':
case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
+ infprintf (is, "0x%x", GET_OP (l, SHAMT));
break;
case 'c':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE) & OP_MASK_CODE);
+ infprintf (is, "0x%x", GET_OP (l, CODE));
break;
case 'q':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE2) & OP_MASK_CODE2);
+ infprintf (is, "0x%x", GET_OP (l, CODE2));
break;
case 'C':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_COPZ) & OP_MASK_COPZ);
+ infprintf (is, "0x%x", GET_OP (l, COPZ));
break;
case 'B':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ infprintf (is, "0x%x", GET_OP (l, CODE20));
break;
case 'J':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE19) & OP_MASK_CODE19);
+ infprintf (is, "0x%x", GET_OP (l, CODE19));
break;
case 'S':
case 'V':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
break;
case 'T':
case 'W':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
break;
case 'D':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
+ infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
break;
case 'E':
'T' format. Therefore, until we gain understanding of
cp2 register names, we can simply print the register
numbers. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RT) & OP_MASK_RT);
+ infprintf (is, "$%d", GET_OP (l, RT));
break;
case 'G':
that FPU (cp1) instructions disassemble this field using
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3. */
- op = (l >> OP_SH_OP) & OP_MASK_OP;
+ op = GET_OP (l, OP);
if (op == OP_OP_COP0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]);
else
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
+ infprintf (is, "$%d", GET_OP (l, RD));
break;
case 'K':
- (*info->fprintf_func) (info->stream, "%s",
- mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
break;
case 'N':
- (*info->fprintf_func) (info->stream,
- ((opp->pinfo & (FP_D | FP_S)) != 0
- ? "$fcc%ld" : "$cc%ld"),
- (l >> OP_SH_BCC) & OP_MASK_BCC);
+ infprintf (is,
+ (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
+ GET_OP (l, BCC));
break;
case 'M':
- (*info->fprintf_func) (info->stream, "$fcc%ld",
- (l >> OP_SH_CCC) & OP_MASK_CCC);
+ infprintf (is, "$fcc%d", GET_OP (l, CCC));
break;
case 'P':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
+ infprintf (is, "%d", GET_OP (l, PERFREG));
break;
case 'e':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
+ infprintf (is, "%d", GET_OP (l, VECBYTE));
break;
case '%':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
+ infprintf (is, "%d", GET_OP (l, VECALIGN));
break;
case 'H':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_SEL) & OP_MASK_SEL);
+ infprintf (is, "%d", GET_OP (l, SEL));
break;
case 'O':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_ALN) & OP_MASK_ALN);
+ infprintf (is, "%d", GET_OP (l, ALN));
break;
case 'Q':
{
- unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+ unsigned int vsel = GET_OP (l, VSEL);
if ((vsel & 0x10) == 0)
{
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
- (*info->fprintf_func) (info->stream, "$v%ld[%d]",
- (l >> OP_SH_FT) & OP_MASK_FT,
- vsel >> 1);
+ infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
}
else if ((vsel & 0x08) == 0)
{
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
}
else
{
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "0x%x", GET_OP (l, FT));
}
}
break;
case 'X':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FD) & OP_MASK_FD);
+ infprintf (is, "$v%d", GET_OP (l, FD));
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FS) & OP_MASK_FS);
+ infprintf (is, "$v%d", GET_OP (l, FS));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ infprintf (is, "$v%d", GET_OP (l, FT));
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined modifier (%c)"),
- *d);
+ infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
return;
}
}
static int
print_insn_mips (bfd_vma memaddr,
- unsigned long int word,
+ int word,
struct disassemble_info *info)
{
+ static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op;
static bfd_boolean init = 0;
- static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ void *is = info->stream;
/* Build a hash table to shorten the search time. */
if (! init)
if (op->pinfo == INSN_MACRO
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
- if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
+ if (i == GET_OP (op->match, OP))
{
mips_hash[i] = op;
break;
info->target = 0;
info->target2 = 0;
- op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
+ op = mips_hash[GET_OP (word, OP)];
if (op != NULL)
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
const char *d;
/* We always allow to disassemble the jalx instruction. */
- if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
+ if (!opcode_is_member (op, mips_isa, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
| INSN_LOAD_MEMORY_DELAY)) != 0)
info->insn_type = dis_dref;
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
d = op->args;
if (d != NULL && *d != '\0')
{
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
print_insn_args (d, word, memaddr, info, op);
}
}
}
}
+#undef GET_OP_S
+#undef GET_OP
/* Handle undefined instructions. */
info->insn_type = dis_noninsn;
- (*info->fprintf_func) (info->stream, "0x%lx", word);
+ infprintf (is, "0x%x", word);
return INSNLEN;
}
\f
bfd_vma memaddr,
struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
+
+#define GET_OP(insn, field) \
+ (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
+ - ((MIPS16OP_MASK_##field >> 1) + 1))
switch (type)
{
case ',':
case '(':
case ')':
- (*info->fprintf_func) (info->stream, "%c", type);
+ infprintf (is, "%c", type);
break;
case 'y':
case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RY)
- & MIPS16OP_MASK_RY)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
break;
case 'x':
case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RX)
- & MIPS16OP_MASK_RX)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
break;
case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RZ)
- & MIPS16OP_MASK_RZ)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
break;
case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
- & MIPS16OP_MASK_MOVE32Z)));
+ infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
break;
case '0':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
+ infprintf (is, "%s", mips_gpr_names[0]);
break;
case 'S':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
+ infprintf (is, "%s", mips_gpr_names[29]);
break;
case 'P':
- (*info->fprintf_func) (info->stream, "$pc");
+ infprintf (is, "$pc");
break;
case 'R':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
+ infprintf (is, "%s", mips_gpr_names[31]);
break;
case 'X':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
- & MIPS16OP_MASK_REGR32)]);
+ infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
break;
case 'Y':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
+ infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
break;
case '<':
{
case '<':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 5;
extu = 1;
break;
case '>':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 5;
extu = 1;
break;
case '[':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+ immed = GET_OP (l, RZ);
extbits = 6;
extu = 1;
break;
case ']':
nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
+ immed = GET_OP (l, RX);
extbits = 6;
extu = 1;
break;
case '4':
nbits = 4;
- immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
+ immed = GET_OP (l, IMM4);
signedp = 1;
extbits = 15;
break;
case '5':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 1;
break;
case 'H':
nbits = 5;
shift = 1;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 2;
break;
case 'W':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
&& (op->pinfo & MIPS16_INSN_READ_SP) == 0)
{
case 'D':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'j':
nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
signedp = 1;
break;
case '6':
nbits = 6;
- immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ immed = GET_OP (l, IMM6);
break;
case '8':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
break;
case 'V':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
/* FIXME: This might be lw, or it might be addiu to $sp or
$pc. We assume it's load. */
info->insn_type = dis_dref;
case 'C':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
info->insn_type = dis_dref;
info->data_size = 8;
break;
case 'U':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
extu = 1;
break;
case 'k':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'K':
nbits = 8;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
break;
case 'p':
nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
signedp = 1;
pcrel = 1;
branch = 1;
break;
case 'q':
nbits = 11;
- immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
+ immed = GET_OP (l, IMM11);
signedp = 1;
pcrel = 1;
branch = 1;
case 'A':
nbits = 8;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
+ immed = GET_OP (l, IMM8);
pcrel = 1;
/* FIXME: This can be lw or la. We assume it is lw. */
info->insn_type = dis_dref;
case 'B':
nbits = 5;
shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
info->insn_type = dis_dref;
info->data_size = 8;
case 'E':
nbits = 5;
shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
+ immed = GET_OP (l, IMM5);
pcrel = 1;
break;
default:
}
if (! pcrel)
- (*info->fprintf_func) (info->stream, "%d", immed);
+ infprintf (is, "%d", immed);
else
{
bfd_vma baseaddr;
need_comma = 0;
- l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
+ l = GET_OP (l, IMM6);
amask = (l >> 3) & 7;
if (amask > 0 && amask < 5)
{
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (amask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[amask + 3]);
+ infprintf (is, "-%s", mips_gpr_names[amask + 3]);
need_comma = 1;
}
smask = (l >> 1) & 3;
if (smask == 3)
{
- (*info->fprintf_func) (info->stream, "%s??",
- need_comma ? "," : "");
+ infprintf (is, "%s??", need_comma ? "," : "");
need_comma = 1;
}
else if (smask > 0)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[16]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
if (smask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[smask + 15]);
+ infprintf (is, "-%s", mips_gpr_names[smask + 15]);
need_comma = 1;
}
if (l & 1)
{
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[31]);
+ infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
need_comma = 1;
}
if (amask == 5 || amask == 6)
{
- (*info->fprintf_func) (info->stream, "%s$f0",
- need_comma ? "," : "");
+ infprintf (is, "%s$f0", need_comma ? "," : "");
if (amask == 6)
- (*info->fprintf_func) (info->stream, "-$f1");
+ infprintf (is, "-$f1");
}
}
break;
}
if (args > 0) {
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
+ infprintf (is, "%s", mips_gpr_names[4]);
if (args > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[4 + args - 1]);
+ infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
need_comma = 1;
}
if (framesz == 0 && !use_extend)
framesz = 128;
- (*info->fprintf_func) (info->stream, "%s%d",
- need_comma ? "," : "",
- framesz);
+ infprintf (is, "%s%d", need_comma ? "," : "", framesz);
if (l & 0x40) /* $ra */
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
+ infprintf (is, ",%s", mips_gpr_names[31]);
nsreg = (l >> 24) & 0x7;
smask = 0;
{
if (smask & (1 << i))
{
- (*info->fprintf_func) (info->stream, ",%s",
- mips_gpr_names[i == 8 ? 30 : (16 + i)]);
+ infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
/* Skip over string of set bits. */
for (j = i; smask & (2 << j); j++)
continue;
if (j > i)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[j == 8 ? 30 : (16 + j)]);
+ infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
i = j + 1;
}
}
/* Statics $ax - $a3. */
if (statics == 1)
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
+ infprintf (is, ",%s", mips_gpr_names[7]);
else if (statics > 0)
- (*info->fprintf_func) (info->stream, ",%s-%s",
- mips_gpr_names[7 - statics + 1],
- mips_gpr_names[7]);
+ infprintf (is, ",%s-%s",
+ mips_gpr_names[7 - statics + 1],
+ mips_gpr_names[7]);
}
break;
default:
/* xgettext:c-format */
- (*info->fprintf_func)
- (info->stream,
- _("# internal disassembler error, unrecognised modifier (%c)"),
- type);
+ infprintf (is,
+ _("# internal disassembler error, "
+ "unrecognised modifier (%c)"),
+ type);
abort ();
}
}
static int
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
int status;
bfd_byte buffer[2];
int length;
bfd_boolean use_extend;
int extend = 0;
const struct mips_opcode *op, *opend;
+ void *is = info->stream;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length;
}
{
if (use_extend)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length - 2;
}
}
}
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
if (op->args[0] != '\0')
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
for (s = op->args; *s != '\0'; s++)
{
if (*s == ','
&& s[1] == 'w'
- && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
- == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
+ && GET_OP (insn, RX) == GET_OP (insn, RY))
{
/* Skip the register and the comma. */
++s;
}
if (*s == ','
&& s[1] == 'v'
- && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
- == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
+ && GET_OP (insn, RZ) == GET_OP (insn, RX))
{
/* Skip the register and the comma. */
++s;
return length;
}
}
+#undef GET_OP_S
+#undef GET_OP
if (use_extend)
- (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
- (*info->fprintf_func) (info->stream, "0x%x", insn);
+ infprintf (is, "0x%x", extend | 0xf000);
+ infprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
#define GET_OP(insn, field) \
(((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
+#define GET_OP_S(insn, field) \
+ ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
+ - ((MICROMIPSOP_MASK_##field >> 1) + 1))
opend = micromips_opcodes + bfd_micromips_num_opcodes;
for (op = micromips_opcodes; op < opend; op++)
{
break;
case '.':
- delta = GET_OP (insn, OFFSET10);
- if (delta & 0x200)
- delta |= ~0x3ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
break;
case '1':
break;
case '~':
- delta = GET_OP (insn, OFFSET12);
- if (delta & 0x800)
- delta |= ~0x7ff;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
break;
case 'a':
| (GET_OP (insn, TARGET) << 2));
else
info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
- | ((GET_OP (insn, TARGET)) << 1));
+ | (GET_OP (insn, TARGET) << 1));
/* For gdb disassembler, force odd address on jalx. */
if (info->flavour == bfd_target_unknown_flavour
&& strcmp (op->name, "jalx") == 0)
case 'j': /* Same as i, but sign-extended. */
case 'o':
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
- infprintf (is, "%d", delta);
+ infprintf (is, "%d", GET_OP_S (insn, DELTA));
break;
case 'k':
case 'p':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
+ delta = GET_OP_S (insn, DELTA);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'A':
/* Sign-extend the immediate. */
- immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
+ immed = GET_OP_S (insn, IMMA) << 2;
infprintf (is, "%d", immed);
break;
case 'D':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
+ delta = GET_OP_S (insn, IMMD);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'E':
/* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
+ delta = GET_OP_S (insn, IMME);
info->target = (delta << 1) + memaddr + length;
(*info->print_address_func) (info->target, info);
break;
case 'Q':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
- immed <<= 2;
+ immed = GET_OP_S (insn, IMMQ) << 2;
infprintf (is, "%d", immed);
break;
case 'X':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
+ immed = GET_OP_S (insn, IMMX);
infprintf (is, "%d", immed);
break;
case 'Y':
/* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
- if (immed >= -2 && immed <= 1)
- immed ^= 0x100;
- immed = immed << 2;
+ immed = GET_OP_S (insn, IMMY) << 2;
+ if ((unsigned int) (immed + 8) < 16)
+ immed ^= 0x400;
infprintf (is, "%d", immed);
break;
return length;
}
}
+#undef GET_OP_S
#undef GET_OP
infprintf (is, "0x%x", insn);
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
if (status == 0)
{
- unsigned long insn;
+ int insn;
if (endianness == BFD_ENDIAN_BIG)
- insn = (unsigned long) bfd_getb32 (buffer);
+ insn = bfd_getb32 (buffer);
else
- insn = (unsigned long) bfd_getl32 (buffer);
+ insn = bfd_getl32 (buffer);
return print_insn_mips (memaddr, insn, info);
}
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
-/* name, args, match, mask, pinfo, pinfo2, membership */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, IOCT|IOCTP|IOCT2 },
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
/* cfc2 is at the bottom of the table. */
/* cfc3 is at the bottom of the table. */
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
-{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
/* ctc2 is at the bottom of the table. */
/* ctc3 is at the bottom of the table. */
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
-{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
+{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
-{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
-{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
-{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
+{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
+{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
+{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
-{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
-{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
+{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
+{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
+{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
-{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
+{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
+{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
+{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
-{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
-{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
+{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
-{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
-{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
+{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
+{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
+{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
-{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
-{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
+{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
+{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
+{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
-{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
-{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
+{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
+{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
-{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
-{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
-{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
-{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
-{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
-{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
+{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, IOCT|IOCTP|IOCT2 },
+{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
-{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
-{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
+{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
+{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
+{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
disassembler recognizes more specific versions first. */
-{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
+{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
-{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
-{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
-{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
+{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }
+{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
+{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
};
#define MIPS_NUM_OPCODES \
projects / fpga / lx-cpu1 / binutils-tumbl.git / commitdiff