+ * config/tc-mips.c (ISA_SUPPORTS_DSP_ASE): Also set if microMIPS
+ mode.
+ (ISA_SUPPORTS_DSPR2_ASE): Likewise.
+ (macro_build) <'2'>: Handle microMIPS.
+2012-07-31 Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+ Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
+ (macro) <M_BALIGN>: Update error handling.
+ (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
+ <'7', '8', '0', '@', '^'>: Likewise.
+ (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
+ <'9'>: Fix formatting.
+ <'0', '@'>: Handle microMIPS.
+ <'^'>: New case.
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* config/tc-ia64.c (reg_symbol): Add a new register.
static int file_ase_dsp;
#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
- || mips_opts.isa == ISA_MIPS64R2)
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.micromips)
#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
static int file_ase_dspr2;
#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
- || mips_opts.isa == ISA_MIPS64R2)
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.micromips)
/* True if -mmt was passed or implied by arguments passed on the
command line (e.g., by -march). */
continue;
case '2':
- gas_assert (!mips_opts.micromips);
- INSERT_OPERAND (0, BP, insn, va_arg (args, int));
+ INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
continue;
case 'n':
case 2:
macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
break;
- default:
+ case 1:
+ case 3:
macro_build (NULL, "balign", "t,s,2", treg, sreg,
(int) imm_expr.X_add_number);
break;
+ default:
+ as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
+ break;
}
break;
break;
case '.': USE_BITS (OFFSET10); break;
case '1': USE_BITS (STYPE); break;
+ case '2': USE_BITS (BP); break;
+ case '3': USE_BITS (SA3); break;
+ case '4': USE_BITS (SA4); break;
+ case '5': USE_BITS (IMM8); break;
+ case '6': USE_BITS (RS); break;
+ case '7': USE_BITS (DSPACC); break;
+ case '8': USE_BITS (WRDSP); break;
+ case '0': USE_BITS (DSPSFT); break;
case '<': USE_BITS (SHAMT); break;
case '>': USE_BITS (SHAMT); break;
+ case '@': USE_BITS (IMM10); break;
case 'B': USE_BITS (CODE10); break;
case 'C': USE_BITS (COPZ); break;
case 'D': USE_BITS (FD); break;
case 'T': USE_BITS (FT); break;
case 'V': USE_BITS (FS); break;
case '\\': USE_BITS (3BITPOS); break;
+ case '^': USE_BITS (RD); break;
case 'a': USE_BITS (TARGET); break;
case 'b': USE_BITS (RS); break;
case 'c': USE_BITS (CODE); break;
return;
break;
- case '2': /* DSP 2-bit unsigned immediate in bit 11. */
- gas_assert (!mips_opts.micromips);
+ case '2':
+ /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
+ code) or 14 (for microMIPS code). */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number != 1
as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
(unsigned long) imm_expr.X_add_number);
}
- INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ BP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
- case '3': /* DSP 3-bit unsigned immediate in bit 21. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if (imm_expr.X_add_number & ~OP_MASK_SA3)
- {
- as_bad (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case '3':
+ /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
+ code) or 21 (for microMIPS code). */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ SA3, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case '4': /* DSP 4-bit unsigned immediate in bit 21. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if (imm_expr.X_add_number & ~OP_MASK_SA4)
- {
- as_bad (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case '4':
+ /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
+ code) or 21 (for microMIPS code). */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ SA4, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case '5': /* DSP 8-bit unsigned immediate in bit 16. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if (imm_expr.X_add_number & ~OP_MASK_IMM8)
- {
- as_bad (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case '5':
+ /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
+ code) or 16 (for microMIPS code). */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ IMM8, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
- case '6': /* DSP 5-bit unsigned immediate in bit 21. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if (imm_expr.X_add_number & ~OP_MASK_RS)
- {
- as_bad (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case '6':
+ /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
+ code) or 21 (for microMIPS code). */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ RS, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
case '7': /* Four DSP accumulators in bits 11,12. */
- gas_assert (!mips_opts.micromips);
- if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
- s[3] >= '0' && s[3] <= '3')
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
+ && s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
- INSERT_OPERAND (0, DSPACC, *ip, regno);
+ INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
continue;
}
else
as_bad (_("Invalid dsp acc register"));
break;
- case '8': /* DSP 6-bit unsigned immediate in bit 11. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
- {
- as_bad (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_WRDSP,
- (unsigned long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ case '8':
+ /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
+ code) or 14 (for microMIPS code). */
+ {
+ unsigned long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_WRDSP
+ : OP_MASK_WRDSP);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number > mask)
+ as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
+ mask, (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ WRDSP, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
case '9': /* Four DSP accumulators in bits 21,22. */
gas_assert (!mips_opts.micromips);
- if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
- s[3] >= '0' && s[3] <= '3')
+ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
+ && s[3] >= '0' && s[3] <= '3')
{
regno = s[3] - '0';
s += 4;
as_bad (_("Invalid dsp acc register"));
break;
- case '0': /* DSP 6-bit signed immediate in bit 20. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- min_range = -((OP_MASK_DSPSFT + 1) >> 1);
- max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
- if (imm_expr.X_add_number < min_range ||
- imm_expr.X_add_number > max_range)
- {
+ case '0':
+ /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
+ code) or 20 (for microMIPS code). */
+ {
+ long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ min_range = -((mask + 1) >> 1);
+ max_range = ((mask + 1) >> 1) - 1;
+ if (imm_expr.X_add_number < min_range
+ || imm_expr.X_add_number > max_range)
as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
- imm_expr.X_op = O_absent;
- s = expr_end;
+ INSERT_OPERAND (mips_opts.micromips,
+ DSPSFT, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
continue;
case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
continue;
case '@': /* DSP 10-bit signed immediate in bit 16. */
- gas_assert (!mips_opts.micromips);
- my_getExpression (&imm_expr, s);
- check_absolute_expr (ip, &imm_expr);
- min_range = -((OP_MASK_IMM10 + 1) >> 1);
- max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
- if (imm_expr.X_add_number < min_range ||
- imm_expr.X_add_number > max_range)
- {
+ {
+ long mask = (mips_opts.micromips
+ ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
+
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ min_range = -((mask + 1) >> 1);
+ max_range = ((mask + 1) >> 1) - 1;
+ if (imm_expr.X_add_number < min_range
+ || imm_expr.X_add_number > max_range)
as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
(long) min_range, (long) max_range,
(long) imm_expr.X_add_number);
- }
- INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
+ INSERT_OPERAND (mips_opts.micromips,
+ IMM10, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
+ continue;
+
+ case '^': /* DSP 5-bit unsigned immediate in bit 11. */
+ gas_assert (mips_opts.micromips);
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ MICROMIPSOP_MASK_RD,
+ (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
+ * gas/mips/micromips@mips32-dsp.d: New test.
+ * gas/mips/micromips@mips32-dspr2.d: New test.
+ * gas/mips/mips32-dsp.s: Update padding.
+ * gas/mips/mips32-dspr2.s: Likewise.
+ * gas/mips/mips.exp: Use run_dump_test_arches to run MIPS32 DSP
+ tests.
+2012-07-31 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * gas/mips/micromips@mips32-dsp.d: New.
+ * gas/mips/micromips@mips32-dspr2.d: New.
+ * gas/mips/mips32-dsp.d: Remove -mips32r2.
+ * gas/mips/mips32-dspr2.d: Likewise.
+ * gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
+ for micromips. Use run_dump_test_arches to run dsp tests.
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* gas/testsuite/gas/ia64/psn.d: New file.
run_dump_test_arches "octeon2" [mips_arch_list_matching octeon2]
run_dump_test "smartmips"
- run_dump_test "mips32-dsp"
- run_dump_test "mips32-dspr2"
+ run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2 \
+ !octeon]
+ run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2 \
+ !octeon]
run_dump_test "mips64-dsp"
run_dump_test "mips32-mt"
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS DSP ASE for MIPS32
-#as: -mdsp -mips32r2 -32
+#as: -mdsp -32
# Check MIPS DSP ASE for MIPS32 Instruction Assembly
multu $ac0,$22,$23
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS DSP ASE Rev2 for MIPS32
-#as: -mdspr2 -mips32r2 -32
+#as: -mdspr2 -32
# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
dpsqx_sa.w.ph $ac2,$18,$19
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
+2012-07-31 Chao-Ying Fu <fu@mips.com>
+ Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Document microMIPS DSP ASE usage.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+ microMIPS DSP ASE support.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
#define MICROMIPSOP_MASK_IMMY 0x1ff
#define MICROMIPSOP_SH_IMMY 1
+/* MIPS DSP ASE */
+#define MICROMIPSOP_MASK_DSPACC 0x3
+#define MICROMIPSOP_SH_DSPACC 14
+#define MICROMIPSOP_MASK_DSPSFT 0x3f
+#define MICROMIPSOP_SH_DSPSFT 16
+#define MICROMIPSOP_MASK_SA3 0x7
+#define MICROMIPSOP_SH_SA3 13
+#define MICROMIPSOP_MASK_SA4 0xf
+#define MICROMIPSOP_SH_SA4 12
+#define MICROMIPSOP_MASK_IMM8 0xff
+#define MICROMIPSOP_SH_IMM8 13
+#define MICROMIPSOP_MASK_IMM10 0x3ff
+#define MICROMIPSOP_SH_IMM10 16
+#define MICROMIPSOP_MASK_WRDSP 0x3f
+#define MICROMIPSOP_SH_WRDSP 14
+#define MICROMIPSOP_MASK_BP 0x3
+#define MICROMIPSOP_SH_BP 14
+
/* Placeholders for fields that only exist in the traditional 32-bit
instruction encoding; see the comment above for details. */
#define MICROMIPSOP_MASK_CODE20 0
#define MICROMIPSOP_SH_VECBYTE 0
#define MICROMIPSOP_MASK_VECALIGN 0
#define MICROMIPSOP_SH_VECALIGN 0
-#define MICROMIPSOP_MASK_DSPACC 0
-#define MICROMIPSOP_SH_DSPACC 0
#define MICROMIPSOP_MASK_DSPACC_S 0
#define MICROMIPSOP_SH_DSPACC_S 0
-#define MICROMIPSOP_MASK_DSPSFT 0
-#define MICROMIPSOP_SH_DSPSFT 0
#define MICROMIPSOP_MASK_DSPSFT_7 0
#define MICROMIPSOP_SH_DSPSFT_7 0
-#define MICROMIPSOP_MASK_SA3 0
-#define MICROMIPSOP_SH_SA3 0
-#define MICROMIPSOP_MASK_SA4 0
-#define MICROMIPSOP_SH_SA4 0
-#define MICROMIPSOP_MASK_IMM8 0
-#define MICROMIPSOP_SH_IMM8 0
-#define MICROMIPSOP_MASK_IMM10 0
-#define MICROMIPSOP_SH_IMM10 0
-#define MICROMIPSOP_MASK_WRDSP 0
-#define MICROMIPSOP_SH_WRDSP 0
#define MICROMIPSOP_MASK_RDDSP 0
#define MICROMIPSOP_SH_RDDSP 0
-#define MICROMIPSOP_MASK_BP 0
-#define MICROMIPSOP_SH_BP 0
#define MICROMIPSOP_MASK_MT_U 0
#define MICROMIPSOP_SH_MT_U 0
#define MICROMIPSOP_MASK_MT_H 0
"f" 32-bit floating point constant
"l" 32-bit floating point constant in .lit4
+ DSP ASE usage:
+ "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
+ "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
+ "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
+ "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
+ "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
+ "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
+ "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
+ "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
+ "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
+ "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
+
Other:
"()" parens surrounding optional value
"," separates operands
"m" start of microMIPS extension sequence
Characters used so far, for quick reference when adding more:
- "1234567890"
- "<>(),+.\|~"
+ "12345678 0"
+ "<>(),+.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
+2012-08-01 Alan Modra <amodra@gmail.com>
+
+ * h8300-dis.c: Fix printf arg warnings.
+ * i960-dis.c: Likewise.
+ * mips-dis.c: Likewise.
+ * pdp11-dis.c: Likewise.
+ * sh-dis.c: Likewise.
+ * v850-dis.c: Likewise.
+ * configure.in: Formatting.
+ * configure: Regenerate.
+ * rl78-decode.c: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+ * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
+2012-07-31 Chao-Ying Fu <fu@mips.com>
+ Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
+ (DSP_VOLA): Likewise.
+ (D32, D33): Likewise.
+ (micromips_opcodes): Add DSP ASE instructions.
+ * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
+ <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
+
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
- bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
+ bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
- bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
- bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
+ bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
- bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
else if (x & CTRL)
- outfn (stream, cregnames[rn]);
+ outfn (stream, "%s", cregnames[rn]);
else if ((x & MODE) == CCR)
outfn (stream, "ccr");
return;
}
- (*info->fprintf_func) (stream, ctrl_tab[i].name);
+ (*info->fprintf_func) (stream, "%s", ctrl_tab[i].name);
if (word1 & 2)
/* Predicts branch not taken. */
(*info->fprintf_func) (stream, ".f");
return;
}
- (*info->fprintf_func) (stream, cobr_tab[i].name);
+ (*info->fprintf_func) (stream, "%s", cobr_tab[i].name);
/* Predicts branch not taken. */
if (word1 & 2)
/* M1 is 1 */
(*info->fprintf_func) (stream, "%d", src1);
else
- (*info->fprintf_func) (stream, reg_names[src1]);
+ (*info->fprintf_func) (stream, "%s", reg_names[src1]);
if (cobr_tab[i].numops > 1)
{
fp = 0;
}
- (*info->fprintf_func) (stream, mnemp);
+ (*info->fprintf_func) (stream, "%s", mnemp);
s1 = (word1 >> 5) & 1;
s2 = (word1 >> 6) & 1;
else
{
/* Non-FP register. */
- (*info->fprintf_func) (stream, reg_names[fp_reg]);
+ (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]);
}
}
else
{
/* Register. */
if (spec == 0)
- (*info->fprintf_func) (stream, reg_names[fp_reg]);
+ (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]);
else
(*info->fprintf_func) (stream, "sf%d", fp_reg);
}
#define I1 INSN_ISA1
#define I3 INSN_ISA3
+/* MIPS DSP ASE support. */
+#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
+#define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */
+#define MOD_a WR_a|RD_a
+#define DSP_VOLA INSN_NO_DELAY_SLOT
+#define D32 INSN_DSP
+#define D33 INSN_DSPR2
+
/* MIPS MCU (MicroController) ASE support. */
#define MC INSN_MCU
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"madd", "7,s,t", 0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 },
{"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 },
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 },
{"mfhi", "mj", 0x4600, 0xffe0, RD_HI, WR_mj, I1 },
{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_s|RD_HI, 0, I1 },
+{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_s|RD_HI, 0, D32 },
{"mflo", "mj", 0x4640, 0xffe0, RD_LO, WR_mj, I1 },
{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_s|RD_LO, 0, I1 },
+{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_s|RD_LO, 0, D32 },
{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S, 0, I1 },
{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D, 0, I1 },
{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"msub", "7,s,t", 0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I1 },
{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I1 },
{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
+{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 },
{"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 },
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 },
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 },
{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_s|WR_HI, 0, I1 },
+{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_s|WR_HI, 0, D32 },
{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_s|WR_LO, 0, I1 },
+{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_s|WR_LO, 0, D32 },
{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 },
{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
+{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t, 0, D32 },
{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+/* MIPS DSP ASE. */
+{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"addq.ph", "d,s,t", 0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addq_s.w", "d,s,t", 0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addsc", "d,s,t", 0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addu.qb", "d,s,t", 0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, D32 },
+{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"cmp.lt.ph", "s,t", 0x00000045, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"cmpu.eq.qb", "s,t", 0x00000245, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"cmpu.le.qb", "s,t", 0x000002c5, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"cmpu.lt.qb", "s,t", 0x00000285, 0xfc00ffff, RD_s|RD_t, 0, D32 },
+{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpsu.h.qbl", "7,s,t", 0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"dpsu.h.qbr", "7,s,t", 0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"extpdp", "t,7,6", 0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA, 0, D32 },
+{"extpdpv", "t,7,s", 0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
+{"extp", "t,7,6", 0x0000267c, 0xfc003fff, WR_t|RD_a, 0, D32 },
+{"extpv", "t,7,s", 0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
+{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
+{"extr_r.w", "t,7,6", 0x00001e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
+{"extr_s.h", "t,7,6", 0x00003e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
+{"extrv_rs.w", "t,7,s", 0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
+{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
+{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
+{"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s, 0, D32 },
+{"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_t|RD_a, 0, D32 },
+{"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
+{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
+{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t, 0, D32 },
+{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"modsub", "d,s,t", 0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"mthlip", "s,7", 0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
+{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
+{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
+{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
+{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
+{"mulq_rs.ph", "d,s,t", 0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
+{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D32 },
+{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"pick.ph", "d,s,t", 0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"pick.qb", "d,s,t", 0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceq.w.phl", "t,s", 0x0000513c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceq.w.phr", "t,s", 0x0000613c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"raddu.w.qb", "t,s", 0x0000f13c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"rddsp", "t", 0x000fc67c, 0xfc1fffff, WR_t, 0, D32 },
+{"rddsp", "t,8", 0x0000067c, 0xfc103fff, WR_t, 0, D32 },
+{"repl.ph", "d,@", 0x0000003d, 0xfc0007ff, WR_d, 0, D32 },
+{"repl.qb", "t,5", 0x000005fc, 0xfc001fff, WR_t, 0, D32 },
+{"replv.ph", "t,s", 0x0000033c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"replv.qb", "t,s", 0x0000133c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
+{"shilo", "7,0", 0x0000001d, 0xffc03fff, MOD_a, 0, D32 },
+{"shilov", "7,s", 0x0000127c, 0xffe03fff, MOD_a|RD_s, 0, D32 },
+{"shll.ph", "t,s,4", 0x000003b5, 0xfc000fff, WR_t|RD_s, 0, D32 },
+{"shll.qb", "t,s,3", 0x0000087c, 0xfc001fff, WR_t|RD_s, 0, D32 },
+{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s, 0, D32 },
+{"shll_s.w", "t,s,^", 0x000003f5, 0xfc0007ff, WR_t|RD_s, 0, D32 },
+{"shllv.ph", "d,t,s", 0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shllv.qb", "d,t,s", 0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shllv_s.ph", "d,t,s", 0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shra.ph", "t,s,4", 0x00000335, 0xfc000fff, WR_t|RD_s, 0, D32 },
+{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s, 0, D32 },
+{"shra_r.w", "t,s,^", 0x000002f5, 0xfc0007ff, WR_t|RD_s, 0, D32 },
+{"shrav.ph", "d,t,s", 0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shrav_r.ph", "d,t,s", 0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"shrl.qb", "t,s,3", 0x0000187c, 0xfc001fff, WR_t|RD_s, 0, D32 },
+{"shrlv.qb", "d,t,s", 0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"subq.ph", "d,s,t", 0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"subq_s.w", "d,s,t", 0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"subu.qb", "d,s,t", 0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
+{"wrdsp", "t", 0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA, 0, D32 },
+{"wrdsp", "t,8", 0x0000167c, 0xfc103fff, RD_t|DSP_VOLA, 0, D32 },
+/* MIPS DSP ASE Rev2. */
+{"absq_s.qb", "t,s", 0x0000013c, 0xfc00ffff, WR_t|RD_s, 0, D33 },
+{"addqh.ph", "d,s,t", 0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"addqh_r.ph", "d,s,t", 0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"addqh.w", "d,s,t", 0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"addu.ph", "d,s,t", 0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"adduh.qb", "d,s,t", 0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"adduh_r.qb", "d,s,t", 0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"append", "t,s,h", 0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
+{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
+{"balign", "t,s,2", 0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s, 0, D33 },
+{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"dpa.w.ph", "7,s,t", 0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dps.w.ph", "7,s,t", 0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"mul.ph", "d,s,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
+{"mul_s.ph", "d,s,t", 0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
+{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
+{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
+{"mulq_s.w", "d,s,t", 0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
+{"mulsa.w.ph", "7,s,t", 0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, D33 },
+{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
+{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
+{"prepend", "t,s,h", 0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
+{"shra.qb", "t,s,3", 0x000001fc, 0xfc001fff, WR_t|RD_s, 0, D33 },
+{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s, 0, D33 },
+{"shrav.qb", "d,t,s", 0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"shrav_r.qb", "d,t,s", 0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"shrl.ph", "t,s,4", 0x000003fc, 0xfc000fff, WR_t|RD_s, 0, D33 },
+{"shrlv.ph", "d,t,s", 0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subu.ph", "d,s,t", 0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subuh.qb", "d,s,t", 0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subuh_r.qb", "d,s,t", 0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subqh.ph", "d,s,t", 0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
+{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
};
const int bfd_micromips_num_opcodes =
infprintf (is, "0x%x", GET_OP (insn, STYPE));
break;
+ case '2':
+ infprintf (is, "0x%x", GET_OP (insn, BP));
+ break;
+
+ case '3':
+ infprintf (is, "0x%x", GET_OP (insn, SA3));
+ break;
+
+ case '4':
+ infprintf (is, "0x%x", GET_OP (insn, SA4));
+ break;
+
+ case '5':
+ infprintf (is, "0x%x", GET_OP (insn, IMM8));
+ break;
+
+ case '6':
+ infprintf (is, "0x%x", GET_OP (insn, RS));
+ break;
+
+ case '7':
+ infprintf (is, "$ac%d", GET_OP (insn, DSPACC));
+ break;
+
+ case '8':
+ infprintf (is, "0x%x", GET_OP (insn, WRDSP));
+ break;
+
+ case '0': /* DSP 6-bit signed immediate in bit 16. */
+ delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20;
+ infprintf (is, "%d", delta);
+ break;
+
case '<':
infprintf (is, "0x%x", GET_OP (insn, SHAMT));
break;
infprintf (is, "0x%x", GET_OP (insn, 3BITPOS));
break;
+ case '^':
+ infprintf (is, "0x%x", GET_OP (insn, RD));
+ break;
+
case '|':
infprintf (is, "0x%x", GET_OP (insn, TRAP));
break;
infprintf (is, "%s", mips_gpr_names[0]);
break;
+ case '@': /* DSP 10-bit signed immediate in bit 16. */
+ delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200;
+ infprintf (is, "%d", delta);
+ break;
+
case 'B':
infprintf (is, "0x%x", GET_OP (insn, CODE10));
break;
switch (OP.type)
{
case PDP11_OPCODE_NO_OPS:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
goto done;
case PDP11_OPCODE_REG:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (dst, info);
goto done;
case PDP11_OPCODE_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (strcmp (OP.name, "jmp") == 0)
dst |= JUMP;
return -1;
goto done;
case PDP11_OPCODE_FOP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (strcmp (OP.name, "jmp") == 0)
dst |= JUMP;
return -1;
goto done;
case PDP11_OPCODE_REG_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (src, info);
FPRINTF (F, OPERAND_SEPARATOR);
return -1;
goto done;
case PDP11_OPCODE_REG_OP_REV:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, dst, info) < 0)
return -1;
case PDP11_OPCODE_AC_FOP:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_freg (ac, info);
FPRINTF (F, OPERAND_SEPARATOR);
case PDP11_OPCODE_FOP_AC:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_foperand (&memaddr, dst, info) < 0)
return -1;
case PDP11_OPCODE_AC_OP:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_freg (ac, info);
FPRINTF (F, OPERAND_SEPARATOR);
case PDP11_OPCODE_OP_AC:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, dst, info) < 0)
return -1;
goto done;
}
case PDP11_OPCODE_OP_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, src, info) < 0)
return -1;
{
int displ = (opcode & 0xff) << 8;
bfd_vma address = memaddr + (sign_extend (displ) >> 7);
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
(*info->print_address_func) (address, info);
goto done;
int displ = (opcode & 0x3f) << 10;
bfd_vma address = memaddr - (displ >> 9);
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (src, info);
FPRINTF (F, OPERAND_SEPARATOR);
case PDP11_OPCODE_IMM8:
{
int code = opcode & 0xff;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
case PDP11_OPCODE_IMM6:
{
int code = opcode & 0x3f;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
case PDP11_OPCODE_IMM3:
{
int code = opcode & 7;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
+xgate-dis.c
+xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
op[0]);
}
SYNTAX("nop");
-#line 887 "rl78-decode.opc"
+#line 886 "rl78-decode.opc"
ID(nop);
/*----------------------------------------------------------------------*/
case 0x07:
{
/** 0000 0rw1 addw %0, %1 */
-#line 253 "rl78-decode.opc"
+#line 252 "rl78-decode.opc"
int rw AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rw = 0x%x\n", rw);
}
SYNTAX("addw %0, %1");
-#line 253 "rl78-decode.opc"
+#line 252 "rl78-decode.opc"
ID(add); W(); DR(AX); SRW(rw); Fzac;
}
op[0]);
}
SYNTAX("addw %0, %e1%!1");
-#line 244 "rl78-decode.opc"
+#line 243 "rl78-decode.opc"
ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("addw %0, #%1");
-#line 250 "rl78-decode.opc"
+#line 249 "rl78-decode.opc"
ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("addw %0, %1");
-#line 256 "rl78-decode.opc"
+#line 255 "rl78-decode.opc"
ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("xch a, x");
-#line 1210 "rl78-decode.opc"
+#line 1209 "rl78-decode.opc"
ID(xch); DR(A); SR(X);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 657 "rl78-decode.opc"
+#line 656 "rl78-decode.opc"
ID(mov); DR(A); SM(B, IMMU(2));
}
op[0]);
}
SYNTAX("add %0, #%1");
-#line 207 "rl78-decode.opc"
+#line 206 "rl78-decode.opc"
ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("add %0, %1");
-#line 201 "rl78-decode.opc"
+#line 200 "rl78-decode.opc"
ID(add); DR(A); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("add %0, #%1");
-#line 195 "rl78-decode.opc"
+#line 194 "rl78-decode.opc"
ID(add); DR(A); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("add %0, %e1%1");
-#line 183 "rl78-decode.opc"
+#line 182 "rl78-decode.opc"
ID(add); DR(A); SM(HL, 0); Fzac;
}
op[0]);
}
SYNTAX("add %0, %e1%1");
-#line 189 "rl78-decode.opc"
+#line 188 "rl78-decode.opc"
ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("add %0, %e1%!1");
-#line 180 "rl78-decode.opc"
+#line 179 "rl78-decode.opc"
ID(add); DR(A); SM(None, IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("addw %0, #%1");
-#line 259 "rl78-decode.opc"
+#line 258 "rl78-decode.opc"
ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("es:");
-#line 172 "rl78-decode.opc"
+#line 171 "rl78-decode.opc"
DE(); SE();
op ++;
pc ++;
case 0x16:
{
/** 0001 0ra0 movw %0, %1 */
-#line 835 "rl78-decode.opc"
+#line 834 "rl78-decode.opc"
int ra AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("movw %0, %1");
-#line 835 "rl78-decode.opc"
+#line 834 "rl78-decode.opc"
ID(mov); W(); DRW(ra); SR(AX);
}
case 0x17:
{
/** 0001 0ra1 movw %0, %1 */
-#line 832 "rl78-decode.opc"
+#line 831 "rl78-decode.opc"
int ra AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("movw %0, %1");
-#line 832 "rl78-decode.opc"
+#line 831 "rl78-decode.opc"
ID(mov); W(); DR(AX); SRW(ra);
}
op[0]);
}
SYNTAX("mov %e0%0, %1");
-#line 708 "rl78-decode.opc"
+#line 707 "rl78-decode.opc"
ID(mov); DM(B, IMMU(2)); SR(A);
}
op[0]);
}
SYNTAX("mov %e0%0, #%1");
-#line 705 "rl78-decode.opc"
+#line 704 "rl78-decode.opc"
ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("addc %0, #%1");
-#line 239 "rl78-decode.opc"
+#line 238 "rl78-decode.opc"
ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("addc %0, %1");
-#line 236 "rl78-decode.opc"
+#line 235 "rl78-decode.opc"
ID(addc); DR(A); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("addc %0, #%1");
-#line 227 "rl78-decode.opc"
+#line 226 "rl78-decode.opc"
ID(addc); DR(A); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("addc %0, %e1%1");
-#line 215 "rl78-decode.opc"
+#line 214 "rl78-decode.opc"
ID(addc); DR(A); SM(HL, 0); Fzac;
}
op[0]);
}
SYNTAX("addc %0, %e1%1");
-#line 224 "rl78-decode.opc"
+#line 223 "rl78-decode.opc"
ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("addc %0, %e1%!1");
-#line 212 "rl78-decode.opc"
+#line 211 "rl78-decode.opc"
ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("subw %0, #%1");
-#line 1174 "rl78-decode.opc"
+#line 1173 "rl78-decode.opc"
ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
case 0x27:
{
/** 0010 0rw1 subw %0, %1 */
-#line 1168 "rl78-decode.opc"
+#line 1167 "rl78-decode.opc"
int rw AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rw = 0x%x\n", rw);
}
SYNTAX("subw %0, %1");
-#line 1168 "rl78-decode.opc"
+#line 1167 "rl78-decode.opc"
ID(sub); W(); DR(AX); SRW(rw); Fzac;
}
op[0]);
}
SYNTAX("subw %0, %e1%!1");
-#line 1159 "rl78-decode.opc"
+#line 1158 "rl78-decode.opc"
ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("subw %0, #%1");
-#line 1165 "rl78-decode.opc"
+#line 1164 "rl78-decode.opc"
ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("subw %0, %1");
-#line 1171 "rl78-decode.opc"
+#line 1170 "rl78-decode.opc"
ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("mov %e0%0, %1");
-#line 720 "rl78-decode.opc"
+#line 719 "rl78-decode.opc"
ID(mov); DM(C, IMMU(2)); SR(A);
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 663 "rl78-decode.opc"
+#line 662 "rl78-decode.opc"
ID(mov); DR(A); SM(C, IMMU(2));
}
op[0]);
}
SYNTAX("sub %0, #%1");
-#line 1122 "rl78-decode.opc"
+#line 1121 "rl78-decode.opc"
ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("sub %0, %1");
-#line 1116 "rl78-decode.opc"
+#line 1115 "rl78-decode.opc"
ID(sub); DR(A); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("sub %0, #%1");
-#line 1110 "rl78-decode.opc"
+#line 1109 "rl78-decode.opc"
ID(sub); DR(A); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("sub %0, %e1%1");
-#line 1098 "rl78-decode.opc"
+#line 1097 "rl78-decode.opc"
ID(sub); DR(A); SM(HL, 0); Fzac;
}
op[0]);
}
SYNTAX("sub %0, %e1%1");
-#line 1104 "rl78-decode.opc"
+#line 1103 "rl78-decode.opc"
ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("sub %0, %e1%!1");
-#line 1095 "rl78-decode.opc"
+#line 1094 "rl78-decode.opc"
ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
}
case 0x36:
{
/** 0011 0rg0 movw %0, #%1 */
-#line 829 "rl78-decode.opc"
+#line 828 "rl78-decode.opc"
int rg AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("movw %0, #%1");
-#line 829 "rl78-decode.opc"
+#line 828 "rl78-decode.opc"
ID(mov); W(); DRW(rg); SC(IMMU(2));
}
case 0x00:
{
/** 0011 0001 0bit 0000 btclr %s1, $%a0 */
-#line 395 "rl78-decode.opc"
+#line 394 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("btclr %s1, $%a0");
-#line 395 "rl78-decode.opc"
+#line 394 "rl78-decode.opc"
ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
/*----------------------------------------------------------------------*/
case 0x01:
{
/** 0011 0001 0bit 0001 btclr %1, $%a0 */
-#line 389 "rl78-decode.opc"
+#line 388 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("btclr %1, $%a0");
-#line 389 "rl78-decode.opc"
+#line 388 "rl78-decode.opc"
ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
}
case 0x02:
{
/** 0011 0001 0bit 0010 bt %s1, $%a0 */
-#line 381 "rl78-decode.opc"
+#line 380 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bt %s1, $%a0");
-#line 381 "rl78-decode.opc"
+#line 380 "rl78-decode.opc"
ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
/*----------------------------------------------------------------------*/
case 0x03:
{
/** 0011 0001 0bit 0011 bt %1, $%a0 */
-#line 375 "rl78-decode.opc"
+#line 374 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bt %1, $%a0");
-#line 375 "rl78-decode.opc"
+#line 374 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
}
case 0x04:
{
/** 0011 0001 0bit 0100 bf %s1, $%a0 */
-#line 342 "rl78-decode.opc"
+#line 341 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bf %s1, $%a0");
-#line 342 "rl78-decode.opc"
+#line 341 "rl78-decode.opc"
ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
/*----------------------------------------------------------------------*/
case 0x05:
{
/** 0011 0001 0bit 0101 bf %1, $%a0 */
-#line 336 "rl78-decode.opc"
+#line 335 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bf %1, $%a0");
-#line 336 "rl78-decode.opc"
+#line 335 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
}
case 0x07:
{
/** 0011 0001 0cnt 0111 shl %0, %1 */
-#line 1051 "rl78-decode.opc"
+#line 1050 "rl78-decode.opc"
int cnt AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" cnt = 0x%x\n", cnt);
}
SYNTAX("shl %0, %1");
-#line 1051 "rl78-decode.opc"
+#line 1050 "rl78-decode.opc"
ID(shl); DR(C); SC(cnt);
}
case 0x08:
{
/** 0011 0001 0cnt 1000 shl %0, %1 */
-#line 1048 "rl78-decode.opc"
+#line 1047 "rl78-decode.opc"
int cnt AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" cnt = 0x%x\n", cnt);
}
SYNTAX("shl %0, %1");
-#line 1048 "rl78-decode.opc"
+#line 1047 "rl78-decode.opc"
ID(shl); DR(B); SC(cnt);
}
case 0x09:
{
/** 0011 0001 0cnt 1001 shl %0, %1 */
-#line 1045 "rl78-decode.opc"
+#line 1044 "rl78-decode.opc"
int cnt AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" cnt = 0x%x\n", cnt);
}
SYNTAX("shl %0, %1");
-#line 1045 "rl78-decode.opc"
+#line 1044 "rl78-decode.opc"
ID(shl); DR(A); SC(cnt);
}
case 0x0a:
{
/** 0011 0001 0cnt 1010 shr %0, %1 */
-#line 1062 "rl78-decode.opc"
+#line 1061 "rl78-decode.opc"
int cnt AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" cnt = 0x%x\n", cnt);
}
SYNTAX("shr %0, %1");
-#line 1062 "rl78-decode.opc"
+#line 1061 "rl78-decode.opc"
ID(shr); DR(A); SC(cnt);
}
case 0x0b:
{
/** 0011 0001 0cnt 1011 sar %0, %1 */
-#line 1009 "rl78-decode.opc"
+#line 1008 "rl78-decode.opc"
int cnt AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" cnt = 0x%x\n", cnt);
}
SYNTAX("sar %0, %1");
-#line 1009 "rl78-decode.opc"
+#line 1008 "rl78-decode.opc"
ID(sar); DR(A); SC(cnt);
}
case 0x8c:
{
/** 0011 0001 wcnt 1100 shlw %0, %1 */
-#line 1057 "rl78-decode.opc"
+#line 1056 "rl78-decode.opc"
int wcnt AU = (op[1] >> 4) & 0x0f;
if (trace)
{
printf (" wcnt = 0x%x\n", wcnt);
}
SYNTAX("shlw %0, %1");
-#line 1057 "rl78-decode.opc"
+#line 1056 "rl78-decode.opc"
ID(shl); W(); DR(BC); SC(wcnt);
/*----------------------------------------------------------------------*/
case 0x8d:
{
/** 0011 0001 wcnt 1101 shlw %0, %1 */
-#line 1054 "rl78-decode.opc"
+#line 1053 "rl78-decode.opc"
int wcnt AU = (op[1] >> 4) & 0x0f;
if (trace)
{
printf (" wcnt = 0x%x\n", wcnt);
}
SYNTAX("shlw %0, %1");
-#line 1054 "rl78-decode.opc"
+#line 1053 "rl78-decode.opc"
ID(shl); W(); DR(AX); SC(wcnt);
}
case 0x8e:
{
/** 0011 0001 wcnt 1110 shrw %0, %1 */
-#line 1065 "rl78-decode.opc"
+#line 1064 "rl78-decode.opc"
int wcnt AU = (op[1] >> 4) & 0x0f;
if (trace)
{
printf (" wcnt = 0x%x\n", wcnt);
}
SYNTAX("shrw %0, %1");
-#line 1065 "rl78-decode.opc"
+#line 1064 "rl78-decode.opc"
ID(shr); W(); DR(AX); SC(wcnt);
/*----------------------------------------------------------------------*/
case 0x8f:
{
/** 0011 0001 wcnt 1111 sarw %0, %1 */
-#line 1012 "rl78-decode.opc"
+#line 1011 "rl78-decode.opc"
int wcnt AU = (op[1] >> 4) & 0x0f;
if (trace)
{
printf (" wcnt = 0x%x\n", wcnt);
}
SYNTAX("sarw %0, %1");
-#line 1012 "rl78-decode.opc"
+#line 1011 "rl78-decode.opc"
ID(sar); W(); DR(AX); SC(wcnt);
/*----------------------------------------------------------------------*/
case 0x80:
{
/** 0011 0001 1bit 0000 btclr %s1, $%a0 */
-#line 392 "rl78-decode.opc"
+#line 391 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("btclr %s1, $%a0");
-#line 392 "rl78-decode.opc"
+#line 391 "rl78-decode.opc"
ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
}
case 0x81:
{
/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */
-#line 386 "rl78-decode.opc"
+#line 385 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("btclr %e1%1, $%a0");
-#line 386 "rl78-decode.opc"
+#line 385 "rl78-decode.opc"
ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
}
case 0x82:
{
/** 0011 0001 1bit 0010 bt %s1, $%a0 */
-#line 378 "rl78-decode.opc"
+#line 377 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bt %s1, $%a0");
-#line 378 "rl78-decode.opc"
+#line 377 "rl78-decode.opc"
ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
}
case 0x83:
{
/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */
-#line 372 "rl78-decode.opc"
+#line 371 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bt %e1%1, $%a0");
-#line 372 "rl78-decode.opc"
+#line 371 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
}
case 0x84:
{
/** 0011 0001 1bit 0100 bf %s1, $%a0 */
-#line 339 "rl78-decode.opc"
+#line 338 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bf %s1, $%a0");
-#line 339 "rl78-decode.opc"
+#line 338 "rl78-decode.opc"
ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
}
case 0x85:
{
/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */
-#line 333 "rl78-decode.opc"
+#line 332 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("bf %e1%1, $%a0");
-#line 333 "rl78-decode.opc"
+#line 332 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
}
case 0x37:
{
/** 0011 0ra1 xchw %0, %1 */
-#line 1215 "rl78-decode.opc"
+#line 1214 "rl78-decode.opc"
int ra AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("xchw %0, %1");
-#line 1215 "rl78-decode.opc"
+#line 1214 "rl78-decode.opc"
ID(xch); W(); DR(AX); SRW(ra);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %e0%0, #%1");
-#line 717 "rl78-decode.opc"
+#line 716 "rl78-decode.opc"
ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("mov %e0%0, #%1");
-#line 711 "rl78-decode.opc"
+#line 710 "rl78-decode.opc"
ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("subc %0, #%1");
-#line 1154 "rl78-decode.opc"
+#line 1153 "rl78-decode.opc"
ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("subc %0, %1");
-#line 1151 "rl78-decode.opc"
+#line 1150 "rl78-decode.opc"
ID(subc); DR(A); SM(None, SADDR); Fzac;
}
op[0]);
}
SYNTAX("subc %0, #%1");
-#line 1142 "rl78-decode.opc"
+#line 1141 "rl78-decode.opc"
ID(subc); DR(A); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("subc %0, %e1%1");
-#line 1130 "rl78-decode.opc"
+#line 1129 "rl78-decode.opc"
ID(subc); DR(A); SM(HL, 0); Fzac;
}
op[0]);
}
SYNTAX("subc %0, %e1%1");
-#line 1139 "rl78-decode.opc"
+#line 1138 "rl78-decode.opc"
ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("subc %0, %e1%!1");
-#line 1127 "rl78-decode.opc"
+#line 1126 "rl78-decode.opc"
ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("cmp %e0%!0, #%1");
-#line 459 "rl78-decode.opc"
+#line 458 "rl78-decode.opc"
ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("mov %0, #%1");
-#line 696 "rl78-decode.opc"
+#line 695 "rl78-decode.opc"
ID(mov); DR(ES); SC(IMMU(1));
}
op[0]);
}
SYNTAX("cmpw %0, %e1%!1");
-#line 510 "rl78-decode.opc"
+#line 509 "rl78-decode.opc"
ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
}
case 0x47:
{
/** 0100 0ra1 cmpw %0, %1 */
-#line 519 "rl78-decode.opc"
+#line 518 "rl78-decode.opc"
int ra AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("cmpw %0, %1");
-#line 519 "rl78-decode.opc"
+#line 518 "rl78-decode.opc"
ID(cmp); W(); DR(AX); SRW(ra); Fzac;
}
op[0]);
}
SYNTAX("cmpw %0, #%1");
-#line 516 "rl78-decode.opc"
+#line 515 "rl78-decode.opc"
ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
}
op[0]);
}
SYNTAX("cmpw %0, %1");
-#line 522 "rl78-decode.opc"
+#line 521 "rl78-decode.opc"
ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %e0%0, %1");
-#line 714 "rl78-decode.opc"
+#line 713 "rl78-decode.opc"
ID(mov); DM(BC, IMMU(2)); SR(A);
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 660 "rl78-decode.opc"
+#line 659 "rl78-decode.opc"
ID(mov); DR(A); SM(BC, IMMU(2));
}
op[0]);
}
SYNTAX("cmp %0, #%1");
-#line 462 "rl78-decode.opc"
+#line 461 "rl78-decode.opc"
ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("cmp %0, %1");
-#line 489 "rl78-decode.opc"
+#line 488 "rl78-decode.opc"
ID(cmp); DR(A); SM(None, SADDR); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("cmp %0, #%1");
-#line 480 "rl78-decode.opc"
+#line 479 "rl78-decode.opc"
ID(cmp); DR(A); SC(IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("cmp %0, %e1%1");
-#line 468 "rl78-decode.opc"
+#line 467 "rl78-decode.opc"
ID(cmp); DR(A); SM(HL, 0); Fzac;
}
op[0]);
}
SYNTAX("cmp %0, %e1%1");
-#line 477 "rl78-decode.opc"
+#line 476 "rl78-decode.opc"
ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
}
op[0]);
}
SYNTAX("cmp %0, %e1%!1");
-#line 465 "rl78-decode.opc"
+#line 464 "rl78-decode.opc"
ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
}
case 0x57:
{
/** 0101 0reg mov %0, #%1 */
-#line 648 "rl78-decode.opc"
+#line 647 "rl78-decode.opc"
int reg AU = op[0] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("mov %0, #%1");
-#line 648 "rl78-decode.opc"
+#line 647 "rl78-decode.opc"
ID(mov); DRB(reg); SC(IMMU(1));
}
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 847 "rl78-decode.opc"
+#line 846 "rl78-decode.opc"
ID(mov); W(); DM(B, IMMU(2)); SR(AX);
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 838 "rl78-decode.opc"
+#line 837 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(B, IMMU(2));
}
op[0]);
}
SYNTAX("and %0, #%1");
-#line 291 "rl78-decode.opc"
+#line 290 "rl78-decode.opc"
ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("and %0, %1");
-#line 288 "rl78-decode.opc"
+#line 287 "rl78-decode.opc"
ID(and); DR(A); SM(None, SADDR); Fz;
}
op[0]);
}
SYNTAX("and %0, #%1");
-#line 279 "rl78-decode.opc"
+#line 278 "rl78-decode.opc"
ID(and); DR(A); SC(IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("and %0, %e1%1");
-#line 267 "rl78-decode.opc"
+#line 266 "rl78-decode.opc"
ID(and); DR(A); SM(HL, 0); Fz;
}
op[0]);
}
SYNTAX("and %0, %e1%1");
-#line 273 "rl78-decode.opc"
+#line 272 "rl78-decode.opc"
ID(and); DR(A); SM(HL, IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("and %0, %e1%!1");
-#line 264 "rl78-decode.opc"
+#line 263 "rl78-decode.opc"
ID(and); DR(A); SM(None, IMMU(2)); Fz;
}
case 0x67:
{
/** 0110 0rba mov %0, %1 */
-#line 651 "rl78-decode.opc"
+#line 650 "rl78-decode.opc"
int rba AU = op[0] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("mov %0, %1");
-#line 651 "rl78-decode.opc"
+#line 650 "rl78-decode.opc"
ID(mov); DR(A); SRB(rba);
}
case 0x07:
{
/** 0110 0001 0000 0reg add %0, %1 */
-#line 204 "rl78-decode.opc"
+#line 203 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("add %0, %1");
-#line 204 "rl78-decode.opc"
+#line 203 "rl78-decode.opc"
ID(add); DRB(reg); SR(A); Fzac;
}
case 0x0f:
{
/** 0110 0001 0000 1rba add %0, %1 */
-#line 198 "rl78-decode.opc"
+#line 197 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("add %0, %1");
-#line 198 "rl78-decode.opc"
+#line 197 "rl78-decode.opc"
ID(add); DR(A); SRB(rba); Fzac;
}
op[0], op[1]);
}
SYNTAX("addw %0, %e1%1");
-#line 247 "rl78-decode.opc"
+#line 246 "rl78-decode.opc"
ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
}
case 0x17:
{
/** 0110 0001 0001 0reg addc %0, %1 */
-#line 233 "rl78-decode.opc"
+#line 232 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("addc %0, %1");
-#line 233 "rl78-decode.opc"
+#line 232 "rl78-decode.opc"
ID(addc); DRB(reg); SR(A); Fzac;
}
case 0x1f:
{
/** 0110 0001 0001 1rba addc %0, %1 */
-#line 230 "rl78-decode.opc"
+#line 229 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("addc %0, %1");
-#line 230 "rl78-decode.opc"
+#line 229 "rl78-decode.opc"
ID(addc); DR(A); SRB(rba); Fzac;
}
case 0x27:
{
/** 0110 0001 0010 0reg sub %0, %1 */
-#line 1119 "rl78-decode.opc"
+#line 1118 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("sub %0, %1");
-#line 1119 "rl78-decode.opc"
+#line 1118 "rl78-decode.opc"
ID(sub); DRB(reg); SR(A); Fzac;
}
case 0x2f:
{
/** 0110 0001 0010 1rba sub %0, %1 */
-#line 1113 "rl78-decode.opc"
+#line 1112 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("sub %0, %1");
-#line 1113 "rl78-decode.opc"
+#line 1112 "rl78-decode.opc"
ID(sub); DR(A); SRB(rba); Fzac;
}
op[0], op[1]);
}
SYNTAX("subw %0, %e1%1");
-#line 1162 "rl78-decode.opc"
+#line 1161 "rl78-decode.opc"
ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
}
case 0x37:
{
/** 0110 0001 0011 0reg subc %0, %1 */
-#line 1148 "rl78-decode.opc"
+#line 1147 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("subc %0, %1");
-#line 1148 "rl78-decode.opc"
+#line 1147 "rl78-decode.opc"
ID(subc); DRB(reg); SR(A); Fzac;
}
case 0x3f:
{
/** 0110 0001 0011 1rba subc %0, %1 */
-#line 1145 "rl78-decode.opc"
+#line 1144 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("subc %0, %1");
-#line 1145 "rl78-decode.opc"
+#line 1144 "rl78-decode.opc"
ID(subc); DR(A); SRB(rba); Fzac;
}
case 0x47:
{
/** 0110 0001 0100 0reg cmp %0, %1 */
-#line 486 "rl78-decode.opc"
+#line 485 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("cmp %0, %1");
-#line 486 "rl78-decode.opc"
+#line 485 "rl78-decode.opc"
ID(cmp); DRB(reg); SR(A); Fzac;
}
case 0x4f:
{
/** 0110 0001 0100 1rba cmp %0, %1 */
-#line 483 "rl78-decode.opc"
+#line 482 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("cmp %0, %1");
-#line 483 "rl78-decode.opc"
+#line 482 "rl78-decode.opc"
ID(cmp); DR(A); SRB(rba); Fzac;
}
op[0], op[1]);
}
SYNTAX("cmpw %0, %e1%1");
-#line 513 "rl78-decode.opc"
+#line 512 "rl78-decode.opc"
ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
}
case 0x57:
{
/** 0110 0001 0101 0reg and %0, %1 */
-#line 285 "rl78-decode.opc"
+#line 284 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("and %0, %1");
-#line 285 "rl78-decode.opc"
+#line 284 "rl78-decode.opc"
ID(and); DRB(reg); SR(A); Fz;
}
case 0x5f:
{
/** 0110 0001 0101 1rba and %0, %1 */
-#line 282 "rl78-decode.opc"
+#line 281 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("and %0, %1");
-#line 282 "rl78-decode.opc"
+#line 281 "rl78-decode.opc"
ID(and); DR(A); SRB(rba); Fz;
}
op[0], op[1]);
}
SYNTAX("inc %e0%0");
-#line 563 "rl78-decode.opc"
+#line 562 "rl78-decode.opc"
ID(add); DM(HL, IMMU(1)); SC(1); Fza;
}
case 0x67:
{
/** 0110 0001 0110 0reg or %0, %1 */
-#line 937 "rl78-decode.opc"
+#line 936 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("or %0, %1");
-#line 937 "rl78-decode.opc"
+#line 936 "rl78-decode.opc"
ID(or); DRB(reg); SR(A); Fz;
}
case 0x6f:
{
/** 0110 0001 0110 1rba or %0, %1 */
-#line 934 "rl78-decode.opc"
+#line 933 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("or %0, %1");
-#line 934 "rl78-decode.opc"
+#line 933 "rl78-decode.opc"
ID(or); DR(A); SRB(rba); Fz;
}
op[0], op[1]);
}
SYNTAX("dec %e0%0");
-#line 530 "rl78-decode.opc"
+#line 529 "rl78-decode.opc"
ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
}
case 0x77:
{
/** 0110 0001 0111 0reg xor %0, %1 */
-#line 1241 "rl78-decode.opc"
+#line 1240 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("xor %0, %1");
-#line 1241 "rl78-decode.opc"
+#line 1240 "rl78-decode.opc"
ID(xor); DRB(reg); SR(A); Fz;
}
case 0x7f:
{
/** 0110 0001 0111 1rba xor %0, %1 */
-#line 1238 "rl78-decode.opc"
+#line 1237 "rl78-decode.opc"
int rba AU = op[1] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("xor %0, %1");
-#line 1238 "rl78-decode.opc"
+#line 1237 "rl78-decode.opc"
ID(xor); DR(A); SRB(rba); Fz;
}
op[0], op[1]);
}
SYNTAX("incw %e0%0");
-#line 577 "rl78-decode.opc"
+#line 576 "rl78-decode.opc"
ID(add); W(); DM(HL, IMMU(1)); SC(1);
}
op[0], op[1]);
}
SYNTAX("add %0, %e1%1");
-#line 186 "rl78-decode.opc"
+#line 185 "rl78-decode.opc"
ID(add); DR(A); SM2(HL, B, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("add %0, %e1%1");
-#line 192 "rl78-decode.opc"
+#line 191 "rl78-decode.opc"
ID(add); DR(A); SM2(HL, C, 0); Fzac;
}
case 0xf7:
{
/** 0110 0001 1nnn 01mm callt [%x0] */
-#line 412 "rl78-decode.opc"
+#line 411 "rl78-decode.opc"
int nnn AU = (op[1] >> 4) & 0x07;
-#line 412 "rl78-decode.opc"
+#line 411 "rl78-decode.opc"
int mm AU = op[1] & 0x03;
if (trace)
{
printf (" mm = 0x%x\n", mm);
}
SYNTAX("callt [%x0]");
-#line 412 "rl78-decode.opc"
+#line 411 "rl78-decode.opc"
ID(call); DM(None, 0x80 + mm*16 + nnn*2);
/*----------------------------------------------------------------------*/
case 0x8f:
{
/** 0110 0001 1000 1reg xch %0, %1 */
-#line 1200 "rl78-decode.opc"
+#line 1199 "rl78-decode.opc"
int reg AU = op[1] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("xch %0, %1");
-#line 1200 "rl78-decode.opc"
+#line 1199 "rl78-decode.opc"
/* Note: DECW uses reg == X, so this must follow DECW */
ID(xch); DR(A); SRB(reg);
op[0], op[1]);
}
SYNTAX("decw %e0%0");
-#line 544 "rl78-decode.opc"
+#line 543 "rl78-decode.opc"
ID(sub); W(); DM(HL, IMMU(1)); SC(1);
}
op[0], op[1]);
}
SYNTAX("addc %0, %e1%1");
-#line 218 "rl78-decode.opc"
+#line 217 "rl78-decode.opc"
ID(addc); DR(A); SM2(HL, B, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("addc %0, %e1%1");
-#line 221 "rl78-decode.opc"
+#line 220 "rl78-decode.opc"
ID(addc); DR(A); SM2(HL, C, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("sub %0, %e1%1");
-#line 1101 "rl78-decode.opc"
+#line 1100 "rl78-decode.opc"
ID(sub); DR(A); SM2(HL, B, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("sub %0, %e1%1");
-#line 1107 "rl78-decode.opc"
+#line 1106 "rl78-decode.opc"
ID(sub); DR(A); SM2(HL, C, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("xch %0, %1");
-#line 1204 "rl78-decode.opc"
+#line 1203 "rl78-decode.opc"
ID(xch); DR(A); SM(None, SADDR);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1197 "rl78-decode.opc"
+#line 1196 "rl78-decode.opc"
ID(xch); DR(A); SM2(HL, C, 0);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%!1");
-#line 1179 "rl78-decode.opc"
+#line 1178 "rl78-decode.opc"
ID(xch); DR(A); SM(None, IMMU(2));
}
op[0], op[1]);
}
SYNTAX("xch %0, %1");
-#line 1207 "rl78-decode.opc"
+#line 1206 "rl78-decode.opc"
ID(xch); DR(A); SM(None, SFR);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1188 "rl78-decode.opc"
+#line 1187 "rl78-decode.opc"
ID(xch); DR(A); SM(HL, 0);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1194 "rl78-decode.opc"
+#line 1193 "rl78-decode.opc"
ID(xch); DR(A); SM(HL, IMMU(1));
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1182 "rl78-decode.opc"
+#line 1181 "rl78-decode.opc"
ID(xch); DR(A); SM(DE, 0);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1185 "rl78-decode.opc"
+#line 1184 "rl78-decode.opc"
ID(xch); DR(A); SM(DE, IMMU(1));
}
op[0], op[1]);
}
SYNTAX("subc %0, %e1%1");
-#line 1133 "rl78-decode.opc"
+#line 1132 "rl78-decode.opc"
ID(subc); DR(A); SM2(HL, B, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("subc %0, %e1%1");
-#line 1136 "rl78-decode.opc"
+#line 1135 "rl78-decode.opc"
ID(subc); DR(A); SM2(HL, C, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("mov %0, %1");
-#line 702 "rl78-decode.opc"
+#line 701 "rl78-decode.opc"
ID(mov); DR(ES); SM(None, SADDR);
}
op[0], op[1]);
}
SYNTAX("xch %0, %e1%1");
-#line 1191 "rl78-decode.opc"
+#line 1190 "rl78-decode.opc"
ID(xch); DR(A); SM2(HL, B, 0);
}
op[0], op[1]);
}
SYNTAX("cmp %0, %e1%1");
-#line 471 "rl78-decode.opc"
+#line 470 "rl78-decode.opc"
ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("cmp %0, %e1%1");
-#line 474 "rl78-decode.opc"
+#line 473 "rl78-decode.opc"
ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
}
op[0], op[1]);
}
SYNTAX("bh $%a0");
-#line 319 "rl78-decode.opc"
+#line 318 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1070 "rl78-decode.opc"
+#line 1069 "rl78-decode.opc"
ID(skip); COND(C);
}
op[0], op[1]);
}
SYNTAX("mov %0, %e1%1");
-#line 639 "rl78-decode.opc"
+#line 638 "rl78-decode.opc"
ID(mov); DR(A); SM2(HL, B, 0);
}
case 0xfa:
{
/** 0110 0001 11rg 1010 call %0 */
-#line 409 "rl78-decode.opc"
+#line 408 "rl78-decode.opc"
int rg AU = (op[1] >> 4) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("call %0");
-#line 409 "rl78-decode.opc"
+#line 408 "rl78-decode.opc"
ID(call); DRW(rg);
}
op[0], op[1]);
}
SYNTAX("br ax");
-#line 359 "rl78-decode.opc"
+#line 358 "rl78-decode.opc"
ID(branch); DR(AX);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("brk");
-#line 367 "rl78-decode.opc"
+#line 366 "rl78-decode.opc"
ID(break);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("pop %s0");
-#line 965 "rl78-decode.opc"
+#line 964 "rl78-decode.opc"
ID(mov); W(); DR(PSW); SPOP();
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("movs %e0%0, %1");
-#line 787 "rl78-decode.opc"
+#line 786 "rl78-decode.opc"
ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
/*----------------------------------------------------------------------*/
case 0xff:
{
/** 0110 0001 11rb 1111 sel rb%1 */
-#line 1017 "rl78-decode.opc"
+#line 1016 "rl78-decode.opc"
int rb AU = (op[1] >> 4) & 0x03;
if (trace)
{
printf (" rb = 0x%x\n", rb);
}
SYNTAX("sel rb%1");
-#line 1017 "rl78-decode.opc"
+#line 1016 "rl78-decode.opc"
ID(sel); SC(rb);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("and %0, %e1%1");
-#line 270 "rl78-decode.opc"
+#line 269 "rl78-decode.opc"
ID(and); DR(A); SM2(HL, B, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("and %0, %e1%1");
-#line 276 "rl78-decode.opc"
+#line 275 "rl78-decode.opc"
ID(and); DR(A); SM2(HL, C, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("bnh $%a0");
-#line 322 "rl78-decode.opc"
+#line 321 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1076 "rl78-decode.opc"
+#line 1075 "rl78-decode.opc"
ID(skip); COND(NC);
}
op[0], op[1]);
}
SYNTAX("mov %e0%0, %1");
-#line 606 "rl78-decode.opc"
+#line 605 "rl78-decode.opc"
ID(mov); DM2(HL, B, 0); SR(A);
}
op[0], op[1]);
}
SYNTAX("ror %0, %1");
-#line 998 "rl78-decode.opc"
+#line 997 "rl78-decode.opc"
ID(ror); DR(A); SC(1);
}
op[0], op[1]);
}
SYNTAX("rolc %0, %1");
-#line 992 "rl78-decode.opc"
+#line 991 "rl78-decode.opc"
ID(rolc); DR(A); SC(1);
}
op[0], op[1]);
}
SYNTAX("push %s1");
-#line 973 "rl78-decode.opc"
+#line 972 "rl78-decode.opc"
ID(mov); W(); DPUSH(); SR(PSW);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("cmps %0, %e1%1");
-#line 505 "rl78-decode.opc"
+#line 504 "rl78-decode.opc"
ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("or %0, %e1%1");
-#line 922 "rl78-decode.opc"
+#line 921 "rl78-decode.opc"
ID(or); DR(A); SM2(HL, B, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("or %0, %e1%1");
-#line 928 "rl78-decode.opc"
+#line 927 "rl78-decode.opc"
ID(or); DR(A); SM2(HL, C, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1073 "rl78-decode.opc"
+#line 1072 "rl78-decode.opc"
ID(skip); COND(H);
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1085 "rl78-decode.opc"
+#line 1084 "rl78-decode.opc"
ID(skip); COND(Z);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("mov %0, %e1%1");
-#line 642 "rl78-decode.opc"
+#line 641 "rl78-decode.opc"
ID(mov); DR(A); SM2(HL, C, 0);
}
op[0], op[1]);
}
SYNTAX("rol %0, %1");
-#line 989 "rl78-decode.opc"
+#line 988 "rl78-decode.opc"
ID(rol); DR(A); SC(1);
}
op[0], op[1]);
}
SYNTAX("retb");
-#line 984 "rl78-decode.opc"
+#line 983 "rl78-decode.opc"
ID(reti);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("halt");
-#line 555 "rl78-decode.opc"
+#line 554 "rl78-decode.opc"
ID(halt);
/*----------------------------------------------------------------------*/
case 0xfe:
{
/** 0110 0001 111r 1110 rolwc %0, %1 */
-#line 995 "rl78-decode.opc"
+#line 994 "rl78-decode.opc"
int r AU = (op[1] >> 4) & 0x01;
if (trace)
{
printf (" r = 0x%x\n", r);
}
SYNTAX("rolwc %0, %1");
-#line 995 "rl78-decode.opc"
+#line 994 "rl78-decode.opc"
ID(rolc); W(); DRW(r); SC(1);
}
op[0], op[1]);
}
SYNTAX("xor %0, %e1%1");
-#line 1226 "rl78-decode.opc"
+#line 1225 "rl78-decode.opc"
ID(xor); DR(A); SM2(HL, B, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("xor %0, %e1%1");
-#line 1232 "rl78-decode.opc"
+#line 1231 "rl78-decode.opc"
ID(xor); DR(A); SM2(HL, C, 0); Fz;
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1079 "rl78-decode.opc"
+#line 1078 "rl78-decode.opc"
ID(skip); COND(NH);
}
op[0], op[1]);
}
SYNTAX("sk%c1");
-#line 1082 "rl78-decode.opc"
+#line 1081 "rl78-decode.opc"
ID(skip); COND(NZ);
}
op[0], op[1]);
}
SYNTAX("mov %e0%0, %1");
-#line 615 "rl78-decode.opc"
+#line 614 "rl78-decode.opc"
ID(mov); DM2(HL, C, 0); SR(A);
}
op[0], op[1]);
}
SYNTAX("rorc %0, %1");
-#line 1001 "rl78-decode.opc"
+#line 1000 "rl78-decode.opc"
ID(rorc); DR(A); SC(1);
/*----------------------------------------------------------------------*/
op[0], op[1]);
}
SYNTAX("reti");
-#line 981 "rl78-decode.opc"
+#line 980 "rl78-decode.opc"
ID(reti);
}
op[0], op[1]);
}
SYNTAX("stop");
-#line 1090 "rl78-decode.opc"
+#line 1089 "rl78-decode.opc"
ID(stop);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 850 "rl78-decode.opc"
+#line 849 "rl78-decode.opc"
ID(mov); W(); DM(C, IMMU(2)); SR(AX);
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 841 "rl78-decode.opc"
+#line 840 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(C, IMMU(2));
}
op[0]);
}
SYNTAX("or %0, #%1");
-#line 943 "rl78-decode.opc"
+#line 942 "rl78-decode.opc"
ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("or %0, %1");
-#line 940 "rl78-decode.opc"
+#line 939 "rl78-decode.opc"
ID(or); DR(A); SM(None, SADDR); Fz;
}
op[0]);
}
SYNTAX("or %0, #%1");
-#line 931 "rl78-decode.opc"
+#line 930 "rl78-decode.opc"
ID(or); DR(A); SC(IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("or %0, %e1%1");
-#line 919 "rl78-decode.opc"
+#line 918 "rl78-decode.opc"
ID(or); DR(A); SM(HL, 0); Fz;
}
op[0]);
}
SYNTAX("or %0, %e1%1");
-#line 925 "rl78-decode.opc"
+#line 924 "rl78-decode.opc"
ID(or); DR(A); SM(HL, IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("or %0, %e1%!1");
-#line 916 "rl78-decode.opc"
+#line 915 "rl78-decode.opc"
ID(or); DR(A); SM(None, IMMU(2)); Fz;
}
case 0x77:
{
/** 0111 0rba mov %0, %1 */
-#line 675 "rl78-decode.opc"
+#line 674 "rl78-decode.opc"
int rba AU = op[0] & 0x07;
if (trace)
{
printf (" rba = 0x%x\n", rba);
}
SYNTAX("mov %0, %1");
-#line 675 "rl78-decode.opc"
+#line 674 "rl78-decode.opc"
ID(mov); DRB(rba); SR(A);
}
case 0x70:
{
/** 0111 0001 0bit 0000 set1 %e0%!0 */
-#line 1022 "rl78-decode.opc"
+#line 1021 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("set1 %e0%!0");
-#line 1022 "rl78-decode.opc"
+#line 1021 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
}
case 0x71:
{
/** 0111 0001 0bit 0001 mov1 %0, cy */
-#line 779 "rl78-decode.opc"
+#line 778 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 %0, cy");
-#line 779 "rl78-decode.opc"
+#line 778 "rl78-decode.opc"
ID(mov); DM(None, SADDR); DB(bit); SCY();
}
case 0x72:
{
/** 0111 0001 0bit 0010 set1 %0 */
-#line 1040 "rl78-decode.opc"
+#line 1039 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("set1 %0");
-#line 1040 "rl78-decode.opc"
+#line 1039 "rl78-decode.opc"
ID(mov); DM(None, SADDR); DB(bit); SC(1);
/*----------------------------------------------------------------------*/
case 0x73:
{
/** 0111 0001 0bit 0011 clr1 %0 */
-#line 435 "rl78-decode.opc"
+#line 434 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("clr1 %0");
-#line 435 "rl78-decode.opc"
+#line 434 "rl78-decode.opc"
ID(mov); DM(None, SADDR); DB(bit); SC(0);
/*----------------------------------------------------------------------*/
case 0x74:
{
/** 0111 0001 0bit 0100 mov1 cy, %1 */
-#line 773 "rl78-decode.opc"
+#line 772 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 cy, %1");
-#line 773 "rl78-decode.opc"
+#line 772 "rl78-decode.opc"
ID(mov); DCY(); SM(None, SADDR); SB(bit);
}
case 0x75:
{
/** 0111 0001 0bit 0101 and1 cy, %s1 */
-#line 305 "rl78-decode.opc"
+#line 304 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("and1 cy, %s1");
-#line 305 "rl78-decode.opc"
+#line 304 "rl78-decode.opc"
ID(and); DCY(); SM(None, SADDR); SB(bit);
/*----------------------------------------------------------------------*/
case 0x76:
{
/** 0111 0001 0bit 0110 or1 cy, %s1 */
-#line 957 "rl78-decode.opc"
+#line 956 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("or1 cy, %s1");
-#line 957 "rl78-decode.opc"
+#line 956 "rl78-decode.opc"
ID(or); DCY(); SM(None, SADDR); SB(bit);
/*----------------------------------------------------------------------*/
case 0x77:
{
/** 0111 0001 0bit 0111 xor1 cy, %s1 */
-#line 1261 "rl78-decode.opc"
+#line 1260 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("xor1 cy, %s1");
-#line 1261 "rl78-decode.opc"
+#line 1260 "rl78-decode.opc"
ID(xor); DCY(); SM(None, SADDR); SB(bit);
/*----------------------------------------------------------------------*/
case 0x78:
{
/** 0111 0001 0bit 1000 clr1 %e0%!0 */
-#line 417 "rl78-decode.opc"
+#line 416 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("clr1 %e0%!0");
-#line 417 "rl78-decode.opc"
+#line 416 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
}
case 0x79:
{
/** 0111 0001 0bit 1001 mov1 %s0, cy */
-#line 782 "rl78-decode.opc"
+#line 781 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 %s0, cy");
-#line 782 "rl78-decode.opc"
+#line 781 "rl78-decode.opc"
ID(mov); DM(None, SFR); DB(bit); SCY();
/*----------------------------------------------------------------------*/
case 0x7a:
{
/** 0111 0001 0bit 1010 set1 %s0 */
-#line 1034 "rl78-decode.opc"
+#line 1033 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("set1 %s0");
-#line 1034 "rl78-decode.opc"
+#line 1033 "rl78-decode.opc"
op0 = SFR;
ID(mov); DM(None, op0); DB(bit); SC(1);
if (op0 == RL78_SFR_PSW && bit == 7)
case 0x7b:
{
/** 0111 0001 0bit 1011 clr1 %s0 */
-#line 429 "rl78-decode.opc"
+#line 428 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("clr1 %s0");
-#line 429 "rl78-decode.opc"
+#line 428 "rl78-decode.opc"
op0 = SFR;
ID(mov); DM(None, op0); DB(bit); SC(0);
if (op0 == RL78_SFR_PSW && bit == 7)
case 0x7c:
{
/** 0111 0001 0bit 1100 mov1 cy, %s1 */
-#line 776 "rl78-decode.opc"
+#line 775 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 cy, %s1");
-#line 776 "rl78-decode.opc"
+#line 775 "rl78-decode.opc"
ID(mov); DCY(); SM(None, SFR); SB(bit);
}
case 0x7d:
{
/** 0111 0001 0bit 1101 and1 cy, %s1 */
-#line 302 "rl78-decode.opc"
+#line 301 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("and1 cy, %s1");
-#line 302 "rl78-decode.opc"
+#line 301 "rl78-decode.opc"
ID(and); DCY(); SM(None, SFR); SB(bit);
}
case 0x7e:
{
/** 0111 0001 0bit 1110 or1 cy, %s1 */
-#line 954 "rl78-decode.opc"
+#line 953 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("or1 cy, %s1");
-#line 954 "rl78-decode.opc"
+#line 953 "rl78-decode.opc"
ID(or); DCY(); SM(None, SFR); SB(bit);
}
case 0x7f:
{
/** 0111 0001 0bit 1111 xor1 cy, %s1 */
-#line 1258 "rl78-decode.opc"
+#line 1257 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("xor1 cy, %s1");
-#line 1258 "rl78-decode.opc"
+#line 1257 "rl78-decode.opc"
ID(xor); DCY(); SM(None, SFR); SB(bit);
}
op[0], op[1]);
}
SYNTAX("set1 cy");
-#line 1031 "rl78-decode.opc"
+#line 1030 "rl78-decode.opc"
ID(mov); DCY(); SC(1);
}
case 0xf1:
{
/** 0111 0001 1bit 0001 mov1 %e0%0, cy */
-#line 761 "rl78-decode.opc"
+#line 760 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 %e0%0, cy");
-#line 761 "rl78-decode.opc"
+#line 760 "rl78-decode.opc"
ID(mov); DM(HL, 0); DB(bit); SCY();
}
case 0xf2:
{
/** 0111 0001 1bit 0010 set1 %e0%0 */
-#line 1025 "rl78-decode.opc"
+#line 1024 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("set1 %e0%0");
-#line 1025 "rl78-decode.opc"
+#line 1024 "rl78-decode.opc"
ID(mov); DM(HL, 0); DB(bit); SC(1);
}
case 0xf3:
{
/** 0111 0001 1bit 0011 clr1 %e0%0 */
-#line 420 "rl78-decode.opc"
+#line 419 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("clr1 %e0%0");
-#line 420 "rl78-decode.opc"
+#line 419 "rl78-decode.opc"
ID(mov); DM(HL, 0); DB(bit); SC(0);
}
case 0xf4:
{
/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */
-#line 767 "rl78-decode.opc"
+#line 766 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 cy, %e1%1");
-#line 767 "rl78-decode.opc"
+#line 766 "rl78-decode.opc"
ID(mov); DCY(); SM(HL, 0); SB(bit);
}
case 0xf5:
{
/** 0111 0001 1bit 0101 and1 cy, %e1%1 */
-#line 296 "rl78-decode.opc"
+#line 295 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("and1 cy, %e1%1");
-#line 296 "rl78-decode.opc"
+#line 295 "rl78-decode.opc"
ID(and); DCY(); SM(HL, 0); SB(bit);
}
case 0xf6:
{
/** 0111 0001 1bit 0110 or1 cy, %e1%1 */
-#line 948 "rl78-decode.opc"
+#line 947 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("or1 cy, %e1%1");
-#line 948 "rl78-decode.opc"
+#line 947 "rl78-decode.opc"
ID(or); DCY(); SM(HL, 0); SB(bit);
}
case 0xf7:
{
/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */
-#line 1252 "rl78-decode.opc"
+#line 1251 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("xor1 cy, %e1%1");
-#line 1252 "rl78-decode.opc"
+#line 1251 "rl78-decode.opc"
ID(xor); DCY(); SM(HL, 0); SB(bit);
}
op[0], op[1]);
}
SYNTAX("clr1 cy");
-#line 426 "rl78-decode.opc"
+#line 425 "rl78-decode.opc"
ID(mov); DCY(); SC(0);
}
case 0xf9:
{
/** 0111 0001 1bit 1001 mov1 %e0%0, cy */
-#line 764 "rl78-decode.opc"
+#line 763 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 %e0%0, cy");
-#line 764 "rl78-decode.opc"
+#line 763 "rl78-decode.opc"
ID(mov); DR(A); DB(bit); SCY();
}
case 0xfa:
{
/** 0111 0001 1bit 1010 set1 %0 */
-#line 1028 "rl78-decode.opc"
+#line 1027 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("set1 %0");
-#line 1028 "rl78-decode.opc"
+#line 1027 "rl78-decode.opc"
ID(mov); DR(A); DB(bit); SC(1);
}
case 0xfb:
{
/** 0111 0001 1bit 1011 clr1 %0 */
-#line 423 "rl78-decode.opc"
+#line 422 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("clr1 %0");
-#line 423 "rl78-decode.opc"
+#line 422 "rl78-decode.opc"
ID(mov); DR(A); DB(bit); SC(0);
}
case 0xfc:
{
/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */
-#line 770 "rl78-decode.opc"
+#line 769 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("mov1 cy, %e1%1");
-#line 770 "rl78-decode.opc"
+#line 769 "rl78-decode.opc"
ID(mov); DCY(); SR(A); SB(bit);
}
case 0xfd:
{
/** 0111 0001 1bit 1101 and1 cy, %1 */
-#line 299 "rl78-decode.opc"
+#line 298 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("and1 cy, %1");
-#line 299 "rl78-decode.opc"
+#line 298 "rl78-decode.opc"
ID(and); DCY(); SR(A); SB(bit);
}
case 0xfe:
{
/** 0111 0001 1bit 1110 or1 cy, %1 */
-#line 951 "rl78-decode.opc"
+#line 950 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("or1 cy, %1");
-#line 951 "rl78-decode.opc"
+#line 950 "rl78-decode.opc"
ID(or); DCY(); SR(A); SB(bit);
}
case 0xff:
{
/** 0111 0001 1bit 1111 xor1 cy, %1 */
-#line 1255 "rl78-decode.opc"
+#line 1254 "rl78-decode.opc"
int bit AU = (op[1] >> 4) & 0x07;
if (trace)
{
printf (" bit = 0x%x\n", bit);
}
SYNTAX("xor1 cy, %1");
-#line 1255 "rl78-decode.opc"
+#line 1254 "rl78-decode.opc"
ID(xor); DCY(); SR(A); SB(bit);
}
op[0], op[1]);
}
SYNTAX("not1 cy");
-#line 892 "rl78-decode.opc"
+#line 891 "rl78-decode.opc"
ID(xor); DCY(); SC(1);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 853 "rl78-decode.opc"
+#line 852 "rl78-decode.opc"
ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 844 "rl78-decode.opc"
+#line 843 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(BC, IMMU(2));
}
op[0]);
}
SYNTAX("xor %0, #%1");
-#line 1247 "rl78-decode.opc"
+#line 1246 "rl78-decode.opc"
ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("xor %0, %1");
-#line 1244 "rl78-decode.opc"
+#line 1243 "rl78-decode.opc"
ID(xor); DR(A); SM(None, SADDR); Fz;
}
op[0]);
}
SYNTAX("xor %0, #%1");
-#line 1235 "rl78-decode.opc"
+#line 1234 "rl78-decode.opc"
ID(xor); DR(A); SC(IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("xor %0, %e1%1");
-#line 1223 "rl78-decode.opc"
+#line 1222 "rl78-decode.opc"
ID(xor); DR(A); SM(HL, 0); Fz;
}
op[0]);
}
SYNTAX("xor %0, %e1%1");
-#line 1229 "rl78-decode.opc"
+#line 1228 "rl78-decode.opc"
ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
}
op[0]);
}
SYNTAX("xor %0, %e1%!1");
-#line 1220 "rl78-decode.opc"
+#line 1219 "rl78-decode.opc"
ID(xor); DR(A); SM(None, IMMU(2)); Fz;
}
case 0x87:
{
/** 1000 0reg inc %0 */
-#line 566 "rl78-decode.opc"
+#line 565 "rl78-decode.opc"
int reg AU = op[0] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("inc %0");
-#line 566 "rl78-decode.opc"
+#line 565 "rl78-decode.opc"
ID(add); DRB(reg); SC(1); Fza;
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 645 "rl78-decode.opc"
+#line 644 "rl78-decode.opc"
ID(mov); DR(A); SM(SP, IMMU(1));
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 627 "rl78-decode.opc"
+#line 626 "rl78-decode.opc"
ID(mov); DR(A); SM(DE, 0);
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 630 "rl78-decode.opc"
+#line 629 "rl78-decode.opc"
ID(mov); DR(A); SM(DE, IMMU(1));
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 633 "rl78-decode.opc"
+#line 632 "rl78-decode.opc"
ID(mov); DR(A); SM(HL, 0);
}
op[0]);
}
SYNTAX("mov %0, %e1%1");
-#line 636 "rl78-decode.opc"
+#line 635 "rl78-decode.opc"
ID(mov); DR(A); SM(HL, IMMU(1));
}
op[0]);
}
SYNTAX("mov %0, %1");
-#line 669 "rl78-decode.opc"
+#line 668 "rl78-decode.opc"
ID(mov); DR(A); SM(None, SADDR);
}
op[0]);
}
SYNTAX("mov %0, %s1");
-#line 666 "rl78-decode.opc"
+#line 665 "rl78-decode.opc"
ID(mov); DR(A); SM(None, SFR);
}
op[0]);
}
SYNTAX("mov %0, %e1%!1");
-#line 624 "rl78-decode.opc"
+#line 623 "rl78-decode.opc"
ID(mov); DR(A); SM(None, IMMU(2));
}
case 0x97:
{
/** 1001 0reg dec %0 */
-#line 533 "rl78-decode.opc"
+#line 532 "rl78-decode.opc"
int reg AU = op[0] & 0x07;
if (trace)
{
printf (" reg = 0x%x\n", reg);
}
SYNTAX("dec %0");
-#line 533 "rl78-decode.opc"
+#line 532 "rl78-decode.opc"
ID(sub); DRB(reg); SC(1); Fza;
}
op[0]);
}
SYNTAX("mov %0, %1");
-#line 621 "rl78-decode.opc"
+#line 620 "rl78-decode.opc"
ID(mov); DM(SP, IMMU(1)); SR(A);
}
op[0]);
}
SYNTAX("mov %e0%0,%1");
-#line 594 "rl78-decode.opc"
+#line 593 "rl78-decode.opc"
ID(mov); DM(DE, 0); SR(A);
}
op[0]);
}
SYNTAX("mov %e0%0, %1");
-#line 600 "rl78-decode.opc"
+#line 599 "rl78-decode.opc"
ID(mov); DM(DE, IMMU(1)); SR(A);
}
op[0]);
}
SYNTAX("mov %e0%0,%1");
-#line 603 "rl78-decode.opc"
+#line 602 "rl78-decode.opc"
ID(mov); DM(HL, 0); SR(A);
}
op[0]);
}
SYNTAX("mov %e0%0, %1");
-#line 612 "rl78-decode.opc"
+#line 611 "rl78-decode.opc"
ID(mov); DM(HL, IMMU(1)); SR(A);
}
op[0]);
}
SYNTAX("mov %0, %1");
-#line 726 "rl78-decode.opc"
+#line 725 "rl78-decode.opc"
ID(mov); DM(None, SADDR); SR(A);
}
op[0]);
}
SYNTAX("mov %0, %1");
-#line 756 "rl78-decode.opc"
+#line 755 "rl78-decode.opc"
ID(mov); DM(None, SFR); SR(A);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %e0%!0, %1");
-#line 591 "rl78-decode.opc"
+#line 590 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); SR(A);
}
op[0]);
}
SYNTAX("inc %e0%!0");
-#line 560 "rl78-decode.opc"
+#line 559 "rl78-decode.opc"
ID(add); DM(None, IMMU(2)); SC(1); Fza;
}
case 0xa7:
{
/** 1010 0rg1 incw %0 */
-#line 580 "rl78-decode.opc"
+#line 579 "rl78-decode.opc"
int rg AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("incw %0");
-#line 580 "rl78-decode.opc"
+#line 579 "rl78-decode.opc"
ID(add); W(); DRW(rg); SC(1);
}
op[0]);
}
SYNTAX("incw %e0%!0");
-#line 574 "rl78-decode.opc"
+#line 573 "rl78-decode.opc"
ID(add); W(); DM(None, IMMU(2)); SC(1);
}
op[0]);
}
SYNTAX("inc %0");
-#line 569 "rl78-decode.opc"
+#line 568 "rl78-decode.opc"
ID(add); DM(None, SADDR); SC(1); Fza;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("incw %0");
-#line 583 "rl78-decode.opc"
+#line 582 "rl78-decode.opc"
ID(add); W(); DM(None, SADDR); SC(1);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("movw %0, %1");
-#line 826 "rl78-decode.opc"
+#line 825 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(SP, IMMU(1));
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 814 "rl78-decode.opc"
+#line 813 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(DE, 0);
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 817 "rl78-decode.opc"
+#line 816 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(DE, IMMU(1));
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 820 "rl78-decode.opc"
+#line 819 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(HL, 0);
}
op[0]);
}
SYNTAX("movw %0, %e1%1");
-#line 823 "rl78-decode.opc"
+#line 822 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(HL, IMMU(1));
}
op[0]);
}
SYNTAX("movw %0, %1");
-#line 856 "rl78-decode.opc"
+#line 855 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(None, SADDR);
}
op[0]);
}
SYNTAX("movw %0, %s1");
-#line 859 "rl78-decode.opc"
+#line 858 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(None, SFR);
}
op[0]);
}
SYNTAX("movw %0, %e1%!1");
-#line 810 "rl78-decode.opc"
+#line 809 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(None, IMMU(2));
op[0]);
}
SYNTAX("dec %e0%!0");
-#line 527 "rl78-decode.opc"
+#line 526 "rl78-decode.opc"
ID(sub); DM(None, IMMU(2)); SC(1); Fza;
}
case 0xb7:
{
/** 1011 0rg1 decw %0 */
-#line 547 "rl78-decode.opc"
+#line 546 "rl78-decode.opc"
int rg AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("decw %0");
-#line 547 "rl78-decode.opc"
+#line 546 "rl78-decode.opc"
ID(sub); W(); DRW(rg); SC(1);
}
op[0]);
}
SYNTAX("decw %e0%!0");
-#line 541 "rl78-decode.opc"
+#line 540 "rl78-decode.opc"
ID(sub); W(); DM(None, IMMU(2)); SC(1);
}
op[0]);
}
SYNTAX("dec %0");
-#line 536 "rl78-decode.opc"
+#line 535 "rl78-decode.opc"
ID(sub); DM(None, SADDR); SC(1); Fza;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("decw %0");
-#line 550 "rl78-decode.opc"
+#line 549 "rl78-decode.opc"
ID(sub); W(); DM(None, SADDR); SC(1);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("movw %0, %1");
-#line 807 "rl78-decode.opc"
+#line 806 "rl78-decode.opc"
ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
}
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 795 "rl78-decode.opc"
+#line 794 "rl78-decode.opc"
ID(mov); W(); DM(DE, 0); SR(AX);
}
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 798 "rl78-decode.opc"
+#line 797 "rl78-decode.opc"
ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
}
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 801 "rl78-decode.opc"
+#line 800 "rl78-decode.opc"
ID(mov); W(); DM(HL, 0); SR(AX);
}
op[0]);
}
SYNTAX("movw %e0%0, %1");
-#line 804 "rl78-decode.opc"
+#line 803 "rl78-decode.opc"
ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
}
op[0]);
}
SYNTAX("movw %0, %1");
-#line 871 "rl78-decode.opc"
+#line 870 "rl78-decode.opc"
ID(mov); W(); DM(None, SADDR); SR(AX);
}
op[0]);
}
SYNTAX("movw %0, %1");
-#line 877 "rl78-decode.opc"
+#line 876 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SR(AX);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("movw %e0%!0, %1");
-#line 792 "rl78-decode.opc"
+#line 791 "rl78-decode.opc"
ID(mov); W(); DM(None, IMMU(2)); SR(AX);
}
case 0xc6:
{
/** 1100 0rg0 pop %0 */
-#line 962 "rl78-decode.opc"
+#line 961 "rl78-decode.opc"
int rg AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("pop %0");
-#line 962 "rl78-decode.opc"
+#line 961 "rl78-decode.opc"
ID(mov); W(); DRW(rg); SPOP();
}
case 0xc7:
{
/** 1100 0rg1 push %1 */
-#line 970 "rl78-decode.opc"
+#line 969 "rl78-decode.opc"
int rg AU = (op[0] >> 1) & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("push %1");
-#line 970 "rl78-decode.opc"
+#line 969 "rl78-decode.opc"
ID(mov); W(); DPUSH(); SRW(rg);
}
op[0]);
}
SYNTAX("mov %0, #%1");
-#line 618 "rl78-decode.opc"
+#line 617 "rl78-decode.opc"
ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("movw %0, #%1");
-#line 868 "rl78-decode.opc"
+#line 867 "rl78-decode.opc"
ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
}
op[0]);
}
SYNTAX("mov %e0%0, #%1");
-#line 597 "rl78-decode.opc"
+#line 596 "rl78-decode.opc"
ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("movw %0, #%1");
-#line 874 "rl78-decode.opc"
+#line 873 "rl78-decode.opc"
ID(mov); W(); DM(None, SFR); SC(IMMU(2));
}
op[0]);
}
SYNTAX("mov %e0%0, #%1");
-#line 609 "rl78-decode.opc"
+#line 608 "rl78-decode.opc"
ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
}
op[0]);
}
SYNTAX("mov %0, #%1");
-#line 723 "rl78-decode.opc"
+#line 722 "rl78-decode.opc"
ID(mov); DM(None, SADDR); SC(IMMU(1));
}
op[0]);
}
SYNTAX("mov %s0, #%1");
-#line 729 "rl78-decode.opc"
+#line 728 "rl78-decode.opc"
op0 = SFR;
op1 = IMMU(1);
ID(mov); DM(None, op0); SC(op1);
op[0]);
}
SYNTAX("mov %e0%!0, #%1");
-#line 588 "rl78-decode.opc"
+#line 587 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
}
case 0xd3:
{
/** 1101 00rg cmp0 %0 */
-#line 497 "rl78-decode.opc"
+#line 496 "rl78-decode.opc"
int rg AU = op[0] & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("cmp0 %0");
-#line 497 "rl78-decode.opc"
+#line 496 "rl78-decode.opc"
ID(cmp); DRB(rg); SC(0); Fzac;
}
op[0]);
}
SYNTAX("cmp0 %0");
-#line 500 "rl78-decode.opc"
+#line 499 "rl78-decode.opc"
ID(cmp); DM(None, SADDR); SC(0); Fzac;
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("cmp0 %e0%!0");
-#line 494 "rl78-decode.opc"
+#line 493 "rl78-decode.opc"
ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
}
op[0]);
}
SYNTAX("mulu x");
-#line 882 "rl78-decode.opc"
+#line 881 "rl78-decode.opc"
ID(mulu);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("ret");
-#line 978 "rl78-decode.opc"
+#line 977 "rl78-decode.opc"
ID(ret);
}
op[0]);
}
SYNTAX("mov %0, %1");
-#line 690 "rl78-decode.opc"
+#line 689 "rl78-decode.opc"
ID(mov); DR(X); SM(None, SADDR);
}
op[0]);
}
SYNTAX("mov %0, %e1%!1");
-#line 687 "rl78-decode.opc"
+#line 686 "rl78-decode.opc"
ID(mov); DR(X); SM(None, IMMU(2));
}
case 0xfa:
{
/** 11ra 1010 movw %0, %1 */
-#line 865 "rl78-decode.opc"
+#line 864 "rl78-decode.opc"
int ra AU = (op[0] >> 4) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("movw %0, %1");
-#line 865 "rl78-decode.opc"
+#line 864 "rl78-decode.opc"
ID(mov); W(); DRW(ra); SM(None, SADDR);
}
case 0xfb:
{
/** 11ra 1011 movw %0, %e1%!1 */
-#line 862 "rl78-decode.opc"
+#line 861 "rl78-decode.opc"
int ra AU = (op[0] >> 4) & 0x03;
if (trace)
{
printf (" ra = 0x%x\n", ra);
}
SYNTAX("movw %0, %e1%!1");
-#line 862 "rl78-decode.opc"
+#line 861 "rl78-decode.opc"
ID(mov); W(); DRW(ra); SM(None, IMMU(2));
}
op[0]);
}
SYNTAX("bc $%a0");
-#line 313 "rl78-decode.opc"
+#line 312 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
}
op[0]);
}
SYNTAX("bz $%a0");
-#line 325 "rl78-decode.opc"
+#line 324 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
}
op[0]);
}
SYNTAX("bnc $%a0");
-#line 316 "rl78-decode.opc"
+#line 315 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
}
op[0]);
}
SYNTAX("bnz $%a0");
-#line 328 "rl78-decode.opc"
+#line 327 "rl78-decode.opc"
ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
/*----------------------------------------------------------------------*/
case 0xe3:
{
/** 1110 00rg oneb %0 */
-#line 900 "rl78-decode.opc"
+#line 899 "rl78-decode.opc"
int rg AU = op[0] & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("oneb %0");
-#line 900 "rl78-decode.opc"
+#line 899 "rl78-decode.opc"
ID(mov); DRB(rg); SC(1);
}
op[0]);
}
SYNTAX("oneb %0");
-#line 903 "rl78-decode.opc"
+#line 902 "rl78-decode.opc"
ID(mov); DM(None, SADDR); SC(1);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("oneb %e0%!0");
-#line 897 "rl78-decode.opc"
+#line 896 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); SC(1);
}
op[0]);
}
SYNTAX("onew %0");
-#line 908 "rl78-decode.opc"
+#line 907 "rl78-decode.opc"
ID(mov); DR(AX); SC(1);
}
op[0]);
}
SYNTAX("onew %0");
-#line 911 "rl78-decode.opc"
+#line 910 "rl78-decode.opc"
ID(mov); DR(BC); SC(1);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %0, %1");
-#line 678 "rl78-decode.opc"
+#line 677 "rl78-decode.opc"
ID(mov); DR(B); SM(None, SADDR);
}
op[0]);
}
SYNTAX("mov %0, %e1%!1");
-#line 672 "rl78-decode.opc"
+#line 671 "rl78-decode.opc"
ID(mov); DR(B); SM(None, IMMU(2));
}
op[0]);
}
SYNTAX("br !%!a0");
-#line 347 "rl78-decode.opc"
+#line 346 "rl78-decode.opc"
ID(branch); DC(IMMU(3));
}
op[0]);
}
SYNTAX("br %!a0");
-#line 350 "rl78-decode.opc"
+#line 349 "rl78-decode.opc"
ID(branch); DC(IMMU(2));
}
op[0]);
}
SYNTAX("br $%!a0");
-#line 353 "rl78-decode.opc"
+#line 352 "rl78-decode.opc"
ID(branch); DC(pc+IMMS(2)+3);
}
op[0]);
}
SYNTAX("br $%a0");
-#line 356 "rl78-decode.opc"
+#line 355 "rl78-decode.opc"
ID(branch); DC(pc+IMMS(1)+2);
}
case 0xf3:
{
/** 1111 00rg clrb %0 */
-#line 443 "rl78-decode.opc"
+#line 442 "rl78-decode.opc"
int rg AU = op[0] & 0x03;
if (trace)
{
printf (" rg = 0x%x\n", rg);
}
SYNTAX("clrb %0");
-#line 443 "rl78-decode.opc"
+#line 442 "rl78-decode.opc"
ID(mov); DRB(rg); SC(0);
}
op[0]);
}
SYNTAX("clrb %0");
-#line 446 "rl78-decode.opc"
+#line 445 "rl78-decode.opc"
ID(mov); DM(None, SADDR); SC(0);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("clrb %e0%!0");
-#line 440 "rl78-decode.opc"
+#line 439 "rl78-decode.opc"
ID(mov); DM(None, IMMU(2)); SC(0);
}
op[0]);
}
SYNTAX("clrw %0");
-#line 451 "rl78-decode.opc"
+#line 450 "rl78-decode.opc"
ID(mov); DR(AX); SC(0);
}
op[0]);
}
SYNTAX("clrw %0");
-#line 454 "rl78-decode.opc"
+#line 453 "rl78-decode.opc"
ID(mov); DR(BC); SC(0);
/*----------------------------------------------------------------------*/
op[0]);
}
SYNTAX("mov %0, %1");
-#line 684 "rl78-decode.opc"
+#line 683 "rl78-decode.opc"
ID(mov); DR(C); SM(None, SADDR);
}
op[0]);
}
SYNTAX("mov %0, %e1%!1");
-#line 681 "rl78-decode.opc"
+#line 680 "rl78-decode.opc"
ID(mov); DR(C); SM(None, IMMU(2));
}
op[0]);
}
SYNTAX("call !%!a0");
-#line 400 "rl78-decode.opc"
+#line 399 "rl78-decode.opc"
ID(call); DC(IMMU(3));
}
op[0]);
}
SYNTAX("call %!a0");
-#line 403 "rl78-decode.opc"
+#line 402 "rl78-decode.opc"
ID(call); DC(IMMU(2));
}
op[0]);
}
SYNTAX("call $%!a0");
-#line 406 "rl78-decode.opc"
+#line 405 "rl78-decode.opc"
ID(call); DC(pc+IMMS(2)+3);
}
op[0]);
}
SYNTAX("brk1");
-#line 364 "rl78-decode.opc"
+#line 363 "rl78-decode.opc"
ID(break);
}
break;
}
-#line 1266 "rl78-decode.opc"
+#line 1265 "rl78-decode.opc"
return rl78->n_bytes;
}
print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
break;
case DSP_REG_X:
- fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
+ fprintf_fn (stream, "%s", sx_tab[(field_b >> 6) & 3]);
break;
case DSP_REG_Y:
- fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
+ fprintf_fn (stream, "%s", sy_tab[(field_b >> 4) & 3]);
break;
case A_MACH:
fprintf_fn (stream, "mach");
else
shown_one = 1;
- info->fprintf_func (info->stream, v850_reg_names[first]);
+ info->fprintf_func (info->stream, "%s", v850_reg_names[first]);
for (bit++; bit < 32; bit++)
if ((mask & (1 << bit)) == 0)
projects / fpga / lx-cpu1 / binutils-tumbl.git / commitdiff