+ \r
+ #if defined(CFG_VLE)\r
+ #define VLE_VAL MAS2_VLE\r
+ #else\r
+ #define VLE_VAL 0\r
+ #endif\r
+\r
+#define SRAM_START 0x40000000\r
+#define FLASH_START 0x00000000\r
+#define PERIPHERAL_START 0xfff00000\r
+\r
+ \r
+ cfg_MMU:\r
+\r
+#***************************************************/\r
+# setup MMU */\r
+#***************************************************/\r
+\r
+#TLB Entry 0 = 1M Internal flash \r
+ LOAD_ADDR_32(5, 0x10000000 + (0<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_4M )\r
+ mtspr SPR_MAS1,r5 \r
+ LOAD_ADDR_32(5, FLASH_START + VLE_VAL )\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, FLASH_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+\r
+\r
+#TLB Entry 1 = Peripheral bridge and BAM\r
+ LOAD_ADDR_32(5, 0x10000000 + (1<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_1M)\r
+ mtspr SPR_MAS1,r5\r
+ LOAD_ADDR_32(5, PERIPHERAL_START + VLE_VAL + MAS2_I)\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, PERIPHERAL_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+\r
+\r
+#TLB Entry 2 = External RAM. Skip this. \r
+\r
+#TLB Entry 3 = Internal SRAM\r
+ LOAD_ADDR_32(5, 0x10000000+(3<<16))\r
+ mtspr SPR_MAS0,r5 \r
+ LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_256K )\r
+ mtspr SPR_MAS1,r5 \r
+ LOAD_ADDR_32(5, SRAM_START + VLE_VAL )\r
+ mtspr SPR_MAS2,r5 \r
+ LOAD_ADDR_32(5, SRAM_START + MAS3_FULL_ACCESS )\r
+ mtspr SPR_MAS3,r5\r
+ msync\r
+ isync\r
+ tlbwe\r
+ isync\r
+ blr\r
+ \r
+ \r