Major split up of mpc5604b and mpc5606s unique stuff

diff --git a/arch/generic/linux/kernel/irq_types.h b/arch/generic/linux/kernel/irq_types.h
index c638de25a9375235ecc8e2142048ce4b77a70c66..2b8d63845660bd98f0d456f0b6b5e45f357c73ab 100644 (file)
--- a/arch/generic/linux/kernel/irq_types.h
+++ b/arch/generic/linux/kernel/irq_types.h
@@ -293,7 +293,7 @@ typedef enum
     RESERVED75,             // 5606-214\r
     RESERVED76,             // 5606-215\r
     RESERVED77,             // 5606-216\r
-#else if defined (CFG_MPC5606S)\r
+#elif defined (CFG_MPC5606S)\r
     EMIOS_0_GFR_F8_F9,      // 5606-141\r
     EMIOS_0_GFR_F10_F11,    // 5606-142\r
     EMIOS_0_GFR_F12_F13,    // 5606-143\r

diff --git a/arch/ppc/mpc55xx/drivers/Adc.c b/arch/ppc/mpc55xx/drivers/Adc.c
index 3e1abd1e3f532170ab132abdfaeb782852b9a37a..c49d97dc9191e2a38e4763a9f2b37d500e887996 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Adc.c
+++ b/arch/ppc/mpc55xx/drivers/Adc.c
@@ -27,11 +27,11 @@
 #include "arc.h"\r
 \r
 /* Uncomment and use DMA for 5606 only if you now what you are doing */\r
-#define DONT_USE_DMA_IN_ADC_MPC5606S\r
+#define DONT_USE_DMA_IN_ADC_MPC560X\r
 \r
 /* Are we gonna use Dma? */\r
-#if (  !defined(CFG_MPC5606S) || \\r
-      ( defined(CFG_MPC5606S) && !defined(DONT_USE_DMA_IN_ADC_MPC5606S) ) )\r
+#if ( !defined(CFG_MPC560X) || \\r
+      ( defined(CFG_MPC5606S) && !defined(DONT_USE_DMA_IN_ADC_MPC560X) ) )\r
        #define ADC_USES_DMA\r
        #include "Dma.h"\r
 #endif\r
@@ -42,7 +42,7 @@
 \r
 #define ADC_GROUP0             0\r
 \r
-#if !defined(CFG_MPC5606S)\r
+#if !defined(CFG_MPC560X)\r
 typedef union\r
 {\r
   vuint32_t R;\r
@@ -209,7 +209,7 @@ typedef enum
 }Adc_StateType;\r
 \r
 /* Function prototypes. */\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
 static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr);\r
 static void Adc_ConfigureADCInterrupts (void);\r
 #else\r
@@ -263,7 +263,7 @@ Std_ReturnType ValidateGroup(Adc_GroupType group,Adc_APIServiceIDType api)
 Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr)\r
 {\r
   (void)ConfigPtr;\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
 \r
   if (E_OK == Adc_CheckDeInit())\r
   {\r
@@ -369,13 +369,13 @@ Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr)
     adcState = ADC_UNINIT;\r
   }\r
   return (E_OK);\r
-#endif /* ENDOF defined(CFG_MPC5606S) */\r
+#endif /* ENDOF defined(CFG_MPC560X) */\r
 }\r
 #endif\r
 \r
 Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr)\r
 {\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
 \r
   if (E_OK == Adc_CheckInit(ConfigPtr))\r
   {\r
@@ -649,7 +649,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
                  adcGroup->groupCallback();\r
          }\r
        #endif\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
                  /* Disable trigger normal conversions for ADC0 */\r
                  ADC_0.MCR.B.NSTART=0;\r
 #else\r
@@ -672,9 +672,9 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
                Dma_ConfigureDestinationAddress((uint32_t)adcGroup->status->currResultBufPtr, adcGroup->dmaResultChannel);\r
 #endif\r
 \r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
                ADC_0.IMR.B.MSKECH = 1;\r
-         ADC_0.MCR.B.NSTART=1;\r
+           ADC_0.MCR.B.NSTART=1;\r
 #else\r
                /* Set single scan enable bit */\r
                EQADC.CFCR[group].B.SSE = 1;\r
@@ -691,7 +691,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
                        adcGroup->groupCallback();\r
                  }\r
                #endif\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
                  /* Disable trigger normal conversions for ADC0 */\r
                  ADC_0.MCR.B.NSTART=0;\r
 #else\r
@@ -712,9 +712,9 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
 #endif\r
                        adcGroup->status->groupStatus = ADC_COMPLETED;\r
 \r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
                        ADC_0.IMR.B.MSKECH = 1;\r
-                 ADC_0.MCR.B.NSTART=1;\r
+                   ADC_0.MCR.B.NSTART=1;\r
 #else\r
                        /* Set single scan enable bit */\r
                        EQADC.CFCR[group].B.SSE = 1;\r
@@ -723,7 +723,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
                else\r
                {\r
                  /* Sample completed. */\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
                  /* Disable trigger normal conversions for ADC*/\r
                  ADC_0.MCR.B.NSTART=0;\r
 #else\r
@@ -746,7 +746,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group)
        }\r
   }\r
 }\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
 void Adc_Group0ConversionComplete (void)\r
 {\r
        /* Clear ECH Flag and disable interruput */\r
@@ -763,7 +763,11 @@ void Adc_Group0ConversionComplete (void)
                /* Copy to result buffer */\r
                for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; index++)\r
                {\r
+#if defined(CFG_MPC5606S)\r
                        AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+#else\r
+                       AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
+#endif\r
                }\r
 #endif\r
 \r
@@ -804,7 +808,6 @@ void Adc_ConfigureADCInterrupts (void)
 #if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
 void Adc_StartGroupConversion (Adc_GroupType group)\r
 {\r
-       uint32 groupChannelIdMask = 0;\r
        Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group];\r
 \r
        /* Run development error check. */\r
@@ -839,6 +842,9 @@ void Adc_StartGroupConversion (Adc_GroupType group)
                ADC_0.MCR.B.OWREN = 1;\r
 \r
                /* Set Conversion Time. */\r
+#if defined(CFG_MPC5606S)\r
+               uint32 groupChannelIdMask = 0;\r
+\r
                ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
                ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
                ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
@@ -848,21 +854,53 @@ void Adc_StartGroupConversion (Adc_GroupType group)
                        groupChannelIdMask |= (1 << groupPtr->channelList[i]);\r
                }\r
 \r
-               /* Enable Normal conversion */\r
-               ADC_0.NCMR[1].R = groupChannelIdMask;\r
-\r
 #if defined(ADC_USES_DMA)\r
                ADC_0.DMAE.R = 0x01;\r
-\r
                /* Enable DMA Transfer */\r
                ADC_0.DMAR[1].R = groupChannelIdMask;\r
-\r
                Dma_StartChannel(DMA_ADC_GROUP0_RESULT_CHANNEL);        /* Enable EDMA channel for ADC */\r
 #endif\r
 \r
+               /* Enable Normal conversion */\r
+               ADC_0.NCMR[1].R = groupChannelIdMask;\r
+\r
                /* Enable Channel Interrupt */\r
                ADC_0.CIMR[1].R = groupChannelIdMask;\r
 \r
+#else\r
+               uint32 groupChannelIdMask[3] = {0,0,0};\r
+\r
+               ADC_0.CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+               ADC_0.CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+               ADC_0.CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+               ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+               ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+               ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+               ADC_0.CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH;\r
+               ADC_0.CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP;\r
+               ADC_0.CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP;\r
+\r
+               for(uint8 i =0; i < groupPtr->numberOfChannels; i++)\r
+               {\r
+                       if(groupPtr->channelList[i] <= 15){\r
+                               groupChannelIdMask[0] |= (1 << groupPtr->channelList[i]);\r
+                       }else if((groupPtr->channelList[i] >= 32) && (groupPtr->channelList[i] <=47)){\r
+                               groupChannelIdMask[1] |= (1 << (groupPtr->channelList[i] - 32));\r
+                       }else if((groupPtr->channelList[i] >= 64) && (groupPtr->channelList[i] <=95)){\r
+                               groupChannelIdMask[2] |= (1 << (groupPtr->channelList[i] - 64));\r
+                       }\r
+               }\r
+\r
+               /* Enable Normal conversion */\r
+               ADC_0.NCMR[0].R = groupChannelIdMask[0];\r
+               ADC_0.NCMR[1].R = groupChannelIdMask[1];\r
+               ADC_0.NCMR[2].R = groupChannelIdMask[2];\r
+\r
+               /* Enable Channel Interrupt */\r
+               ADC_0.CIMR[0].R = groupChannelIdMask[0];\r
+               ADC_0.CIMR[1].R = groupChannelIdMask[1];\r
+               ADC_0.CIMR[2].R = groupChannelIdMask[2];\r
+#endif\r
                /* Clear interrupts */\r
                ADC_0.ISR.B.ECH = 1;\r
                /* Enable ECH interrupt */\r

diff --git a/arch/ppc/mpc55xx/drivers/Gpt.c b/arch/ppc/mpc55xx/drivers/Gpt.c
index 2356100c7e211232d00a0be30e90e8ebe6dc89a9..8fae322a7b710644e2cab9323a60051c8ddff5d6 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Gpt.c
+++ b/arch/ppc/mpc55xx/drivers/Gpt.c
@@ -203,7 +203,7 @@ GPT_ISR( 8 )
 #if defined(CFG_MPC560X)\r
        #if defined(CFG_MPC5606S)\r
                #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_3\r
-       #else if defined(CFG_MPC5604B)\r
+       #elif defined(CFG_MPC5604B)\r
                #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_5\r
        #endif\r
 #endif\r

diff --git a/arch/ppc/mpc55xx/drivers/Pwm.c b/arch/ppc/mpc55xx/drivers/Pwm.c
index ad4e07da255fd55dcb160707850a50b26aef106b..b7027ff4b9afca625b534171e74b468f2dbd6201 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Pwm.c
+++ b/arch/ppc/mpc55xx/drivers/Pwm.c
@@ -33,7 +33,10 @@
 #include "arc.h"\r
 #endif\r
 \r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC5604B)\r
+       #define PWM_RUNTIME_CHANNEL_COUNT       56\r
+    #define CHANNELS_OK (Channel <= PWM_MAX_CHANNEL-1)\r
+#elif defined(CFG_MPC5606S)\r
        #define PWM_RUNTIME_CHANNEL_COUNT       48\r
     #define CHANNELS_OK (((Channel <= PWM_MAX_CHANNEL-1) && (Channel >= 40)) || ((Channel <= 23) && (Channel >= 16)))\r
 #else\r
@@ -104,7 +107,7 @@ static void calcPeriodTicksAndPrescaler(
        uint32_t pre_global = 0;\r
        uint32_t f_in = 0;\r
 \r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
        Pwm_ChannelType channel = channelConfig->channel;\r
 \r
        if(channel <= PWM_NUMBER_OF_EACH_EMIOS-1) {\r
@@ -151,7 +154,7 @@ static void configureChannel(Pwm_ChannelType channel_iterator, const Pwm_Channel
 \r
        Pwm_ChannelType channel = channelConfig->channel;\r
 \r
-       #if defined(CFG_MPC5606S)\r
+       #if defined(CFG_MPC560X)\r
                volatile struct EMIOS_tag *emiosHw;\r
                if(channel <= PWM_NUMBER_OF_EACH_EMIOS-1) {\r
                        emiosHw = &EMIOS_0;\r
@@ -244,7 +247,7 @@ void Pwm_Init(const Pwm_ConfigType* ConfigPtr) {
         #endif\r
     #endif\r
 \r
-       #if defined(CFG_MPC5606S)\r
+       #if defined(CFG_MPC560X)\r
 \r
                PwmConfigPtr = ConfigPtr;\r
                /* Clock scaler uses system clock (~64MHz) as source, so prescaler 64 => 1MHz. */\r
@@ -293,7 +296,125 @@ void Pwm_Init(const Pwm_ConfigType* ConfigPtr) {
                 // Pwm_DisableNotification(channel);\r
 \r
                 // Install ISR\r
-                       #if defined(CFG_MPC5606S)\r
+                       #if defined(CFG_MPC5604B)\r
+                               switch(channel)\r
+                               {\r
+                               case 0:\r
+                               case 1:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F0_F1),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 2:\r
+                               case 3:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F2_F3),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 4:\r
+                               case 5:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F4_F5),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 6:\r
+                               case 7:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F6_F7),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 8:\r
+                               case 9:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F8_F9),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 10:\r
+                               case 11:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F10_F11),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 12:\r
+                               case 13:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F12_F13),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 14:\r
+                               case 15:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F14_F15),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 16:\r
+                               case 17:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F16_F17),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 18:\r
+                               case 19:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F18_F19),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 20:\r
+                               case 21:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F20_F21),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 22:\r
+                               case 23:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F22_F23),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 24:\r
+                               case 25:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F24_F25),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 26:\r
+                               case 27:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F26_F27),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 28:\r
+                               case 29:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F0_F1),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 30:\r
+                               case 31:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F2_F3),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 32:\r
+                               case 33:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F4_F5),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 34:\r
+                               case 35:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F6_F7),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 36:\r
+                               case 37:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F8_F9),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 38:\r
+                               case 39:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F10_F11),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 40:\r
+                               case 41:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F12_F13),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 42:\r
+                               case 43:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F14_F15),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 44:\r
+                               case 45:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F16_F17),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 46:\r
+                               case 47:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F18_F19),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 48:\r
+                               case 49:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F20_F21),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 50:\r
+                               case 51:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F22_F23),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 52:\r
+                               case 53:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F24_F25),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               case 54:\r
+                               case 55:\r
+                                       ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F26_F27),PWM_ISR_PRIORITY, 0);\r
+                                       break;\r
+                               default:\r
+                                       break;\r
+                               }\r
+                       #elif defined(CFG_MPC5606S)\r
                                switch(channel)\r
                                {\r
                                case 16:\r
@@ -419,7 +540,7 @@ void inline Pwm_DeInitChannel(Pwm_ChannelType Channel) {
        #if defined(CFG_MPC5516)\r
         // Set the disable bit for this channel\r
        EMIOS.UCDIS.R |= (1 << (31 - Channel));\r
-    #elif defined(CFG_MPC5606S)\r
+    #elif defined(CFG_MPC560X)\r
         // Set the disable bit for this channel\r
         if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
         {\r
@@ -461,7 +582,7 @@ void Pwm_DeInit() {
 \r
                EMIOS.MCR.B.MDIS = 1;\r
 \r
-    #elif defined(CFG_MPC5606S)\r
+    #elif defined(CFG_MPC560X)\r
 \r
                EMIOS_0.MCR.B.MDIS = 1;\r
                EMIOS_1.MCR.B.MDIS = 1;\r
@@ -504,7 +625,7 @@ void Pwm_DeInit() {
                        /* Timer instant for the period to restart */\r
                        EMIOS.CH[Channel].CBDR.R = Period;\r
 \r
-               #elif defined(CFG_MPC5606S)\r
+               #elif defined(CFG_MPC560X)\r
 \r
                        if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
                        {\r
@@ -559,7 +680,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
                 */\r
                EMIOS.CH[Channel].CADR.R = leading_edge_position;\r
 \r
-       #elif defined(CFG_MPC5606S)\r
+       #elif defined(CFG_MPC560X)\r
 \r
                if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
                {\r
@@ -594,7 +715,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
 \r
                        EMIOS.CH[Channel].CADR.R = 0;\r
 \r
-               #elif defined(CFG_MPC5606S)\r
+               #elif defined(CFG_MPC560X)\r
 \r
 \r
                        for (Pwm_ChannelType channel_iterator = 0; channel_iterator < PWM_NUMBER_OF_CHANNELS; channel_iterator++)\r
@@ -639,7 +760,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
 \r
                        return EMIOS.CH[Channel].CSR.B.UCOUT;\r
 \r
-               #elif defined(CFG_MPC5606S)\r
+               #elif defined(CFG_MPC560X)\r
 \r
                        if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
                        {\r
@@ -669,7 +790,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
 \r
                        EMIOS.CH[Channel].CCR.B.FEN = 0;\r
 \r
-               #elif defined(CFG_MPC5606S)\r
+               #elif defined(CFG_MPC560X)\r
 \r
                        if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
                        {\r
@@ -698,7 +819,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
 \r
                        EMIOS.CH[Channel].CCR.B.FEN = 1;\r
 \r
-               #elif defined(CFG_MPC5606S)\r
+               #elif defined(CFG_MPC560X)\r
 \r
                        if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1)\r
                        {\r
@@ -739,7 +860,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle)
                                EMIOS.CH[emios_ch].CSR.B.FLAG = 1;\r
                        }\r
                }\r
-        #elif defined(CFG_MPC5606S)\r
+        #elif defined(CFG_MPC560X)\r
                        uint32_t flagmask_0 = EMIOS_0.GFR.R;\r
                        uint32_t flagmask_1 = EMIOS_1.GFR.R;\r
 \r

diff --git a/arch/ppc/mpc55xx/kernel/irq_types.h b/arch/ppc/mpc55xx/kernel/irq_types.h
index d7722e6cb3dbd7a2cd0efa032d2189babfa0a22e..dff619e1590c5f1646588525e97dab104fbe1623 100644 (file)
--- a/arch/ppc/mpc55xx/kernel/irq_types.h
+++ b/arch/ppc/mpc55xx/kernel/irq_types.h
@@ -291,7 +291,7 @@ typedef enum
     RESERVED75,             // 5606-214\r
     RESERVED76,             // 5606-215\r
     RESERVED77,             // 5606-216\r
-#else if defined (CFG_MPC5606S)\r
+#elif defined (CFG_MPC5606S)\r
     EMIOS_0_GFR_F8_F9,      // 5606-141\r
     EMIOS_0_GFR_F10_F11,    // 5606-142\r
     EMIOS_0_GFR_F12_F13,    // 5606-143\r