From: jcar Date: Tue, 14 Feb 2012 15:35:35 +0000 (+0100) Subject: Major split up of mpc5604b and mpc5606s unique stuff X-Git-Url: https://rtime.felk.cvut.cz/gitweb/arc.git/commitdiff_plain/a805728bf2156591ea0b54c2c26fd690e43d9b2e Major split up of mpc5604b and mpc5606s unique stuff --- diff --git a/arch/generic/linux/kernel/irq_types.h b/arch/generic/linux/kernel/irq_types.h index c638de25..2b8d6384 100644 --- a/arch/generic/linux/kernel/irq_types.h +++ b/arch/generic/linux/kernel/irq_types.h @@ -293,7 +293,7 @@ typedef enum RESERVED75, // 5606-214 RESERVED76, // 5606-215 RESERVED77, // 5606-216 -#else if defined (CFG_MPC5606S) +#elif defined (CFG_MPC5606S) EMIOS_0_GFR_F8_F9, // 5606-141 EMIOS_0_GFR_F10_F11, // 5606-142 EMIOS_0_GFR_F12_F13, // 5606-143 diff --git a/arch/ppc/mpc55xx/drivers/Adc.c b/arch/ppc/mpc55xx/drivers/Adc.c index 3e1abd1e..c49d97dc 100644 --- a/arch/ppc/mpc55xx/drivers/Adc.c +++ b/arch/ppc/mpc55xx/drivers/Adc.c @@ -27,11 +27,11 @@ #include "arc.h" /* Uncomment and use DMA for 5606 only if you now what you are doing */ -#define DONT_USE_DMA_IN_ADC_MPC5606S +#define DONT_USE_DMA_IN_ADC_MPC560X /* Are we gonna use Dma? */ -#if ( !defined(CFG_MPC5606S) || \ - ( defined(CFG_MPC5606S) && !defined(DONT_USE_DMA_IN_ADC_MPC5606S) ) ) +#if ( !defined(CFG_MPC560X) || \ + ( defined(CFG_MPC5606S) && !defined(DONT_USE_DMA_IN_ADC_MPC560X) ) ) #define ADC_USES_DMA #include "Dma.h" #endif @@ -42,7 +42,7 @@ #define ADC_GROUP0 0 -#if !defined(CFG_MPC5606S) +#if !defined(CFG_MPC560X) typedef union { vuint32_t R; @@ -209,7 +209,7 @@ typedef enum }Adc_StateType; /* Function prototypes. */ -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) static void Adc_ConfigureADC (const Adc_ConfigType *ConfigPtr); static void Adc_ConfigureADCInterrupts (void); #else @@ -263,7 +263,7 @@ Std_ReturnType ValidateGroup(Adc_GroupType group,Adc_APIServiceIDType api) Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr) { (void)ConfigPtr; -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) if (E_OK == Adc_CheckDeInit()) { @@ -369,13 +369,13 @@ Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr) adcState = ADC_UNINIT; } return (E_OK); -#endif /* ENDOF defined(CFG_MPC5606S) */ +#endif /* ENDOF defined(CFG_MPC560X) */ } #endif Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr) { -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) if (E_OK == Adc_CheckInit(ConfigPtr)) { @@ -649,7 +649,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group) adcGroup->groupCallback(); } #endif -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) /* Disable trigger normal conversions for ADC0 */ ADC_0.MCR.B.NSTART=0; #else @@ -672,9 +672,9 @@ void Adc_GroupConversionComplete (Adc_GroupType group) Dma_ConfigureDestinationAddress((uint32_t)adcGroup->status->currResultBufPtr, adcGroup->dmaResultChannel); #endif -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) ADC_0.IMR.B.MSKECH = 1; - ADC_0.MCR.B.NSTART=1; + ADC_0.MCR.B.NSTART=1; #else /* Set single scan enable bit */ EQADC.CFCR[group].B.SSE = 1; @@ -691,7 +691,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group) adcGroup->groupCallback(); } #endif -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) /* Disable trigger normal conversions for ADC0 */ ADC_0.MCR.B.NSTART=0; #else @@ -712,9 +712,9 @@ void Adc_GroupConversionComplete (Adc_GroupType group) #endif adcGroup->status->groupStatus = ADC_COMPLETED; -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) ADC_0.IMR.B.MSKECH = 1; - ADC_0.MCR.B.NSTART=1; + ADC_0.MCR.B.NSTART=1; #else /* Set single scan enable bit */ EQADC.CFCR[group].B.SSE = 1; @@ -723,7 +723,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group) else { /* Sample completed. */ -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) /* Disable trigger normal conversions for ADC*/ ADC_0.MCR.B.NSTART=0; #else @@ -746,7 +746,7 @@ void Adc_GroupConversionComplete (Adc_GroupType group) } } } -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) void Adc_Group0ConversionComplete (void) { /* Clear ECH Flag and disable interruput */ @@ -763,7 +763,11 @@ void Adc_Group0ConversionComplete (void) /* Copy to result buffer */ for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; index++) { +#if defined(CFG_MPC5606S) AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA; +#else + AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = ADC_0.CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA; +#endif } #endif @@ -804,7 +808,6 @@ void Adc_ConfigureADCInterrupts (void) #if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) void Adc_StartGroupConversion (Adc_GroupType group) { - uint32 groupChannelIdMask = 0; Adc_GroupDefType *groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[group]; /* Run development error check. */ @@ -839,6 +842,9 @@ void Adc_StartGroupConversion (Adc_GroupType group) ADC_0.MCR.B.OWREN = 1; /* Set Conversion Time. */ +#if defined(CFG_MPC5606S) + uint32 groupChannelIdMask = 0; + ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH; ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP; ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP; @@ -848,21 +854,53 @@ void Adc_StartGroupConversion (Adc_GroupType group) groupChannelIdMask |= (1 << groupPtr->channelList[i]); } - /* Enable Normal conversion */ - ADC_0.NCMR[1].R = groupChannelIdMask; - #if defined(ADC_USES_DMA) ADC_0.DMAE.R = 0x01; - /* Enable DMA Transfer */ ADC_0.DMAR[1].R = groupChannelIdMask; - Dma_StartChannel(DMA_ADC_GROUP0_RESULT_CHANNEL); /* Enable EDMA channel for ADC */ #endif + /* Enable Normal conversion */ + ADC_0.NCMR[1].R = groupChannelIdMask; + /* Enable Channel Interrupt */ ADC_0.CIMR[1].R = groupChannelIdMask; +#else + uint32 groupChannelIdMask[3] = {0,0,0}; + + ADC_0.CTR[0].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH; + ADC_0.CTR[0].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP; + ADC_0.CTR[0].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP; + ADC_0.CTR[1].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH; + ADC_0.CTR[1].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP; + ADC_0.CTR[1].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP; + ADC_0.CTR[2].B.INPLATCH = groupPtr->adcChannelConvTime.INPLATCH; + ADC_0.CTR[2].B.INPCMP = groupPtr->adcChannelConvTime.INPCMP; + ADC_0.CTR[2].B.INPSAMP = groupPtr->adcChannelConvTime.INPSAMP; + + for(uint8 i =0; i < groupPtr->numberOfChannels; i++) + { + if(groupPtr->channelList[i] <= 15){ + groupChannelIdMask[0] |= (1 << groupPtr->channelList[i]); + }else if((groupPtr->channelList[i] >= 32) && (groupPtr->channelList[i] <=47)){ + groupChannelIdMask[1] |= (1 << (groupPtr->channelList[i] - 32)); + }else if((groupPtr->channelList[i] >= 64) && (groupPtr->channelList[i] <=95)){ + groupChannelIdMask[2] |= (1 << (groupPtr->channelList[i] - 64)); + } + } + + /* Enable Normal conversion */ + ADC_0.NCMR[0].R = groupChannelIdMask[0]; + ADC_0.NCMR[1].R = groupChannelIdMask[1]; + ADC_0.NCMR[2].R = groupChannelIdMask[2]; + + /* Enable Channel Interrupt */ + ADC_0.CIMR[0].R = groupChannelIdMask[0]; + ADC_0.CIMR[1].R = groupChannelIdMask[1]; + ADC_0.CIMR[2].R = groupChannelIdMask[2]; +#endif /* Clear interrupts */ ADC_0.ISR.B.ECH = 1; /* Enable ECH interrupt */ diff --git a/arch/ppc/mpc55xx/drivers/Gpt.c b/arch/ppc/mpc55xx/drivers/Gpt.c index 2356100c..8fae322a 100644 --- a/arch/ppc/mpc55xx/drivers/Gpt.c +++ b/arch/ppc/mpc55xx/drivers/Gpt.c @@ -203,7 +203,7 @@ GPT_ISR( 8 ) #if defined(CFG_MPC560X) #if defined(CFG_MPC5606S) #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_3 - #else if defined(CFG_MPC5604B) + #elif defined(CFG_MPC5604B) #define GPT_CHANNEL_PIT_LAST GPT_CHANNEL_PIT_5 #endif #endif diff --git a/arch/ppc/mpc55xx/drivers/Pwm.c b/arch/ppc/mpc55xx/drivers/Pwm.c index ad4e07da..b7027ff4 100644 --- a/arch/ppc/mpc55xx/drivers/Pwm.c +++ b/arch/ppc/mpc55xx/drivers/Pwm.c @@ -33,7 +33,10 @@ #include "arc.h" #endif -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC5604B) + #define PWM_RUNTIME_CHANNEL_COUNT 56 + #define CHANNELS_OK (Channel <= PWM_MAX_CHANNEL-1) +#elif defined(CFG_MPC5606S) #define PWM_RUNTIME_CHANNEL_COUNT 48 #define CHANNELS_OK (((Channel <= PWM_MAX_CHANNEL-1) && (Channel >= 40)) || ((Channel <= 23) && (Channel >= 16))) #else @@ -104,7 +107,7 @@ static void calcPeriodTicksAndPrescaler( uint32_t pre_global = 0; uint32_t f_in = 0; -#if defined(CFG_MPC5606S) +#if defined(CFG_MPC560X) Pwm_ChannelType channel = channelConfig->channel; if(channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -151,7 +154,7 @@ static void configureChannel(Pwm_ChannelType channel_iterator, const Pwm_Channel Pwm_ChannelType channel = channelConfig->channel; - #if defined(CFG_MPC5606S) + #if defined(CFG_MPC560X) volatile struct EMIOS_tag *emiosHw; if(channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { emiosHw = &EMIOS_0; @@ -244,7 +247,7 @@ void Pwm_Init(const Pwm_ConfigType* ConfigPtr) { #endif #endif - #if defined(CFG_MPC5606S) + #if defined(CFG_MPC560X) PwmConfigPtr = ConfigPtr; /* Clock scaler uses system clock (~64MHz) as source, so prescaler 64 => 1MHz. */ @@ -293,7 +296,125 @@ void Pwm_Init(const Pwm_ConfigType* ConfigPtr) { // Pwm_DisableNotification(channel); // Install ISR - #if defined(CFG_MPC5606S) + #if defined(CFG_MPC5604B) + switch(channel) + { + case 0: + case 1: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F0_F1),PWM_ISR_PRIORITY, 0); + break; + case 2: + case 3: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F2_F3),PWM_ISR_PRIORITY, 0); + break; + case 4: + case 5: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F4_F5),PWM_ISR_PRIORITY, 0); + break; + case 6: + case 7: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F6_F7),PWM_ISR_PRIORITY, 0); + break; + case 8: + case 9: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F8_F9),PWM_ISR_PRIORITY, 0); + break; + case 10: + case 11: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F10_F11),PWM_ISR_PRIORITY, 0); + break; + case 12: + case 13: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F12_F13),PWM_ISR_PRIORITY, 0); + break; + case 14: + case 15: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F14_F15),PWM_ISR_PRIORITY, 0); + break; + case 16: + case 17: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F16_F17),PWM_ISR_PRIORITY, 0); + break; + case 18: + case 19: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F18_F19),PWM_ISR_PRIORITY, 0); + break; + case 20: + case 21: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F20_F21),PWM_ISR_PRIORITY, 0); + break; + case 22: + case 23: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F22_F23),PWM_ISR_PRIORITY, 0); + break; + case 24: + case 25: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F24_F25),PWM_ISR_PRIORITY, 0); + break; + case 26: + case 27: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_0_GFR_F26_F27),PWM_ISR_PRIORITY, 0); + break; + case 28: + case 29: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F0_F1),PWM_ISR_PRIORITY, 0); + break; + case 30: + case 31: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F2_F3),PWM_ISR_PRIORITY, 0); + break; + case 32: + case 33: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F4_F5),PWM_ISR_PRIORITY, 0); + break; + case 34: + case 35: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F6_F7),PWM_ISR_PRIORITY, 0); + break; + case 36: + case 37: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F8_F9),PWM_ISR_PRIORITY, 0); + break; + case 38: + case 39: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F10_F11),PWM_ISR_PRIORITY, 0); + break; + case 40: + case 41: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F12_F13),PWM_ISR_PRIORITY, 0); + break; + case 42: + case 43: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F14_F15),PWM_ISR_PRIORITY, 0); + break; + case 44: + case 45: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F16_F17),PWM_ISR_PRIORITY, 0); + break; + case 46: + case 47: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F18_F19),PWM_ISR_PRIORITY, 0); + break; + case 48: + case 49: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F20_F21),PWM_ISR_PRIORITY, 0); + break; + case 50: + case 51: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F22_F23),PWM_ISR_PRIORITY, 0); + break; + case 52: + case 53: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F24_F25),PWM_ISR_PRIORITY, 0); + break; + case 54: + case 55: + ISR_INSTALL_ISR2("PwmIsr", Pwm_Isr, (IrqType)(EMIOS_1_GFR_F26_F27),PWM_ISR_PRIORITY, 0); + break; + default: + break; + } + #elif defined(CFG_MPC5606S) switch(channel) { case 16: @@ -419,7 +540,7 @@ void inline Pwm_DeInitChannel(Pwm_ChannelType Channel) { #if defined(CFG_MPC5516) // Set the disable bit for this channel EMIOS.UCDIS.R |= (1 << (31 - Channel)); - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) // Set the disable bit for this channel if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -461,7 +582,7 @@ void Pwm_DeInit() { EMIOS.MCR.B.MDIS = 1; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) EMIOS_0.MCR.B.MDIS = 1; EMIOS_1.MCR.B.MDIS = 1; @@ -504,7 +625,7 @@ void Pwm_DeInit() { /* Timer instant for the period to restart */ EMIOS.CH[Channel].CBDR.R = Period; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -559,7 +680,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) */ EMIOS.CH[Channel].CADR.R = leading_edge_position; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -594,7 +715,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) EMIOS.CH[Channel].CADR.R = 0; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) for (Pwm_ChannelType channel_iterator = 0; channel_iterator < PWM_NUMBER_OF_CHANNELS; channel_iterator++) @@ -639,7 +760,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) return EMIOS.CH[Channel].CSR.B.UCOUT; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -669,7 +790,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) EMIOS.CH[Channel].CCR.B.FEN = 0; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -698,7 +819,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) EMIOS.CH[Channel].CCR.B.FEN = 1; - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) if(Channel <= PWM_NUMBER_OF_EACH_EMIOS-1) { @@ -739,7 +860,7 @@ void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) EMIOS.CH[emios_ch].CSR.B.FLAG = 1; } } - #elif defined(CFG_MPC5606S) + #elif defined(CFG_MPC560X) uint32_t flagmask_0 = EMIOS_0.GFR.R; uint32_t flagmask_1 = EMIOS_1.GFR.R; diff --git a/arch/ppc/mpc55xx/kernel/irq_types.h b/arch/ppc/mpc55xx/kernel/irq_types.h index d7722e6c..dff619e1 100644 --- a/arch/ppc/mpc55xx/kernel/irq_types.h +++ b/arch/ppc/mpc55xx/kernel/irq_types.h @@ -291,7 +291,7 @@ typedef enum RESERVED75, // 5606-214 RESERVED76, // 5606-215 RESERVED77, // 5606-216 -#else if defined (CFG_MPC5606S) +#elif defined (CFG_MPC5606S) EMIOS_0_GFR_F8_F9, // 5606-141 EMIOS_0_GFR_F10_F11, // 5606-142 EMIOS_0_GFR_F12_F13, // 5606-143