--- /dev/null
+/_build
+/_compiled
+/config.omk
+/config.target
+/config.omk-default
+/Doxyfile
+/linkarch
+cscope.files
+cscope.out
--- /dev/null
+common/Makefile
\ No newline at end of file
--- /dev/null
+common/Makefile.omk
\ No newline at end of file
--- /dev/null
+common/Makefile.rules
\ No newline at end of file
--- /dev/null
+../common/app/Makefile
\ No newline at end of file
--- /dev/null
+../common/app/Makefile.omk
\ No newline at end of file
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+#za bin_programs se dava nazev programu
+bin_PROGRAMS = armtest_leds
+
+# za nazev_programu_SOURCES = se davaji vsechny c zdrojaky, ktere se maji prelozit, oddelovac je mezernik
+armtest_leds_SOURCES = main.c
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (14745000) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+#error Fosc out of range (10MHz-25MHz)\r
+#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Philips LPC210X LED Example\r
+//\r
+// Description\r
+// -----------\r
+// This example demonstrates writing to the GPIO port by using four leds connected to P0.16, P0.17, P0.18, P0.19\r
+// (It is also a way to see if the initialization functions are correct)\r
+//version 1.0 15/08/2005\r
+//Author : Guillaume LAGARRIGUE\r
+////////////////////////////////////////////////////////////////////////////////\r
+\r
+#include <types.h>\r
+#include <LPC210x.h>\r
+#include "config.h"\r
+#include "armVIC.h"\r
+\r
+/*////////////////////////////////////////////////////////INITIALISATION FUNCTIONS///////////////////////////////////*/\r
+\r
+\r
+/**\r
+ * Function Name: lowInit()\r
+ *\r
+ * Description:\r
+ * This function starts up the PLL then sets up the GPIO pins before\r
+ * waiting for the PLL to lock. It finally engages the PLL and\r
+ * returns\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ * \r
+ */\r
+static void lowInit(void) {\r
+ // set PLL multiplier & divisor.\r
+ // values computed from config.h\r
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;\r
+\r
+ // enable PLL\r
+ PLLCON = PLLCON_PLLE;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+\r
+ // setup the parallel port pin\r
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output\r
+ IOSET = PIO_ONE_BITS; // set the ONEs output\r
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction\r
+\r
+ // wait for PLL lock\r
+ while (!(PLLSTAT & PLLSTAT_LOCK))\r
+ continue;\r
+\r
+ // enable & connect PLL\r
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+\r
+ // setup & enable the MAM\r
+ MAMTIM = MAMTIM_CYCLES;\r
+ MAMCR = MAMCR_FULL;\r
+\r
+ // set the peripheral bus speed\r
+ // value computed from config.h\r
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed\r
+}\r
+\r
+\r
+/**\r
+ * Function Name: sysInit()\r
+ *\r
+ * Description:\r
+ * This function is responsible for initializing the program\r
+ * specific hardware\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ * \r
+ */\r
+static void sysInit(void) {\r
+ lowInit(); // setup clocks and processor port pins\r
+\r
+ // set the interrupt controller defaults\r
+ #define RAM_RUN\r
+ #if defined(RAM_RUN)\r
+\r
+ MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM\r
+ #elif defined(ROM_RUN)\r
+\r
+ MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH\r
+ #else\r
+ #error RUN_MODE not defined!\r
+ #endif\r
+\r
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts\r
+ VICIntSelect = 0x00000000; // clear all FIQ selections\r
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()\r
+\r
+ // wdtInit(); // initialize the watchdog timer\r
+ // initSysTime(); // initialize the system timer\r
+ // uart0Init(UART_BAUD(HOST_BAUD), UART_8N1, UART_FIFO_8); // setup the UART\r
+}\r
+\r
+\r
+\r
+/*////////////////////////////LEDS INITIALISATION///////////////////////*/\r
+\r
+#define NUM_LEDS 4\r
+static int leds[] = { 0x10000, 0x20000, 0x40000, 0x80000 };\r
+static int All_leds = 0xF0000;\r
+\r
+\r
+/**\r
+ * Initializes leds.\r
+ */\r
+static void\r
+ledInit() {\r
+ IODIR |= 0x000F0000; /*leds connected to P0.16 17 18 & 19 should blink*/\r
+ IOSET = 0x000F0000; /* all leds are switched on */\r
+}\r
+\r
+/**\r
+ * Switches the leds off.\r
+ * @param led switched off led number. (integer)\r
+ */\r
+static void /* Ioclr.i =1 => IOset.i cleared */\r
+ledOff(int led) {\r
+ IOCLR = led;\r
+}\r
+\r
+/**\r
+ * Switches the leds on. \r
+ * @param led switched on led number. (integer)\r
+ */\r
+static void /* Ioset.i = 1 => P0.i = 1 */\r
+ledOn(int led) {\r
+ IOSET = led;\r
+}\r
+\r
+/**\r
+ * Creates a delay\r
+ * @param d duration (unit not defined yet)\r
+ */\r
+void\r
+delay(int d) {\r
+ volatile int x;\r
+ int i;\r
+ for (i = 0; i < 10; i++)\r
+ for(x = d; x; --x)\r
+ ;\r
+}\r
+\r
+\r
+\r
+/*/////////////////////////////////////MAIN///////////////////////////////*/\r
+\r
+/**\r
+ * Makes the leds blink four times together then two times one after one\r
+ * \r
+ * \r
+ */\r
+int\r
+main(void) {\r
+\r
+ sysInit();\r
+\r
+ int i;\r
+ MAMCR = 2;\r
+ ledInit();\r
+ while (1) {\r
+ for (i=0; i < 4 ; i++) {\r
+ ledOn(All_leds);\r
+ delay ( 20000 );\r
+ ledOff (All_leds);\r
+ }\r
+\r
+ for (i = 0; i < NUM_LEDS; ++i) {\r
+ ledOn(leds[i]);\r
+ delay(20000);\r
+ }\r
+ for (i = 0; i < NUM_LEDS; ++i) {\r
+ ledOff(leds[i]);\r
+ delay(20000);\r
+ }\r
+ for (i = NUM_LEDS - 1; i >= 0; --i) {\r
+ ledOn(leds[i]);\r
+ delay(20000);\r
+ }\r
+ for (i = NUM_LEDS - 1; i >= 0; --i) {\r
+ ledOff(leds[i]);\r
+ delay(20000);\r
+ }\r
+\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+ifdef ID
+CFLAGS += -DCANLOAD_ID=$(ID)
+endif
+
+link_VARIANTS = canld
+bin_PROGRAMS = canldtg
+canldtg_LIBS = can
+canldtg_SOURCES = canld_tg.c
--- /dev/null
+/* CAN loader */
+#include <string.h>
+#include <periph/can.h>
+
+#define CANLOAD_HEAD 0x7fe
+#define CANLOAD_BODY 0x7ff
+
+#define CANLOAD_CMD_NOP 0x00
+#define CANLOAD_CMD_LOAD 0x01
+#define CANLOAD_CMD_GO 0x02
+#define CANLOAD_CMD_ON 0xfa
+
+#ifndef CANLOAD_ID
+#warning Unique 32bit number CANLOAD_ID must be defined for each compiled target board.
+#define CANLOAD_ID 0
+#endif
+extern uint32_t canload_id;
+
+#define STATUS_LED
+#ifdef STATUS_LED
+/* define i/o port addr&values for lighting status LED */
+#define LED_PINSEL2 PINSEL2
+#define LED_PINSEL_VAL2 0xfffffff3
+#define LED_IODIR2 IODIR1
+#define LED_IOSET2 IOSET1
+#define LED_IOCLR2 IOCLR1
+#define LED_IOBIT3 0x00080000
+
+#define LED_PINSEL PINSEL1
+#define LED_PINSEL_VAL 0xfffc0fff;
+#define LED_IODIR IODIR0
+#define LED_IOSET IOSET0
+#define LED_IOCLR IOCLR0
+#define LED_IOBIT0 0x00400000
+#define LED_IOBIT1 0x00800000
+#define LED_IOBIT2 0x01000000
+#endif
+
+can_msg_t received_msg;
+
+void rx_msg(uint32_t id) {
+ do {
+ while (!can_msg_received);
+ can_msg_received = 0;
+ } while (can_rx_msg.id != id);
+ memcpy(&received_msg, (void*)&can_rx_msg, sizeof(can_msg_t));
+}
+
+int main() {
+ can_msg_t msg = {.flags = 0, .dlc = 5, .id = CANLOAD_ID & 0x7ff};
+ uint8_t cmd;
+ void *address;
+ void (*user_code)();
+
+ canload_id = CANLOAD_ID;
+ /* peripheral clock = CPU clock (10MHz) */
+ VPBDIV = 1;
+ /** map exception handling to ROM **/
+ MEMMAP = 0x1;
+ /* init Vector Interrupt Controller */
+ VICIntEnClr = 0xFFFFFFFF;
+ VICIntSelect = 0x00000000;
+#ifdef STATUS_LED
+ /* turn LED on */
+ LED_PINSEL &= LED_PINSEL_VAL;
+ LED_PINSEL2 &= LED_PINSEL_VAL2;
+ LED_IODIR |= LED_IOBIT0;
+ LED_IODIR |= LED_IOBIT1;
+ LED_IODIR |= LED_IOBIT2;
+ LED_IODIR2 |= LED_IOBIT3;
+ LED_IOCLR = LED_IOBIT0;
+ LED_IOSET = LED_IOBIT1;
+ LED_IOCLR = LED_IOBIT2;
+ LED_IOCLR2 = LED_IOBIT3;
+#endif
+ /* 10MHz CPU, 10MHz VPB, 1Mb/s CAN */
+ can_init(0x00250000, 14, NULL);
+ /* announce ourself to the world */
+ msg.data[4] = CANLOAD_CMD_ON;
+ ((uint32_t*)msg.data)[0] = canload_id;
+#ifdef STATUS_LED
+ LED_IOCLR = LED_IOBIT1;
+#endif
+ while (can_tx_msg(&msg));
+#ifdef STATUS_LED
+ LED_IOSET = LED_IOBIT1;
+#endif
+ /* command processing loop */
+ for (;;) {
+ /* wait for loader HEAD message */
+ rx_msg(CANLOAD_HEAD);
+ /* check target ID and mask */
+ if ((received_msg.dlc != 8) ||
+ (((uint32_t*)received_msg.data)[0] !=
+ (((uint32_t*)received_msg.data)[1] & canload_id)))
+ continue;
+#ifdef STATUS_LED
+ LED_IOCLR = LED_IOBIT1;
+#endif
+ /* receive loader command message */
+ rx_msg(CANLOAD_BODY);
+ switch (cmd = received_msg.data[0]) {
+ case CANLOAD_CMD_NOP:
+ break;
+ case CANLOAD_CMD_LOAD:
+ /* set starting load address */
+ memcpy(&address, (void*)received_msg.data + 1, 4);
+ /* receive data, until last packet (~shorter msg) arrive */
+ do {
+ rx_msg(CANLOAD_BODY);
+ memcpy(address, (void*)received_msg.data, received_msg.dlc);
+ address += received_msg.dlc;
+ } while (received_msg.dlc == 8);
+ break;
+ case CANLOAD_CMD_GO:
+ memcpy(&user_code, (void*)received_msg.data + 1, 4);
+ /* GO! */
+ user_code();
+ break;
+ default:
+ /* unrecognized command -- do not acknowledge */
+ continue;
+ }
+#ifdef STATUS_LED
+ LED_IOSET = LED_IOBIT1;
+#endif
+ /* command executed -- acknowledge */
+ msg.data[4] = cmd;
+ ((uint32_t*)msg.data)[0] = canload_id;
+ while (can_tx_msg(&msg));
+ }
+}
+
+/* KOHE||, */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = test
+
+test_SOURCES = test.c sys_pll.c sys_dev.c sys_vpb.c sys_mam.c sys_time.c
+#test_LIBS = boot_fn
+
+#link_VARIANTS = boot ram bload flash
--- /dev/null
+#include <reent.h>\r
+#include "dev_cntrl.h"\r
+\r
+#define DEVICE(x) ((x) & 0xFF)\r
+ /*lint -emacro(702,SUB_FILE) right shift of signed qty */\r
+#define SUB_FILE(x) ((x) >> 8) \r
+\r
+\r
--- /dev/null
+/**************************** sys_dev.c *********************************/\r
+/* Copyright 2003/12/27 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* System device. Right now mostly a place holder. */\r
+/* Provides hooks needed to work as a device driver. */\r
+/* Note: All the actual routines are private to this module. The only */\r
+/* element publically visible is the device table entry structure. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 sys_dev.c 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+#include <errno.h>\r
+#include <limits.h>\r
+//#include "lpc210x.h"\r
+#include "dev_cntrl.h"\r
+#include <stdio.h>\r
+\r
+ /**** Local Prototypes ****/\r
+static _ssize_t sys_read ( struct _reent *r, int file, void *ptr, size_t len);\r
+static _ssize_t sys_write ( struct _reent *r, int file, const void *ptr, size_t len);\r
+static int sys_open( struct _reent *r, const char *name, int o_flags, int o_mode);\r
+static int sys_close( struct _reent *r, int file);\r
+\r
+/************************** sys_read ************************************/\r
+/* Reads from 'sys'. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* int file -- number referring to the open file. Generally */\r
+/* obtained from a corresponding call to open. */\r
+/* Only one file number (0) is supported. */\r
+/* void *ptr -- memory area to place read bytes into. */\r
+/* size_t len -- maximum number of bytes to read. */\r
+/* Note: will only return a single byte on every call. That byte is */\r
+/* just a dummy. */\r
+/* Returns number of bytes read. (_ssize_t)-1 on error. */\r
+/*lint -e{715} multiple arguments not referenced since this is */\r
+/* basically a placeholder. */\r
+static _ssize_t sys_read (\r
+ struct _reent *r, /* Re-entrancy structure, used to make */\r
+ /* thread safe. */\r
+ int file, /* File handle. Used to distinguish */\r
+ /* multiple instances. */\r
+ void *ptr, /* Where to place data. */\r
+ size_t len) /* Max data to read. */\r
+{\r
+unsigned char *p;\r
+\r
+ if( file != 0) { /* Only one device. */\r
+ r->_errno = EBADF; /* Bad file number. */\r
+ return (_ssize_t)-1;\r
+ }\r
+\r
+ p = ptr;\r
+ *p = (unsigned char)'a'; /* Dummy operation for now. */\r
+ return (_ssize_t)1;\r
+}\r
+\r
+/************************** sys_write ***********************************/\r
+/* Writes to 'sys'. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* int file -- number referring to the open file. Generally */\r
+/* obtained from a corresponding call to open. */\r
+/* Only one file number (0) is supported. */\r
+/* const void *ptr -- memory area to place read bytes from. */\r
+/* size_t len -- maximum number of bytes to write. */\r
+/* Returns number of bytes written. (_ssize_t)-1 on error. */\r
+/* Note: simply returns indicating it wrote everything requested. IE */\r
+/*lint -e{715} multiple arguments not referenced since this is */\r
+/* basically a placeholder. */\r
+static _ssize_t sys_write (\r
+ struct _reent *r, /* Re-entrancy structure, used to make */\r
+ /* thread safe. */\r
+ int file, /* File handle. Used to distinguish */\r
+ /* multiple instances. */\r
+ const void *ptr, /* Pointer to data to write. */\r
+ size_t len) /* Amount of data to write. */\r
+ {\r
+\r
+ if( file != 0) { /* Only one device. */\r
+ r->_errno = EBADF; /* Bad file number. */\r
+ return (_ssize_t)-1;\r
+ }\r
+\r
+ return (_ssize_t)len;\r
+}\r
+\r
+/************************** sys_open ************************************/\r
+/* Opens 'sys' */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* const char *name -- name of file/device to open. Since sys */\r
+/* supports no sub devices this should be an empty */\r
+/* string. */\r
+/* int flags -- Flags to control open. Not used at the */\r
+/* moment. */\r
+/* int mode -- Mode to open in. Not used at the moment. */\r
+/* Returns file number >= 0 if successful. Otherwise the error code */\r
+/* may be found in errno. */\r
+/*lint -e{715} multiple arguments not referenced since this is */\r
+/* basically a placeholder. */\r
+static int sys_open( \r
+ struct _reent *r, /* Re-entrancy structure, used to make */\r
+ /* thread safe. */\r
+ const char *name, /* Name to open. */\r
+ int o_flags, /* Flags to control open. */\r
+ /* Read, write binary etc... */\r
+ /* See flags.c for values generated by */\r
+ /* newlib. */\r
+ int o_mode) /* Mode to open in. This is a */\r
+ /* security or permissions value. */\r
+ /* Newlib uses the classic 0666 for all */\r
+ /* fopens. See fopen.c */\r
+{\r
+\r
+ /* Check against null pointer. Also no sub-devices available */\r
+ /* so make sure we aren't asked to open one. */\r
+ if( (name == 0) || (*name != '\0')) {\r
+ r->_errno = ENOENT; /* No such file or directory. */\r
+ return( -1);\r
+ }\r
+ return( 0); /* Always sub-handle 0. Note we never */\r
+ /* fail on this open. */\r
+}\r
+\r
+/************************** sys_close ***********************************/\r
+/* Close sys. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* int file -- number referring to the open file. Generally */\r
+/* obtained from a corresponding call to open. */\r
+/* Only one file number (0) is supported. */\r
+/* Returns 0 if successful. Otherwise the error code may be found in */\r
+/* errno. */\r
+static int sys_close(\r
+ struct _reent *r, /* Re-entrancy structure, used to make */\r
+ /* thread safe. */\r
+ int file) /* File/device sub handle. */\r
+{\r
+\r
+ if( file != 0) { /* Only one device. */\r
+ r->_errno = EBADF; /* Bad file number. */\r
+ return -1;\r
+ }\r
+ return( 0); /* Always succeeds. */\r
+}\r
+\r
+/************************** sys *****************************************/\r
+/* Device table entry used to add this device. */\r
+const struct device_table_entry sys = {\r
+ "sys", /* Device name. */\r
+ sys_open, /* Open method. */\r
+ sys_close, /* Close method. */\r
+ sys_read, /* Read method. */\r
+ sys_write, /* Write method. */\r
+ 0 }; /* ioctl not supported. */\r
--- /dev/null
+/**************************** sys_mam.c *********************************/\r
+/* Copyright 2003/12/27 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* A shallow wrapper around the MAM device. A little bit of error */\r
+/* checking. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 sys_mam.c 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+#include <errno.h>\r
+#include "lpc210x.h"\r
+#include "lpc_sys.h"\r
+\r
+/********************* SetMAM *******************************************/\r
+/* SetMAM -- Set up the MAM. Minimal error checking, not much more */\r
+/* than a wrapper around the register. Returns 0 if successful, */\r
+/* something else. Sets errno in case of an error. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned int cycle_time -- number of cycles to access the flash. */\r
+/* MAM_CONTROL ctrl -- Mode to place MAM in. One of: */\r
+/* MAM_disabled, MAM_part_enable, or */\r
+/* MAM_full_enable. */\r
+/* Returns 0 if successful. Additional error/sanity checks are possible*/\r
+int SetMAM( \r
+ struct _reent *r, \r
+ unsigned int cycle_time,\r
+ MAM_CONTROL ctrl)\r
+{\r
+ if( cycle_time > 7) { /* Cycle time is limited, */\r
+ r->_errno = EINVAL; /* complain if set too high. */\r
+ return -1;\r
+ }\r
+\r
+ MAMCR = (unsigned char)ctrl; /*lint !e930 cast from enum */\r
+ MAMTIM = (unsigned char)cycle_time;\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+/**************************** sys_pll.c *********************************/\r
+/* Copyright 2003/12/27 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* A wrapper around the PLL device. Adds little bit of error checking */\r
+/* and does the arithmetic needed to determione the register values for */\r
+/* a particular clock frequency. Also provides hooks so other parts */\r
+/* of the application can determine the operating frequency. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 sys_pll.c 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+#include "lpc210x.h"\r
+#include "lpc_sys.h"\r
+#include "errno_lpc.h"\r
+\r
+ /**** Local Macros ****/\r
+#define PLL_ENABLE ((unsigned char)1u) /* enable pll */\r
+#define PLL_CONNECT ((unsigned char)3u) /* connect pll */\r
+#define PLL_FEED_SEQ1 ((unsigned char)0xAAu) /* First feed */\r
+ /* value. */\r
+#define PLL_FEED_SEQ2 ((unsigned char)0x55u) /* Second feed */\r
+ /* value. */\r
+#define PLL_LOCK_MASK ((unsigned short)0x400u)/* Masks PLL */\r
+ /* lock bit. */\r
+#define MIN_OSCILLATOR_IN (10000uL)\r
+#define MAX_OSCILLATOR_IN (25000uL)\r
+#define MAX_OPERATING_SPEED (60000uL)\r
+\r
+ /**** Local Variables ****/\r
+static unsigned long native_speed = 10000uL; /* Default to 10MHz */\r
+\r
+/********************* SetNativeSpeed ***********************************/\r
+/* SetNativeSpeed -- Set the oscillator frequency for the external */\r
+/* oscillator. This is used to inform the routines that deal with cpu */\r
+/* frequencies what the starting point is. Any error here will be */\r
+/* multiplied later. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned long speed -- external oscillator/crystal frequency in kHz.*/\r
+/* Note: There is no way to determine or verify this value so we have */\r
+/* to trust the caller to get it right. */\r
+/* Returns 0 if successful. */\r
+int SetNativeSpeed( \r
+ struct _reent *r, \r
+ unsigned long speed)\r
+{\r
+\r
+ if( (speed < MIN_OSCILLATOR_IN) || (speed > MAX_OSCILLATOR_IN)) {\r
+ r->_errno = ELPC_OOR;\r
+ return -1;\r
+ }\r
+ native_speed = speed;\r
+ return 0;\r
+}\r
+\r
+/********************* SetDesiredSpeed **********************************/\r
+/* SetDesiredSpeed -- Set the cpu to desired frequency. Relies on */\r
+/* earlier call to set native oscillator speed correctly. Returns 0 */\r
+/* if successful. desired_speed is set to actual speed obtained on */\r
+/* return. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned long desired_speed -- CPU operating frequency in kHz. */\r
+/* Returns 0 if successful. errno will be set on error. */\r
+int SetDesiredSpeed( \r
+ struct _reent *r, \r
+ unsigned long desired_speed)\r
+{\r
+ unsigned long multiplier, remainder, pll_speed, i;\r
+\r
+ /* First check that the requested speed is within allowable */\r
+ /* limits. */\r
+ if( (desired_speed < native_speed) || (desired_speed > MAX_OPERATING_SPEED)) {\r
+ r->_errno =ELPC_OOR;\r
+ return -1;\r
+ }\r
+\r
+ /* Find the nearest multiple between the native speed and the */\r
+ /* desired speed. */\r
+ multiplier = desired_speed/native_speed;\r
+ remainder = desired_speed%native_speed;\r
+ if( remainder > (native_speed/2)) {\r
+ multiplier++;\r
+ \r
+ /* If nearest speed is higher than maximum reduce to next */\r
+ /* closest. */\r
+ if( (native_speed * multiplier) > MAX_OPERATING_SPEED) {\r
+ multiplier--;\r
+ }\r
+ }\r
+\r
+ /* Finally limit multiplier range. Note: we are unlikely to */\r
+ /* exceed the maximum. */\r
+ if( multiplier < 1uL) {\r
+ multiplier = 1uL;\r
+ }\r
+ if( multiplier > 32uL) {\r
+ multiplier = 32uL;\r
+ }\r
+\r
+ /* Now we need a PLL divider that will keep the PLL frequency */\r
+ /* within the allowable range. Simply ramp up through dividers */\r
+ /* until we find one that works. */\r
+ pll_speed = native_speed * multiplier;\r
+ for( i = 0uL; i < 4uL; i++) {\r
+ if( (pll_speed * 2 * (1 << i)) > 156000uL) {\r
+ if((pll_speed * 2 * (1 << i)) > 320000uL) {\r
+ r->_errno = ELPC_CANT;\r
+ return -1;\r
+ }\r
+ break; /*lint !e960 non switch break. */\r
+ }\r
+ }\r
+ if( i >= 4) { /* Check to make sure we found a */\r
+ r->_errno = ELPC_CANT; /* divisor that works. */\r
+ return -1;\r
+ }\r
+\r
+ /* Set PLL divisor, multiplier */\r
+ PLLCFG = (unsigned char)((multiplier -1) | (i << 5));\r
+ PLLCON = PLL_ENABLE; /* Enables PLL */\r
+ PLLFEED = PLL_FEED_SEQ1; /* Change to setting above. These two */\r
+ PLLFEED = PLL_FEED_SEQ2; /* updates MUST occur in sequence on */\r
+ /* the VPB bus. */\r
+\r
+ /* wait for lock */\r
+ while( (PLLSTAT & PLL_LOCK_MASK) == 0) {\r
+ }\r
+\r
+ \r
+ PLLCON = PLL_CONNECT; /* Enables and connects PLL */\r
+ PLLFEED = PLL_FEED_SEQ1; /* Change to setting above. These two */\r
+ PLLFEED = PLL_FEED_SEQ2; /* updates MUST occur in sequence on */\r
+ /* the VPB bus. */\r
+ return 0;\r
+}\r
+\r
+/********************* ActualSpeed **************************************/\r
+/* ActualSpeed -- Returns the operating speed of the CPU. Relies on */\r
+/* earlier call to set native oscillator speed correctly. */\r
+unsigned long ActualSpeed( void)\r
+{\r
+\r
+ /* Use PLL multiplier if connected. */\r
+ if( (PLLCON & PLL_CONNECT) == PLL_CONNECT) {\r
+ return( native_speed * ((PLLCFG & 0x1F) + 1));\r
+ }\r
+ return native_speed; /* No multiplier, just return native speed. */\r
+}\r
+\r
+\r
+\r
+\r
+void endless_loop()\r
+{\r
+ while(1);\r
+}
\ No newline at end of file
--- /dev/null
+/**************************** sys_time.c ********************************/\r
+/* Copyright 2003/12/28 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Time routines. Polled implementations of routines to provide timed */\r
+/* waits and elapsed time. */\r
+/* Could be refined yet. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 sys_time.c 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* 2 sys_time.c 17-Jan-2004,16:07:18,`RADSETT' Move max_microsecond storage and\r
+* init out of timing function\r
+* into initialization.\r
+* 3 sys_time.c 29-Jan-2004,10:29:08,`RADSETT' Update StartClock minimum count\r
+* measurement to use a better comparison\r
+* Add section to StartClock to measure the overhead of a WaitUs call.\r
+* Change WaitUs to avoid attempting measurements with counts below\r
+* min_count.\r
+* Change WaitUs to reduce the requested wait time to compensate for call\r
+* overhead.\r
+* Change UsToCounts to replace /CLOCK_SPEED operation with shift and add\r
+* operations so that it takes constant time. Add ifdef so it can be\r
+* switched\r
+* back to divide if CLOCK_SPEED is changed.\r
+* TLIB revision history ends.\r
+*/\r
+#include <stdio.h>\r
+#include <limits.h>\r
+#include "lpc210x.h"\r
+#include "lpc_sys.h"\r
+#include "errno_lpc.h"\r
+\r
+ /**** Local Macros ****/\r
+\r
+ /* If TIME_TO_COUNTS_USE_DIV is defined then the routines will */\r
+ /* use a normal divide operation. Otherwise the division will */\r
+ /* be replaced with shift and add operations. This is */\r
+ /* marginally faster. More important it does the operation in */\r
+ /* the same time no matter what the value used. */\r
+ /* Note: If CLOCK_SPEED is changed then either */\r
+ /* TIME_TO_COUNTS_USE_DIV must be defined OR UsToCounts and */\r
+ /* divx must be changed to reflect the new value. */\r
+/* #define TIME_TO_COUNTS_USE_DIV */\r
+#define CLOCK_SPEED (10000000) /* Nominal speed for internal */\r
+ /* clock in Hz. */\r
+\r
+ /* Used for converting between counts and uS for time function.*/\r
+ /* An unsigned long long so overflows are not possible during */\r
+ /* the conversion. Note relationship to CLOCK_SPEED. */\r
+#define COUNTS_PER_US (10uLL)\r
+\r
+#define COUNTER_RESET ((unsigned char)2) /* Hold counter in reset. */\r
+#define COUNTER_ENABLE ((unsigned char)1) /* Let counter run. */ \r
+\r
+ /* Used to control and detect matches. Use R3 since it has no */\r
+ /* matching external output on T0. */\r
+#define MATCH_T0_R3_NOTHING (~0xE00u)/* Do nothing when match */\r
+ /* register 3 matches T0. */\r
+#define EXTERN_MATCH_T0_R3 (~0xC08u)/* Set External output low (if */\r
+ /* connected), do nothing on */\r
+ /* match. */\r
+#define EXTERN_MATCH_T0_R3_SET (0x800) /* Set external output high */\r
+ /* (if connected) on match. */\r
+\r
+ /*** Local Variables ***/\r
+\r
+ /* Scales between desired nominal clock frequency and what we */\r
+ /* were actually able to achieve. This ends up being the */\r
+ /* actual clock rate in Hz. */\r
+static unsigned long timing_scale_factor; \r
+\r
+ /* Provides high order timing bits so internal timer can */\r
+ /* record a running time longer than ~.12 Hrs. In fact this */\r
+ /* allows a representation of > 50,000 years clearly (I hope) */\r
+ /* unreasonably long. */\r
+static unsigned long high_counts = 0uL;\r
+\r
+ /* Maximum number of microseconds that a single timing */\r
+ /* operation can handle. Larger values have to be split into */\r
+ /* multiple operations. */\r
+static unsigned int max_microsec = 0;\r
+\r
+ /* Minimum number of counts a core timing operation takes. */\r
+static unsigned int min_count = 0;\r
+\r
+ /* Minimum number of counts a WaitUs call takes. */\r
+static unsigned int count_overhead = 0;\r
+\r
+ /**** Internal Prototypes ****/\r
+\r
+/********************* counts_to_us *************************************/\r
+/* counts_to_us -- converts from internal units in counts to uS. */\r
+static unsigned int counts_to_us( unsigned int counts);\r
+\r
+/********************* divx *********************************************/\r
+/* Divide by 78125. Constant time operation. */\r
+static unsigned long long divx(unsigned long long x);\r
+\r
+/********************* accumulate_time **********************************/\r
+/* accumulate_time -- Check for rollover of HW timer and increments */\r
+/* the high order count if it is detected. Must be called at at least */\r
+/* twice the rollover frequency of the HW timer to ensure proper */\r
+/* detection of rollover. That works out to about once every 3.5 */\r
+/* minutes at nominal clock rate. */\r
+static void accumulate_time( void);\r
+\r
+/********************* get_full_counts **********************************/\r
+/* get_full_counts -- Concatenate the stored high counts and the HW */\r
+/* timer low counts to get a large number containing the full count. */\r
+static unsigned long long get_full_counts( void);\r
+\r
+ /**** Implementation ****/\r
+\r
+/********************* StartClock ***************************************/\r
+/* StartClock -- Starts up the clock used for internal timing. */\r
+/* Attempts to match the desired clock speed (CLOCK_SPEED) and */\r
+/* initializes timing_scale_factor to a compensating scale. Returns 0 */\r
+/* if successful, otherwise error code will be retained in errno. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* Note: Should be called only after all clocks have been set up. */\r
+/* Otherwise time scale will not be correct. */\r
+/* Returns 0 if successful. */\r
+int StartClock(\r
+ struct _reent *r) /* Reentrancy structure. */\r
+{\r
+ unsigned long rate, divider;\r
+ unsigned long lclmax_microsec = 0uL;\r
+ unsigned int start_count, end_count;\r
+ unsigned int test_us;\r
+\r
+ rate = VPBRate(); /* Get the clock rate of the */\r
+ /* peripheral bus. */\r
+ if( rate == 0) { /* Internal error, complain and exit. */\r
+ r->_errno = ELPC_INTERNAL;\r
+ return -1;\r
+ }\r
+\r
+ /* Set clock to reset. This will keep it at zero. */\r
+ T0TCR = COUNTER_RESET;\r
+\r
+ /* Calculate a divider that will cause the internal clock to */\r
+ /* approximate the target clock speed. This should give a */\r
+ /* clock counting rate between the desired rate and twice the */\r
+ /* desired rate. */\r
+ divider = rate/ CLOCK_SPEED;\r
+ if( divider == 0) { /* Sanity check on the divider. If we have a */\r
+ divider = 1uL; /* pclk slower than our desired rate we won't */\r
+ } /* be able to reach the desired rate so just */\r
+ /* run as fast as we can. */\r
+ T0PR = divider - 1; /* Set prescaler to give us our target rate. */\r
+\r
+ /* Since the actual clock rate we have and our target rate may */\r
+ /* not be the same, calculate a corrective factor for routines */\r
+ /* that make use of it. This value will be divided by */\r
+ /* CLOCK_SPEED when dealing with time and so should produce a */\r
+ /* result precise to 1 part in CLOCK_SPEED. */\r
+ timing_scale_factor = rate / divider;\r
+\r
+ /* Set to do nothing on match, and set output to 0. */\r
+ T0MCR = (unsigned short)(T0MCR & MATCH_T0_R3_NOTHING); \r
+ T0EMR = (unsigned short)(T0EMR & EXTERN_MATCH_T0_R3);\r
+\r
+ T0TCR = COUNTER_ENABLE; /* Enable clocks. */\r
+\r
+ if( max_microsec == 0) { /* Find saturation point. */\r
+ lclmax_microsec = counts_to_us( UINT_MAX);\r
+ max_microsec = lclmax_microsec;\r
+ }\r
+\r
+ /* Find the minimum number of counts it takes to set up and */\r
+ /* detect a time period. This simulates the normal timer */\r
+ /* operation. The purpose is to avoid any possible missed time */\r
+ /* periods by shortcutting the time wait process if the time */\r
+ /* would have passed by the time we had performed the operation */\r
+ /* anyway. */\r
+ /* We deliberately set out to slightly overestimate the time */\r
+ /* involved to avoid the danger of underestimating. This */\r
+ /* overestimation occurs in three ways: */\r
+ /* 1 - Operations that would normally occur after a match */\r
+ /* would be detected are included in the count. */\r
+ /* 2 - One count is added so that any fractional counts will */\r
+ /* be compensated for. */\r
+ /* 3 - The operations that do the counting are invariably */\r
+ /* included. */\r
+ /* Note that we are at the tender mercies of the compiler not */\r
+ /* to generate significantly different code for this and the */\r
+ /* code used for actual timing. */\r
+ start_count = T0TC; /* Starting time. */\r
+\r
+ /* This main loop is copied from WaitUs and modified in a */\r
+ /* fashion to try and preserve all the operations in a fashion */\r
+ /* that the compiler will not optimize this passage differently */\r
+ /* than the 'real' version. Comments from the original version */\r
+ /* are kept with notes added to indicate what operations are */\r
+ /* performed. */\r
+\r
+ /* First perform a comparison of a local variable against */\r
+ /* global variable. Note: this comparison assumes that */\r
+ /* high_counts is still zero. If StartClock is run more than */\r
+ /* once between resets this code may fail to operate correctly. */\r
+ if( lclmax_microsec > high_counts) { \r
+\r
+ /* Add a local variable to current time counter and store in */\r
+ /* match register. */\r
+ T0MR3 = T0TC + start_count; /* Set match to current time + delay */\r
+ /* time. */\r
+\r
+ /* Exact match for 'real' operation. */\r
+ /* Set operation on match to set to 1. */\r
+ T0EMR = (unsigned short)(T0EMR | EXTERN_MATCH_T0_R3_SET);\r
+\r
+ /* Compare external register to local. This does not match */\r
+ /* the original operation which masks the external register and */\r
+ /* compares it to zero. The hope is that the operations will */\r
+ /* be close enough together that any differences (particularly */\r
+ /* short counts) will be masked by the over-estimation */\r
+ /* precautions. Since the difference between the two is only */\r
+ /* an instruction or two this appears to be a reasonable */\r
+ /* assumption. */\r
+ while( T0TC == start_count) { /* Wait for match to set output*/\r
+ } /* to 1. */\r
+\r
+ /* Exact match for 'real' operation. */\r
+ /* Set external match 0 output to 0 and operation on */\r
+ /* match to do nothing. */\r
+ /* Set external match 0 output to 0 and operation on */\r
+ /* match to do nothing so we don't trigger next wait */\r
+ /* early by accident. */\r
+ T0EMR = (unsigned short)(T0EMR & EXTERN_MATCH_T0_R3);\r
+ }\r
+ /* End of the copied main loop. */\r
+\r
+ end_count = T0TC; /* Ending time. */\r
+\r
+ /* Calculate the counts needed to perform a timing operation. */\r
+ /* Add a count for safety. */\r
+ min_count = (end_count - start_count) + 1;\r
+\r
+ /* Now find overhead for a wait call. This will be used to */\r
+ /* compensate for that overhead to increase the accuracy at */\r
+ /* short waits. We do this by waiting for a short period and */\r
+ /* measuring how long it actually takes. */\r
+\r
+ /* First figure out how long to wait. Want as short as */\r
+ /* possible so we wait for the minimum useable period which */\r
+ /* will be the minimum detectable plus 1 microsecond */\r
+ test_us = counts_to_us(min_count) + 1u;\r
+\r
+ start_count = T0TC; /* Starting time. */\r
+ WaitUs( test_us);\r
+ end_count = T0TC; /* Ending time. */\r
+\r
+ /* Total time spent. Add 1/2 of a microsecond for rounding. */\r
+ count_overhead = (end_count - start_count) - UsToCounts( test_us);\r
+\r
+ return 0;\r
+}\r
+\r
+/********************* counts_to_us *************************************/\r
+/* counts_to_us -- converts from internal units in counts to uS. */\r
+/* unsigned int counts -- # of counts to be converted. */\r
+/* Returns number of microseconds corresponding to counts. Truncates */\r
+/* result to microsecond resolution. */\r
+static unsigned int counts_to_us( unsigned int counts)\r
+{\r
+ unsigned int us;\r
+\r
+ /* Convert the counts to microseconds taking the actual clock */\r
+ /* rate into account. Note that as long as */\r
+ /* CLOCK_SPEED/(timing_scale_factor * COUNTS_PER_US) is less */\r
+ /* than 1 this cannot overflow a long. With nominal CLOCK_SPEED*/\r
+ /* at 10000000 this will be true as long as the actual clock */\r
+ /* speed is > 1000000. */\r
+ us = (unsigned int)((counts * (unsigned long long)CLOCK_SPEED)/\r
+ (timing_scale_factor * COUNTS_PER_US));\r
+\r
+ return us;\r
+}\r
+\r
+#ifdef TIME_TO_COUNTS_USE_DIV\r
+\r
+/********************* UsToCounts ***************************************/\r
+/* UsToCounts -- converts to internal units in counts from uS. Other */\r
+/* Modules use this counter for a timebase so this needs to be */\r
+/* available to them. */\r
+/* unsigned int us -- microseconds to convert to counts. */\r
+/* Returns number of counts corresponding to us. Saturates on */\r
+/* overflow so for large time periods it is possible to get a result */\r
+/* lower than requested. */\r
+unsigned int UsToCounts( unsigned int us)\r
+{\r
+ unsigned long long counts;\r
+\r
+ /* Convert the nanoseconds to counts taking the actual clock */\r
+ /* rate into account. Note: NS_PER_COUNT * CLOCK_SPEED should */\r
+ /* always be 1,000,000,000. The expanded form just shows the */\r
+ /* intent more clearly. */\r
+ counts = (COUNTS_PER_US * us * timing_scale_factor)/(CLOCK_SPEED);\r
+\r
+ if( counts > ULONG_MAX) {\r
+ return ULONG_MAX;\r
+ }\r
+ return (unsigned int)counts;\r
+}\r
+\r
+#else\r
+\r
+/********************* divx *********************************************/\r
+/* Divide by 78125. Constant time operation. */\r
+static unsigned long long divx(unsigned long long x)\r
+{\r
+ unsigned long long res;\r
+\r
+ /* None of these operations overflow only since before this */\r
+ /* routine is called the calling routine uses a shift operation */\r
+ /* to perform a divide by 128 to provide enough headroom to */\r
+ /* allow this to succeed w/o overflow. */\r
+ res = (84*x)>> 7;\r
+ res = (73*x - res)>> 7;\r
+ res = (94*x + res) >> 8;\r
+ res = (121*x + res) >> 7;\r
+ res = (106*x + res) >> 9;\r
+ res = (101*x + res) >> 7;\r
+ res = (95*x + res) >> 8;\r
+ res = (107*x + res) >> 23;\r
+ return res;\r
+}\r
+\r
+/********************* UsToCounts ***************************************/\r
+/* UsToCounts -- converts to internal units in counts from uS. Other */\r
+/* Modules use this counter for a timebase so this needs to be */\r
+/* available to them. Replaces division operation with an equivalent */\r
+/* series of multiplies, shifts and adds. */\r
+/* unsigned int us -- microseconds to convert to counts. */\r
+/* Returns number of counts corresponding to us. Saturates on */\r
+/* overflow so for large time periods it is possible to get a result */\r
+/* lower than requested. */\r
+unsigned int UsToCounts( unsigned int us)\r
+{\r
+ unsigned long long tmp;\r
+\r
+ tmp = COUNTS_PER_US * us * timing_scale_factor;\r
+ tmp >>= 7; /* First divide by 128. Doing this first */\r
+ /* ensures 7 bits of overhead for later divide */\r
+ /* by 5 operations. */\r
+\r
+ tmp = divx(tmp);\r
+\r
+ if( tmp > ULONG_MAX) {\r
+ return ULONG_MAX;\r
+ }\r
+ return (unsigned int)tmp;\r
+}\r
+\r
+#endif /* TIME_TO_COUNTS_USE_DIV */\r
+\r
+/********************* accumulate_time **********************************/\r
+/* accumulate_time -- Check for rollover of HW timer and increments */\r
+/* the high order count if it is detected. Must be called at at least */\r
+/* twice the rollover frequency of the HW timer to ensure proper */\r
+/* detection of rollover. That works out to about once every 3.5 */\r
+/* minutes at nominal clock rate. */\r
+static void accumulate_time( void)\r
+{\r
+ static unsigned int last_time = 0;\r
+ unsigned long current_time;\r
+\r
+ /* A simple polled rollover check. This should work as long as*/\r
+ /* this routine is called at least once every time the counter */\r
+ /* has incremented 1/2 of its maximum count. */\r
+ current_time = T0TC; /* Get the current count */\r
+ if(current_time < last_time) { /* If we have rolled over, */\r
+ high_counts++; /* increment the high order */\r
+ } /* accumulator. */\r
+ last_time = current_time; /* Record last read value for */\r
+ /* the next check. */\r
+}\r
+\r
+/********************* get_full_counts **********************************/\r
+/* get_full_counts -- Concatenate the stored high counts and the HW */\r
+/* timer low counts to get a large number containing the full count. */\r
+/* Returns number of counts since start. */\r
+static unsigned long long get_full_counts( void)\r
+{\r
+ unsigned long low;\r
+ unsigned long long full_count;\r
+\r
+\r
+ /* Read in the clock counts. It is necessary to perform a */\r
+ /* rollover check so we don't end up with the low order value */\r
+ /* that of after the rollover and the high order count from */\r
+ /* before the rollover. If that were to happen our time would */\r
+ /* not increase in a monotonic fashion. */\r
+ do {\r
+ accumulate_time(); /* Check for rollover of HW clock. */\r
+ low = T0TC; /* Read current count. */\r
+\r
+ /* Form low order and high order counts into a single value. */\r
+ full_count = ((unsigned long long)high_counts << 32) | low;\r
+\r
+ } while( low > T0TC); /* Check for rollover and redo if one */\r
+ /* has happened. */\r
+ return full_count; /* All done. */\r
+}\r
+\r
+/********************* WaitUs *******************************************/\r
+/* WaitUs -- Wait for 'wait_time' us */\r
+/* unsigned long wait_time -- microseconds to convert to counts. */\r
+/* Will break wait into multiple waits if needed to avoid saturation. */\r
+void WaitUs( unsigned int wait_time)\r
+{\r
+ unsigned int counts;\r
+\r
+ accumulate_time(); /* Check for rollover of HW clock. */\r
+\r
+ /* Convert from requested wait in uS to counts used by the HW */\r
+ /* counter. If necessary break into multiple waits. */\r
+ while( wait_time > 0) {\r
+ if( wait_time > max_microsec) {\r
+ counts = UsToCounts( max_microsec);\r
+ wait_time -= max_microsec;\r
+ }\r
+\r
+ /* Note that we always execute the else portion of this test */\r
+ /* once for every call to WaitUs. */\r
+ else {\r
+ counts = UsToCounts( wait_time);\r
+\r
+ /* Compensate for overhead. Subtract out overhead for */\r
+ /* waits that are long enough. For shorter periods */\r
+ /* simply minimize the wait. */\r
+ if( counts > count_overhead) {\r
+ counts -= count_overhead;\r
+ }\r
+ else {\r
+ counts = 0;\r
+ }\r
+ wait_time = 0;\r
+ }\r
+\r
+ /* If counts is lower than min_count zero then the wait */\r
+ /* interval is too small and we should just return. The */\r
+ /* smallest count we can deal with is the count that occurs */\r
+ /* between reading the HW clock and setting the match register. */\r
+ /* The value of this minimum will depend on the timer rate and */\r
+ /* the CPU execution speed. */\r
+ if( counts > min_count) { \r
+\r
+ T0MR3 = T0TC + counts; /* Set match to current time + delay */\r
+ /* time. */\r
+\r
+ /* Set operation on match to set to 1. */\r
+ T0EMR = (unsigned short)(T0EMR | EXTERN_MATCH_T0_R3_SET);\r
+\r
+ while( (T0EMR & 0x8) == 0) { /* Wait for match to set output*/\r
+ } /* to 1. */\r
+\r
+ /* Set external match 0 output to 0 and operation on */\r
+ /* match to do nothing. */\r
+ /* Set external match 0 output to 0 and operation on */\r
+ /* match to do nothing so we don't trigger next wait */\r
+ /* early by accident. */\r
+ T0EMR = (unsigned short)(T0EMR & EXTERN_MATCH_T0_R3);\r
+ }\r
+\r
+ accumulate_time(); /* Check for rollover of HW clock. */\r
+ }\r
+} \r
+\r
+/********************* GetUs ********************************************/\r
+/* GetUs -- Get the current time in uS. */\r
+unsigned long long GetUs( void)\r
+{\r
+ unsigned long long counts, us;\r
+\r
+ counts = get_full_counts(); /* Get the total passed time sice */\r
+ /* counter start. */\r
+ /* Convert low order of timer to nS. */\r
+ us = counts_to_us( (unsigned int)(counts & UINT_MAX));\r
+ \r
+ counts >>= 32; /* Now get the high order count. */\r
+\r
+ /* Given a 64 bit number uS resolution provides a range */\r
+ /* exceeding 500,000 years. I think we'll skip overflow */\r
+ /* detection. */\r
+ us += counts_to_us(UINT_MAX) * counts;\r
+ return us;\r
+}\r
+\r
+/********************* MinimumAchievableWait ****************************/\r
+/* MinimumAchievableWait -- Get the shortest wait we can do. */\r
+unsigned int MinimumAchievableWait(void)\r
+{\r
+ return counts_to_us( count_overhead + min_count + (UsToCounts( 1u)/2));\r
+}\r
--- /dev/null
+/**************************** sys_vpb.c *********************************/\r
+/* Copyright 2003/12/28 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Wrapper around VPB clock rate. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 sys_vpb.c 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* 2 sys_vpb.c 30-Jan-2004,14:13:14,`RADSETT' Add note on double read of VPBDiv.\r
+* TLIB revision history ends.\r
+*/\r
+#include <stdio.h>\r
+#include "lpc210x.h"\r
+#include "lpc_sys.h"\r
+#include "errno.h"\r
+\r
+ /**** Local Macros ****/\r
+#define VPB_DIV_QUARTER ((unsigned char)0) /* Sets VPB clock to */\r
+ /* 1/4 cclk. */\r
+#define VPB_DIV_HALF ((unsigned char)2) /* Sets VPB clock to */\r
+ /* 1/2 cclk. */\r
+#define VPB_DIV_ONE ((unsigned char)1) /* Sets VPB clock to */\r
+ /* cclk. */\r
+\r
+ /**** Local Prototypes ****/\r
+static VPB_param VPBQuery( void);\r
+\r
+/********************* VPBQuery *****************************************/\r
+/* VPBQuery -- Finds and returns the divider of the clock from the CPU */\r
+/* to the peripheral bus. */\r
+static VPB_param VPBQuery( void)\r
+{\r
+\r
+ (void)VPBDIV; /* Dummy read, single doesn't always work? */\r
+ /* Apparently a real chip problem but no publically */\r
+ /* available documentation yet. */\r
+ /* See http://groups.yahoo.com/group/lpc2100/ A search */\r
+ /* for VPB should reveal the discussion. */\r
+\r
+ /* Read divisor and convert to internal representation. */\r
+ switch( VPBDIV & 0x3) {\r
+ default:\r
+ case VPB_DIV_ONE:\r
+ return( VPB_DIV1);\r
+\r
+ case VPB_DIV_HALF:\r
+ return( VPB_DIV2);\r
+\r
+ case VPB_DIV_QUARTER:\r
+ return( VPB_DIV4);\r
+ }\r
+}\r
+\r
+/********************* VPBControl ***************************************/\r
+/* VPBControl -- Control the clock divider on the peripheral bus. */\r
+/* Returns the actual divider in ptr (requested is also passed in ptr. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* VPB_parm p -- requested VPB to CPU freq rate. */\r
+/* Returns 0 if successful. */\r
+int VPBControl( struct _reent *r, VPB_param p) \r
+{\r
+\r
+ switch( p) {\r
+ case VPB_DIV1:\r
+ VPBDIV = VPB_DIV_ONE;\r
+ break;\r
+\r
+ case VPB_DIV2:\r
+ VPBDIV = VPB_DIV_HALF;\r
+ break;\r
+\r
+ case VPB_DIV4:\r
+ VPBDIV = VPB_DIV_QUARTER;\r
+ break;\r
+\r
+ default:\r
+ r->_errno = EINVAL;\r
+ return -1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/********************* VPBRate ******************************************/\r
+/* VPBRate -- Finds and returns the rate of the clock on the */\r
+/* peripheral bus (in Hz). */\r
+unsigned long VPBRate( void)\r
+{\r
+ VPB_param vpb;\r
+\r
+ vpb = VPBQuery(); /* Find current divisor. */\r
+\r
+ /* Use divisor to convert from CPU speed in kHz to VPB speed */\r
+ /* in Hz. */\r
+ switch( vpb) {\r
+ case VPB_DIV1:\r
+ return( ActualSpeed()*1000uL);\r
+\r
+ case VPB_DIV2:\r
+ return( ActualSpeed()*500uL);\r
+\r
+ case VPB_DIV4:\r
+ return( ActualSpeed()*250uL);\r
+ }\r
+return 0;\r
+}\r
--- /dev/null
+\r
+/*\r
+ * This is a little test application to test your eclipse IDE with the\r
+ * GNUARM-Toolchain and newlib-lpc_rel_2 provided by aeolus\r
+ */\r
+\r
+#include <stdio.h>\r
+#include <errno.h>\r
+\r
+#include <lpc210x.h>\r
+#include <dev_cntrl.h>\r
+#include <lpc_ioctl.h>\r
+#include <lpc_sys.h>\r
+\r
+\r
+\r
+\r
+\r
+int main(void)\r
+{\r
+unsigned long actual_freq; \r
+\r
+ /*\r
+ * set oscillator frequency (round it up ;)\r
+ * 7373kHz (7,373MHz)\r
+ */\r
+ SetNativeSpeed(_impure_ptr, 7373uL);\r
+ \r
+ /*\r
+ * set up memory access, CPU and bus speeds, this may be very oversized,\r
+ * just copied and pasted from the newlib examples...\r
+ */\r
+ \r
+ SetMAM(_impure_ptr, 3u, MAM_full_enable);\r
+ VPBControl(_impure_ptr, VPB_DIV1);\r
+ SetDesiredSpeed(_impure_ptr, 60000uL);\r
+ \r
+ \r
+ StartClock(_impure_ptr);\r
+ \r
+ actual_freq = ActualSpeed();\r
+ \r
+ return(0);\r
+}\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = armtest_pwm
+
+test_SOURCES = armtest_pwm.c
+#test_LIBS = boot_fn
+
+#link_VARIANTS = boot ram bload flash
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (14745000) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+#error Fosc out of range (10MHz-25MHz)\r
+#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+ /******************************************************************************/\r
+ /* This file is part of the uVision/ARM development tools */\r
+ /* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */\r
+ /******************************************************************************/\r
+ /* */\r
+ /* PWM.C: LED Flasher */\r
+ /* */\r
+ /******************************************************************************/\r
+ \r
+ \r
+ \r
+#include <types.h>\r
+#include <LPC210x.h>\r
+#include "config.h"\r
+#include "armVIC.h"\r
+ \r
+ \r
+ \r
+ /**\r
+ * * Function Name: lowInit()\r
+ *\r
+ * Description:\r
+ * This function starts up the PLL then sets up the GPIO pins before\r
+ * waiting for the PLL to lock. It finally engages the PLL and\r
+ * returns\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ * \r
+ */\r
+ static void lowInit(void)\r
+{\r
+ // set PLL multiplier & divisor.\r
+ // values computed from config.h\r
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;\r
+ \r
+ // enable PLL\r
+ PLLCON = PLLCON_PLLE;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup the parallel port pin\r
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output\r
+ IOSET = PIO_ONE_BITS; // set the ONEs output\r
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction\r
+ \r
+ // wait for PLL lock\r
+ while (!(PLLSTAT & PLLSTAT_LOCK))\r
+ continue;\r
+ \r
+ // enable & connect PLL\r
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup & enable the MAM\r
+ MAMTIM = MAMTIM_CYCLES;\r
+ MAMCR = MAMCR_FULL;\r
+ \r
+ // set the peripheral bus speed\r
+ // value computed from config.h\r
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed\r
+}\r
+ \r
+ \r
+ /**\r
+ * Function Name: sysInit()\r
+ *\r
+ * Description:\r
+ * This function is responsible for initializing the program\r
+ * specific hardware\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ * \r
+ */\r
+ \r
+\r
+ static void sysInit(void)\r
+{\r
+ lowInit(); // setup clocks and processor port pins\r
+ \r
+ // set the interrupt controller defaults\r
+#define RAM_RUN\r
+#if defined(RAM_RUN)\r
+ MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM\r
+#elif defined(ROM_RUN)\r
+ MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH\r
+#else\r
+#error RUN_MODE not defined!\r
+#endif\r
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts\r
+ VICIntSelect = 0x00000000; // clear all FIQ selections\r
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()\r
+ \r
+ // wdtInit(); // initialize the watchdog timer\r
+ // initSysTime(); // initialize the system timer\r
+ // uart0Init(UART_BAUD(HOST_BAUD), UART_8N1, UART_FIFO_8); // setup the UART\r
+}\r
+ \r
+ void PWM0_isr(void) __attribute__ ((interrupt ("IRQ")));\r
+ void PWM0_isr(void)\r
+{\r
+ PWMIR |= 0x00000001; // Clear match0 interrupt \r
+ VICVectAddr = 0x00000000;\r
+} \r
+ \r
+ \r
+ \r
+ /**\r
+ * *********************************** void init_PWM (void)***********************************************\r
+ * This function initialise PWM registers in order to:\r
+ * -use PWM 2,4,6 channels\r
+ * -set the corresponding output pins enable\r
+ * -be able to modify the duty cycle while running\r
+ * \r
+ */\r
+ void init_PWM (void) {\r
+ VICVectAddr8 = (unsigned)PWM0_isr; /* Set the PWM ISR vector address */\r
+ VICVectCntl8 = 0x00000028; /* Set channel */\r
+ VICIntEnable = 0x00000100; /* Enable the interrupt */\r
+ \r
+ PINSEL0 |= 0x000A8000; /* Enable P0.7, 8 and P0.9 as alternate PWM outputs functions*/\r
+ PINSEL0 &= 0xFFFABFFF;\r
+ \r
+ PWMPR = 0x00000000; /* Load prescaler */\r
+ \r
+ PWMPCR = 0x00005400; /* PWM channel 2 & 3 double edge control, output enabled */\r
+ PWMMCR = 0x00000002; /* On match with timer reset the counter */\r
+ PWMMR0 = 0x400; /* set cycle rate */\r
+ \r
+ PWMMR2 = 0x100; /* set falling edge of PWM2 */\r
+ PWMMR2 = 0x200; /* set falling edge of PWM2 */\r
+ PWMMR6 = 0x300; /* set falling edge of PWM3 */\r
+ PWMLER = 0x55; /* enable shadow latch for match 1 - 6 */ \r
+ //PWMEMR = 0x00210A8E; /* Match 1 and Match 2 outputs set high */\r
+ PWMTCR = 0x00000002; /* Reset counter and prescaler */ \r
+ PWMTCR = 0x00000009; /* enable counter and PWM, release counter from reset */\r
+ \r
+ }\r
+ \r
+ \r
+ void main() {\r
+ // unsigned int n;\r
+ // int rx_char;\r
+ sysInit();\r
+ \r
+ init_PWM();\r
+ \r
+ while (1) { /* Loop forever */\r
+ \r
+ \r
+ }\r
+ }\r
--- /dev/null
+#include "can.h"
+
+volatile int can_msg_received = 0;
+volatile can_msg_t can_rx_msg;
+
+/* private global variables */
+uint32_t *can_rx_msg_data = (uint32_t*)can_rx_msg.data;
+can_rx_callback can_rx_cb;
+
+void can_init(uint32_t btr, unsigned rx_isr_vect, can_rx_callback rx_cb) {
+ /* enable CAN1 Rx pin */
+ PINSEL1 |= 0x00040000;
+ PINSEL1 &= 0xfff7ffff;
+ /* receive all messages, no filtering */
+ AFMR = 0x2;
+ /* reset mode */
+ C1MOD = 0x1;
+ /* -- addition from lpc2000 maillist msg #3052: */
+ C1CMR = 0x0e; //Clear receive buffer, data overrun, abort tx
+ /* -- end of addition */
+ C1IER = 0x0;
+ C1GSR = 0x0;
+ /* set baudrate & timing */
+ C1BTR = btr;
+ /* register Rx handler */
+ can_rx_cb = rx_cb;
+ /* set interrupt vector */
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (uint32_t)can_rx_isr;
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x20 | 26;
+ /* enable Rx int */
+ VICIntEnable = 0x04000000;
+ C1IER = 0x1;
+ /* normal (operating) mode */
+ C1MOD = 0x0;
+#if 0
+ /* LPC2119 CAN.5 erratum workaround */
+ C1TFI1 = 0x00000000;
+ C1TID1 = 0x0;
+ C1CMR = 0x23;
+#endif
+}
+
+void can_rx_isr() {
+ can_rx_msg.flags = C1RFS;
+ can_rx_msg.dlc = (can_rx_msg.flags>>16) & 0xf;
+ can_rx_msg.id = C1RID;
+ can_rx_msg_data[0] = C1RDA;
+ can_rx_msg_data[1] = C1RDB;
+ can_msg_received = 1;
+ if (can_rx_cb != NULL)
+ can_rx_cb((can_msg_t*)&can_rx_msg);
+ /* release Rx buffer */
+ C1CMR = 0x4;
+ /* int acknowledge */
+ VICVectAddr = 0;
+}
+
+int can_tx_msg(can_msg_t *tx_msg) {
+ uint32_t *data = (uint32_t*)tx_msg->data;
+
+ /* check, if buffer is ready (previous Tx completed) */
+ if ((C1SR & 0x4) == 0)
+ return -1; /* busy */
+ C1TFI1 = (tx_msg->flags & 0xc0000000) |
+ ((tx_msg->dlc<<16) & 0x000f0000);
+ C1TID1 = tx_msg->id;
+ C1TDA1 = data[0];
+ C1TDB1 = data[1];
+ /* start transmission */
+ C1CMR = 0x21;
+ return 0; /* OK */
+}
+
+/*EOF*/
--- /dev/null
+# Doxyfile 1.4.1-KDevelop
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = first.kdevelop
+PROJECT_NUMBER = $VERSION$
+OUTPUT_DIRECTORY =
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = NO
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = YES
+STRIP_FROM_PATH = /home/cabrit/
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = NO
+INHERIT_DOCS = YES
+DISTRIBUTE_GROUP_DOC = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = NO
+OPTIMIZE_OUTPUT_JAVA = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = NO
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = NO
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = YES
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = /home/cabrit/arm/h8300-boot/app/arm/first
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm \
+ *.dox \
+ *.C \
+ *.CC \
+ *.C++ \
+ *.II \
+ *.I++ \
+ *.H \
+ *.HH \
+ *.H++ \
+ *.CS \
+ *.PHP \
+ *.PHP3 \
+ *.M \
+ *.MM \
+ *.C \
+ *.H \
+ *.tlh \
+ *.diff \
+ *.patch \
+ *.moc \
+ *.xpm \
+ *.dox
+RECURSIVE = yes
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION = YES
+VERBATIM_HEADERS = YES
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = YES
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = yes
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE = first.tag
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = YES
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = NO
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = first
+
+first_SOURCES = main.c
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (14745000) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+#error Fosc out of range (10MHz-25MHz)\r
+#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+<?xml version = '1.0'?>
+<kdevelop>
+ <general>
+ <author>LAGARRIGUE</author>
+ <email>glagarri@etud.insa-toulouse.fr</email>
+ <version>$VERSION$</version>
+ <projectmanagement>KDevCustomProject</projectmanagement>
+ <primarylanguage>C</primarylanguage>
+ <ignoreparts/>
+ </general>
+ <kdevcustomproject>
+ <run>
+ <mainprogram>first</mainprogram>
+ <directoryradio>executable</directoryradio>
+ </run>
+ </kdevcustomproject>
+ <kdevdebugger>
+ <general>
+ <dbgshell/>
+ </general>
+ </kdevdebugger>
+ <kdevdoctreeview>
+ <ignoretocs>
+ <toc>ada</toc>
+ <toc>ada_bugs_gcc</toc>
+ <toc>bash</toc>
+ <toc>bash_bugs</toc>
+ <toc>clanlib</toc>
+ <toc>fortran_bugs_gcc</toc>
+ <toc>gnome1</toc>
+ <toc>gnustep</toc>
+ <toc>gtk</toc>
+ <toc>gtk_bugs</toc>
+ <toc>haskell</toc>
+ <toc>haskell_bugs_ghc</toc>
+ <toc>java_bugs_gcc</toc>
+ <toc>java_bugs_sun</toc>
+ <toc>kde2book</toc>
+ <toc>libstdc++</toc>
+ <toc>opengl</toc>
+ <toc>pascal_bugs_fp</toc>
+ <toc>php</toc>
+ <toc>php_bugs</toc>
+ <toc>perl</toc>
+ <toc>perl_bugs</toc>
+ <toc>python</toc>
+ <toc>python_bugs</toc>
+ <toc>qt-kdev3</toc>
+ <toc>ruby</toc>
+ <toc>ruby_bugs</toc>
+ <toc>sdl</toc>
+ <toc>stl</toc>
+ <toc>sw</toc>
+ <toc>w3c-dom-level2-html</toc>
+ <toc>w3c-svg</toc>
+ <toc>w3c-uaag10</toc>
+ <toc>wxwidgets_bugs</toc>
+ </ignoretocs>
+ <ignoreqt_xml>
+ <toc>Guide to the Qt Translation Tools</toc>
+ <toc>Qt Assistant Manual</toc>
+ <toc>Qt Designer Manual</toc>
+ <toc>Qt Reference Documentation</toc>
+ <toc>qmake User Guide</toc>
+ </ignoreqt_xml>
+ <ignoredoxygen>
+ <toc>KDE Libraries (Doxygen)</toc>
+ </ignoredoxygen>
+ </kdevdoctreeview>
+ <kdevfilecreate>
+ <filetypes/>
+ <useglobaltypes>
+ <type ext="c" />
+ <type ext="h" />
+ </useglobaltypes>
+ </kdevfilecreate>
+ <kdevcppsupport>
+ <references/>
+ <codecompletion>
+ <includeGlobalFunctions>true</includeGlobalFunctions>
+ <includeTypes>true</includeTypes>
+ <includeEnums>true</includeEnums>
+ <includeTypedefs>false</includeTypedefs>
+ <automaticCodeCompletion>true</automaticCodeCompletion>
+ <automaticArgumentsHint>true</automaticArgumentsHint>
+ <automaticHeaderCompletion>true</automaticHeaderCompletion>
+ <codeCompletionDelay>250</codeCompletionDelay>
+ <argumentsHintDelay>400</argumentsHintDelay>
+ <headerCompletionDelay>250</headerCompletionDelay>
+ </codecompletion>
+ </kdevcppsupport>
+ <kdevfileview>
+ <groups>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ <hidenonlocation>false</hidenonlocation>
+ </groups>
+ <tree>
+ <hidepatterns>*.o,*.lo,CVS</hidepatterns>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ </tree>
+ </kdevfileview>
+</kdevelop>
--- /dev/null
+# KDevelop Custom Project File List
+main.c
+Makefile
+Makefile.omk
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE KDevPrjSession>
+<KDevPrjSession>
+ <DocsAndViews NumberOfDocuments="4" >
+ <Doc0 NumberOfViews="1" URL="file:/home/cabrit/arm/h8300-boot/app/arm/first/main.c" >
+ <View0 line="88" Type="Source" />
+ </Doc0>
+ <Doc1 NumberOfViews="1" URL="file:/home/cabrit/arm/h8300-boot/arch/arm/mach-lpc2106/libs/crt0.S" >
+ <View0 line="28" Type="Source" />
+ </Doc1>
+ <Doc2 NumberOfViews="1" URL="file:/home/cabrit/arm/h8300-boot/arch/arm/mach-lpc2106/libs/lpc2106.ld-ramisp" >
+ <View0 line="0" Type="Source" />
+ </Doc2>
+ <Doc3 NumberOfViews="1" URL="file:/home/cabrit/arm/h8300-boot/arch/arm/mach-lpc2106/tools/lpc21isp.c" >
+ <View0 line="119" Type="Source" />
+ </Doc3>
+ </DocsAndViews>
+ <pluginList>
+ <kdevdebugger>
+ <breakpointList/>
+ </kdevdebugger>
+ <kdevbookmarks>
+ <bookmarks/>
+ </kdevbookmarks>
+ <kdevrbdebugger>
+ <breakpointList/>
+ <watchExpressions/>
+ </kdevrbdebugger>
+ <kdevvalgrind>
+ <executable path="" params="" />
+ <valgrind path="" params="" />
+ <calltree path="" params="" />
+ <kcachegrind path="" />
+ </kdevvalgrind>
+ </pluginList>
+</KDevPrjSession>
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * A simple program which sends a greeting to UART0, then echos\r
+ * characters on UART0 and blinks an LED every 1/2 second.\r
+ * from: Bill Knight, R O SoftWare <BillK@rosw.com>\r
+ * ----------------------------------------------------------------------------\r
+ *\r
+ * - Adapted to the Olimex LPC-P2106 demo-board (Philips LPC2106).\r
+ * - Sends message if button/switch on demo-board is hit.\r
+ * - Slightly modified and extended as WinARM demo-application.\r
+ * by Martin THOMAS <eversmith@heizung-thomas.de>\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ *****************************************************************************/\r
+#include <types.h>\r
+#include <LPC210x.h>\r
+#include "config.h"\r
+#include "armVIC.h"\r
+//#include "sysTime.h"\r
+//#include "uart.h"\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: lowInit()\r
+ *\r
+ * Description:\r
+ * This function starts up the PLL then sets up the GPIO pins before\r
+ * waiting for the PLL to lock. It finally engages the PLL and\r
+ * returns\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ *****************************************************************************/\r
+static void lowInit(void)\r
+{\r
+ // set PLL multiplier & divisor.\r
+ // values computed from config.h\r
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;\r
+\r
+ // enable PLL\r
+ PLLCON = PLLCON_PLLE;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+\r
+ // setup the parallel port pin\r
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output\r
+ IOSET = PIO_ONE_BITS; // set the ONEs output\r
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction\r
+\r
+ // wait for PLL lock\r
+ while (!(PLLSTAT & PLLSTAT_LOCK))\r
+ continue;\r
+\r
+ // enable & connect PLL\r
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+\r
+ // setup & enable the MAM\r
+ MAMTIM = MAMTIM_CYCLES;\r
+ MAMCR = MAMCR_FULL;\r
+\r
+ // set the peripheral bus speed\r
+ // value computed from config.h\r
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed\r
+}\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: sysInit()\r
+ *\r
+ * Description:\r
+ * This function is responsible for initializing the program\r
+ * specific hardware\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ *****************************************************************************/\r
+static void sysInit(void)\r
+{\r
+ lowInit(); // setup clocks and processor port pins\r
+\r
+ // set the interrupt controller defaults\r
+ #define RAM_RUN\r
+#if defined(RAM_RUN)\r
+ MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM\r
+#elif defined(ROM_RUN)\r
+ MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH\r
+#else\r
+#error RUN_MODE not defined!\r
+#endif\r
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts\r
+ VICIntSelect = 0x00000000; // clear all FIQ selections\r
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()\r
+\r
+// wdtInit(); // initialize the watchdog timer\r
+// initSysTime(); // initialize the system timer\r
+// uart0Init(UART_BAUD(HOST_BAUD), UART_8N1, UART_FIFO_8); // setup the UART\r
+}\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: button_state()\r
+ *\r
+ * Description:\r
+ * This function checks if a key has been pressed. Assumes\r
+ * key to be "active low" (PIN-Bit==0 -> pressed). Does\r
+ * debouncing for given debounce time-difference\r
+ *\r
+ * Calling Sequence: \r
+ * GPIO-Initialisation for Inputs\r
+ *\r
+ * Returns:\r
+ * -1 : key changed or bouncing\r
+ * 0 : key released\r
+ * 1 : key pressed\r
+ *\r
+ *****************************************************************************/\r
+#define KEY_DEBOUNCE FIFTY_MS\r
+#if 0\r
+static int button_state(void)\r
+{\r
+ static uint32_t lastchangetime;\r
+ static boolean laststate=FALSE;\r
+ boolean actstate;\r
+ \r
+ actstate = (IOPIN & SW1_BIT) ? FALSE : TRUE; // TRUE if pressed (active low)\r
+ \r
+ if (laststate != actstate) {\r
+ lastchangetime = getSysTICs();\r
+ laststate = actstate;\r
+ }\r
+ else {\r
+ if (getElapsedSysTICs(lastchangetime) > KEY_DEBOUNCE) {\r
+ if (actstate) return 1;\r
+ else return 0;\r
+ }\r
+ }\r
+ return -1; // changed or bouncing\r
+}\r
+#endif\r
+/******************************************************************************\r
+ *\r
+ * Function Name: main()\r
+ *\r
+ * Description:\r
+ * This function is the program entry point. After initializing the\r
+ * system, it sends a greeting out UART0 then enters an endless loop\r
+ * echoing chracters on the UART and blinking an LED every half\r
+ * second.\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ *****************************************************************************/\r
+int main(void)\r
+{\r
+ uint32_t startTime;\r
+ boolean lock=FALSE;\r
+ \r
+ sysInit();\r
+#if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)\r
+ //enableIRQ();\r
+#endif\r
+\r
+#if 0\r
+ startTime = getSysTICs();\r
+ \r
+ uart0Puts("\r\nHello World!\r\n");\r
+ uart0Puts("(a WinARM Demo-Application based on code from R O Software)\r\n\r\n");\r
+\r
+ for (;;)\r
+ {\r
+ do\r
+ {\r
+ int ch;\r
+\r
+ if ((ch = uart0Getch()) >= 0) {\r
+ uart0Puts("the <");\r
+ uart0Putch(ch);\r
+ uart0Puts("> key has been pressed\r\n");\r
+ }\r
+ \r
+ // send button-pressed string only once if hit\r
+ if (button_state()==0) lock=FALSE; // release lock if button is released\r
+ if ((button_state()==1) && !lock) \r
+ {\r
+ uart0Puts("\r\nButton Pressed!\r\n");\r
+ lock=TRUE;\r
+ }\r
+ }\r
+ while (getElapsedSysTICs(startTime) < HALF_SEC);\r
+\r
+ if (IOPIN & LED1_BIT) IOCLR = LED1_BIT;\r
+ else IOSET = LED1_BIT; \r
+\r
+ startTime += HALF_SEC;\r
+ }\r
+#endif\r
+ return 0;\r
+ \r
+}\r
--- /dev/null
+!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/
+!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/
+!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/
+!_TAG_PROGRAM_NAME Exuberant Ctags //
+!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/
+!_TAG_PROGRAM_VERSION 5.5.4 //
+BIT config.h /^#define BIT(/;" d
+CCLK config.h /^#define CCLK /;" d
+FALSE config.h /^#define FALSE /;" d
+FOSC config.h /^#define FOSC /;" d
+HOST_BAUD config.h /^#define HOST_BAUD /;" d
+INC_CONFIG_H config.h /^#define INC_CONFIG_H$/;" d
+KEY_DEBOUNCE main.c /^#define KEY_DEBOUNCE /;" d file:
+LED1_BIT config.h /^#define LED1_BIT /;" d
+P02_UNUSED_BIT config.h /^#define P02_UNUSED_BIT /;" d
+P03_UNUSED_BIT config.h /^#define P03_UNUSED_BIT /;" d
+P04_UNUSED_BIT config.h /^#define P04_UNUSED_BIT /;" d
+P05_UNUSED_BIT config.h /^#define P05_UNUSED_BIT /;" d
+P06_UNUSED_BIT config.h /^#define P06_UNUSED_BIT /;" d
+P08_UNUSED_BIT config.h /^#define P08_UNUSED_BIT /;" d
+P09_UNUSED_BIT config.h /^#define P09_UNUSED_BIT /;" d
+P10_UNUSED_BIT config.h /^#define P10_UNUSED_BIT /;" d
+P11_UNUSED_BIT config.h /^#define P11_UNUSED_BIT /;" d
+P12_UNUSED_BIT config.h /^#define P12_UNUSED_BIT /;" d
+P13_UNUSED_BIT config.h /^#define P13_UNUSED_BIT /;" d
+P14_UNUSED_BIT config.h /^#define P14_UNUSED_BIT /;" d
+P15_UNUSED_BIT config.h /^#define P15_UNUSED_BIT /;" d
+P16_UNUSED_BIT config.h /^#define P16_UNUSED_BIT /;" d
+P17_UNUSED_BIT config.h /^#define P17_UNUSED_BIT /;" d
+P18_UNUSED_BIT config.h /^#define P18_UNUSED_BIT /;" d
+P19_UNUSED_BIT config.h /^#define P19_UNUSED_BIT /;" d
+P20_UNUSED_BIT config.h /^#define P20_UNUSED_BIT /;" d
+P21_UNUSED_BIT config.h /^#define P21_UNUSED_BIT /;" d
+P22_UNUSED_BIT config.h /^#define P22_UNUSED_BIT /;" d
+P23_UNUSED_BIT config.h /^#define P23_UNUSED_BIT /;" d
+P24_UNUSED_BIT config.h /^#define P24_UNUSED_BIT /;" d
+P25_UNUSED_BIT config.h /^#define P25_UNUSED_BIT /;" d
+P26_UNUSED_BIT config.h /^#define P26_UNUSED_BIT /;" d
+P27_UNUSED_BIT config.h /^#define P27_UNUSED_BIT /;" d
+P28_UNUSED_BIT config.h /^#define P28_UNUSED_BIT /;" d
+P29_UNUSED_BIT config.h /^#define P29_UNUSED_BIT /;" d
+P30_UNUSED_BIT config.h /^#define P30_UNUSED_BIT /;" d
+PBSD config.h /^#define PBSD /;" d
+PCLK config.h /^#define PCLK /;" d
+PIO_INPUT_BITS config.h /^#define PIO_INPUT_BITS /;" d
+PIO_ONE_BITS config.h /^#define PIO_ONE_BITS /;" d
+PIO_OUTPUT_BITS config.h /^#define PIO_OUTPUT_BITS /;" d
+PIO_ZERO_BITS config.h /^#define PIO_ZERO_BITS /;" d
+PLL_MUL config.h /^#define PLL_MUL /;" d
+RAM_RUN main.c /^ #define RAM_RUN$/;" d file:
+RXD0_BIT config.h /^#define RXD0_BIT /;" d
+SW1_BIT config.h /^#define SW1_BIT /;" d
+TRUE config.h /^#define TRUE /;" d
+TXD0_BIT config.h /^#define TXD0_BIT /;" d
+WDOG config.h /^#define WDOG(/;" d
+abort config.h /^extern void abort(void);$/;" p
+lowInit main.c /^static void lowInit(void)$/;" f file:
+main main.c /^int main(void)$/;" f
+reset config.h /^extern void reset(void);$/;" p
+sysInit main.c /^static void sysInit(void)$/;" f file:
--- /dev/null
+#include <lpc21xx.h>
+#include <types.h>
+
+
+void delay() {
+ unsigned u;
+
+ for (u = 0; u < 1000000; u++);
+}
+
+/*** PWM ***/
+
+int PWM_PINSEL[] = {
+ /*nothing*/ 1, /*PWM1*/ 1, 15, 3, 17, /*PWM5*/ 11, /*PWM6*/ 19
+};
+
+uint32_t *PWM_MR[] = {
+ (uint32_t*)&(PWMMR0),
+ (uint32_t*)&(PWMMR1),
+ (uint32_t*)&(PWMMR2),
+ (uint32_t*)&(PWMMR3),
+ (uint32_t*)&(PWMMR4),
+ (uint32_t*)&(PWMMR5),
+ (uint32_t*)&(PWMMR6)
+};
+
+void pwm_channel(int n, int double_edge) {
+ uint32_t bit;
+
+ PWMPCR |= (0x100 | (double_edge && n)) << n;
+ if (n == 5) {
+ PINSEL1 |= 0x00000400;
+ PINSEL1 &= 0xfffff7ff;
+ }
+ else {
+ bit = 1 << PWM_PINSEL[n];
+ PINSEL0 |= bit;
+ bit = ~(bit >> 1);
+ PINSEL0 &= bit;
+ }
+}
+
+void pwm_set(int n, uint32_t when) {
+ *PWM_MR[n] = when;
+ PWMLER |= 1 << n;
+}
+
+void pwm_set_double(int n, uint32_t from, uint32_t to) {
+ *PWM_MR[n-1] = from;
+ *PWM_MR[n] = to;
+ PWMLER |= 0x3 << (n-1);
+}
+
+void pwm_init(uint32_t prescale, uint32_t period) {
+ PWMPR = prescale;
+ PWMMR0 = period;
+ PWMLER |= 0x1;
+ PWMMCR |= 0x00000002;
+ PWMTCR &= ~0x2;
+ PWMTCR |= 0x9;
+}
+
+/***********/
+
+void motor_drive(float u) {
+ uint32_t d = (float)PWMMR0*(0.5*(1.0+u));
+
+ pwm_set_double(2, 0, d);
+ pwm_set_double(4, d, 0);
+}
+
+
+int main() {
+ pwm_channel(2, 1);
+ pwm_channel(4, 1);
+ pwm_init(0, 50);
+
+ motor_drive(0);
+
+ for (;;);
+}
--- /dev/null
+# Doxyfile 1.4.1-KDevelop
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = test_pwm.kdevelop
+PROJECT_NUMBER = $VERSION$
+OUTPUT_DIRECTORY =
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = NO
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = YES
+STRIP_FROM_PATH = /home/cabrit/arm/lpc21xx-boot/app/arm/armtest_pwm/
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = NO
+INHERIT_DOCS = YES
+DISTRIBUTE_GROUP_DOC = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = NO
+OPTIMIZE_OUTPUT_JAVA = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = NO
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = NO
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = YES
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = /home/cabrit/arm/lpc21xx-boot/app/arm/test_pwm
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm \
+ *.dox \
+ *.C \
+ *.CC \
+ *.C++ \
+ *.II \
+ *.I++ \
+ *.H \
+ *.HH \
+ *.H++ \
+ *.CS \
+ *.PHP \
+ *.PHP3 \
+ *.M \
+ *.MM \
+ *.C \
+ *.H \
+ *.tlh \
+ *.diff \
+ *.patch \
+ *.moc \
+ *.xpm \
+ *.dox
+RECURSIVE = yes
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION = YES
+VERBATIM_HEADERS = YES
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = YES
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = yes
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE = test_pwm.tag
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = YES
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = NO
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = test_pwm
+
+test_pwm_SOURCES = test_pwm.c pwm.c
+#test_LIBS = boot_fn
+
+#link_VARIANTS = boot ram bload flash
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (7372800) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+#error Fosc out of range (10MHz-25MHz)\r
+#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+/*
+* C Implementation: pwm
+*
+* Description: configuration of PWM unit
+*
+*
+* Author: LAGARRIGUE <glagarri@etud.insa-toulouse.fr>, (C) 2005
+*
+* Copyright: See COPYING file that comes with this distribution
+*
+*/
+
+
+#include <LPC210x.h>
+#include "config.h"
+#include "pwm.h"
+
+#define MINFREQ (PCLK/(0xFFFFFFFF))
+
+/**
+ * Initializes PWM frequency with match0 register
+ * @param freq frequency in Hz
+ */
+void Init_PWM(int freq)
+{
+ if ((freq <= PCLK) | (freq >= MINFREQ))
+ {
+ PWMPR = 0x00000000; //no prescaler
+ PWMMCR = 0x00000002; // on match with MATCH0 Register, reset the counter
+ PWMMR0 = (int)(PCLK/(freq));
+ }
+
+
+}
+
+/**
+ * Initilizes and sets the duty cycle of the desired pwm channel
+ * @param channel = channel number (1,2,3,4,5,6)
+ * @param duty_cycle = float between 0 and 1
+ */
+void Set_PWM (int channel, float duty_cycle)
+{
+ int Pwmmatch;
+ Pwmmatch = (int) (duty_cycle * PWMMR0);
+
+
+
+ //PINSEL0 |= ...; /* Enable P0.7, 8 and P0.9 as alternate PWM outputs functions*/
+ //PINSEL0 &= ...;
+
+ //PWMPCR = ...; /* single edge control only*/
+
+ //PWMMRX = 0x500; /* set falling edge of PWM channel X */
+
+ //PWMLER = 0x..; /* enable shadow latch for match 1 - 6 */
+
+
+ switch (channel)
+ {
+
+
+ case 1 :
+ PWMMR1 =Pwmmatch;
+ PWMPCR |= 0x0200;
+ PWMLER |= 0x02;
+ PINSEL0 |= 0x00000002;
+ PINSEL0 &= 0xFFFFFFFE;
+ break;
+
+ case 2 :
+ PWMMR2 =Pwmmatch;
+ PWMPCR |= 0x0400;
+ PWMLER |= 0x04;
+ PINSEL0 |= 0x00008000;
+ PINSEL0 &= 0xFFFFBFFF;
+ break;
+
+ case 3 :
+ PWMMR3 =Pwmmatch;
+ PWMPCR |= 0x0800;
+ PWMLER |= 0x08;
+ PINSEL0 |= 0x00000008;
+ PINSEL0 &= 0xFFFFFFFB;
+ break;
+ case 4 :
+ PWMMR4 =Pwmmatch;
+ PWMPCR |= 0x1000;
+ PWMLER |= 0x10;
+ PINSEL0 |= 0x00020000;
+ PINSEL0 &= 0xFFFEFFFF;
+ break;
+
+ case 5 :
+ PWMMR5 =Pwmmatch;
+ PWMPCR |= 0x2000;
+ PWMLER |= 0x20;
+ PINSEL1 |= 0x00000400;
+ PINSEL1 &= 0xFFFFF7FF;
+ break;
+
+ case 6 :
+ PWMMR6 =Pwmmatch;
+ PWMPCR |= 0x4000;
+ PWMLER |= 0x40;
+ PINSEL0 |= 0x00080000;
+ PINSEL0 &= 0xFFFBFFFF;
+ break;
+
+
+ }
+
+}
+
+
+/**
+ * Resets the counter and runs the PWM unit
+ * @param
+ */
+void Run_PWM (void)
+{
+ PWMTCR = 0x2; /* Reset counter and prescaler */
+ PWMTCR = 0x9; /* enable counter and PWM, release counter from reset */
+}
+
+
+/**
+ * Stops PWM unit and resets the timer
+ * @param
+ */
+void Stop_PWM (void)
+{
+ int i;
+ for (i=1 ; i < 7 ; i++)
+ {
+ Set_PWM (i, 0);
+ }
+ PWMTCR = 0x2;
+}
\ No newline at end of file
--- /dev/null
+//
+// pwm.h
+//
+// Description: PWM unit configuration
+//
+//
+// Author: LAGARRIGUE <glagarri@etud.insa-toulouse.fr>, (C) 2005
+//
+// Copyright: See COPYING file that comes with this distribution
+//
+//
+#include <LPC210x.h>
+#include "config.h"
+
+
+#define MINFREQ (PCLK/(0xFFFFFFFF))
+
+void Init_PWM(int freq);
+void Set_PWM (int channel, float duty_cycle);
+void Run_PWM (void);
+void Stop_PWM (void);
--- /dev/null
+#!/bin/sh
+
+cd `pwd|sed -e 's/lpc21xx-boot/h8300-boot/'`
+
+make load
--- /dev/null
+ /******************************************************************************/\r
+ /* This file is part of the uVision/ARM development tools */\r
+ /* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */\r
+ /******************************************************************************/\r
+ /* */\r
+ /* PWM.C: LED Flasher */\r
+ /* */\r
+ /******************************************************************************/\r
+ \r
+ \r
+ \r
+#include <types.h>\r
+#include <LPC210x.h>\r
+#include "config.h"\r
+#include "pwm.h"\r
+ \r
+ \r
+\r
+ /**\r
+ * * Function Name: lowInit()\r
+ *\r
+ * Description:\r
+ * This function starts up the PLL then sets up the GPIO pins before\r
+ * waiting for the PLL to lock. It finally engages the PLL and\r
+ * returns\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ * \r
+ */\r
+ static void lowInit(void)\r
+{\r
+ // set PLL multiplier & divisor.\r
+ // values computed from config.h\r
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;\r
+ \r
+ // enable PLL\r
+ PLLCON = PLLCON_PLLE;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup the parallel port pin\r
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output\r
+ IOSET = PIO_ONE_BITS; // set the ONEs output\r
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction\r
+ \r
+ // wait for PLL lock\r
+ while (!(PLLSTAT & PLLSTAT_LOCK))\r
+ continue;\r
+ \r
+ // enable & connect PLL\r
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup & enable the MAM\r
+ MAMTIM = MAMTIM_CYCLES;\r
+ MAMCR = MAMCR_FULL;\r
+ \r
+ // set the peripheral bus speed\r
+ // value computed from config.h\r
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed\r
+}\r
+ \r
+ \r
+ /**\r
+ * Function Name: sysInit()\r
+ *\r
+ * Description:\r
+ * This function is responsible for initializing the program\r
+ * specific hardware\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ * \r
+ */\r
+ \r
+\r
+ static void sysInit(void)\r
+{\r
+ lowInit(); // setup clocks and processor port pins\r
+ \r
+ // set the interrupt controller defaults\r
+#define RAM_RUN\r
+#if defined(RAM_RUN)\r
+ MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM\r
+#elif defined(ROM_RUN)\r
+ MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH\r
+#else\r
+#error RUN_MODE not defined!\r
+#endif\r
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts\r
+ VICIntSelect = 0x00000000; // clear all FIQ selections\r
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()\r
+ \r
+ \r
+}\r
+ \r
+ /**\r
+ * Creates a delay\r
+ * @param d duration (unit not defined yet)\r
+ */\r
+void\r
+ delay(int d)\r
+{\r
+ volatile int x;\r
+ int i;\r
+ for (i = 0; i < 10; i++)\r
+ for(x = d; x; --x)\r
+ ;\r
+}\r
+ \r
+ \r
+\r
+ /**\r
+ * this function has been created to test PWM unit\r
+ * It has been tested with the DC motor of M.Sojka ;-)\r
+ * One accelerated phase with upward rotation then one constant speed phase with backward rotation\r
+ * DC motor pin 2 = PWM4\r
+ * DC motor pin 3 = PWM6\r
+ * DC motor pin 25 = GND\r
+ * @return \r
+ */\r
+ int main() {\r
+ \r
+ int j;\r
+ \r
+ \r
+ sysInit();\r
+ \r
+ Init_PWM(20000);\r
+ \r
+ Run_PWM();\r
+ Set_PWM (6,0); \r
+ for (j = 0 ; j < 10 ; j++) \r
+ {\r
+ Set_PWM (4, j*0.1);\r
+ delay (500000);\r
+ }\r
+ \r
+ \r
+ \r
+ while (1) \r
+ { /* Loop forever */\r
+ \r
+ }\r
+ return 0;\r
+ }\r
--- /dev/null
+<?xml version = '1.0'?>
+<kdevelop>
+ <general>
+ <author>LAGARRIGUE</author>
+ <email>glagarri@etud.insa-toulouse.fr</email>
+ <version>$VERSION$</version>
+ <projectmanagement>KDevCustomProject</projectmanagement>
+ <primarylanguage>C</primarylanguage>
+ <ignoreparts>
+ <part>kdevpartexplorer</part>
+ <part>kdevrbdebugger</part>
+ <part>kdevvisualboyadvance</part>
+ </ignoreparts>
+ <projectdirectory>.</projectdirectory>
+ <absoluteprojectpath>false</absoluteprojectpath>
+ <description/>
+ <versioncontrol/>
+ </general>
+ <kdevcustomproject>
+ <run>
+ <mainprogram>run</mainprogram>
+ <directoryradio>build</directoryradio>
+ <customdirectory>/home/cabrit/arm/h8300-boot/app/arm/armtest_pwm/</customdirectory>
+ <programargs/>
+ <terminal>false</terminal>
+ <autocompile>true</autocompile>
+ <envvars/>
+ </run>
+ <build>
+ <buildtool>make</buildtool>
+ <builddir>/home/cabrit/arm/h8300-boot/app/arm/test_pwm/</builddir>
+ </build>
+ <make>
+ <abortonerror>false</abortonerror>
+ <numberofjobs>1</numberofjobs>
+ <prio>0</prio>
+ <dontact>false</dontact>
+ <makebin/>
+ <defaulttarget>all</defaulttarget>
+ <makeoptions/>
+ <selectedenvironment>default</selectedenvironment>
+ <environments>
+ <default/>
+ </environments>
+ </make>
+ </kdevcustomproject>
+ <kdevdebugger>
+ <general>
+ <dbgshell/>
+ <programargs/>
+ <gdbpath/>
+ <configGdbScript/>
+ <runShellScript/>
+ <runGdbScript/>
+ <breakonloadinglibs>true</breakonloadinglibs>
+ <separatetty>false</separatetty>
+ <floatingtoolbar>false</floatingtoolbar>
+ </general>
+ <display>
+ <staticmembers>false</staticmembers>
+ <demanglenames>true</demanglenames>
+ <outputradix>10</outputradix>
+ </display>
+ </kdevdebugger>
+ <kdevdoctreeview>
+ <ignoretocs>
+ <toc>ada</toc>
+ <toc>ada_bugs_gcc</toc>
+ <toc>bash</toc>
+ <toc>bash_bugs</toc>
+ <toc>clanlib</toc>
+ <toc>fortran_bugs_gcc</toc>
+ <toc>gnome1</toc>
+ <toc>gnustep</toc>
+ <toc>gtk</toc>
+ <toc>gtk_bugs</toc>
+ <toc>haskell</toc>
+ <toc>haskell_bugs_ghc</toc>
+ <toc>java_bugs_gcc</toc>
+ <toc>java_bugs_sun</toc>
+ <toc>kde2book</toc>
+ <toc>libstdc++</toc>
+ <toc>opengl</toc>
+ <toc>pascal_bugs_fp</toc>
+ <toc>php</toc>
+ <toc>php_bugs</toc>
+ <toc>perl</toc>
+ <toc>perl_bugs</toc>
+ <toc>python</toc>
+ <toc>python_bugs</toc>
+ <toc>qt-kdev3</toc>
+ <toc>ruby</toc>
+ <toc>ruby_bugs</toc>
+ <toc>sdl</toc>
+ <toc>stl</toc>
+ <toc>sw</toc>
+ <toc>w3c-dom-level2-html</toc>
+ <toc>w3c-svg</toc>
+ <toc>w3c-uaag10</toc>
+ <toc>wxwidgets_bugs</toc>
+ </ignoretocs>
+ <ignoreqt_xml>
+ <toc>Guide to the Qt Translation Tools</toc>
+ <toc>Qt Assistant Manual</toc>
+ <toc>Qt Designer Manual</toc>
+ <toc>Qt Reference Documentation</toc>
+ <toc>qmake User Guide</toc>
+ </ignoreqt_xml>
+ <ignoredoxygen>
+ <toc>KDE Libraries (Doxygen)</toc>
+ </ignoredoxygen>
+ </kdevdoctreeview>
+ <kdevfilecreate>
+ <filetypes/>
+ <useglobaltypes>
+ <type ext="c" />
+ <type ext="h" />
+ </useglobaltypes>
+ </kdevfilecreate>
+ <kdevcppsupport>
+ <references/>
+ <codecompletion>
+ <includeGlobalFunctions>true</includeGlobalFunctions>
+ <includeTypes>true</includeTypes>
+ <includeEnums>true</includeEnums>
+ <includeTypedefs>false</includeTypedefs>
+ <automaticCodeCompletion>true</automaticCodeCompletion>
+ <automaticArgumentsHint>true</automaticArgumentsHint>
+ <automaticHeaderCompletion>true</automaticHeaderCompletion>
+ <codeCompletionDelay>250</codeCompletionDelay>
+ <argumentsHintDelay>400</argumentsHintDelay>
+ <headerCompletionDelay>250</headerCompletionDelay>
+ </codecompletion>
+ <creategettersetter>
+ <prefixGet/>
+ <prefixSet>set</prefixSet>
+ <prefixVariable>m_,_</prefixVariable>
+ <parameterName>theValue</parameterName>
+ <inlineGet>true</inlineGet>
+ <inlineSet>true</inlineSet>
+ </creategettersetter>
+ </kdevcppsupport>
+ <kdevfileview>
+ <groups>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ <hidenonlocation>false</hidenonlocation>
+ </groups>
+ <tree>
+ <hidepatterns>*.o,*.lo,CVS</hidepatterns>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ </tree>
+ </kdevfileview>
+ <cppsupportpart>
+ <filetemplates>
+ <interfacesuffix>.h</interfacesuffix>
+ <implementationsuffix>.cpp</implementationsuffix>
+ </filetemplates>
+ </cppsupportpart>
+ <kdevvisualadvance>
+ <emulator>VisualBoyAdvance</emulator>
+ <binary/>
+ <addOptions/>
+ <terminal>false</terminal>
+ <fullscreen>false</fullscreen>
+ <graphicFilter>-f0</graphicFilter>
+ <scaling>-1</scaling>
+ </kdevvisualadvance>
+ <kdevdocumentation>
+ <projectdoc>
+ <docsystem/>
+ <docurl/>
+ <usermanualurl/>
+ </projectdoc>
+ </kdevdocumentation>
+ <ctagspart>
+ <customArguments/>
+ <customTagfilePath/>
+ </ctagspart>
+</kdevelop>
--- /dev/null
+# KDevelop Custom Project File List
+test_pwm.c
+
+
+
+/home/cabrit/arm/lpc21xx-boot/app/arm/armtest_pwm/test_pwm.c
+pwm.c
+pwm.h
--- /dev/null
+<?xml version = '1.0' encoding = 'UTF-8'?>
+<!DOCTYPE KDevPrjSession>
+<KDevPrjSession>
+ <DocsAndViews NumberOfDocuments="3" >
+ <Doc0 NumberOfViews="1" URL="file:/home/cabrit/arm/lpc21xx-boot/app/arm/test_pwm/test_pwm.c" >
+ <View0 Type="Source" />
+ </Doc0>
+ <Doc1 NumberOfViews="1" URL="file:/home/cabrit/arm/lpc21xx-boot/app/arm/test_pwm/pwm.c" >
+ <View0 line="126" Type="Source" />
+ </Doc1>
+ <Doc2 NumberOfViews="1" URL="file:/home/cabrit/arm/lpc21xx-boot/app/arm/test_pwm/pwm.h" >
+ <View0 line="3" Type="Source" />
+ </Doc2>
+ </DocsAndViews>
+ <pluginList>
+ <kdevdebugger>
+ <breakpointList/>
+ </kdevdebugger>
+ <kdevbookmarks>
+ <bookmarks/>
+ </kdevbookmarks>
+ <kdevvalgrind>
+ <executable path="" params="" />
+ <valgrind path="" params="" />
+ <calltree path="" params="" />
+ <kcachegrind path="" />
+ </kdevvalgrind>
+ </pluginList>
+</KDevPrjSession>
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides interface routines to the LPC ARM UARTs.\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ * reduced to see what has to be done for minimum UART-support by mthomas\r
+ *****************************************************************************/\r
+\r
+// #warning "this is a reduced version of the R O Software code"\r
+\r
+#include "uart.h"\r
+\r
+/* on LPC210x: UART0 TX-Pin=P0.2, RX-Pin=P0.1 \r
+ PINSEL0 has to be set to "UART-Function" = Function "01" \r
+ for Pin 0.0 and 0.1 */\r
+ \r
+#define PINSEL_BITPIN0 0\r
+#define PINSEL_BITPIN1 2\r
+// #define PINSEL_BITPIN2 4\r
+#define PINSEL_FIRST_ALT_FUNC 1\r
+// #define PINSEL_SECOND_ALT_FUNC 2\r
+\r
+// Values of Bits 0-3 in PINSEL to activate UART0\r
+#define UART0_PINSEL ((PINSEL_FIRST_ALT_FUNC<<PINSEL_BITPIN0)|(PINSEL_FIRST_ALT_FUNC<<PINSEL_BITPIN1))\r
+// Mask of Bits 0-4\r
+#define UART0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */\r
+\r
+// U0_LCR devisor latch bit \r
+#define UART0_LCR_DLAB 7\r
+\r
+/* baudrate divisor - use UART_BAUD macro\r
+ * mode - see typical modes (uart.h)\r
+ * fmode - see typical fmodes (uart.h)\r
+ * NOTE: uart0Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8); \r
+ */\r
+void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)\r
+{\r
+ // setup Pin Function Select Register (Pin Connect Block) \r
+ // make sure old values of Bits 0-4 are masked out and\r
+ // set them according to UART0-Pin-Selection\r
+/* PCB_PINSEL0 = (PCB_PINSEL0 & ~UART0_PINMASK) | UART0_PINSEL; */\r
+\r
+ U0IER = 0x00; // disable all interrupts\r
+ U0IIR = 0x00; // clear interrupt ID register\r
+ U0LSR = 0x00; // clear line status register\r
+\r
+ // set the baudrate - DLAB must be set to access DLL/DLM\r
+ U0LCR = (1<<UART0_LCR_DLAB); // set divisor latches (DLAB)\r
+ U0DLL = (uint8_t)baud; // set for baud low byte\r
+ U0DLM = (uint8_t)(baud >> 8); // set for baud high byte\r
+ \r
+ // set the number of characters and other\r
+ // user specified operating parameters\r
+ // Databits, Parity, Stopbits - Settings in Line Control Register\r
+ U0LCR = (mode & ~(1<<UART0_LCR_DLAB)); // clear DLAB "on-the-fly"\r
+ // setup FIFO Control Register (fifo-enabled + xx trig) \r
+ U0FCR = fmode;\r
+}\r
+\r
+int uart0Putch(int ch)\r
+{\r
+ while (!(U0LSR & ULSR_THRE)) // wait for TX buffer to empty\r
+ continue; // also either WDOG() or swap()\r
+\r
+ U0THR = (uint8_t)ch; // put char to Transmit Holding Register\r
+ return (uint8_t)ch; // return char ("stdio-compatible"?)\r
+}\r
+\r
+const char *uart0Puts(const char *string)\r
+{\r
+ char ch;\r
+ \r
+ while ((ch = *string)) {\r
+ if (uart0Putch(ch)<0) break;\r
+ string++;\r
+ }\r
+ \r
+ return string;\r
+}\r
+\r
+int uart0TxEmpty(void)\r
+{\r
+ return (U0LSR & (ULSR_THRE | ULSR_TEMT)) == (ULSR_THRE | ULSR_TEMT);\r
+}\r
+\r
+void uart0TxFlush(void)\r
+{\r
+ U0FCR |= UFCR_TX_FIFO_RESET; // clear the TX fifo\r
+}\r
+\r
+\r
+/* Returns: character on success, -1 if no character is available */\r
+int uart0Getch(void)\r
+{\r
+ if (U0LSR & ULSR_RDR) // check if character is available\r
+ return U0RBR; // return character\r
+\r
+ return -1;\r
+}\r
--- /dev/null
+/******************************************************************************\r
+ * based on software from:\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ * \r
+ * reduced to learn what has to be done to enable and use UART0\r
+ *****************************************************************************/\r
+#ifndef INC_UART_H\r
+#define INC_UART_H\r
+\r
+#include <types.h>\r
+#include <LPC210x.h>\r
+\r
+#include "lpcUART.h"\r
+#include "config.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// use the following macros to determine the 'baud' parameter values\r
+// for uart0Init() and uart1Init()\r
+// CAUTION - 'baud' SHOULD ALWAYS BE A CONSTANT or\r
+// a lot of code will be generated.\r
+// Baud-Rate is calculated based on pclk (VPB-clock)\r
+// the devisor must be 16 times the desired baudrate\r
+#define UART_BAUD(baud) (uint16_t)(((FOSC*PLL_MUL/PBSD) / ((baud) * 16.0)) + 0.5)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'baud' settings\r
+#define B1200 UART_BAUD(1200)\r
+#define B9600 UART_BAUD(9600)\r
+#define B19200 UART_BAUD(19200)\r
+#define B38400 UART_BAUD(38400)\r
+#define B57600 UART_BAUD(57600)\r
+#define B115200 UART_BAUD(115200)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'mode' settings\r
+#define UART_8N1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_7N1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_8N2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_7N2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_8E1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_7E1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_8E2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_7E2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_8O1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_7O1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_8O2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+#define UART_7O2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'fmode' settings\r
+#define UART_FIFO_OFF (0x00)\r
+#define UART_FIFO_1 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG1)\r
+#define UART_FIFO_4 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG4)\r
+#define UART_FIFO_8 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG8)\r
+#define UART_FIFO_14 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG14)\r
+\r
+void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode);\r
+int uart0Putch(int ch);\r
+uint16_t uart0Space(void);\r
+const char *uart0Puts(const char *string);\r
+int uart0TxEmpty(void);\r
+void uart0TxFlush(void);\r
+int uart0Getch(void);\r
+\r
+#endif\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+# eb_blink je nazev programu, pod timto navzem bude systemem prekladan
+bin_PROGRAMS = eb_blink
+
+
+# za nazev_programu_SOURCES se davaji vsechny C zdrojaky, ktere se budou kompilovat
+eb_blink_SOURCES = main.c
+
+
--- /dev/null
+////////////////////////////////////////////////////////////////////////////////
+//
+// Eurobot BLINK TEST (with LPC2129)
+//
+// Description
+// -----------
+// This software blinks on debug leds. Use it with lpceurobot board
+// Author : Jiri Kubias DCE CVUT
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <deb_led.h>
+
+
+void dummy_wait()
+{
+ unsigned int wait = 5000000;
+ while(--wait);
+}
+
+int main (void) {
+
+
+
+
+ while(1)
+ {
+ deb_led_change(LEDR);
+ dummy_wait();
+ deb_led_change(LEDG);
+ dummy_wait();
+ deb_led_change(LEDB);
+ dummy_wait();
+ deb_led_change(LEDY);
+ dummy_wait();
+
+ }
+}
+
+
+
--- /dev/null
+//-------------------------------------------------\r
+Created by: Jiri Kubias - CVUT Prague\r
+ \r
+\r
+\r
+ servo.c use ISR vector 1 for Timer 1
\ No newline at end of file
--- /dev/null
+# Doxyfile 1.5.4
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING = UTF-8
+PROJECT_NAME = eb_ebb
+PROJECT_NUMBER = 1
+OUTPUT_DIRECTORY = doc
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class " \
+ "The $name widget " \
+ "The $name file " \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+QT_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+CPP_CLI_SUPPORT = NO
+SIP_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+TYPEDEF_HIDES_STRUCT = NO
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+EXTRACT_ANON_NSPACES = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = NO
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text "
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = .
+INPUT_ENCODING = UTF-8
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.d \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm \
+ *.dox \
+ *.py \
+ *.C \
+ *.CC \
+ *.C++ \
+ *.II \
+ *.I++ \
+ *.H \
+ *.HH \
+ *.H++ \
+ *.CS \
+ *.PHP \
+ *.PHP3 \
+ *.M \
+ *.MM \
+ *.PY \
+ *.C \
+ *.H \
+ *.tlh \
+ *.diff \
+ *.patch \
+ *.moc \
+ *.xpm \
+ *.dox
+RECURSIVE = YES
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXCLUDE_SYMBOLS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+HTML_DYNAMIC_SECTIONS = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE = eb_ebb.tag
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = YES
+MSCGEN_PATH =
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+DOT_GRAPH_MAX_NODES = 50
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = NO
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = eb_ebb
+
+eb_ebb_SOURCES = main.c
+eb_ebb_LIBS = can ebb
+
+
+lib_LIBRARIES = ebb
+ebb_SOURCES = powswitch.c uart.c servo.c engine.c adc.c adc_filtr.c
+
+include_HEADERS = engine.h powswitch.h servo.h uart.h adc.h adc_filtr.h
+
+link_VARIANTS = flash
+
--- /dev/null
+#include <lpc21xx.h> // LPC21XX Peripheral Registers
+#include <types.h>
+#include "adc.h"
+#include <stdlib.h>
+
+
+#define ADCCH0 22 ///< ADC0 value for PINSEL
+#define ADCCH1 24 ///< ADC1 value for PINSEL
+#define ADCCH2 26 ///< ADC2 value for PINSEL
+#define ADCCH3 28 ///< ADC3 value for PINSEL
+
+/**
+ * ADC ISR routine. This routine reads selected ADC value and
+ * multiplies it by #ADC_MUL and adds #ADC_OFFSET to calculate the
+ * volage (3.25mV/div). After this reading the next ADC channel is
+ * set up for measuring.
+ */
+void adc_isr(void) __attribute__ ((interrupt));
+void adc_isr(void)
+{
+ unsigned char chan =0;
+ unsigned int val =0;
+
+
+ chan = (char) ((ADDR>>24) & 0x07);
+ val = (((((ADDR >> 6) & 0x3FF) * ADC_MUL + ADC_OFFSET) + adc_val[chan]) >> 1) ;
+
+
+
+ adc_val[chan] = val;
+
+ ADCR &= ~(ADC_CR_START_OFF_m);
+
+
+ switch(chan)
+ {
+ case 0:
+ ADCR = ((ADC_CR_ADC1_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (20*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 1:
+ ADCR = ((ADC_CR_ADC2_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (20*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 2:
+ ADCR = ((ADC_CR_ADC3_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (20*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 3:
+ ADCR = ((ADC_CR_ADC0_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (20*ADC_CR_CLK_DIV_1_m));
+ break;
+ }
+
+ VICVectAddr = 0;
+
+}
+
+/**
+ * Inicializes ADC service for all ADC (4) channels and installs ISR routine to VIC.
+ * Automaticly starts the conversion of first channel on given conversion frequency.
+ */
+void init_adc(unsigned rx_isr_vect)
+{
+
+ PINSEL1 |= ((PINSEL_1 << ADCCH0) | (PINSEL_1 << ADCCH1) | (PINSEL_1 << ADCCH2) | (PINSEL_1 << ADCCH3));
+
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x32;
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned) adc_isr;
+ VICIntEnable = 0x40000;
+
+ ADCR = ((ADC_CR_ADC0_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+}
--- /dev/null
+#ifndef ADC_H
+#define ADC_H
+
+
+#define ADC_MUL 1 ///< This value multiplies mesured value from ADC
+#define ADC_OFFSET 0 ///< This valueis added to mesured value from ADC
+
+#define ADC_VPB_DIV 255 ///< VPB divisor for ADC FIXME
+
+
+
+
+volatile unsigned int adc_val[4]; ///< measured ADC values
+
+
+
+
+
+/** inicializes ADC lines and starts converion (use ISR)
+ * @param rx_isr_vect ISR vector
+ */
+void init_adc(unsigned rx_isr_vect);
+
+#endif
--- /dev/null
+#include <lpc21xx.h> // LPC21XX Peripheral Registers
+#include <types.h>
+#include "adc_filtr.h"
+#include <stdlib.h>
+#include <string.h>
+#include <deb_led.h>
+
+
+
+#define ADCCH0 22 ///< ADC0 value for PINSEL
+#define ADCCH1 24 ///< ADC1 value for PINSEL
+#define ADCCH2 26 ///< ADC2 value for PINSEL
+#define ADCCH3 28 ///< ADC3 value for PINSEL
+
+
+/**
+ * Comparsion function for quicksort
+ *
+ * @param *a first number for comparion
+ * @param *b second number for comparion
+ *
+ * @return 1 if b is higher than a
+ */
+int compare( const void *a, const void *b)
+{
+ return (*((unsigned int*)a) < *(((unsigned int*)b)));
+}
+
+
+/**
+ * Median filter for ADC. If new data is available the median is recalculated.
+ * This function may be called from main function, it should take long time
+ * to calculate the median for all ADC value.
+ *
+ * @param chan bit oriented (0~3) value, defines which ADC channels have new data
+ */
+void adc_filter(unsigned char chan)
+{
+ if(adc_update_adc & 1)
+ {
+ memcpy(&adc_filtr_0_m, adc_filtr_0, sizeof(uint16_t) * ADC_FILTR_SIZE );
+ qsort(adc_filtr_0_m , ADC_FILTR_SIZE , sizeof(uint16_t), compare);
+ adc_val[0] = adc_filtr_0_m[(ADC_FILTR_SIZE/2 + 1)];
+ adc_update_adc &= ~ 1;
+
+ }
+ if(adc_update_adc & 2)
+ {
+ memcpy(&adc_filtr_1_m, adc_filtr_1, sizeof(uint16_t) * ADC_FILTR_SIZE );
+ qsort(adc_filtr_1_m , ADC_FILTR_SIZE , sizeof(uint16_t), compare);
+ adc_val[1] = adc_filtr_1_m[(ADC_FILTR_SIZE/2 + 1)];
+ adc_update_adc &= ~ 2;
+ }
+ if(adc_update_adc & 4)
+ {
+ memcpy(&adc_filtr_2_m, adc_filtr_2, sizeof(uint16_t) * ADC_FILTR_SIZE );
+ qsort(adc_filtr_2_m , ADC_FILTR_SIZE , sizeof(uint16_t), compare);
+ adc_val[2] = adc_filtr_2_m[(ADC_FILTR_SIZE/2 + 1)];
+ adc_update_adc &= ~ 4;
+ }
+ if(adc_update_adc & 8)
+ {
+ memcpy(&adc_filtr_3_m, adc_filtr_3, sizeof(uint16_t) * ADC_FILTR_SIZE );
+ qsort(adc_filtr_3_m , ADC_FILTR_SIZE , sizeof(uint16_t), compare);
+ adc_val[3] = adc_filtr_3_m[(ADC_FILTR_SIZE/2 + 1)];
+ adc_update_adc &= ~ 8;
+ }
+}
+
+
+
+
+/**
+ * ADC ISR routine. This routine reads selected ADC value and
+ * multiplies it by #ADC_MUL and adds #ADC_OFFSET to calculate the
+ * volage (3.25mV/div). After this reading the next ADC channel is
+ * set up for measuring.
+ */
+void adc_isr_filtr(void) __attribute__ ((interrupt));
+void adc_isr_filtr(void)
+{
+ unsigned char chan =0;
+ unsigned int val =0;
+
+
+ chan = (char) ((ADDR>>24) & 0x07);
+ val = (((((ADDR >> 6) & 0x3FF) * ADC_MUL + ADC_OFFSET) + adc_val[chan]) >> 1) ;
+
+
+ if(chan == 0)
+ {
+ adc_filtr_0[adc_filtr_p] = val;
+ adc_update_adc |= 1;
+ }
+ else if(chan == 1)
+ {
+ adc_filtr_1[adc_filtr_p] = val;
+ adc_update_adc |= 2;
+ }
+ else if(chan == 2)
+ {
+ adc_filtr_2[adc_filtr_p] = val;
+ adc_update_adc |= 4;
+ }
+ else if(chan == 3)
+ {
+ adc_filtr_3[adc_filtr_p] = val;
+ adc_update_adc |= 8;
+
+ if(adc_filtr_p == (ADC_FILTR_SIZE -1 )) adc_filtr_p = 0;
+ else ++adc_filtr_p;
+ }
+
+
+ ADCR &= ~(ADC_CR_START_OFF_m);
+
+
+ switch(chan)
+ {
+ case 0:
+ ADCR = ((ADC_CR_ADC1_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 1:
+ ADCR = ((ADC_CR_ADC2_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 2:
+ ADCR = ((ADC_CR_ADC3_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+ break;
+
+ case 3:
+ ADCR = ((ADC_CR_ADC0_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+ break;
+ }
+
+ VICVectAddr = 0;
+
+}
+
+/**
+ * Inicializes ADC service for all ADC (4) channels and installs ISR routine to VIC.
+ * Automaticly starts the conversion of first channel on given conversion frequency.
+ */
+void init_adc_filter(unsigned rx_isr_vect)
+{
+
+ PINSEL1 |= ((PINSEL_1 << ADCCH0) | (PINSEL_1 << ADCCH1) | (PINSEL_1 << ADCCH2) | (PINSEL_1 << ADCCH3));
+
+ int x;
+
+ for (x = 0; x < 21; ++x)
+ {
+ adc_filtr_0[x] = 0;
+ adc_filtr_1[x] = 0;
+ adc_filtr_2[x] = 0;
+ adc_filtr_3[x] = 0;
+ }
+
+ adc_filtr_p = 0;
+ adc_update_adc = 0;
+
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x32;
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned) adc_isr_filtr;
+ VICIntEnable = 0x40000;
+
+ ADCR = ((ADC_CR_ADC0_m) | (ADC_CR_CLKS_11_m) | (ADC_CR_PDN_ON_m) | (ADC_CR_START_NOW_m) | (ADC_VPB_DIV*ADC_CR_CLK_DIV_1_m));
+}
--- /dev/null
+#ifndef ADC_FILTR_H
+#define ADC_FILTR_H
+
+#include <system_def.h>
+
+
+#define ADC_MUL 1 ///< This value multiplies mesured value from ADC
+#define ADC_OFFSET 0 ///< This valueis added to mesured value from ADC
+
+#define ACD_HZ 3000 ///< Sampling frequency
+
+#define ADC_VPB_DIV 0x80 ///< VPB divisor
+
+
+
+#if ADC_VPB_DIV & 0xffffff00
+ #error Wrong ACD_HZ
+#endif
+
+
+#define ADC_FILTR_SIZE 201 ///< Size of the median filter for each channel, be aware sinal size is size * 8
+
+volatile unsigned int adc_val[4]; ///< Final ADC value
+volatile unsigned int adc_update_adc; ///< bite oriented, updated when new ADC channel is measured
+
+
+
+uint16_t adc_filtr_0_m[ADC_FILTR_SIZE]; ///<
+uint16_t adc_filtr_1_m[ADC_FILTR_SIZE];
+uint16_t adc_filtr_2_m[ADC_FILTR_SIZE];
+uint16_t adc_filtr_3_m[ADC_FILTR_SIZE];
+
+
+
+volatile uint16_t adc_filtr_0[ADC_FILTR_SIZE];
+volatile uint16_t adc_filtr_1[ADC_FILTR_SIZE];
+volatile uint16_t adc_filtr_2[ADC_FILTR_SIZE];
+volatile uint16_t adc_filtr_3[ADC_FILTR_SIZE];
+volatile uint16_t adc_filtr_p ;
+
+void adc_filter(unsigned char chan);
+
+
+
+void init_adc_filter(unsigned rx_isr_vect);
+
+#endif
--- /dev/null
+
+
+
+
+#include <lpc21xx.h>
+#include <deb_led.h>
+#include <system_def.h>
+#include "engine.h"
+
+#define ENGINE_PIN_A 7 ///< PWM output for engine A, pin P0.7
+#define ENGINE_PIN_B 8 ///< PWM output for engine B, pin P0.8
+
+#define ENGINE_ENA 28 ///< Enable output for engine A, pin P1.28
+#define ENGINE_ENB 30 ///< Enable output for engine B, pin P1.30
+
+#define ENGINE_IN2A 27 ///< Direction output for engine A , pin P1.27
+#define ENGINE_IN2B 29 ///< Direction output for engine A , pin P1.29
+
+#define PWM_FREQ 20000 ///< PWM frequency
+#define PWM_RES 100 ///< PWM resolution
+
+#define PWM_STEP ((CPU_APB_HZ / PWM_FREQ)/PWM_RES + 1) ///< Calculates smallest step PWM for resolution 0~100%
+
+
+
+unsigned int pwm_A = 0; ///< Actual value of PWM A
+unsigned int pwm_B = 0; ///< Actual value of PWM B
+
+
+/**
+ * Enables or disables the ouput on engine A. Causes smooth stop, without break.
+ *
+ * @param status status parameters are defined in engine.h
+ *
+ */
+void engine_A_en(unsigned status)
+{
+ if (status == ENGINE_EN_ON)
+ IO1SET |= (1<<ENGINE_ENA);
+ else
+ IO1CLR |= (1<<ENGINE_ENA);
+}
+
+/**
+ * Enables or disables the ouput on engine B. Causes smooth stop, without break.
+ *
+ * @param status status parameters are defined in engine.h
+ *
+ */
+void engine_B_en(unsigned status)
+{
+ if (status == ENGINE_EN_ON)
+ IO1SET |= (1<<ENGINE_ENB);
+ else
+ IO1CLR |= (1<<ENGINE_ENB);
+}
+
+/**
+ * Changes motor A direction
+ *
+ * @param dir direction parameters are defined in engine.h
+ *
+ */
+void engine_A_dir(unsigned dir)
+{
+ if (dir == ENGINE_DIR_BW)
+ IO1SET |= (1<<ENGINE_IN2A);
+ else
+ IO1CLR |= (1<<ENGINE_IN2A);
+
+ engine_A_pwm(pwm_A);
+
+}
+
+/**
+ * Changes motor B direction
+ *
+ * @param dir direction parameters are defined in engine.h
+ *
+ */
+void engine_B_dir(unsigned dir)
+{
+ if (dir == ENGINE_DIR_BW)
+ IO1SET |= (1<<ENGINE_IN2B);
+ else
+ IO1CLR |= (1<<ENGINE_IN2B);
+
+ engine_B_pwm(pwm_B);
+}
+
+/**
+ * Sets motor A PWM value
+ *
+ * @param pwm Unsigned int, 0~100%
+ *
+ * @note 0 causes fast stop
+ */
+void engine_A_pwm(unsigned pwm)
+{
+ if (pwm>100) pwm = 100;
+
+ pwm_A = pwm;
+ if (IO1PIN & (1<<ENGINE_IN2A)) PWMMR2 = PWM_STEP * (100 - pwm);
+ else PWMMR2 = PWM_STEP * (pwm);
+ PWMLER |= PWMLER_LA2_m;
+
+}
+
+/**
+ * Sets motor B PWM value
+ *
+ * @param pwm Unsigned int, 0~100%
+ *
+ * @note 0 causes fast stop
+ */
+void engine_B_pwm(unsigned pwm)
+{
+ if (pwm>100) pwm = 100;
+ pwm_B = pwm;
+ if (IO1PIN & (1<<ENGINE_IN2B)) PWMMR4 = PWM_STEP * (100 - pwm);
+ else PWMMR4 = PWM_STEP * (pwm);
+ PWMLER |= PWMLER_LA4_m;
+
+}
+
+
+/**
+ * Inicializes Engine A - enables PWM outputs and sets IOs. Uses PWM channel - PWMMR2.
+ * If is somthing other set on PWM channels, it will affect the main PWM frequency
+ * If the engine B is set it will afect its output for one cycle
+ *
+ *
+ */
+void init_engine_A()
+{
+ PINSEL0 &= ~((PINSEL_3 << 14) );
+ PINSEL0 |= (PINSEL_2 << 14) ;
+
+ IO0DIR |= (1<<ENGINE_PIN_A);
+ IO1DIR |= (1<<ENGINE_ENA) | (1<<ENGINE_IN2A);
+ IO1SET |= (1<<ENGINE_ENA) | (1<<ENGINE_IN2A);
+
+ PWMPR = 0;
+ PWMMR0 = CPU_APB_HZ / 20000;
+
+ PWMMR2 =0;
+
+ PWMPCR |= PWMPCR_PWMENA2_m;
+ PWMLER |= PWMLER_LA0_m | PWMLER_LA2_m;
+ PWMMCR |= PWMMCR_PWMMR0R_m;
+ PWMTCR |= PWMTCR_CE_m | PWMTCR_EN_m;
+}
+
+/**
+ * Inicializes Engine B - enables PWM outputs and sets IOs. Uses PWM channel - PWMMR2.
+ * If is somthing other set on PWM channels, it will affect the main PWM frequency
+ * If the engine A is set it will afect its output for one cycle
+ *
+ *
+ */
+void init_engine_B()
+{
+ PINSEL0 &= ~((PINSEL_3 << 16));
+ PINSEL0 |= (PINSEL_2 << 16);
+
+ IO0DIR |= (1<<ENGINE_PIN_B);
+ IO1DIR |= (1<<ENGINE_ENB) | (1<<ENGINE_IN2B);
+
+ IO1SET |= (1<<ENGINE_ENB) | (1<<ENGINE_IN2B);
+
+
+ PWMPR = 0;
+ PWMMR0 = CPU_APB_HZ / 20000;
+
+ PWMMR4 = 0;
+
+ PWMPCR |= PWMPCR_PWMENA4_m;
+ PWMLER |= PWMLER_LA0_m | PWMLER_LA4_m;
+ PWMMCR |= PWMMCR_PWMMR0R_m;
+ PWMTCR |= PWMTCR_CE_m | PWMTCR_EN_m;
+}
\ No newline at end of file
--- /dev/null
+/**
+ * @file engine.h
+ *
+ * @brief Engines control
+ * This file provides simply how-to use eb_ebb library.
+ * From main function is called init_perip function
+ * where is initialized servos, engines, power switch,
+ * CAN,ADC and serial port. After this initialization is shown
+ * how to control each devices. This sample also include simply
+ * sample of sending and receiving CAN message.
+ *
+ * Due to small number of PWM channels are only one PWM assigned
+ * to one motor. For this case there is two ways how to stop the
+ * engine. If you use engine_x_pwm(0); the motors will be stopped
+ * by shorting its coils. This will stop as fast as possible, but
+ * it also generates huge electromagnetic noise. If you want to
+ * stop smoothly use engine_x_en(ENGINE_EN_OFF); this will disconnect
+ * the power from the engines.
+ *
+ */
+
+
+
+// Author: Jirka Kubias <jirka@Jirka-NB>, (C) 2008
+//
+// Copyright: See COPYING file that comes with this distribution
+//
+//
+
+
+
+
+
+#ifndef ENGINE_H
+#define ENGINE_H
+
+
+#define ENGINE_EN_ON 1 ///< Enables Engine
+#define ENGINE_EN_OFF 0 ///< Disables Engine
+
+
+#define ENGINE_DIR_BW 1 ///< Backward direction
+#define ENGINE_DIR_FW 0 ///< Forward direction
+
+
+void init_engine_A();
+void init_engine_B();
+
+void engine_A_en(unsigned status);
+void engine_B_en(unsigned status);
+
+void engine_A_dir(unsigned dir);
+void engine_B_dir(unsigned dir);
+
+void engine_A_pwm(unsigned pwm); // pwm is in percent, range 0~100
+void engine_B_pwm(unsigned pwm); // pwm is in percent, range 0~100
+
+
+
+#endif
--- /dev/null
+// $Id$
+// $Name$
+// $ProjectName$
+
+/**
+ * \mainpage EB-ebb code sample
+ *
+ * \section Introduction
+ * This codes are designed for use with ebBoard developed in DCE CVUT.
+ * There are two purpose of this program:
+ *
+ * 1) library named ebb, it contains function for handling engines,
+ * servos, ADC (median or avery filtered) and power switch.
+ *
+ * 2) in main.c file is simply HOW-TO use this libraries
+ *
+ * Short description of ebb library:
+ *
+ * ADC \96 This library use 4 ADC channels which parameters I defined
+ * in adc.h or adc_filtr.h. There is two implementation of ADC output
+ * filter. First is simply averaging ((last value + actual value)/2),
+ * for this filter you have to include adc.h. The Second filter is
+ * median filter in adc_filtr.h . The size of this filter is defined
+ * in adc_filtr.h.
+ *
+ * PowerSwitch \96 ebboard have one 6A power switch which can be used for
+ * switching small loads (capacity or resistant recommended). In powswitch.h is defined initialization, on and off function.
+ *
+ * Servos \96 ebboard have three servo connectors. In servo.h is defined
+ * functions for setting them. The servo range is divided into 256 (0~255)
+ * steps.
+ *
+ * Engines \96 this part can controls up two DC motors (5A each) or in
+ * special cases one motor (up to 10A). In engines.h is defined several
+ * controls function. Read carefully description in this section. Is
+ * important to understanding the way how to stop engines.
+ *
+ */
+
+/**
+ * @file main.c
+ *
+* @brief Demo application demonstrating use of eb_ebb library.
+ * This file provides simply how-to use eb_ebb library.
+ * From main function is called init_perip function
+ * where is initialized servos, engines, power switch,
+ * CAN,ADC and serial port. After this initialization is shown
+ * how to control each devices. This sample also include simply
+ * sample of sending and receiving CAN message.
+ *
+ */
+
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <errno.h>
+#include <periph/can.h>
+#include <string.h>
+#include <deb_led.h>
+#include "uart.h"
+#include "servo.h"
+#include "powswitch.h"
+#include "engine.h"
+//#include "adc.h" // header ADC with averaging filter
+#include "adc_filtr.h" // header ADC with mean filter
+
+
+
+
+#define CAN_SPEED 1000000 ///< CAN speed
+
+#define CAN_SERVO 0x32 ///< CAN ID for servo message
+
+/**
+ * Variables ISR values
+ */
+/*@{*/
+#define CAN_ISR 0
+#define ENG_ISR 1
+#define ADC_ISR 3
+#define SERVO_ISR 5
+/*@}*/
+
+#define SPEED 30 ///< Motor speed
+
+
+/**
+ * Dummy wait (busy wait)
+ * This function shoul be removed in future
+ */
+void dummy_wait(void)
+{
+ int i = 1000000;
+
+ while(--i);
+}
+
+/**
+ * This function is called when we recieve CAN message.
+ * Its called from CAN ISR
+ *
+ * @param *msg structure of can message (can_msg_t)
+ *
+ */
+void can_rx(can_msg_t *msg) {
+ can_msg_t rx_msg;
+
+ memcpy(&rx_msg, msg, sizeof(can_msg_t));
+
+ switch (rx_msg.id) { // demo sample parsing recieved message by ID
+ case CAN_SERVO:
+
+ set_servo(0, rx_msg.data[0]);
+ set_servo(1, rx_msg.data[1]);
+ set_servo(2, rx_msg.data[2]);
+ break;
+
+ default:
+ break;
+ }
+}
+
+
+/**
+ * Inicializes pepherials used in ebb library - sample use
+ *
+ */
+void init_perip(void)
+{
+ init_servo(SERVO_ISR);
+ init_pow_switch();
+
+ init_engine_A();
+ init_engine_B();
+
+ init_uart0((int)9600 ,UART_BITS_8, UART_STOP_BIT_1, UART_PARIT_OFF, 0 );
+ //init_adc(ADC_ISR); // inicialization ADC with averaging filter
+ init_adc_filter(ADC_ISR); // inicialization ADC with mean filter
+ can_init_baudrate(CAN_SPEED, CAN_ISR, can_rx);
+}
+
+
+/**
+ * Main function contains a small sample how to use ebb library.
+ *
+ */
+int main (void) {
+
+ init_perip(); // sys init MCU
+
+ set_servo(0, 0x80); // set servo 1 to center position
+ set_servo(1, 0x80); // set servo 2 to center position
+ set_servo(2, 0x80); // set servo 3 to center position
+
+ engine_A_dir(ENGINE_DIR_FW); // set engine A to direction forward
+ engine_B_dir(ENGINE_DIR_BW); // set engine B to direction backward
+ engine_A_en(ENGINE_EN_ON); // enables engine A
+ engine_B_en(ENGINE_EN_ON); // enables engine B
+ engine_A_pwm(SPEED); // sets speed on Engine A
+ engine_B_pwm(SPEED); // sets speed on Engine B
+
+
+ can_msg_t msg; // This part is sending CAN messge
+ msg.id = 0xAA; // CAN message ID
+ msg.flags = 0;
+ msg.dlc = 1; // number of transmited data bytes
+ msg.data[0] = 0x55; // data byte
+ while(can_tx_msg(&msg)); // sending function
+
+
+ while(1) // this will blink for ever
+ {
+ __deb_led_on(LEDG);
+ dummy_wait();
+ __deb_led_off(LEDG);
+ dummy_wait();
+ }
+}
+
+
+
--- /dev/null
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include "powswitch.h"
+
+
+
+
+
+#define ESW (1<<16) ///< Pin define
+
+
+
+void init_pow_switch(void)
+{
+ IO0DIR |= ESW; // enable output
+ IO0CLR |= ESW; // sets to LOW level
+
+
+ PINSEL1 &= ~(PINSEL_3 << 0); // set as GPIO
+}
+
+void pow_switch_on(void)
+{
+ IO0SET |= ESW; // sets to LOW level
+}
+
+
+void pow_switch_off(void)
+{
+ IO0CLR |= ESW; // sets to LOW level
+}
--- /dev/null
+#ifndef POWSWITCH_H
+#define POWSWITCH_H
+
+/** Initializes power switch
+ */
+void init_pow_switch(void);
+
+
+/** Power switch ON
+ */
+void pow_switch_on(void);
+
+/** Power switch OFF
+ */
+void pow_switch_off(void);
+
+#endif
--- /dev/null
+
+
+#include <lpc21xx.h> // LPC21XX Peripheral Registers
+#include <deb_led.h>
+#include <system_def.h>
+#include "servo.h"
+
+
+#define SERVO2 (1<<10)
+#define SERVO0 (1<<12)
+#define SERVO1 (1<<13)
+
+
+
+#define TIM_EMR_NOTHING 0
+#define TIM_EMR_CLEAR 1
+#define TIM_EMR_SET 2
+#define TIM_EMR_TOGLE 3
+
+#define TIM_EMR_PIN_ON 1
+#define TIM_EMR_PIN_OFF 0
+
+#define TIME20MS ((CPU_APB_HZ) / 50)
+#define SERVOTICK (((CPU_APB_HZ / 50) / 20) / 256)
+
+
+unsigned char servo[3];
+
+
+
+// ---------------- SERVO PART -------------------------------
+
+
+void tc1 (void) __attribute__ ((interrupt));
+
+void tc1 (void) {
+
+ time_ms +=20;
+
+ T1EMR |= (TIM_EMR_PIN_ON<<0) | (TIM_EMR_PIN_ON<<1) | (TIM_EMR_PIN_ON<<3);
+
+ T1MR0 = (servo[0] + 256) * SERVOTICK;
+ T1MR1 = (servo[1] + 256) * SERVOTICK;
+ T1MR3 = (servo[2] + 256) * SERVOTICK;
+
+ if (T1IR != 4)
+ {
+ __deb_led_on(LEDR);
+ }
+
+ T1IR = 4; // Vynulovani priznaku preruseni
+ VICVectAddr = 0; // Potvrzeni o obsluze preruseni
+}
+
+void set_servo(char serv, char position)
+{
+ if (serv == 0) servo[0] = position;
+ if (serv == 1) servo[1] = position;
+ if (serv == 2) servo[2] = position;
+}
+
+/* Setup the Timer Counter 1 Interrupt */
+void init_servo (unsigned rx_isr_vect)
+{
+
+ IO0DIR |= (SERVO0 | SERVO1 | SERVO2); // enables servo output
+ IO0SET |= (SERVO0 | SERVO1 | SERVO2); // sets to High level
+
+ PINSEL0 &= ~((PINSEL_3 << 24) | (PINSEL_3 << 26));
+ PINSEL0 |= (PINSEL_2 << 24) | (PINSEL_2 << 26);
+ PINSEL1 &= ~(PINSEL_3 << 8);
+ PINSEL1 |= (PINSEL_1 << 8);
+
+
+ servo[0] = 0;
+ servo[1] = 127;
+ servo[2] = 0xFF;
+
+ T1PR = 0;
+ T1MR2 = TIME20MS;
+ T1MR0 = (servo[0] + 256) * SERVOTICK;
+ T1MR1 = (servo[1] + 256) * SERVOTICK;
+ T1MR3 = (servo[2] + 256)* SERVOTICK;
+ T1MCR = (3<<6); // interrupt on MR1
+
+ T1EMR = (TIM_EMR_PIN_ON<<0) | (TIM_EMR_PIN_ON<<1) | (TIM_EMR_PIN_ON<<3) \
+ | (TIM_EMR_CLEAR << 4) | (TIM_EMR_CLEAR << 6) | (TIM_EMR_CLEAR << 10);
+
+
+ T1TCR = 1; // Starts Timer 1
+
+
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned long)tc1; // Nastaveni adresy vektotu preruseni
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x20 | 0x5; // vyber casovece pro preruseni
+ VICIntEnable = (1<<5); // Povoli obsluhu preruseni
+}
+
+
+// ---------------- powSitch PART -------------------------------
+
--- /dev/null
+/**
+ * @file servo.h
+ *
+ * @brief FIXME
+ * This file provides simply how-to use eb_ebb library.
+ * From main function is called init_perip function
+ * where is initialized servos, engines, power switch,
+ * CAN,ADC and serial port. After this initialization is shown
+ * how to control each devices. This sample also include simply
+ * sample of sending and receiving CAN message.
+ *
+ */
+
+
+
+#ifndef SERVO_H
+#define SERVO_H
+
+
+
+/** gobal time
+ * @note incremented twenty 20ms, overrun every 1194hours
+ */
+volatile unsigned int time_ms;
+
+/** Initialize servos
+ * @note All three servos - should be fixed FIXME
+ */
+void init_servo(unsigned rx_isr_vect);
+
+
+/** Sets serv position
+ * @return 0
+ * @note VPB = APB - name conflict FIXME
+ * @param servo define servo
+ * @param position new position for servo
+ */
+void set_servo(char servo, char position);
+
+#endif
--- /dev/null
+\r
+ #include <lpc21xx.h> \r
+ #include "uart.h"\r
+ #include <system_def.h>\r
+\r
+\r
+\r
+\r
+ #define UART_DLAB 0x80\r
+\r
+\r
+void init_uart0(int baudrate, char bits, char stopbit, char parit_en, char parit_mode ) \r
+{ \r
+\r
+ int pom , vala, valb;\r
+\r
+ PINSEL0 |= ( PINSEL_1<< 0) | ( PINSEL_1 << 2); \r
+\r
+ U0LCR =UART_DLAB | bits | stopbit | parit_en | parit_mode; // nastaven� datov�ho slova na 8 bit� a jeden stop bit bez parity, nastaven� DLAB na log "1"\r
+ \r
+ \r
+ pom = (CPU_APB_HZ)/(16 * baudrate);\r
+ \r
+ vala = (CPU_APB_HZ)/(16 * pom);\r
+ valb = (CPU_APB_HZ)/(16 * (pom + 1));\r
+\r
+ vala = baudrate - vala;\r
+ valb = baudrate - valb;\r
+\r
+ if (vala < 0) vala *= -1;\r
+ if (valb < 0) valb *= -1;\r
+ \r
+ if (vala > valb) pom += 1;\r
+\r
+ U0DLL = (char) (pom & 0xFF);\r
+ U0DLM = (char) ((pom >> 8) & 0xFF); // nastaven� p�edd�li�ky na 57600Bd\r
+ \r
+ U0LCR &= ~UART_DLAB; // vynulov�n� DLAB \r
+\r
+ }\r
+\r
+\r
+unsigned char uart1GetCh(void) // Nuceny prijem z uart1\r
+{\r
+ while (!(U1LSR & 1)); // cekani na prichozi byte\r
+ return (unsigned char)U1RBR; // navraceni prijateho byte\r
+}\r
+\r
+unsigned char uart0GetCh(void) // Nuceny prijem z uart1\r
+{\r
+ while (!(U0LSR & 1)); // cekani na prichozi byte\r
+ return (unsigned char)U0RBR; // navraceni prijateho byte\r
+}\r
+\r
+void uart1SendCh(char ch) // vyslani znaku na uart1\r
+{\r
+ while (!(U1LSR & 0x20)); // ceka na odeslani predchozich dat\r
+ U1THR=ch; // odeslani Byte\r
+ \r
+}\r
+\r
+void uart0SendCh(char ch) // vyslani znaku na uart0\r
+{\r
+ while (!(U0LSR & 0x20)); // ceka na odeslani predchozich dat\r
+ U0THR=ch; // odeslani Byte\r
+}\r
+\r
+\r
+void init_uart1(int baudrate, char bits, char stopbit, char parit_en, char parit_mode ) \r
+{ \r
+\r
+ int pom , vala, valb;\r
+\r
+ PINSEL0 |= ( PINSEL_1<< 16) | ( PINSEL_1 << 18); \r
+\r
+ U1LCR =UART_DLAB | bits | stopbit | parit_en | parit_mode; // nastaven� datov�ho slova na 8 bit� a jeden stop bit bez parity, nastaven� DLAB na log "1"\r
+ \r
+ \r
+ pom = (CPU_APB_HZ)/(16 * baudrate);\r
+ \r
+ vala = (CPU_APB_HZ)/(16 * pom);\r
+ valb = (CPU_APB_HZ)/(16 * (pom + 1));\r
+\r
+ vala = baudrate - vala;\r
+ valb = baudrate - valb;\r
+\r
+ if (vala < 0) vala *= -1;\r
+ if (valb < 0) valb *= -1;\r
+ \r
+ if (vala > valb) pom += 1;\r
+\r
+ U1DLL = (char) (pom & 0xFF);\r
+ U1DLM = (char) ((pom >> 8) & 0xFF); // nastaven� p�edd�li�ky na 57600Bd\r
+ \r
+ U1LCR &= ~UART_DLAB; // vynulov�n� DLAB \r
+\r
+ }\r
+\r
+\r
+\r
--- /dev/null
+#ifndef UART_H\r
+#define UART_H\r
+\r
+#define UART_BITS_5 0x0\r
+#define UART_BITS_6 0x1\r
+#define UART_BITS_7 0x2\r
+#define UART_BITS_8 0x3\r
+\r
+#define UART_STOP_BIT_1 (0x0 << 2)\r
+#define UART_STOP_BIT_2 (0x1 << 2)\r
+\r
+#define UART_PARIT_ENA (0x1 << 3)\r
+#define UART_PARIT_OFF (0x0 << 3)\r
+#define UART_PARIT_ODD (0x0 << 4)\r
+#define UART_PARIT_EVEN (0x1 << 4)\r
+#define UART_PARIT_FORCE_1 (0x2 << 4)\r
+#define UART_PARIT_FORCE_0 (0x3 << 4)\r
+\r
+\r
+\r
+\r
+void init_uart1(int baudrate, char bits, char stopbit, char parit_en, char parit_mode );\r
+void init_uart0(int baudrate, char bits, char stopbit, char parit_en, char parit_mode );\r
+unsigned char uart1GetCh(void);\r
+unsigned char uart0GetCh(void);\r
+void uart1SendCh(char ch);\r
+void uart0SendCh(char ch);\r
+\r
+#endif\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = eb_pwr
+
+eb_pwr_SOURCES = pwrstep.c uart.c main.c
+
+eb_pwr_LIBS = can
--- /dev/null
+////////////////////////////////////////////////////////////////////////////////
+//
+// Eurobot POWER BOAD (with LPC2129)
+//
+// Description
+// -----------
+// This software controls the eurobot powerboard
+// Author : Jiri Kubias DCE CVUT
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <string.h>
+#include <deb_led.h>
+#include <system_def.h>
+#include <periph/can.h>
+#include <can_ids.h>
+
+
+#include "pwrstep.h"
+#include "uart.h"
+
+#define CAN_SPEED 1000000
+#define CAN_ISR 0
+#define ADC_ISR 1
+#define TIME_ISR 2
+
+
+#define CAN_TRY 20
+
+#define ALERT_LOW 1
+#define ALERT_MAIN 2
+#define ALERT_BYE 3
+#define ALERT_33V 4
+#define ALERT_50V 5
+#define ALERT_80V 6
+
+#define BAT_CNT 10
+#define BAT_STAT_LOW 120000
+#define BAT_STAT_MAIN 110000
+#define BAT_STAT_BYE 105000
+
+#define V33_MIN 30000
+#define V50_MIN 45000
+#define V80_MIN 75000
+
+#define CAN_TIMEOUT 10
+
+//extern unsigned int adc_val[4];
+
+//#define TEST
+
+can_msg_t msg;// = {.flags = 0, .dlc = 1};
+
+unsigned int time_blink = 0;
+unsigned int time_send_can = 0;
+unsigned int time_alert = 0;
+
+unsigned int time_timeout = 0;
+
+unsigned int can_send_cnt = 0;
+
+
+void led_blik()
+{
+ if (time_blink == 0) time_blink = time_ms + 500;
+
+ if (time_ms > time_blink)
+ {
+ deb_led_change(LEDG);
+ time_blink = time_ms + 500;
+ }
+
+}
+
+void send_alert(unsigned char type )
+{
+
+
+ msg.id = CAN_PWR_ALERT;
+ msg.flags = 0;
+ msg.dlc = 1;
+ msg.data[0] = type;
+
+ while (can_tx_msg(&msg));
+
+}
+
+unsigned int cnt_12V;
+unsigned int cnt_10V;
+
+
+
+void power_alert()
+{
+ if (time_alert == 0) time_alert = time_ms + 200;
+
+ if (time_ms > time_alert)
+ {
+
+ if (adc_val[0] < BAT_STAT_BYE) // bat < 9,5V
+ {
+ deb_led_on(LEDR);
+ send_alert(ALERT_BYE);
+ pwr_50(PWR_OFF);
+ //pwr_80(PWR_OFF);
+ pwr_33(PWR_OFF);
+
+
+ }
+ else if (adc_val[0] < BAT_STAT_MAIN) // bat < 12V
+ {
+ deb_led_on(LEDB);
+ ++cnt_10V;
+ if (cnt_10V > BAT_CNT)
+ {
+ send_alert(ALERT_MAIN);
+ pwr_50(PWR_OFF);
+ //pwr_80(PWR_OFF);
+ }
+
+
+ }
+ else if (adc_val[0] < BAT_STAT_LOW) // bat < 12V
+ {
+ deb_led_on(LEDY);
+ ++cnt_12V;
+ if (cnt_12V > BAT_CNT)
+ send_alert(ALERT_LOW);
+ }
+ else
+ deb_led_off(LEDY);
+
+ if (cnt_10V < BAT_CNT)
+ {
+ if (adc_val[3] < V80_MIN)
+ {
+ send_alert(ALERT_80V);
+ }
+
+ if (adc_val[2] < V50_MIN)
+ {
+ send_alert(ALERT_50V);
+ }
+
+ if (adc_val[1] < V33_MIN)
+ {
+ send_alert(ALERT_33V);
+ }
+ }
+ time_alert = time_ms + 500;
+ }
+}
+
+void send_can()
+{
+ if (time_send_can == 0) time_send_can = time_ms + 200;
+
+ if (time_ms > time_send_can)
+ {
+ deb_led_on(LEDB);
+
+ msg.id = CAN_PWR_ADC1;
+ msg.flags = 0;
+ msg.dlc = 8;
+ msg.data[0] = (((adc_val[0]) >> 24) & 0xFF);
+ msg.data[1] = (((adc_val[0]) >> 16) & 0xFF);
+ msg.data[2] = (((adc_val[0]) >> 8) & 0xFF);
+ msg.data[3] = (((adc_val[0]) >> 0) & 0xFF);
+ msg.data[4] = (((adc_val[1]) >> 24) & 0xFF);
+ msg.data[5] = (((adc_val[1]) >> 16) & 0xFF);
+ msg.data[6] = (((adc_val[1]) >> 8) & 0xFF);
+ msg.data[7] = (((adc_val[1]) >> 0) & 0xFF);
+
+ time_timeout = time_ms + CAN_TIMEOUT;
+ //while(can_tx_msg(&msg) & (time_timeout > time_ms))
+
+ while (can_tx_msg(&msg));
+
+
+ msg.id = CAN_PWR_ADC2;
+ msg.flags = 0;
+ msg.dlc = 8;
+ msg.data[0] = (((adc_val[2]) >> 24) & 0xFF);
+ msg.data[1] = (((adc_val[2]) >> 16) & 0xFF);
+ msg.data[2] = (((adc_val[2]) >> 8) & 0xFF);
+ msg.data[3] = (((adc_val[2]) >> 0) & 0xFF);
+ msg.data[4] = (((adc_val[3]) >> 24) & 0xFF);
+ msg.data[5] = (((adc_val[3]) >> 16) & 0xFF);
+ msg.data[6] = (((adc_val[3]) >> 8) & 0xFF);
+ msg.data[7] = (((adc_val[3]) >> 0) & 0xFF);
+
+ time_timeout = time_ms + CAN_TIMEOUT;
+ //while(can_tx_msg(&msg) & (time_timeout > time_ms))
+
+ while (can_tx_msg(&msg));
+ deb_led_off(LEDB);
+ time_send_can = time_ms + 500;
+ }
+
+}
+
+
+
+
+void can_rx(can_msg_t *msg) {
+ can_msg_t rx_msg;
+
+ memcpy(&rx_msg, msg, sizeof(can_msg_t));
+
+
+ if (rx_msg.id == CAN_PWR)
+ {
+ if(rx_msg.data[0] & (1<<0)) pwr_33(PWR_ON);
+ if(rx_msg.data[0] & (1<<1)) pwr_50(PWR_ON);
+ if(rx_msg.data[0] & (1<<2)) pwr_80(PWR_ON);
+
+ if(rx_msg.data[0] & (1<<3)) pwr_33(PWR_OFF);
+ if(rx_msg.data[0] & (1<<4)) pwr_50(PWR_OFF);
+ if(rx_msg.data[0] & (1<<5)) pwr_80(PWR_OFF);
+ }
+}
+
+
+
+void init_perip(void) // inicializace periferii mikroprocesoru
+{
+
+ init_pwr();
+ can_init_baudrate(CAN_SPEED, CAN_ISR, can_rx);
+ init_adc(ADC_ISR);
+ init_time (TIME_ISR);
+ init_uart0((int)9600 ,UART_BITS_8, UART_STOP_BIT_1, UART_PARIT_OFF, 0 );
+
+
+#ifdef TEST
+ pwr_33(PWR_ON);
+ pwr_50(PWR_ON);
+ pwr_80(PWR_ON);
+#else
+ pwr_33(PWR_OFF);
+ pwr_50(PWR_OFF);
+ pwr_80(PWR_OFF);
+#endif
+
+ pwr_33(PWR_ON);
+ pwr_50(PWR_ON);
+ pwr_80(PWR_ON);
+}
+
+
+unsigned int time_delay = 0;
+
+
+int main (void) {
+
+
+ init_perip(); // sys init MCU
+
+ time_delay = time_ms + 1000;
+
+ while(time_ms < time_delay);
+
+ while(1)
+ {
+ led_blik();
+ send_can(); //FIXME
+ power_alert();
+
+ }
+}
+
+
+
--- /dev/null
+#include <lpc21xx.h> // LPC21XX Peripheral Registers\r
+#include <types.h> \r
+#include <deb_led.h>\r
+#include <system_def.h>\r
+#include "pwrstep.h"\r
+\r
+\r
+#define PWR33 (1<<22) \r
+#define PWR50 (1<<24)\r
+#define PWR80 (1<<23)\r
+\r
+#define ADC0 (1<<27) \r
+#define ADC1 (1<<28) \r
+#define ADC2 (1<<29) \r
+#define ADC3 (1<<30) \r
+\r
+\r
+\r
+#define ADCCH0 22\r
+#define ADCCH1 24\r
+#define ADCCH2 26\r
+#define ADCCH3 28\r
+\r
+#define TIME1MS ((CPU_APB_HZ) / 1000)\r
+\r
+// tohla me byt definovano nekde jinde FIXME\r
+\r
+\r
+#define ADC_PIN_0 0x1\r
+#define ADC_PIN_1 0x2\r
+#define ADC_PIN_2 0x4\r
+#define ADC_PIN_3 0x8\r
+\r
+#define ADC_CR_ADC0 0x1\r
+#define ADC_CR_ADC1 0x2\r
+#define ADC_CR_ADC2 0x4\r
+#define ADC_CR_ADC3 0x8\r
+\r
+#define ADC_CR_CLK_DIV_1 (1<<8) // this nuber should be multipied sampe\r
+ // requested divisor 4 ---- clk_div = 4 * ADC_CR_CLK_DIV_1\r
+#define ADC_CR_BURST (1<<16)\r
+#define ADC_CR_CLKS_11 (0<<17)\r
+#define ADC_CR_CLKS_10 (1<<17)\r
+#define ADC_CR_CLKS_9 (2<<17)\r
+#define ADC_CR_CLKS_8 (3<<17)\r
+#define ADC_CR_CLKS_7 (4<<17)\r
+#define ADC_CR_CLKS_6 (5<<17)\r
+#define ADC_CR_CLKS_5 (6<<17)\r
+#define ADC_CR_CLKS_4 (7<<17)\r
+\r
+#define ADC_CR_PDN_ON (1<<21)\r
+\r
+#define ADC_CR_START_OFF (0<<24)\r
+#define ADC_CR_START_NOW (1<<24)\r
+#define ADC_CR_START_P016 (2<<24)\r
+#define ADC_CR_START_P022 (3<<24)\r
+#define ADC_CR_START_MAT01 (4<<24)\r
+#define ADC_CR_START_MAT03 (5<<24)\r
+#define ADC_CR_START_MAT10 (6<<24)\r
+#define ADC_CR_START_MAT11 (7<<24)\r
+\r
+#define ADC_CR_EDGE_RISING (0<<27)\r
+#define ADC_CR_EDGE_FALLING (1<<27)\r
+\r
+\r
+\r
+\r
+\r
+ \r
+\r
+void pwr_33(char mode) // switch on/off 3,3V power line\r
+{\r
+ if (mode != PWR_ON)\r
+ {\r
+ IO1SET |= PWR33; \r
+ }\r
+ else\r
+ {\r
+ IO1CLR |= PWR33; \r
+ }\r
+}\r
+\r
+\r
+void pwr_50(char mode) // switch on/off 5V power line\r
+{\r
+ if (mode != PWR_ON)\r
+ {\r
+ IO1SET |= PWR50; \r
+ }\r
+ else\r
+ {\r
+ IO1CLR |= PWR50; \r
+ }\r
+}\r
+\r
+\r
+void pwr_80(char mode) // switch on/off 8V power line\r
+{\r
+ if (mode != PWR_ON)\r
+ {\r
+ IO1SET |= PWR80; \r
+ }\r
+ else\r
+ {\r
+ IO1CLR |= PWR80; \r
+ }\r
+}\r
+\r
+\r
+ volatile char test =0xF;\r
+\r
+void adc_isr(void) __attribute__ ((interrupt));\r
+\r
+void adc_isr(void) \r
+{\r
+ unsigned char chan =0; \r
+ unsigned int val =0;\r
+\r
+\r
+ chan = (char) ((ADDR>>24) & 0x07);\r
+ val = ((ADDR >> 6) & 0x3FF); \r
+\r
+ \r
+\r
+\r
+ adc_val[chan] = (((val * ADC_CON_CONST + ADC_OFFSET) + adc_val[chan]) >> 1) ;\r
+\r
+ ADCR &= ~(ADC_CR_START_OFF);\r
+\r
+\r
+ switch(chan)\r
+ {\r
+ case 0:\r
+ ADCR = ((ADC_CR_ADC1) | (ADC_CR_CLKS_11) | (ADC_CR_PDN_ON) | (ADC_CR_START_NOW) | (20*ADC_CR_CLK_DIV_1));\r
+ break;\r
+\r
+ case 1:\r
+ ADCR = ((ADC_CR_ADC2) | (ADC_CR_CLKS_11) | (ADC_CR_PDN_ON) | (ADC_CR_START_NOW) | (20*ADC_CR_CLK_DIV_1));\r
+ break;\r
+ \r
+ case 2:\r
+ ADCR = ((ADC_CR_ADC3) | (ADC_CR_CLKS_11) | (ADC_CR_PDN_ON) | (ADC_CR_START_NOW) | (20*ADC_CR_CLK_DIV_1));\r
+ break;\r
+ \r
+ case 3:\r
+ ADCR = ((ADC_CR_ADC0) | (ADC_CR_CLKS_11) | (ADC_CR_PDN_ON) | (ADC_CR_START_NOW) | (20*ADC_CR_CLK_DIV_1));\r
+ break; \r
+ }\r
+ \r
+ VICVectAddr = 0;\r
+\r
+}\r
+\r
+\r
+void init_adc(unsigned rx_isr_vect)\r
+{\r
+ \r
+ PINSEL1 |= ((PINSEL_1 << ADCCH0) | (PINSEL_1 << ADCCH1) | (PINSEL_1 << ADCCH2) | (PINSEL_1 << ADCCH3)); \r
+\r
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x32;\r
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned) adc_isr;\r
+ VICIntEnable = 0x40000;\r
+\r
+\r
+\r
+\r
+\r
+ ADCR = ((ADC_CR_ADC0) | (ADC_CR_CLKS_11) | (ADC_CR_PDN_ON) | (ADC_CR_START_NOW) | (10*ADC_CR_CLK_DIV_1));\r
+}\r
+\r
+\r
+void init_pwr(void) // init power lines\r
+{\r
+ IO1DIR |= (PWR33 | PWR50 | PWR80);\r
+ pwr_33(PWR_OFF);\r
+ pwr_50(PWR_OFF);\r
+ pwr_80(PWR_OFF);\r
+\r
+ //init_adc();\r
+\r
+}\r
+\r
+\r
+\r
+\r
+void tc1 (void) __attribute__ ((interrupt));\r
+\r
+void tc1 (void) {\r
+ \r
+ time_ms +=1;\r
+ \r
+ \r
+\r
+ if (T1IR != 4)\r
+ { \r
+ __deb_led_on(LEDR); \r
+ } \r
+\r
+ T1IR = 4; // Vynulovani priznaku preruseni\r
+ VICVectAddr = 0; // Potvrzeni o obsluze preruseni\r
+}\r
+\r
+\r
+/* Setup the Timer Counter 1 Interrupt */\r
+void init_time (unsigned rx_isr_vect)\r
+{\r
+\r
+ \r
+\r
+\r
+\r
+ T1PR = 0;\r
+ T1MR2 = TIME1MS;\r
+ T1MCR = (3<<6); // interrupt on MR1\r
+\r
+ T1TCR = 1; // Starts Timer 1 \r
+\r
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned long)tc1; // Nastaveni adresy vektotu preruseni\r
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x20 | 0x5; // vyber casovece pro preruseni\r
+ VICIntEnable = (1<<5); // Povoli obsluhu preruseni\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+#ifndef PWRSTEP_H\r
+#define PWRSTEP_H\r
+\r
+#define PWR_ON 1\r
+#define PWR_OFF 0\r
+\r
+#define ADC_DIV 10\r
+#define ADC_CON_CONST 322\r
+#define ADC_OFFSET 2000\r
+\r
+\r
+ volatile unsigned int adc_val[4];\r
+\r
+/** pwr_33 Switch on/off 3,3V power line\r
+ * @param mode - PWR_ON/PWR_OFF \r
+ */\r
+void pwr_33(char mode);\r
+\r
+/** pwr_50 Switch on/off 5,0V power line\r
+ * @param mode - PWR_ON/PWR_OFF \r
+ */\r
+void pwr_50(char mode);\r
+\r
+/** pwr_80 Switch on/off 8,0V power line\r
+ * @param mode - PWR_ON/PWR_OFF \r
+ */\r
+void pwr_80(char mode);\r
+\r
+/** init_pwr inicializes power lines - default: all lines is off\r
+ */\r
+void init_pwr(void);\r
+\r
+\r
+/** inicializes ADC lines and starts converion (use ISR)\r
+ * @param rx_isr_vect ISR vector\r
+ */\r
+void init_adc(unsigned rx_isr_vect);\r
+\r
+/** gobal time\r
+ * @note incremented twenty 20ms, overrun every 1194hours\r
+ */\r
+volatile unsigned int time_ms;\r
+\r
+/** inicializes time counter (use ISR)\r
+ * @param rx_isr_vect ISR vector\r
+ */\r
+void init_time (unsigned rx_isr_vect);\r
+#endif\r
--- /dev/null
+\r
+ #include <lpc21xx.h> \r
+ #include "uart.h"\r
+ #include <system_def.h>
+\r
+\r
+\r
+\r
+ #define UART_DLAB 0x80\r
+\r
+\r
+void init_uart0(int baudrate, char bits, char stopbit, char parit_en, char parit_mode ) \r
+{ \r
+\r
+ int pom , vala, valb;\r
+\r
+ PINSEL0 |= ( PINSEL_1<< 0) | ( PINSEL_1 << 2); \r
+\r
+ U0LCR =UART_DLAB | bits | stopbit | parit_en | parit_mode; // nastaven� datov�ho slova na 8 bit� a jeden stop bit bez parity, nastaven� DLAB na log "1"\r
+ \r
+ \r
+ pom = (CPU_APB_HZ)/(16 * baudrate);\r
+ \r
+ vala = (CPU_APB_HZ)/(16 * pom);\r
+ valb = (CPU_APB_HZ)/(16 * (pom + 1));\r
+\r
+ vala = baudrate - vala;\r
+ valb = baudrate - valb;\r
+\r
+ if (vala < 0) vala *= -1;\r
+ if (valb < 0) valb *= -1;\r
+ \r
+ if (vala > valb) pom += 1;\r
+\r
+ U0DLL = (char) (pom & 0xFF);\r
+ U0DLM = (char) ((pom >> 8) & 0xFF); // nastaven� p�edd�li�ky na 57600Bd\r
+ \r
+ U0LCR &= ~UART_DLAB; // vynulov�n� DLAB \r
+\r
+ }\r
+\r
+\r
+unsigned char uart1GetCh(void) // Nuceny prijem z uart1\r
+{\r
+ while (!(U1LSR & 1)); // cekani na prichozi byte\r
+ return (unsigned char)U1RBR; // navraceni prijateho byte\r
+}\r
+\r
+unsigned char uart0GetCh(void) // Nuceny prijem z uart1\r
+{\r
+ while (!(U0LSR & 1)); // cekani na prichozi byte\r
+ return (unsigned char)U0RBR; // navraceni prijateho byte\r
+}\r
+\r
+void uart1SendCh(char ch) // vyslani znaku na uart1\r
+{\r
+ while (!(U1LSR & 0x20)); // ceka na odeslani predchozich dat\r
+ U1THR=ch; // odeslani Byte\r
+ \r
+}\r
+\r
+void uart0SendCh(char ch) // vyslani znaku na uart0\r
+{\r
+ while (!(U0LSR & 0x20)); // ceka na odeslani predchozich dat\r
+ U0THR=ch; // odeslani Byte\r
+}\r
+\r
+\r
+void init_uart1(int baudrate, char bits, char stopbit, char parit_en, char parit_mode ) \r
+{ \r
+\r
+ int pom , vala, valb;\r
+\r
+ PINSEL0 |= ( PINSEL_1<< 16) | ( PINSEL_1 << 18); \r
+\r
+ U1LCR =UART_DLAB | bits | stopbit | parit_en | parit_mode; // nastaven� datov�ho slova na 8 bit� a jeden stop bit bez parity, nastaven� DLAB na log "1"\r
+ \r
+ \r
+ pom = (CPU_APB_HZ)/(16 * baudrate);\r
+ \r
+ vala = (CPU_APB_HZ)/(16 * pom);\r
+ valb = (CPU_APB_HZ)/(16 * (pom + 1));\r
+\r
+ vala = baudrate - vala;\r
+ valb = baudrate - valb;\r
+\r
+ if (vala < 0) vala *= -1;\r
+ if (valb < 0) valb *= -1;\r
+ \r
+ if (vala > valb) pom += 1;\r
+\r
+ U1DLL = (char) (pom & 0xFF);\r
+ U1DLM = (char) ((pom >> 8) & 0xFF); // nastaven� p�edd�li�ky na 57600Bd\r
+ \r
+ U1LCR &= ~UART_DLAB; // vynulov�n� DLAB \r
+\r
+ }\r
+\r
+\r
+\r
--- /dev/null
+#define UART_BITS_5 0x0\r
+#define UART_BITS_6 0x1\r
+#define UART_BITS_7 0x2\r
+#define UART_BITS_8 0x3\r
+\r
+#define UART_STOP_BIT_1 (0x0 << 2)\r
+#define UART_STOP_BIT_2 (0x1 << 2)\r
+\r
+#define UART_PARIT_ENA (0x1 << 3)\r
+#define UART_PARIT_OFF (0x0 << 3)\r
+#define UART_PARIT_ODD (0x0 << 4)\r
+#define UART_PARIT_EVEN (0x1 << 4)\r
+#define UART_PARIT_FORCE_1 (0x2 << 4)\r
+#define UART_PARIT_FORCE_0 (0x3 << 4)\r
+\r
+\r
+\r
+\r
+void init_uart1(int baudrate, char bits, char stopbit, char parit_en, char parit_mode );\r
+void init_uart0(int baudrate, char bits, char stopbit, char parit_en, char parit_mode );\r
+unsigned char uart1GetCh(void);\r
+unsigned char uart0GetCh(void);\r
+void uart1SendCh(char ch);\r
+void uart0SendCh(char ch);\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = interrupt_t0_test
+
+interrupt_t0_test_SOURCES = interrupt_t0_test.c
+
+# Switch off compiler optimization and debug info.
+#OPTIMIZE=
+#DEBUG=
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (7372800) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+//#error Fosc out of range (10MHz-25MHz)\r
+//#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+////////////////////////////////////////////////////////////////////////////////
+//
+// Philips LPC210X interrupt use example
+//
+// Description
+// -----------
+// This example demonstrates
+//version 1.0 15/08/2005
+//Author : Guillaume LAGARRIGUE
+////////////////////////////////////////////////////////////////////////////////
+
+#include <LPC210x.h>
+#include <types.h>
+#include <cpu_def.h>
+#include "config.h"
+
+
+#define NUM_LEDS 4
+static int leds[] = { 0x10000, 0x20000, 0x40000, 0x80000 };
+
+
+
+/*////////////////////////////////////////////////////////INITIALISATION FUNCTIONS///////////////////////////////////*/
+
+
+/**
+* Function Name: lowInit()
+*
+* Description:
+* This function starts up the PLL then sets up the GPIO pins before
+* waiting for the PLL to lock. It finally engages the PLL and
+* returns
+*
+* Calling Sequence:
+* void
+*
+* Returns:
+* void
+*
+*/
+static void lowInit(void)
+{
+ // set PLL multiplier & divisor.
+ // values computed from config.h
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;
+
+ // enable PLL
+ PLLCON = PLLCON_PLLE;
+ PLLFEED = 0xAA; // Make it happen. These two updates
+ PLLFEED = 0x55; // MUST occur in sequence.
+
+ // setup the parallel port pin
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output
+ IOSET = PIO_ONE_BITS; // set the ONEs output
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction
+
+ // wait for PLL lock
+ while (!(PLLSTAT & PLLSTAT_LOCK))
+ continue;
+
+ // enable & connect PLL
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;
+ PLLFEED = 0xAA; // Make it happen. These two updates
+ PLLFEED = 0x55; // MUST occur in sequence.
+
+ // setup & enable the MAM
+ MAMTIM = MAMTIM_CYCLES;
+ MAMCR = MAMCR_FULL;
+
+ // set the peripheral bus speed
+ // value computed from config.h
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed
+}
+
+
+/**
+* Function Name: sysInit()
+*
+* Description:
+* This function is responsible for initializing the program
+* specific hardware
+*
+* Calling Sequence:
+* void
+*
+* Returns:
+* void
+*
+*/
+static void sysInit(void)
+{
+ lowInit(); // setup clocks and processor port pins
+
+ MEMMAP = 1; // map interrupt vectors space into FLASH
+
+ //MEMMAP = 1; // map interrupt vectors space into FLASH
+ MEMMAP = 0x2; /** user RAM mode **/
+
+}
+
+/*////////////////////////////LEDS INITIALISATION///////////////////////*/
+
+/**
+* Initializes leds.
+*/
+static void ledInit()
+{
+ IODIR |= 0x000F0000; /*leds connected to P0.16 17 18 & 19 should blink*/
+ IOSET = 0x00000000; /* all leds are switched off */
+}
+
+/**
+* Switches the leds off.
+* @param led switched off led number. (integer)
+*/
+static void ledOff(int led) /* Ioclr.i =1 => IOset.i cleared */
+{
+ IOCLR = led;
+}
+
+/**
+* Switches the leds on.
+* @param led switched on led number. (integer)
+*/
+static void ledOn(int led) /* Ioset.i = 1 => P0.i = 1 */
+{
+ IOSET = led;
+}
+
+
+/**
+* Creates a delay
+* @param d duration (unit not defined yet)
+*/
+void
+delay(int d)
+{
+ volatile int x;
+ int i;
+ for (i = 0; i < 10; i++)
+ for(x = d; x; --x)
+ ;
+}
+
+
+
+/**
+ * Switches on and off the 4 leds one after one:
+ *
+ * A led is switched on when an interrupt occurs
+ * then switched off when the next interrupt occurs
+ * @param void
+ */
+void timer0_isr(void) __attribute__ ((interrupt));
+
+int i=0 ;
+int led_num=0 ;
+
+void timer0_isr(void)
+{
+
+ if (i ==0)
+ {
+ ledOn(leds[led_num]);
+ i=1;
+ }
+
+
+ else
+ {
+ ledOff(leds[led_num]);
+ i =0;
+ led_num++;
+ }
+
+
+ if (led_num == NUM_LEDS)
+ {
+ led_num=0;
+ }
+
+ T0IR |= 0x00000001; // Clear match0 interrupt
+ VICVectAddr = 0x00000000;
+}
+
+
+
+
+/**
+ * initializes timer T0 to raise an interrupt and to reset T0counter when it matches T0MatchRegister0
+ * @param
+ */
+static void Init_timer(void)
+{
+ VICVectAddr0 = (unsigned)timer0_isr; /* Set the ISR vector address vector0 = highest priority */
+ VICVectCntl0 = 0x20|4; /* Enable this vector and assign Timer IRQ to it */
+ VICIntEnable = 0x00000010; /* Enable the interrupt of timer0*/
+
+
+ T0MR0 = 0x0010000; //Match 0 control register = 65536
+ T0MCR = 0x3; //resets timer0 and generates interrupt when timer0 counter match MR0 register
+
+ T0TCR = 0x3; //Reset timer 0
+
+}
+
+
+int main(void)
+{
+ sysInit();
+ ledInit();
+ Init_timer();
+
+ T0TCR = 0x01; //Run timer 0
+
+ while(1) //infinite loop
+ {
+ }
+
+ return 0;
+}
--- /dev/null
+# Doxyfile 1.5.4
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING = UTF-8
+PROJECT_NAME = "Minibee - ZigBee radio Module"
+PROJECT_NUMBER = 1
+OUTPUT_DIRECTORY = ./doc
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class " \
+ "The $name widget " \
+ "The $name file " \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH = /home/jirka/
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+QT_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 1
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+CPP_CLI_SUPPORT = NO
+SIP_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+TYPEDEF_HIDES_STRUCT = NO
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+EXTRACT_ANON_NSPACES = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = NO
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text "
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = ./
+INPUT_ENCODING = UTF-8
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.d \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm \
+ *.dox \
+ *.py \
+ *.f90 \
+ *.f \
+ *.vhd \
+ *.vhdl \
+ *.C \
+ *.CC \
+ *.C++ \
+ *.II \
+ *.I++ \
+ *.H \
+ *.HH \
+ *.H++ \
+ *.CS \
+ *.PHP \
+ *.PHP3 \
+ *.M \
+ *.MM \
+ *.PY \
+ *.F90 \
+ *.F \
+ *.VHD \
+ *.VHDL \
+ *.C \
+ *.H \
+ *.tlh \
+ *.diff \
+ *.patch \
+ *.moc \
+ *.xpm \
+ *.dox
+RECURSIVE = YES
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXCLUDE_SYMBOLS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+HTML_DYNAMIC_SECTIONS = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = YES
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = YES
+USE_PDFLATEX = YES
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE = minibee.tag
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+MSCGEN_PATH =
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = YES
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+DOT_GRAPH_MAX_NODES = 50
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = YES
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+//\r
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008\r
+//\r
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering\r
+// License: GNU GPL v.2\r
+//\r
+\r
+\r
+/**\r
+ * @file MC1319x.c\r
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008\r
+ * \r
+ * @brief Library for MC13xx2 freescale radio\r
+ * \r
+ */\r
+\r
+\r
+\r
+#include "spi.h"\r
+#include "MC1319x.h"\r
+#include "MC1319xdef.h"\r
+\r
+\r
+#ifdef LPC\r
+ #include <lpc21xx.h> /* LPC21xx definitions */\r
+ #include <types.h>\r
+ #include <deb_led.h>\r
+#endif \r
+\r
+struct Message *rcvBuf; ///< Pointer to recieve Message buffer\r
+struct Message *sndBuf; ///< Pointer to send Message buffer\r
+\r
+\r
+uint8_t MC_RecievePaket(struct Message *msg);\r
+\r
+\r
+\r
+/**\r
+ * Interupt handling. Here is reading IRQ register and deremine what generates IRQ\r
+ * @note This function is platform depended\r
+ */\r
+\r
+#ifdef ATmega88 \r
+ ISR(INT0_vect)\r
+#endif\r
+#ifdef LPC\r
+ void ext_isr(void)\r
+#endif\r
+ \r
+{ \r
+ uint16_t dummy =0;\r
+\r
+#ifdef LPC \r
+ EXTINT |= EXTINT_EINT3_m ; // Acknowledge interupt source\r
+#endif\r
+ \r
+ deb_led_on(LEDR); \r
+// send_rs_str("ISR\n"); // printout that ISR occurs\r
+ \r
+ uint16_t mask = spi_Read(IRQ_STATUS); \r
+\r
+ if((mask & IRQ_STATUS_RX_RCVD_IRQm) == IRQ_STATUS_RX_RCVD_IRQm) // Recieved data\r
+ {\r
+ CLR(RXTXEN); // clear \r
+ \r
+ dummy = (spi_Read(RX_STATUS) & 0x7F);\r
+ \r
+ if(!(mask & 1)) \r
+ {\r
+ MC_RecievePaket(rcvBuf);\r
+ goto ISR_END;\r
+ }\r
+\r
+ rcvBuf->done = 1;\r
+ rcvBuf->len = dummy;\r
+\r
+ spi_Read_Buf(rcvBuf);\r
+ }\r
+\r
+\r
+ if((mask & IRQ_STATUS_TX_SENT_IRQm) == IRQ_STATUS_TX_SENT_IRQm) // Data send done\r
+ {\r
+ CLR(RXTXEN); // clear \r
+ sndBuf->done = 1;\r
+ }\r
+ \r
+ \r
+// if((mask & IRQ_STATUS_PLL_LOCK_IRQm) == IRQ_STATUS_PLL_LOCK_IRQm); //todo , lost PLL LOCK\r
+// if((mask & IRQ_STATUS_RAM_ADR_ERRm) == IRQ_STATUS_RAM_ADR_ERRm) ; //todo, RAM buffer overrun\r
+// if((mask & IRQ_STATUS_ARB_BUSY_ERRm) == IRQ_STATUS_ARB_BUSY_ERRm) ; //todo\r
+// if((mask & IRQ_STATUS_SRTM_DATA_ERRm) == IRQ_STATUS_SRTM_DATA_ERRm); //todo Streaming data requested/aviable\r
+// if((mask & IRQ_STATUS_ATTN_IRQm) == IRQ_STATUS_ATTN_IRQm); //todo ATTN asserted \r
+// if((mask & IRQ_STATUS_DOZE_IRQm) == IRQ_STATUS_DOZE_IRQm); // todo timer event - return to idle from doze \r
+// if((mask & IRQ_STATUS_CCA_IRQm) == IRQ_STATUS_CCA_IRQm); //todo CCA/ED done\r
+// if((mask & IRQ_STATUS_TMR1_IRQm) == IRQ_STATUS_TMR1_IRQm);//todo timer 1 match\r
+// if((mask & IRQ_STATUS_TMR2_IRQm) == IRQ_STATUS_TMR2_IRQm);//todo timer 2 match\r
+// if((mask & IRQ_STATUS_TMR3_IRQm) == IRQ_STATUS_TMR3_IRQm);//todo timer 3 match\r
+// if((mask & IRQ_STATUS_TMR4_IRQm) == IRQ_STATUS_TMR4_IRQm);//todo timer 4 match \r
+// if((mask & IRQ_STATUS_CCAm) == IRQ_STATUS_CCAm); // output of the comparation of CCA\r
+// if((mask & IRQ_STATUS_CRC_VALIDm) == IRQ_STATUS_CRC_VALIDm); // recieved correct CRC\r
+ \r
+ISR_END:\r
+ \r
+#ifdef LPC\r
+ VICVectAddr = 0; // acknowledge ISR in VIC\r
+#endif\r
+ deb_led_off(LEDR);\r
+}\r
+/**\r
+ * Delay function.\r
+ * @note Should be removed in future\r
+ */\r
+void dummy_wait()\r
+{\r
+ unsigned int wait = 5000000;\r
+ while(--wait);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * Woodoo function inicialize radio. I hove no idea what it is doing, but its VERY inportatnt.\r
+ */\r
+void MC_Woodoo(void)\r
+{\r
+ spi_ReadModifiWrite(0x08, 0x0001, 0xFFFF);\r
+ spi_ReadModifiWrite(0x08, 0x0010, 0xFFFF);\r
+ spi_ReadModifiWrite(0x11, 0x0000, 0xFCFF);\r
+ spi_ReadModifiWrite(0x06, 0x4000, 0xFFFF); \r
+}\r
+\r
+\r
+/**\r
+ * Reset the radio to it default state and inicialize it\r
+ */\r
+uint8_t MC_Reset(void) // generate reset on MC13192x\r
+{\r
+\r
+ \r
+ disable_IRQ_pin();\r
+ \r
+ // reset MC radio\r
+ SET(ATTN);\r
+ CLR(RXTXEN);\r
+ CLR(RST);\r
+ dummy_wait();\r
+ SET(RST); \r
+\r
+\r
+ // wait for IRQ\r
+ while( (IO0PIN & (1<<IRQ)) == (1<<IRQ)); // waiting for incomming interrupt\r
+ \r
+ MC_Woodoo(); // radio init woodoo\r
+ \r
+ if(spi_Read(RST_IND) & RST_IND_RESET_INDm) // test reset indicator\r
+ {\r
+ return 1; // return 1 if test fails\r
+ } \r
+\r
+ spi_Read(IRQ_STATUS); // acknowledge power-on IRQ\r
+ \r
+ spi_ReadModifiWrite( GPIO_DATA_OUT, (1<<7) | (1<<9) ,0xFFFF); // eneble IRQ pullup and set moderate drive strenght\r
+ spi_ReadModifiWrite( CONTROL_B, (1<<12)|(1<<14),0xFFFF);\r
+ spi_ReadModifiWrite( CONTROL_A, CONTROL_A_RX_RCVDm|CONTROL_A_TX_SENTm,0xFFFF);\r
+\r
+#ifdef LPC\r
+ EXTINT |= EXTINT_EINT3_m ; // acknowledge ISR\r
+#endif\r
+ \r
+ enable_IRQ_pin();\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Scan selected radio channel and returns measured energy (lower is better)\r
+ * @note This function is not using ISR, but in future it may do.\r
+ */\r
+uint8_t MC_ED(void)\r
+{\r
+ uint16_t mask;\r
+ uint8_t val;\r
+\r
+ disable_IRQ_pin();\r
+\r
+ CLR(RXTXEN); //switch off radio output\r
+ spi_ReadModifiWrite(CONTROL_A,CONTROL_A_CCA_EDm|CONTROL_A_CCA_XCVR_CCAEDm | CONTROL_A_CCAm, \\r
+ ~(CONTROL_A_CCA_TYPE0m | CONTROL_A_CCA_XCVR_SEG1m ));\r
+ // selects CCA as ED type and sets transerciver to CCA/ED mode and alows to generate CCA interrupt\r
+ \r
+ \r
+ SET(RXTXEN); // starts the ED detection\r
+ \r
+ while( (IO0PIN & (1<<IRQ)) == (1<<IRQ)); // waiting for incomming interrupt\r
+\r
+ CLR(RXTXEN); //switch off radio output\r
+ \r
+ mask = spi_Read(IRQ_STATUS); // acknowledge interrupt\r
+ if((mask & IRQ_STATUS_CCA_IRQm) != IRQ_STATUS_CCA_IRQm) return 1;\r
+ \r
+ val = (uint8_t)(spi_Read(RX_STATUS) >> 8);\r
+\r
+ enable_IRQ_pin();\r
+\r
+ return val;\r
+}\r
+\r
+/**\r
+ * Sends the packed stored in Message structure\r
+ * @param *msg ponter to Message structure\r
+ */\r
+uint8_t MC_SendPaket(struct Message *msg)\r
+{\r
+\r
+ sndBuf = msg;\r
+ msg->done = 0;\r
+\r
+ CLR(RXTXEN); //switch off radio output\r
+\r
+ spi_ReadModifiWrite(CONTROL_A, CONTROL_A_TX_SENTm | CONTROL_A_RX_RCVDm \\r
+ ,~(CONTROL_A_TX_STRMm|CONTROL_A_RX_STRMm|CONTROL_A_TMR_TRIG_ENm|CONTROL_A_CCA_XCVR_CLRm) );\r
+ // selects CCA as ED type and sets transerciver to CCA/ED mode and alows to generate CCA interrupt\r
+ \r
+ spi_Write(TX_PKT_CTL, TX_PKT_CTL_PKT_LENGHT(msg->len)); // write the number data bytes in message + 2\r
+ spi_Write_Buf (msg); // recursive write data to MC radio\r
+\r
+ spi_ReadModifiWrite(CONTROL_A, CONTROL_A_CCA_XCVR_PMTXm, 0xFFFF); // Sets TX mode\r
+ SET(RXTXEN); // starts transmit\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Resend the packed stored in radio transmit buffer\r
+ * @param *msg pointer to Message structure\r
+ * @note Not sure if it is working\r
+ */\r
+uint8_t MC_ReSendPaket(struct Message *msg)\r
+{\r
+ sndBuf = msg;\r
+ msg->done = 0;\r
+\r
+ CLR(RXTXEN); //switch off radio output\r
+\r
+ spi_ReadModifiWrite(CONTROL_A, CONTROL_A_TX_SENTm | CONTROL_A_RX_RCVDm \\r
+ ,~(CONTROL_A_TX_STRMm|CONTROL_A_RX_STRMm|CONTROL_A_TMR_TRIG_ENm|CONTROL_A_CCA_XCVR_CLRm) );\r
+ // selects CCA as ED type and sets transerciver to CCA/ED mode and alows to generate CCA interrupt\r
+ spi_Write(TX_PKT_CTL, TX_PKT_CTL_PKT_LENGHT(msg->len)); // recursive write data to MC radio\r
+\r
+ spi_ReadModifiWrite(CONTROL_A, CONTROL_A_CCA_XCVR_PMTXm, 0xFFFF); // Sets TX mode\r
+\r
+ SET(RXTXEN); // starts transmit\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * Reads packet stored in radio buffer\r
+ * @param *msg pointer to Message structure\r
+ */\r
+uint8_t MC_RecievePaket(struct Message *msg)\r
+{\r
+ uint16_t dummy;\r
+\r
+ rcvBuf = msg;\r
+ msg->done = 0;\r
+\r
+ CLR(RXTXEN); //switch off radio output\r
+\r
+ spi_ReadModifiWrite(CONTROL_A, CONTROL_A_TX_SENTm | CONTROL_A_RX_RCVDm | CONTROL_A_CCA_XCVR_PMRXm \\r
+ ,~(CONTROL_A_TX_STRMm|CONTROL_A_RX_STRMm|CONTROL_A_TMR_TRIG_ENm|CONTROL_A_CCA_XCVR_CLRm) );\r
+ // selects CCA as ED type and sets transerciver to CCA/ED mode and alows to generate CCA interrupt\r
+\r
+ dummy = (spi_Read(RX_STATUS) & 0x7F);\r
+ SET(RXTXEN); // starts recieving\r
+\r
+ return 0; \r
+}\r
+\r
+\r
+/**\r
+ * Returns radio identification\r
+ */\r
+uint16_t MC_WhoAmI(void)\r
+{\r
+ return spi_Read(CHIP_ID);\r
+}\r
+\r
+/**\r
+ * Sets radio frequency channel\r
+ * @param channel specifies frequency output (1~16)\r
+ * @note See definions from MC1319xdef.h\r
+ */\r
+uint8_t MC_SetChannel(uint8_t channel)\r
+{\r
+ uint16_t int_div = 0;\r
+ uint16_t lo1_num = 0;\r
+\r
+ switch(channel)\r
+ {\r
+ case 1: int_div = LO1_INT_DIV_CH1;\r
+ lo1_num = LO1_NUM_CH1;\r
+ break;\r
+\r
+ case 2: int_div = LO1_INT_DIV_CH2;\r
+ lo1_num = LO1_NUM_CH2;\r
+ break;\r
+\r
+ case 3: int_div = LO1_INT_DIV_CH3;\r
+ lo1_num = LO1_NUM_CH3;\r
+ break;\r
+\r
+ case 4: int_div = LO1_INT_DIV_CH4;\r
+ lo1_num = LO1_NUM_CH4;\r
+ break;\r
+\r
+ case 5: int_div = LO1_INT_DIV_CH5;\r
+ lo1_num = LO1_NUM_CH5;\r
+ break;\r
+\r
+ case 6: int_div = LO1_INT_DIV_CH6;\r
+ lo1_num = LO1_NUM_CH6;\r
+ break;\r
+\r
+ case 7: int_div = LO1_INT_DIV_CH7;\r
+ lo1_num = LO1_NUM_CH7;\r
+ break;\r
+\r
+ case 8: int_div = LO1_INT_DIV_CH8;\r
+ lo1_num = LO1_NUM_CH8;\r
+ break;\r
+\r
+ case 9: int_div = LO1_INT_DIV_CH9;\r
+ lo1_num = LO1_NUM_CH9;\r
+ break;\r
+\r
+ case 10: int_div = LO1_INT_DIV_CH10;\r
+ lo1_num = LO1_NUM_CH10;\r
+ break;\r
+\r
+ case 11: int_div = LO1_INT_DIV_CH11;\r
+ lo1_num = LO1_NUM_CH11;\r
+ break;\r
+\r
+ case 12: int_div = LO1_INT_DIV_CH12;\r
+ lo1_num = LO1_NUM_CH12;\r
+ break;\r
+\r
+ case 13: int_div = LO1_INT_DIV_CH13;\r
+ lo1_num = LO1_NUM_CH13;\r
+ break;\r
+\r
+ case 14: int_div = LO1_INT_DIV_CH14;\r
+ lo1_num = LO1_NUM_CH14;\r
+ break;\r
+\r
+ case 15: int_div = LO1_INT_DIV_CH15;\r
+ lo1_num = LO1_NUM_CH15;\r
+ break;\r
+ \r
+ case 16: int_div = LO1_INT_DIV_CH16;\r
+ lo1_num = LO1_NUM_CH16;\r
+ break;\r
+\r
+ default: return 0;\r
+ }\r
+\r
+ spi_Write(LO1_NUM,lo1_num);\r
+ spi_ReadModifiWrite(LO1_INT_DIV,int_div,0xFF00);\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * Sets CLKO pin to specified clock output\r
+ * @param tick specifies frequency output \r
+ * @param enable enable or disable output\r
+ * @note Use definions from MC1319xdef.h\r
+ */\r
+uint8_t MC_SetClko(uint16_t tick, uint8_t enable)\r
+{\r
+ \r
+ spi_ReadModifiWrite(CLKO_CTL,tick,~(CLKO_CTL_CLKO_CLRm));\r
+\r
+ if (enable == 1)\r
+ {\r
+ spi_ReadModifiWrite(CONTROL_C,CONTROL_C_CLKO_ENm,0xFFFF);\r
+ }\r
+ else\r
+ {\r
+ spi_ReadModifiWrite(CONTROL_C,0,~(CONTROL_C_CLKO_ENm));\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * Im not remeber what is this doing.\r
+ */\r
+uint8_t MC_SetPa(uint8_t val)\r
+{\r
+ spi_ReadModifiWrite(PA_LVL,(uint16_t)val,0xFFFF);\r
+ return 0;\r
+}\r
--- /dev/null
+//\r
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008\r
+//\r
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering\r
+// License: GNU GPL v.2\r
+//\r
+/**\r
+ * @file MC1319x.h\r
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008\r
+ * \r
+ * @brief Function prototypes for MC1319x.c\r
+ * \r
+ */\r
+\r
+\r
+#ifndef MC1319x_H\r
+#define MC1319x_H\r
+\r
+\r
+#include "MC1319xdef.h"\r
+\r
+\r
+uint8_t MC_Reset(void); // generate reset on MC1319x\r
+uint16_t MC_WhoAmI(void); // returns ID of MC1319x\r
+uint8_t MC_ED(void); // measure ED on current channel\r
+uint8_t MC_SendPaket(struct Message *msg); // send message wia zigbee\r
+uint8_t MC_ReSend(struct Message *msg); // send message wia zigbee\r
+uint8_t MC_RecievePaket(struct Message *msg); // Initate recieving packet \r
+uint8_t MC_SetClko(uint16_t tick, uint8_t enable); // sets and enables CLKO\r
+uint8_t MC_SetPa(uint8_t val); // sets PA level\r
+void dummy_wait(); // dummy wait cycle\r
+\r
+void ext_isr(void) __attribute__ ((interrupt)); ///< protype if ISR function, platform dependent\r
+\r
+#endif //MC1319x_H\r
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+
+/**
+ * @file MC1319xdef.h
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief Radio register definition and platform specific definitions.
+ *
+ */
+
+#ifndef MC1319XDEF_H
+#define MC1319XDEF_H
+
+// define proctype
+
+//#define ATmega88 ///< Select ATmega88 as master MCU
+#define LPC ///< Select LPC as master MCU
+
+
+//------------- procesor ATmega88 specific definitons ------------
+
+// control pins
+#ifdef ATmega88
+
+ #define IRQ PD2 ///< Inverted , input, ISR request
+ #define CE PD4 ///< slave select , #CE on MC radio
+ #define ATTN PD5 ///< Inverted , output
+ #define RXTXEN PD6 ///< enable RX or TX operations
+ #define RST PD7 ///< Inverted , output
+ #define DD_MOSI PB3 ///< SPI - master output
+ #define DD_MISO PB4 ///< SPI - master input
+ #define DD_SCK PB5 ///< SPI - master clock
+
+
+
+ #define CLR(x) \ ///< clear pin command
+ { PORTD &= ~(1<<(x)); }
+
+
+ #define SET(x) \ ///< clear pin command
+ { PORTD |= (1<<(x)); }
+#endif
+
+#ifdef LPC
+
+#include <types.h>
+
+ #define IRQ 9 ///< P0.9 Inverted , input, ISR request
+ #define CE 7 ///< P0.7 slave select , #CE on MC radio
+ #define ATTN 11 ///< P0.11 Inverted , output
+ #define RXTXEN 8 ///< P0.8 enable RX or TX operations
+ #define RST 12 ///< P0.12 Inverted , output
+ #define MOSI 6 ///< P0.6 SPI - master output
+ #define MISO 5 ///< P0.5 SPI - master input
+ #define SCK 4 ///< P0.4 SPI - master clock
+
+ /// clear pin command
+ #define CLR(x) \
+ { IO0CLR |= (1<<(x)); }
+
+ /// set pin command
+ #define SET(x) \
+ { IO0SET |= (1<<(x)); }
+
+#endif
+
+
+// ------------------ message definitons ----------------
+
+
+
+
+/// Radio message structure
+struct Message{
+ uint8_t done; ///< Send / recieve flag
+ uint8_t error; ///< error flag - ocured during send or recieveng
+ uint8_t len; ///< data length t osend (0 to 125)
+ uint8_t data[25]; ///< data
+} ;
+
+
+
+
+
+
+//-------------- MC1319x definitions -----------------------------
+
+
+// SPI read and write mask comands
+#define RD 0x80
+#define WR 0x00
+
+// Reset register
+#define RESET 0x00
+
+// Recieve buffer register
+#define RX_PKT_RAM 0x01
+
+// Transmit buffer register
+#define TX_PKT_RAM 0x02
+
+// Transmit control register
+#define TX_PKT_CTL 0x03
+ #define TX_PKT_CTL_RAM2_SELm 15
+ #define TX_PKT_CTL_PKT_LENGHT(x) ( x + 2 )
+
+// CCA treshold register
+#define CCA_THRESH 0x04
+
+// IRQ mas register
+#define IRQ_MASK 0x05
+ #define IRQ_MASK_ATTNm 0x8000
+ #define IRQ_MASK_RAM_ADDRm 0x1000
+ #define IRQ_MASK_ARB_BUSYm 0x0800
+ #define IRQ_MASK_STRM_DATAm 0x0400
+ #define IRQ_MASK_PPL_LOCKm 0x0200
+ #define IRQ_MASK_ACOMAm 0x0100
+ #define IRQ_MASK_DOZEm 0x0010
+ #define IRQ_MASK_TMR4m 0x0008
+ #define IRQ_MASK_TMR3m 0x0004
+ #define IRQ_MASK_TMR2m 0x0002
+ #define IRQ_MASK_TMR1m 0x0001
+
+
+#define CONTROL_A 0x06
+ #define CONTROL_A_TX_STRMm 0x1000
+ #define CONTROL_A_RX_STRMm 0x0800
+ #define CONTROL_A_CCAm 0x0400
+ #define CONTROL_A_TX_SENTm 0x0200
+ #define CONTROL_A_RX_RCVDm 0x0100
+ #define CONTROL_A_TMR_TRIG_ENm 0x0080
+ #define CONTROL_A_CCA_TYPE1m 0x0020
+ #define CONTROL_A_CCA_TYPE0m 0x0010
+ #define CONTROL_A_CCA_CCAm CONTROL_A_CCA_TYPE0m
+ #define CONTROL_A_CCA_EDm CONTROL_A_CCA_TYPE1m
+ #define CONTROL_A_CCA_XCVR_SEG1m 0x0002
+ #define CONTROL_A_CCA_XCVR_SEG0m 0x0001
+ #define CONTROL_A_CCA_XCVR_IDLEm 0
+ #define CONTROL_A_CCA_XCVR_CCAEDm CONTROL_A_CCA_XCVR_SEG0m
+ #define CONTROL_A_CCA_XCVR_PMRXm CONTROL_A_CCA_XCVR_SEG1m
+ #define CONTROL_A_CCA_XCVR_PMTXm (CONTROL_A_CCA_XCVR_SEG1m | CONTROL_A_CCA_XCVR_SEG0m)
+ #define CONTROL_A_CCA_XCVR_CLRm (CONTROL_A_CCA_XCVR_SEG1m | CONTROL_A_CCA_XCVR_SEG0m)
+
+#define CONTROL_B 0x07
+ #define CONTROL_B_TMR_LOADm 0x8000
+ #define CONTROL_B_MISO_HIZ_ENm 0x0800
+ #define CONTROL_B_CLKO_DOZE_ENm 0x0200
+ #define CONTROL_B_TX_DONEm 0x0080
+ #define CONTROL_B_RX_DONEm 0x0040
+ #define CONTROL_B_USE_STM_MODEm 0x0020
+ #define CONTROL_B_HIB_ENm 0x0002
+ #define CONTROL_B_DOZE_ENm 0x0001
+
+#define PA_ENABLE 0x08
+ #define PA_ENABLE_PA_ENm 0x8000
+
+#define CONTROL_C 0x09
+ #define CONTROL_C_GPIO_ALT_ENm 0x0080
+ #define CONTROL_C_CLKO_ENm 0x0020
+ #define CONTROL_C_TMR_PRESCALE2m 0x0004
+ #define CONTROL_C_TMR_PRESCALE1m 0x0002
+ #define CONTROL_C_TMR_PRESCALE0m 0x0001
+
+#define CLKO_CTL 0x0A
+ #define CLKO_CTL_CLKO_RATE2m 0x0004
+ #define CLKO_CTL_CLKO_RATE1m 0x0002
+ #define CLKO_CTL_CLKO_RATE0m 0x0001
+ #define CLKO_CTL_CLKO_16Mm 0x00
+ #define CLKO_CTL_CLKO_8Mm CLKO_CTL_CLKO_RATE0m
+ #define CLKO_CTL_CLKO_4Mm CLKO_CTL_CLKO_RATE1m
+ #define CLKO_CTL_CLKO_2Mm (CLKO_CTL_CLKO_RATE0m | CLKO_CTL_CLKO_RATE1m)
+ #define CLKO_CTL_CLKO_1Mm CLKO_CTL_CLKO_RATE2m
+ #define CLKO_CTL_CLKO_62Km (CLKO_CTL_CLKO_RATE0m | CLKO_CTL_CLKO_RATE2m)
+ #define CLKO_CTL_CLKO_32Km (CLKO_CTL_CLKO_RATE1m | CLKO_CTL_CLKO_RATE2m)
+ #define CLKO_CTL_CLKO_16Km (CLKO_CTL_CLKO_RATE0m | CLKO_CTL_CLKO_RATE1m| CLKO_CTL_CLKO_RATE2m)
+
+ #define CLKO_CTL_CLKO_ONm 0x01 // additional definition, not in register
+ #define CLKO_CTL_CLKO_OFFm 0x00 // additional definition, not in register
+ #define CLKO_CTL_CLKO_CLRm (CLKO_CTL_CLKO_RATE0m | CLKO_CTL_CLKO_RATE1m| CLKO_CTL_CLKO_RATE2m)
+
+
+#define GPIO_DIR 0x0B // not finished
+#define GPIO_DATA_OUT 0x0C // not finished
+
+
+#define LO1_INT_DIV 0x0F
+ #define LO1_INT_DIV_CH1 0x95
+ #define LO1_INT_DIV_CH2 0x95
+ #define LO1_INT_DIV_CH3 0x95
+ #define LO1_INT_DIV_CH4 0x96
+ #define LO1_INT_DIV_CH5 0x96
+ #define LO1_INT_DIV_CH6 0x96
+ #define LO1_INT_DIV_CH7 0x97
+ #define LO1_INT_DIV_CH8 0x97
+ #define LO1_INT_DIV_CH9 0x97
+ #define LO1_INT_DIV_CH10 0x98
+ #define LO1_INT_DIV_CH11 0x98
+ #define LO1_INT_DIV_CH12 0x98
+ #define LO1_INT_DIV_CH13 0x99
+ #define LO1_INT_DIV_CH14 0x99
+ #define LO1_INT_DIV_CH15 0x99
+ #define LO1_INT_DIV_CH16 0x9A
+
+
+#define LO1_NUM 0x10
+ #define LO1_NUM_CH1 0x5000
+ #define LO1_NUM_CH2 0xA000
+ #define LO1_NUM_CH3 0xF000
+ #define LO1_NUM_CH4 0x4000
+ #define LO1_NUM_CH5 0x9000
+ #define LO1_NUM_CH6 0xE000
+ #define LO1_NUM_CH7 0x3000
+ #define LO1_NUM_CH8 0x8000
+ #define LO1_NUM_CH9 0xD000
+ #define LO1_NUM_CH10 0x2000
+ #define LO1_NUM_CH11 0x7000
+ #define LO1_NUM_CH12 0xC000
+ #define LO1_NUM_CH13 0x1000
+ #define LO1_NUM_CH14 0x6000
+ #define LO1_NUM_CH15 0xB000
+ #define LO1_NUM_CH16 0x0000
+
+
+// channel decimal definiton
+#define ZB_CH1 1
+#define ZB_CH2 2
+#define ZB_CH3 3
+#define ZB_CH4 4
+#define ZB_CH5 5
+#define ZB_CH6 6
+#define ZB_CH7 7
+#define ZB_CH8 8
+#define ZB_CH9 9
+#define ZB_CH10 10
+#define ZB_CH11 11
+#define ZB_CH12 12
+#define ZB_CH13 13
+#define ZB_CH14 14
+#define ZB_CH15 15
+#define ZB_CH16 16
+
+// channel 802.15.4 definiton
+#define ZB_CH802_11 ZB_CH1
+#define ZB_CH802_12 ZB_CH2
+#define ZB_CH802_13 ZB_CH3
+#define ZB_CH802_14 ZB_CH4
+#define ZB_CH802_15 ZB_CH5
+#define ZB_CH802_16 ZB_CH6
+#define ZB_CH802_17 ZB_CH7
+#define ZB_CH802_18 ZB_CH8
+#define ZB_CH802_19 ZB_CH9
+#define ZB_CH802_20 ZB_CH10
+#define ZB_CH802_21 ZB_CH11
+#define ZB_CH802_22 ZB_CH12
+#define ZB_CH802_23 ZB_CH13
+#define ZB_CH802_24 ZB_CH14
+#define ZB_CH802_25 ZB_CH15
+#define ZB_CH802_26 ZB_CH16
+
+
+
+
+#define PA_LVL 0x12// not finished
+
+#define TMR_CMP1_A 0x1B// not finished
+#define TMR_CMP1_B 0x1C// not finished
+
+#define TMR_CMP2_A 0x1D// not finished
+#define TMR_CMP2_B 0x1E// not finished
+
+#define TMR_CMP3_A 0x1F// not finished
+#define TMR_CMP3_B 0x20// not finished
+
+#define TMR_CMP4_A 0x21// not finished
+#define TMR_CMP4_B 0x22// not finished
+
+#define TC2_PRIME 0x23// not finished
+
+#define IRQ_STATUS 0x24
+ #define IRQ_STATUS_PLL_LOCK_IRQm 0x8000
+ #define IRQ_STATUS_RAM_ADR_ERRm 0x4000
+ #define IRQ_STATUS_ARB_BUSY_ERRm 0x2000
+ #define IRQ_STATUS_SRTM_DATA_ERRm 0x1000
+ #define IRQ_STATUS_ATTN_IRQm 0x0400
+ #define IRQ_STATUS_DOZE_IRQm 0x0200
+ #define IRQ_STATUS_TMR1_IRQm 0x0100
+ #define IRQ_STATUS_RX_RCVD_IRQm 0x0080
+ #define IRQ_STATUS_TX_SENT_IRQm 0x0040
+ #define IRQ_STATUS_CCA_IRQm 0x0020
+ #define IRQ_STATUS_TMR3_IRQm 0x0010
+ #define IRQ_STATUS_TMR4_IRQm 0x0008
+ #define IRQ_STATUS_TMR2_IRQm 0x0004
+ #define IRQ_STATUS_CCAm 0x0002
+ #define IRQ_STATUS_CRC_VALIDm 0x0001
+
+#define RST_IND 0x25
+ #define RST_IND_RESET_INDm 0x0080
+
+
+#define CURRENT_TIME_A 0x26
+#define CURRENT_TIME_B 0x27
+
+#define GPIO_DATA_IN 0x28 // not finished
+
+#define CHIP_ID 0x2C // not finished
+
+#define RX_STATUS 0x2D
+
+#define TIMESTAMP_A 0x2E
+#define TIMESTAMP_B 0x2F
+
+#define BER_ENABLE 0x30
+ #define BER_ENABLE_BER_EN 0x8000
+
+
+
+
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+# eb_blink je nazev programu, pod timto navzem bude systemem prekladan
+bin_PROGRAMS = minibee
+
+
+# za nazev_programu_SOURCES se davaji vsechny C zdrojaky, ktere se budou kompilovat
+minibee_SOURCES = main.c spi_LPC.c MC1319x.c uart_minibee.c
+
+
+minibee_LIBS = ebb
+
+
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+
+/**
+ * \mainpage Zigbee radio MC13192 or MC13202
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ * \section Introduction
+ * This code provides same sample how to use MC13xx2 radio in packet mode.
+ * The basic libraries for testing are writen mostly platform independent.
+ * See the function description. In some function is noted that use some platform
+ * depended parts whis should be modified. Originaly this code was developed for
+ * MC13192 radio, but now we use MC13202 radio which is almost fully compatible.
+ *
+ * MC1319x.c - is mostly platform independent, see notes inside. This library
+ * contains basic function which contains funcion for send, recieve, set clko,
+ * read ID, set frequency and do energy detect.
+ *
+ * MC1319xdef.h - contains register definions and bit masks for MC13xxx radio
+ *
+ * spi.h - platform independent. Contains function prototypes and definition
+ * SPI_SPEED for setting SPI speed in Hz.
+ *
+ * spi_LPC.c - platform dependent. Contains inicializing function for SPI channel,
+ * all other used pins and installs ISR.
+ *
+ * uart_minibee.h - platform independent. Function prototypes for uart communication
+ *
+ * uart_minibee.c - particulary platform dependent. Some part of this code must be ported
+ * for new platform.
+ *
+ * Porting to another platform:
+ * For another platform you must implement your own SPI function,
+ * set pins and install ISR. It must support the prototypes functions
+ * which is defined in spi.h. You also must implement your
+ * function for uart communication (see uart_minibee.c).
+ *
+ * The last tested platform is LpcEurobot which is ARM7 micproporcesor LPC2119.
+ * It also use eurobot ebb library for UART communication for ARM7. Older platform
+ * was AVR which is no longer supported due to no platform for testing. In this code
+ * is added spi_avr.c which is not fully ported.
+ *
+ * @note Known issues:
+ * 1) IRQ edge sensive - in this code are parts where is ISR at IRQ pins is disabled.
+ * If this code didnt fully acknowledge IRQ in radio the renewed ISR will not recognise
+ * IRQ request. If this occurs the main MCU must be reseted.
+ * Solutions:
+ * a) comment line 73 in spi_LPC.c - in commnent is ***
+ * b) move all code to ISR and never disable ISR on IRQ pin - recomended
+ */
+
+/**
+ * @file main.c
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief Demo application demonstrating use of MC1319x library.
+ * This file provides simply how-to use MC1319x library.
+ * From main function is called init function of SPI and UART.
+ * After sucessfull inicialize it tries read chip ID and recognize
+ * connected radio. Whan everythig is sucessfull it runs command
+ * processor which allows you to test radio functions.
+ *
+ */
+
+
+
+
+
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <deb_led.h>
+#include <types.h>
+#include "MC1319x.h"
+#include "spi.h"
+#include "uart_minibee.h"
+
+
+
+struct Message MsgSnd; ///< Send buffer
+struct Message MsgRcv; ///< Recieve buffer
+
+
+
+
+/**
+ * Send data via radio
+ * @param *msg pointer to Message sructure
+ */
+void sendData(struct Message *msg)
+{
+ msg->done = 0;
+ msg->error = 0;
+ MC_SendPaket(msg);
+}
+
+/**
+ * Reads data from Radio buffer
+ */
+void recieveData(void)
+{
+ MsgRcv.done = 0;
+ MsgRcv.error = 0;
+
+ MC_RecievePaket(&MsgRcv);
+}
+/**
+ * At first it inicializes serial and SPI line + other pins + ISR (RXTXEN, IRQ....)
+ * then it inicialzes Radio and reads radio ID. Whan everything is sucessfull
+ * runs the serial command processor.
+ *
+ */
+
+int main (void) {
+
+ volatile uint32_t test =0;
+
+ // init serial line
+ init_uart();
+
+ // init SPI line, ISR and oter pins
+ send_rs_str("SPI init.\n");
+ spi_Init(5);
+
+ // reset and inicialize radio
+ send_rs_str("\nMC reset\n");
+ if (MC_Reset()==1)
+ {
+ send_rs_str("FAIL\n");
+ while(1);
+ }
+
+ // Read and test radio ID
+ send_rs_str("Who am i:\n");
+ test = MC_WhoAmI();
+ if((test == 0x5000) | (test == 0x5400))
+ {
+ send_rs_str("MC13192 Detected\n");
+ }
+ else if ((test == 0x6000) | (test == 0x6400))
+ send_rs_str("MC13202 Detected\n");
+ else
+ {
+ send_rs_str("ID FAIL: ");
+ send_rs_int(test);
+ while(1);
+ }
+
+
+ MC_SetPa(0xFF); // nastavi vysilaci vykon
+ MC_SetChannel(ZB_CH802_21); // nastavi kanal
+
+
+
+ int command = 0;
+ int myvar = 0;
+ int j = 0;
+ send_rs_str("Entering command processor loop\n");
+
+ while(1)
+ {
+ send_rs_str("-----------------------------------\n");
+ send_rs_str("1 Send message\n");
+ send_rs_str("2 Recieve message\n");
+ send_rs_str("3 Get IRQ pin\n");
+ send_rs_str("4 enable ISR\n");
+ send_rs_str("5 Read IRQ\n");
+ send_rs_str("6 Set channel\n");
+ send_rs_str("7 Energy detect\n");
+ send_rs_str("8 Set clock output\n");
+ send_rs_str("-----------------------------------\n");
+
+ command = uart_get_char();
+ uart_send_char(command);
+ uart_send_char('\n');
+
+ switch(command){
+ case '1':
+ send_rs_str("Sending message\n");
+ MsgSnd.len = 14;
+ MsgSnd.data[0] = 0x88;
+ MsgSnd.data[1] = 0x41;
+ MsgSnd.data[2] = 0x22;
+ MsgSnd.data[3] = 0x88;
+ MsgSnd.data[4] = 0xFF;
+ MsgSnd.data[5] = 0x00;
+ MsgSnd.data[6] = 0x01;
+ MsgSnd.data[7] = 0xFF;
+ MsgSnd.data[8] = 0x06;
+ MsgSnd.data[9] = 0x00;
+ MsgSnd.data[10] = 0x01;
+ MsgSnd.data[11] = 0x00;
+ MsgSnd.data[12] = 0x89;
+ MsgSnd.data[13] = 0x00;
+ sendData(&MsgSnd);
+ break;
+
+ case '5':
+ disable_IRQ_pin();
+ send_rs_str("IRQ register is: ");
+ myvar = spi_Read(IRQ_STATUS); // acknowledge power-on IRQ
+ send_rs_int(myvar);
+ enable_IRQ_pin();
+ break;
+
+ case '3':
+ send_rs_str("IRQ pin is: ");
+ if((IO0PIN & (1<<IRQ)) == (1<<IRQ))
+ send_rs_str("true\n");
+ else
+ send_rs_str("false\n");
+ break;
+
+ case '4': send_rs_str("Enable ISR: OK\n");
+ enable_IRQ_pin();
+ break;
+
+ case '2': send_rs_str("Recieving:\n");
+ recieveData();
+ myvar = 0;
+ while(myvar<10)
+ {
+ if((MsgRcv.done == 1))
+ {
+ send_rs_str("Recieved Data:\n");
+ send_rs_str("Msg.len: ");
+ send_rs_int(MsgRcv.len);
+ send_rs_str("\nMsg.data: \n");
+ for (j = 0; j < MsgRcv.len; j++)
+ {
+ send_rs_int(MsgRcv.data[j]);
+ send_rs_str("\n");
+ }
+
+ break;
+ }
+ else{
+ ++myvar;
+ dummy_wait();
+ }
+ }
+
+ if(myvar == 10)
+ send_rs_str("Timed out\n");
+ else
+ send_rs_str("Reading done!\n");
+ break;
+
+ case '6':
+ send_rs_str("Select channel (11~26)\n");
+ j = uart_get_char();
+ uart_send_char(j);
+
+ if(!((j == '1')|(j=='2'))){
+ send_rs_str("Bad value\n");
+ break;
+ }
+
+ myvar = (j - '0')* 10;
+
+ j = uart_get_char();
+ uart_send_char(j);
+ if(!((j >= '0')&(j<='9'))){
+ send_rs_str("Bad value\n");
+ break;
+ }
+ myvar += (j - '0');
+ myvar -= 10;
+ MC_SetChannel(myvar);
+ break;
+
+ case '7':
+ send_rs_str("Energy detect: ");
+ send_rs_int(MC_ED());
+ break;
+
+ case '8':
+ send_rs_str("Enable CLKO? (y/n) ");
+ j = uart_get_char();
+ uart_send_char(j);
+ if( j == 'n')
+ {
+ send_rs_str("CLKO - Switching OFF");
+ MC_SetClko(CLKO_CTL_CLKO_16Km, CLKO_CTL_CLKO_OFFm);
+ break;
+ }
+ else if( j != 'y')
+ {
+ send_rs_str("\nInvalid command\n");
+ break;
+ }
+
+
+ send_rs_str("Select clock\n");
+ send_rs_str("1 16.393kHz\n");
+ send_rs_str("2 32.786kHz\n");
+ send_rs_str("3 62.5kHz\n");
+ send_rs_str("4 1Mhz\n");
+ send_rs_str("5 2Mhz\n");
+ send_rs_str("6 4Mhz\n");
+ send_rs_str("7 8Mhz\n");
+ send_rs_str("8 16Mhz\n");
+
+ j = uart_get_char();
+ uart_send_char(j);
+
+ if(('0' < j) & (j < '9'))
+ {
+ switch(j){
+ case '1':
+ MC_SetClko(CLKO_CTL_CLKO_16Km, CLKO_CTL_CLKO_ONm);
+ break;
+ case '2':
+ MC_SetClko(CLKO_CTL_CLKO_32Km, CLKO_CTL_CLKO_ONm);
+ break;
+ case '3':
+ MC_SetClko(CLKO_CTL_CLKO_62Km, CLKO_CTL_CLKO_ONm);
+ break;
+ case '4':
+ MC_SetClko(CLKO_CTL_CLKO_1Mm, CLKO_CTL_CLKO_ONm);
+ break;
+ case '5':
+ MC_SetClko(CLKO_CTL_CLKO_2Mm, CLKO_CTL_CLKO_ONm);
+ break;
+ case '6':
+ MC_SetClko(CLKO_CTL_CLKO_4Mm, CLKO_CTL_CLKO_ONm);
+ break;
+ case '7':
+ MC_SetClko(CLKO_CTL_CLKO_8Mm, CLKO_CTL_CLKO_ONm);
+ break;
+ case '8':
+ MC_SetClko(CLKO_CTL_CLKO_16Mm, CLKO_CTL_CLKO_ONm);
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+
+ send_rs_str("Invalid command\n");
+ }
+ break;
+
+
+ default:
+ send_rs_str("Bad command!\n");
+ break;
+
+ }
+
+ dummy_wait();
+
+ // test if sessage is sent
+ if ((MsgSnd.done == 1))
+ {
+ send_rs_str("Message sent!!!!!!!!!!!!!!\n");
+ MsgSnd.done = 0;
+ // add same handle code her
+ }
+
+ // test if some packet is recieved
+ if ((MsgRcv.done == 1))
+ {
+ // add same handle code here
+ }
+
+
+
+ send_rs_str("\nHit key to continue ...");
+ uart_get_char();
+ send_rs_str("\n\n\n\n\n\n\n\n\n\n");
+ }
+
+}
+
+
+
--- /dev/null
+<?xml version = '1.0'?>
+<kdevelop>
+ <general>
+ <author>Bc. Jiri Kubias</author>
+ <email>Jiri.kubias@gmail.com</email>
+ <version>1</version>
+ <projectmanagement>KDevCustomProject</projectmanagement>
+ <primarylanguage>C</primarylanguage>
+ <ignoreparts/>
+ <projectname>minibee</projectname>
+ <projectdirectory>.</projectdirectory>
+ <absoluteprojectpath>false</absoluteprojectpath>
+ <description/>
+ <defaultencoding/>
+ <versioncontrol/>
+ </general>
+ <kdevcustomproject>
+ <run>
+ <directoryradio>executable</directoryradio>
+ <mainprogram>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee</mainprogram>
+ <programargs/>
+ <globaldebugarguments>make load-flash</globaldebugarguments>
+ <globalcwd>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee</globalcwd>
+ <useglobalprogram>false</useglobalprogram>
+ <terminal>false</terminal>
+ <autocompile>false</autocompile>
+ <autoinstall>false</autoinstall>
+ <autokdesu>false</autokdesu>
+ <envvars/>
+ </run>
+ <filetypes>
+ <filetype>*.java</filetype>
+ <filetype>*.h</filetype>
+ <filetype>*.H</filetype>
+ <filetype>*.hh</filetype>
+ <filetype>*.hxx</filetype>
+ <filetype>*.hpp</filetype>
+ <filetype>*.c</filetype>
+ <filetype>*.C</filetype>
+ <filetype>*.cc</filetype>
+ <filetype>*.cpp</filetype>
+ <filetype>*.c++</filetype>
+ <filetype>*.cxx</filetype>
+ <filetype>Makefile</filetype>
+ <filetype>CMakeLists.txt</filetype>
+ </filetypes>
+ <blacklist>
+ <path>spi.c</path>
+ <path>spi.h</path>
+ <path>zigbee.c</path>
+ <path>doc</path>
+ <path>doc/latex</path>
+ <path>doc/latex/Makefile</path>
+ </blacklist>
+ <build>
+ <buildtool>make</buildtool>
+ <builddir/>
+ </build>
+ <other>
+ <prio>0</prio>
+ <otherbin/>
+ <defaulttarget/>
+ <otheroptions/>
+ <selectedenvironment>default</selectedenvironment>
+ <environments>
+ <default/>
+ </environments>
+ </other>
+ <make>
+ <abortonerror>false</abortonerror>
+ <numberofjobs>0</numberofjobs>
+ <prio>0</prio>
+ <dontact>false</dontact>
+ <makebin>/usr/bin/make</makebin>
+ <defaulttarget/>
+ <makeoptions/>
+ <selectedenvironment>default</selectedenvironment>
+ <environments>
+ <default/>
+ </environments>
+ </make>
+ </kdevcustomproject>
+ <kdevdebugger>
+ <general>
+ <dbgshell/>
+ <gdbpath/>
+ <configGdbScript/>
+ <runShellScript/>
+ <runGdbScript/>
+ <breakonloadinglibs>true</breakonloadinglibs>
+ <separatetty>false</separatetty>
+ <floatingtoolbar>false</floatingtoolbar>
+ <raiseGDBOnStart>false</raiseGDBOnStart>
+ </general>
+ <display>
+ <staticmembers>false</staticmembers>
+ <demanglenames>true</demanglenames>
+ <outputradix>10</outputradix>
+ </display>
+ </kdevdebugger>
+ <kdevdoctreeview>
+ <ignoretocs>
+ <toc>ada</toc>
+ <toc>ada_bugs_gcc</toc>
+ <toc>bash</toc>
+ <toc>bash_bugs</toc>
+ <toc>clanlib</toc>
+ <toc>fortran_bugs_gcc</toc>
+ <toc>gnome1</toc>
+ <toc>gnustep</toc>
+ <toc>gtk</toc>
+ <toc>gtk_bugs</toc>
+ <toc>haskell</toc>
+ <toc>haskell_bugs_ghc</toc>
+ <toc>java_bugs_gcc</toc>
+ <toc>java_bugs_sun</toc>
+ <toc>kde2book</toc>
+ <toc>libstdc++</toc>
+ <toc>opengl</toc>
+ <toc>pascal_bugs_fp</toc>
+ <toc>php</toc>
+ <toc>php_bugs</toc>
+ <toc>perl</toc>
+ <toc>perl_bugs</toc>
+ <toc>python</toc>
+ <toc>python_bugs</toc>
+ <toc>qt-kdev3</toc>
+ <toc>ruby</toc>
+ <toc>ruby_bugs</toc>
+ <toc>sdl</toc>
+ <toc>stl</toc>
+ <toc>sw</toc>
+ <toc>w3c-dom-level2-html</toc>
+ <toc>w3c-svg</toc>
+ <toc>w3c-uaag10</toc>
+ <toc>wxwidgets_bugs</toc>
+ </ignoretocs>
+ <ignoreqt_xml>
+ <toc>Guide to the Qt Translation Tools</toc>
+ <toc>Qt Assistant Manual</toc>
+ <toc>Qt Designer Manual</toc>
+ <toc>Qt Reference Documentation</toc>
+ <toc>qmake User Guide</toc>
+ </ignoreqt_xml>
+ <ignoredoxygen>
+ <toc>KDE Libraries (Doxygen)</toc>
+ </ignoredoxygen>
+ </kdevdoctreeview>
+ <kdevfilecreate>
+ <filetypes/>
+ <useglobaltypes>
+ <type ext="c" />
+ <type ext="h" />
+ </useglobaltypes>
+ </kdevfilecreate>
+ <kdevcppsupport>
+ <qt>
+ <used>false</used>
+ <version>3</version>
+ <includestyle>3</includestyle>
+ <root>/usr/qt/3</root>
+ <designerintegration>EmbeddedKDevDesigner</designerintegration>
+ <qmake>/usr/qt/3/bin/qmake</qmake>
+ <designer>/usr/qt/3/bin/designer</designer>
+ <designerpluginpaths/>
+ </qt>
+ <codecompletion>
+ <automaticCodeCompletion>false</automaticCodeCompletion>
+ <automaticArgumentsHint>true</automaticArgumentsHint>
+ <automaticHeaderCompletion>true</automaticHeaderCompletion>
+ <codeCompletionDelay>250</codeCompletionDelay>
+ <argumentsHintDelay>400</argumentsHintDelay>
+ <headerCompletionDelay>250</headerCompletionDelay>
+ <showOnlyAccessibleItems>false</showOnlyAccessibleItems>
+ <completionBoxItemOrder>0</completionBoxItemOrder>
+ <howEvaluationContextMenu>true</howEvaluationContextMenu>
+ <showCommentWithArgumentHint>true</showCommentWithArgumentHint>
+ <statusBarTypeEvaluation>false</statusBarTypeEvaluation>
+ <namespaceAliases>std=_GLIBCXX_STD;__gnu_cxx=std</namespaceAliases>
+ <processPrimaryTypes>true</processPrimaryTypes>
+ <processFunctionArguments>false</processFunctionArguments>
+ <preProcessAllHeaders>false</preProcessAllHeaders>
+ <parseMissingHeadersExperimental>false</parseMissingHeadersExperimental>
+ <resolveIncludePathsUsingMakeExperimental>false</resolveIncludePathsUsingMakeExperimental>
+ <alwaysParseInBackground>true</alwaysParseInBackground>
+ <usePermanentCaching>true</usePermanentCaching>
+ <alwaysIncludeNamespaces>false</alwaysIncludeNamespaces>
+ <includePaths>.;</includePaths>
+ </codecompletion>
+ <creategettersetter>
+ <prefixGet/>
+ <prefixSet>set</prefixSet>
+ <prefixVariable>m_,_</prefixVariable>
+ <parameterName>theValue</parameterName>
+ <inlineGet>true</inlineGet>
+ <inlineSet>true</inlineSet>
+ </creategettersetter>
+ <splitheadersource>
+ <enabled>false</enabled>
+ <synchronize>true</synchronize>
+ <orientation>Vertical</orientation>
+ </splitheadersource>
+ <references/>
+ </kdevcppsupport>
+ <cppsupportpart>
+ <filetemplates>
+ <interfacesuffix>.h</interfacesuffix>
+ <implementationsuffix>.cpp</implementationsuffix>
+ </filetemplates>
+ </cppsupportpart>
+ <kdevdocumentation>
+ <projectdoc>
+ <docsystem/>
+ <docurl/>
+ <usermanualurl/>
+ </projectdoc>
+ </kdevdocumentation>
+ <kdevfileview>
+ <groups>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ <hidenonlocation>false</hidenonlocation>
+ </groups>
+ <tree>
+ <hidepatterns>*.o,*.lo,CVS</hidepatterns>
+ <hidenonprojectfiles>false</hidenonprojectfiles>
+ </tree>
+ </kdevfileview>
+ <ctagspart>
+ <customArguments/>
+ <customTagfilePath>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/tags</customTagfilePath>
+ <activeTagsFiles/>
+ </ctagspart>
+</kdevelop>
--- /dev/null
+# KDevelop Custom Project File List
+MC1319x.c
+MC1319x.h
+MC1319xdef.h
+Makefile
+main.c
+spi_LPC.c
+spi_avr.c
+uart_minibee.c
+uart_minibee.h
--- /dev/null
+<?xml version = '1.0' encoding = 'UTF-8'?>
+<!DOCTYPE KDevPrjSession>
+<KDevPrjSession>
+ <DocsAndViews NumberOfDocuments="9" >
+ <Doc0 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/main.c" >
+ <View0 Encoding="" line="25" Type="Source" />
+ </Doc0>
+ <Doc1 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/MC1319x.c" >
+ <View0 Encoding="" line="3" Type="Source" />
+ </Doc1>
+ <Doc2 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/uart_minibee.c" >
+ <View0 Encoding="" line="52" Type="Source" />
+ </Doc2>
+ <Doc3 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/uart_minibee.h" >
+ <View0 Encoding="" line="19" Type="Source" />
+ </Doc3>
+ <Doc4 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/MC1319x.h" >
+ <View0 Encoding="" Type="Source" />
+ </Doc4>
+ <Doc5 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/Makefile.omk" >
+ <View0 Encoding="" line="2" Type="Source" />
+ </Doc5>
+ <Doc6 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/spi.h" >
+ <View0 Encoding="" line="34" Type="Source" />
+ </Doc6>
+ <Doc7 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/spi_LPC.c" >
+ <View0 Encoding="" line="111" Type="Source" />
+ </Doc7>
+ <Doc8 NumberOfViews="1" URL="file:///home/data/robot/eurobot/sysless-lpc21xx/app/minibee/MC1319xdef.h" >
+ <View0 Encoding="" line="25" Type="Source" />
+ </Doc8>
+ </DocsAndViews>
+ <pluginList>
+ <kdevdebugger>
+ <breakpointList/>
+ <showInternalCommands value="0" />
+ </kdevdebugger>
+ <kdevastyle>
+ <Extensions ext="*.cpp *.h *.hpp,*.c *.h,*.cxx *.hxx,*.c++ *.h++,*.cc *.hh,*.C *.H,*.diff ,*.inl,*.java,*.moc,*.patch,*.tlh,*.xpm" />
+ <AStyle IndentPreprocessors="0" FillCount="4" PadParenthesesOut="1" IndentNamespaces="1" IndentLabels="1" Fill="Tabs" MaxStatement="40" Brackets="Break" MinConditional="-1" IndentBrackets="0" PadParenthesesUn="1" BlockBreak="0" KeepStatements="1" KeepBlocks="1" BlockIfElse="0" IndentSwitches="1" PadOperators="0" FStyle="ANSI" IndentCases="0" FillEmptyLines="0" BracketsCloseHeaders="0" BlockBreakAll="0" PadParenthesesIn="1" IndentClasses="1" IndentBlocks="0" FillForce="0" />
+ </kdevastyle>
+ <kdevbookmarks>
+ <bookmarks/>
+ </kdevbookmarks>
+ <kdevvalgrind>
+ <executable path="" params="" />
+ <valgrind path="" params="" />
+ <calltree path="" params="" />
+ <kcachegrind path="" />
+ </kdevvalgrind>
+ </pluginList>
+</KDevPrjSession>
--- /dev/null
+<?xml version='1.0' encoding='ISO-8859-1' standalone='yes' ?>
+<tagfile>
+ <compound kind="page">
+ <name>index</name>
+ <title>Zigbee radio MC13192 or MC13202</title>
+ <filename>index</filename>
+ <docanchor file="index">Introduction</docanchor>
+ </compound>
+ <compound kind="file">
+ <name>main.c</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>main_8c</filename>
+ <includes id="MC1319x_8h" name="MC1319x.h" local="yes" imported="no">MC1319x.h</includes>
+ <includes id="spi_8h" name="spi.h" local="yes" imported="no">spi.h</includes>
+ <includes id="uart__minibee_8h" name="uart_minibee.h" local="yes" imported="no">uart_minibee.h</includes>
+ <member kind="function">
+ <type>void</type>
+ <name>sendData</name>
+ <anchorfile>main_8c.html</anchorfile>
+ <anchor>ee6000bc24613b40e31fa4879578fb31</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>recieveData</name>
+ <anchorfile>main_8c.html</anchorfile>
+ <anchor>abecc12f56c4bb08f5b9beb4e655742b</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>int</type>
+ <name>main</name>
+ <anchorfile>main_8c.html</anchorfile>
+ <anchor>840291bc02cba5474a4cb46a9b9566fe</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="variable">
+ <type>struct Message</type>
+ <name>MsgSnd</name>
+ <anchorfile>main_8c.html</anchorfile>
+ <anchor>0ede4cc1258337c4c600518d2cc34a5e</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="variable">
+ <type>struct Message</type>
+ <name>MsgRcv</name>
+ <anchorfile>main_8c.html</anchorfile>
+ <anchor>5ead1224beac6631f8f3ca0f57fffc2c</anchor>
+ <arglist></arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>MC1319x.c</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>MC1319x_8c</filename>
+ <includes id="spi_8h" name="spi.h" local="yes" imported="no">spi.h</includes>
+ <includes id="MC1319x_8h" name="MC1319x.h" local="yes" imported="no">MC1319x.h</includes>
+ <includes id="MC1319xdef_8h" name="MC1319xdef.h" local="yes" imported="no">MC1319xdef.h</includes>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_RecievePaket</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>3fe506ae7cef806e892a0f736bf742e5</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>ext_isr</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>e42a33dfd728c53890e5ecb159f57c7f</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>dummy_wait</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>0ed86ef3cd64826822473dbbebe0d7a4</anchor>
+ <arglist>()</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>MC_Woodoo</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>b088fe90babf0fdf82ee824d04858094</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_Reset</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>099634cdb7405d32200e6556fca27b6c</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_ED</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>98f73499d8a965377ebb976c8a682d0c</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SendPaket</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>f4f8db7c7df1b7982e6b9a3bd217be0b</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_ReSendPaket</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>9263dab03a7f0a473ef7fada3e54c837</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint16_t</type>
+ <name>MC_WhoAmI</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>1a3a6d44b176d3b528f464ca74a4f7b3</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetChannel</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>bfbc2cbe1edf2878ccb09cc58edffd22</anchor>
+ <arglist>(uint8_t channel)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetClko</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>339d44adf7ab46d02a17a11208a25800</anchor>
+ <arglist>(uint16_t tick, uint8_t enable)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetPa</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>02257409afdb9f37b481989507fb5024</anchor>
+ <arglist>(uint8_t val)</arglist>
+ </member>
+ <member kind="variable">
+ <type>struct Message *</type>
+ <name>rcvBuf</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>eb0be220f20aa0923d8122c5c42c5971</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="variable">
+ <type>struct Message *</type>
+ <name>sndBuf</name>
+ <anchorfile>MC1319x_8c.html</anchorfile>
+ <anchor>0382b4fc5cd190a5c5e83670d1e4f2bb</anchor>
+ <arglist></arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>MC1319x.h</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>MC1319x_8h</filename>
+ <includes id="MC1319xdef_8h" name="MC1319xdef.h" local="yes" imported="no">MC1319xdef.h</includes>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_Reset</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>099634cdb7405d32200e6556fca27b6c</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint16_t</type>
+ <name>MC_WhoAmI</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>1a3a6d44b176d3b528f464ca74a4f7b3</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_ED</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>98f73499d8a965377ebb976c8a682d0c</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SendPaket</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>f4f8db7c7df1b7982e6b9a3bd217be0b</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_ReSend</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>cc2bfa1d89a61fc6370a82404947bec3</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_RecievePaket</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>3fe506ae7cef806e892a0f736bf742e5</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetClko</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>339d44adf7ab46d02a17a11208a25800</anchor>
+ <arglist>(uint16_t tick, uint8_t enable)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetPa</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>02257409afdb9f37b481989507fb5024</anchor>
+ <arglist>(uint8_t val)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>dummy_wait</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>0ed86ef3cd64826822473dbbebe0d7a4</anchor>
+ <arglist>()</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>ext_isr</name>
+ <anchorfile>MC1319x_8h.html</anchorfile>
+ <anchor>2d5b82f5c627f8123fc48a6ab2795743</anchor>
+ <arglist>(void) __attribute__((interrupt))</arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>MC1319xdef.h</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>MC1319xdef_8h</filename>
+ <class kind="struct">Message</class>
+ <member kind="define">
+ <type>#define</type>
+ <name>LPC</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3dee031a5e8ffec497faf7e5e5d42565</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>46fc8a17c0936cda0556a966cc2f62fb</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CE</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f332f65aca07c44deeda884c8f6c353c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ATTN</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>67481fc0148df36eb20f078ff1ce2d7c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RXTXEN</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>75eaa04e13035b83f95c3598bf0fef44</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RST</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>c5d957e4fd3dc11cd97a54cf9ca057a4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>MOSI</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5d3f11f2fdf8a7e27b975291e0c2c8cc</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>MISO</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7334c540878c8c4d801fd75ed9fd8063</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>SCK</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2dd443a4430713d325ab86895a4a45eb</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLR</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>74bc9444cf3ef3289a07cea717e16764</anchor>
+ <arglist>(x)</arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>SET</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1e573d4c5b004a71c86c15800b65708f</anchor>
+ <arglist>(x)</arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RD</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>efaf886fe6a8977a1a887fb491a6e82c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>WR</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>c1efd35edf6555320eb2a4b0b2d9c3a7</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RESET</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b702106cf3b3e96750b6845ded4e0299</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RX_PKT_RAM</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5dbcafbeb02080d09e78e52bcadb1fb0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TX_PKT_RAM</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ef9d1f4f568dc8d568c508ace69cb0c4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TX_PKT_CTL</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ca3f7b52cd37cf4e19aaccb3705492ed</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TX_PKT_CTL_RAM2_SELm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5e21c8cf94564a8e982aafd43f2b51a0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TX_PKT_CTL_PKT_LENGHT</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4e6e1ca84ae3a3c72effbf7ba360fe72</anchor>
+ <arglist>(x)</arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CCA_THRESH</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>880d164cbc98171e082c9554ff99dd02</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>300b7e28a313b19099713ea04f09fdaa</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_ATTNm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2058a9037b76ad2aa0e58b56e21a5d3a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_RAM_ADDRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>fdb37cb7a5705480c01ed27837a4de2c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_ARB_BUSYm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>cd2c8c3ab879d459f020937d48ef8f0c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_STRM_DATAm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>04136886c78ee543a535469a04dc0024</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_PPL_LOCKm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b4cbcabfa5fc3a1cc629f850837e761e</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_ACOMAm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6bcf0982d5b7ed6a894ea67b57d67696</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_DOZEm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f3080a2c1781eab4959dfc4ba207966c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_TMR4m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f6c0584bbcfed769be34f75ff7298fca</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_TMR3m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7affba036c584bcc7443dbb3d395bbbe</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_TMR2m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3ccfe72ab064a6c1989c32d1e6e913cb</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_MASK_TMR1m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5f6abe73e9473ae483fae1e33cef9130</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>32782596b83917d3ac2000ee2114807f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_TX_STRMm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2b47fec88c7ae45d3e143c1204f8e205</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_RX_STRMm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>31405fd6c34f97776ce08e04b290e039</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCAm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e31a0f9699124efbeba1b03605861222</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_TX_SENTm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>135b40fc49c8928232368b0e2ab945cf</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_RX_RCVDm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a72b9d79fdf692d4745c46de3a8ac9e7</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_TMR_TRIG_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>19db7d302b1adaca235f4b23643761a8</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_TYPE1m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6a9ceab99f026a86acf0118f000a0ea5</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_TYPE0m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>43a0428a419cb65541b776157ce03181</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_CCAm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ad34e01523309e53b1bd2a39587b69bd</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_EDm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>def18f0318ff5e45578492b68c031bd1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_SEG1m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f07851303ac030fa45293517e87bfd51</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_SEG0m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>214e92f0776df62a191edfc135da40fd</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_IDLEm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1575fe96d0855965ede245beeb37def3</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_CCAEDm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>68c3ef1f27068d2137f4497f85d88a44</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_PMRXm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4cbc11d3d1be22405f6b4b1758f6b52d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_PMTXm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a9c7f23a2e1016d403b16eea7634ef69</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_A_CCA_XCVR_CLRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>0994c15a3bcf145696c112fa2446baa3</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e1d91669b06dc7d7ea30e41d9048c24a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_TMR_LOADm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>52638c2633f541320f2287e7a3d41bcf</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_MISO_HIZ_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6e3dc0539fb74080b152173dbf5249d4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_CLKO_DOZE_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>47efa6299949f8282564b6ddff8361de</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_TX_DONEm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2e92d84c42aa565f1c8a3a2aeb96b05e</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_RX_DONEm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7d578ade881dd6f42da81129c483768d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_USE_STM_MODEm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4e862c709c5744ff81cafe421cd39230</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_HIB_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>41b1e45b4f7834017facd0c0c271c3e1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_B_DOZE_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3abcad46bcaadf1f96857f10e8153c17</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>PA_ENABLE</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>03d8a3cfd38ec5b486574866d25e7160</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>PA_ENABLE_PA_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>11221505bac308b205cb5f44329089f0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>13c2a9e1f2b382c5a68735dfd1c67ff9</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C_GPIO_ALT_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4fb17fccc237e0aa44bc163885f41607</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C_CLKO_ENm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3ceb2e0ba9fa782849bf58ef7a42dbd8</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C_TMR_PRESCALE2m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>501c7e4655ba80c362f870355239a89d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C_TMR_PRESCALE1m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>0d1c78de1fe7d1f8c1bb3fe95ae4fc1a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CONTROL_C_TMR_PRESCALE0m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>dd87271c69ce838f76b39bcc28302637</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>48b3d5ea128025ef2bb93b69472e2e76</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_RATE2m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b6a90e47e9204a2cdb9a8c0792a342dd</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_RATE1m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>0b119f41dc0193c0f581f7b41a14faf4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_RATE0m</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b6727557837aeb16c4411bef5a05b286</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_16Mm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>21d5b7a3aa938c82af3ba51709bc939d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_8Mm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a064e808fcaf27bb504d651963a1387c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_4Mm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>794670cd1c019221c6407cfd8818d5a0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_2Mm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>af17045ee51561e7d132cf6d545dd579</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_1Mm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>479f24a20e83b23f6dc02f5356997d32</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_62Km</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>9c97032a5f2c63dc7a004832e00a2702</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_32Km</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5685e76f4f1b7594670f20d9e0a3f10b</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_16Km</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>d258c47d3822ab8e2280fefe8e8d670a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_ONm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ae16c3c3c02814f174b355f2370e8345</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_OFFm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>60d6f5ef48ff9a7c1e25dad819f443d5</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CLKO_CTL_CLKO_CLRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>81af51f369345a34d4d2c1fbf938b60c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>GPIO_DIR</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>637a20b456c93e8248c861fa48510841</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>GPIO_DATA_OUT</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>c7f8340f1080d59df32708a2455100d1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ca2fcb248af07823b5886b348147ef77</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH1</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3d8cc422bd40604871cea8560533c349</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH2</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5828d649515d40f2efa45adf909b40f2</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH3</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2b9841efc56c22fef5b7761c07608c02</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH4</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1873bb919beb0f3b00adc47a88f7b42a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH5</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b6d2b844931e00597abf0791d1275935</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH6</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1e1aa4ddfe8c9e2f3f9f5895cdd751c5</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH7</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>10c4723cb836a3fe91038f4bf8a778ec</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH8</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>3dc6818a0c97ca323a66da1fa17aecef</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH9</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a8bf98d75a543e72b4e18b71b3c116bc</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH10</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>30f1a46a6bfd01ff7fdb761f08ccc00b</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH11</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6d53ae069f2db801a8aa5ca588154d5d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH12</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>be4a9b341b8ef487c2b52e6d453c8b2f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH13</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>bd14afc4fda0fe79399f872485d06e93</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH14</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>8d0551fd82943350b1823e73d9b75f10</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH15</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>26942e0ee9e2a2bb7cb0d65706272419</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_INT_DIV_CH16</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e626dced715d6d66b912f8d3ea2ae1e0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ee243f6fb1b3ce251b930cb54b23f79a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH1</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f5068b92d6689a67ed049a0cba5169f6</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH2</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>50d85c92c1990a95c5aefcee73934ce6</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH3</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e421d0e3ff2c2e4509fe3d9b5b88af92</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH4</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>02c947074cd499e03ee4c220f90d1eab</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH5</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6dd8f5ac6bcfbb4497d497445dcc0463</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH6</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5e39d950d283afb15348988954157381</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH7</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ebb64bc2122bdcbb14ced1f0a4582490</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH8</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>74c61e029b4de5ea1c2b5e1a153f7b76</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH9</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>019b4cdba93a4389755cda6734e65d50</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH10</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b3c3c89927d46541d426782763d2e735</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH11</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1f0a5c59a135d9727596cdfd05a846bf</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH12</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>72aee0649597e7a5fa3ca7eacda5ce99</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH13</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>9aa250768ccb29f252984121068d58df</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH14</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7cb73d3ef359fea2c4890107c8bbc2e7</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH15</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>15e2d2c3f13c0d95bff881a29c3ebea1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>LO1_NUM_CH16</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>384176be7d57b8074ca2f82b6c5b42af</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH1</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f0006c05c4805a128d72844be86117e0</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH2</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7bfda5ea1d061ec6f3bf37bc660bc617</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH3</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>1af5e53fb85e1e625e59fb8a09a489ae</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH4</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f26e5f28479ab253427f9b7d38b770b4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH5</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2999354d1bb49b8821db71d70e940138</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH6</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6de37bb572cb3af47d63bc56dafdc0ea</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH7</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2c6e23deb902bffa8c8691933dbdc60e</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH8</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e2ac642a24cbf28a52d1c6169a9f9659</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH9</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>50fb7c4a3d6ea560bc713d5e6c87f195</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH10</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>fb83f0555eeaf966f6d3f150e40e7c3f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH11</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4ad013cb3d33a46238f5039a5c9b279c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH12</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>23fe1fc2d00a43d5575814d431a65606</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH13</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>48f3d8c16f245f9679badc36726b4398</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH14</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b74d49877e12fdfa277f673cdfafc3c9</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH15</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4f9cd9fe7fca8245504d7f4c09037012</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH16</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7c20da487a0e4b366e20682602422d0b</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_11</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>add0e37c1b38c9e0955ef41d80b4a996</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_12</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f3b93763bd0614b8386ce6f9564f45a3</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_13</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>c3dd7741bff2172736a7e254edb691de</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_14</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>772d39dab2bb87d7cd6d01bd9663b462</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_15</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6d8d19096d0efb253ec8f962303d94e1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_16</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>5bcb9b9838b8987b7ae303b08ca99a21</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_17</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a42d94a638095e514bf313e8b2b61689</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_18</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>febe80e9aef311e427955b35711d159e</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_19</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>c984c397b20815cca07b749185d5159f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_20</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>8574fc3e1bbb87f8b5b8e9131cc34c10</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_21</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a49bc4ffb27ccbb9b0d1a679478bea42</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_22</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>9fdf04c0081acb570253d3b985486740</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_23</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b25eb6c47e4e0b25b3eb74edb0a29a09</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_24</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>ebd9e404761772dbf5cbb2104af05ffb</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_25</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>07cbd4348da4bb44921b3104dc113d16</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>ZB_CH802_26</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>878672cb6bbb2bba1107c15a6bb67148</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>PA_LVL</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b837bb078e0fd8faa4ee20cd6d2c3834</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP1_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>17e25931d2b07605940ea4d52e8db955</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP1_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b6341691cfe50e5635ecf6d10ef56c6f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP2_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e33c3e9cf354e579a97b396653b223ee</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP2_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a657c55c046dd6d05bd252de05531019</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP3_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f6965c3a07ed9d9bc6b3e538ae8d3eb1</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP3_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>574a0202652adc3814bab565246abc94</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP4_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>fd71dd54d591f2d3e3daafc17b5d1a34</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TMR_CMP4_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6b421528226949439ebd37b8192e68a4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TC2_PRIME</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>8e2f16b12eb58396b7c7935a74fd74cd</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>8cc14b27cb7ca6346eb2cb77f60a7162</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_PLL_LOCK_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>63045dd1094419c36eef6b9756207869</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_RAM_ADR_ERRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>10816fac2f92317f815c40009cc03865</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_ARB_BUSY_ERRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>a5b1710f897be1686888449ada16de3b</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_SRTM_DATA_ERRm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>9b34fa209fa94e518af14c75ff4bf332</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_ATTN_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>23a37ad91f39fd42da5dac455f33b425</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_DOZE_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>32115d02f58d9b2b80e47dea985ec2da</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_TMR1_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>7e554504f3365987340bfde581e318a4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_RX_RCVD_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>53b72aad750dafa7c91272a75b8eb1ca</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_TX_SENT_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>d08e0d0ffe644e8e1e9711a59ce57c98</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_CCA_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>2ccc3e0f3c733a465a897b02cf9a3979</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_TMR3_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>60da12a1f658c65956e0d053f976ca7d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_TMR4_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>01ca426dc8f08a51319499cab08265e6</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_TMR2_IRQm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>989b3258d9b8de2e632cb2aa65ed81c3</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_CCAm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>e49891dee228c6228fd3781b4b721109</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>IRQ_STATUS_CRC_VALIDm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>820c37f43676f86c52b55e69fb5447b4</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RST_IND</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>4a2e072154eaa212f2350194ae32599b</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RST_IND_RESET_INDm</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>8d2089e7cd64d0f70c3a4e3b36c20709</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CURRENT_TIME_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>94975bae26111e45a2af6937c4d04a91</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CURRENT_TIME_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>418cebf4c10e28e7f72b339ae3dff26f</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>GPIO_DATA_IN</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>f6602aa14449f25f424cf3cb17878b15</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>CHIP_ID</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>b0aa3e54cd2934b67b9882957456c391</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>RX_STATUS</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>731d30ee0b5f9f0471fa8e742ef1784c</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TIMESTAMP_A</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>6e4773e12809f5b733361dbccda1289a</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>TIMESTAMP_B</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>33dd86aa81fb87c913253e5f3db9dad3</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>BER_ENABLE</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>02d472151e2c7429cf0d3bcbb2d2807d</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="define">
+ <type>#define</type>
+ <name>BER_ENABLE_BER_EN</name>
+ <anchorfile>MC1319xdef_8h.html</anchorfile>
+ <anchor>69f2a6088bf5db62f8f994e598255e30</anchor>
+ <arglist></arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>spi.h</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>spi_8h</filename>
+ <includes id="MC1319xdef_8h" name="MC1319xdef.h" local="yes" imported="no">MC1319xdef.h</includes>
+ <member kind="define">
+ <type>#define</type>
+ <name>SPI_SPEED</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>0056b7fdd0f81fad9cd38e9fd389a4b6</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Init</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>cb06ef92bde513fe8c00bb87ece1e408</anchor>
+ <arglist>(int rx_isr_vect)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint16_t</type>
+ <name>spi_Read</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>02fffb26d66333b3c6428ff7a3bbc3fd</anchor>
+ <arglist>(uint8_t reg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>9431e598f3537a5369afb01627ad24a3</anchor>
+ <arglist>(uint8_t reg, uint16_t val)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_ReadModifiWrite</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>45835fb3ddc2778b07b2d63b72ccef11</anchor>
+ <arglist>(uint8_t reg, uint16_t ormask, uint16_t andmask)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write_Buf</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>a3d5ab927bca2d3c5deb2d49d3bd0be6</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Read_Buf</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>fa22a171b888b8cd8676d160d69d1d7e</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint8_t</type>
+ <name>MC_SetChannel</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>bfbc2cbe1edf2878ccb09cc58edffd22</anchor>
+ <arglist>(uint8_t channel)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>disable_IRQ_pin</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>6ad5b67346e28c06a14b412451c9c042</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>enable_IRQ_pin</name>
+ <anchorfile>spi_8h.html</anchorfile>
+ <anchor>df95af49d1fd2524c60090ba3499923a</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>spi_avr.c</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>spi__avr_8c</filename>
+ <includes id="MC1319xdef_8h" name="MC1319xdef.h" local="yes" imported="no">MC1319xdef.h</includes>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Init</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>3243eee798d6c71f2e826659953b5480</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint16_t</type>
+ <name>spi_Read</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>02fffb26d66333b3c6428ff7a3bbc3fd</anchor>
+ <arglist>(uint8_t reg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>9431e598f3537a5369afb01627ad24a3</anchor>
+ <arglist>(uint8_t reg, uint16_t val)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Read_Buf</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>fa22a171b888b8cd8676d160d69d1d7e</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write_Buf</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>a3d5ab927bca2d3c5deb2d49d3bd0be6</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_ReadModifiWrite</name>
+ <anchorfile>spi__avr_8c.html</anchorfile>
+ <anchor>45835fb3ddc2778b07b2d63b72ccef11</anchor>
+ <arglist>(uint8_t reg, uint16_t ormask, uint16_t andmask)</arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>spi_LPC.c</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>spi__LPC_8c</filename>
+ <includes id="MC1319x_8h" name="MC1319x.h" local="yes" imported="no">MC1319x.h</includes>
+ <includes id="spi_8h" name="spi.h" local="yes" imported="no">spi.h</includes>
+ <member kind="function">
+ <type>void</type>
+ <name>disable_IRQ_pin</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>6ad5b67346e28c06a14b412451c9c042</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>enable_IRQ_pin</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>df95af49d1fd2524c60090ba3499923a</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Init</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>cb06ef92bde513fe8c00bb87ece1e408</anchor>
+ <arglist>(int rx_isr_vect)</arglist>
+ </member>
+ <member kind="function">
+ <type>uint16_t</type>
+ <name>spi_Read</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>02fffb26d66333b3c6428ff7a3bbc3fd</anchor>
+ <arglist>(uint8_t reg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>9431e598f3537a5369afb01627ad24a3</anchor>
+ <arglist>(uint8_t reg, uint16_t val)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Read_Buf</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>fa22a171b888b8cd8676d160d69d1d7e</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_Write_Buf</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>a3d5ab927bca2d3c5deb2d49d3bd0be6</anchor>
+ <arglist>(struct Message *msg)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>spi_ReadModifiWrite</name>
+ <anchorfile>spi__LPC_8c.html</anchorfile>
+ <anchor>45835fb3ddc2778b07b2d63b72ccef11</anchor>
+ <arglist>(uint8_t reg, uint16_t ormask, uint16_t andmask)</arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>uart_minibee.c</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>uart__minibee_8c</filename>
+ <includes id="MC1319xdef_8h" name="MC1319xdef.h" local="yes" imported="no">MC1319xdef.h</includes>
+ <member kind="function">
+ <type>void</type>
+ <name>uart_send_char</name>
+ <anchorfile>uart__minibee_8c.html</anchorfile>
+ <anchor>7025f92d7c751a4ff7812be0f67c2de1</anchor>
+ <arglist>(char val)</arglist>
+ </member>
+ <member kind="function">
+ <type>char</type>
+ <name>uart_get_char</name>
+ <anchorfile>uart__minibee_8c.html</anchorfile>
+ <anchor>62268b25625c1c7803674cb13c5ec518</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>init_uart</name>
+ <anchorfile>uart__minibee_8c.html</anchorfile>
+ <anchor>c7b3df0fa68526d64c732d5f916e34b1</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>send_rs_str</name>
+ <anchorfile>uart__minibee_8c.html</anchorfile>
+ <anchor>f67eb7f2c24524147b3c3b82f534e138</anchor>
+ <arglist>(char data[])</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>send_rs_int</name>
+ <anchorfile>uart__minibee_8c.html</anchorfile>
+ <anchor>94258c25fb6ea7026fa3de55ce8d32d1</anchor>
+ <arglist>(int val)</arglist>
+ </member>
+ </compound>
+ <compound kind="file">
+ <name>uart_minibee.h</name>
+ <path>/home/data/robot/eurobot/sysless-lpc21xx/app/minibee/</path>
+ <filename>uart__minibee_8h</filename>
+ <member kind="function">
+ <type>void</type>
+ <name>uart_send_char</name>
+ <anchorfile>uart__minibee_8h.html</anchorfile>
+ <anchor>7025f92d7c751a4ff7812be0f67c2de1</anchor>
+ <arglist>(char val)</arglist>
+ </member>
+ <member kind="function">
+ <type>char</type>
+ <name>uart_get_char</name>
+ <anchorfile>uart__minibee_8h.html</anchorfile>
+ <anchor>62268b25625c1c7803674cb13c5ec518</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>init_uart</name>
+ <anchorfile>uart__minibee_8h.html</anchorfile>
+ <anchor>c7b3df0fa68526d64c732d5f916e34b1</anchor>
+ <arglist>(void)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>send_rs_int</name>
+ <anchorfile>uart__minibee_8h.html</anchorfile>
+ <anchor>94258c25fb6ea7026fa3de55ce8d32d1</anchor>
+ <arglist>(int val)</arglist>
+ </member>
+ <member kind="function">
+ <type>void</type>
+ <name>send_rs_str</name>
+ <anchorfile>uart__minibee_8h.html</anchorfile>
+ <anchor>f67eb7f2c24524147b3c3b82f534e138</anchor>
+ <arglist>(char data[])</arglist>
+ </member>
+ </compound>
+ <compound kind="struct">
+ <name>Message</name>
+ <filename>structMessage.html</filename>
+ <member kind="variable">
+ <type>uint8_t</type>
+ <name>done</name>
+ <anchorfile>structMessage.html</anchorfile>
+ <anchor>000a1958e29d9c3ef65e53c143be1884</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="variable">
+ <type>uint8_t</type>
+ <name>error</name>
+ <anchorfile>structMessage.html</anchorfile>
+ <anchor>58cdbd3bb182ccba3f374eeec2e87f36</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="variable">
+ <type>uint8_t</type>
+ <name>len</name>
+ <anchorfile>structMessage.html</anchorfile>
+ <anchor>0e2f37b0ed471c18c4d1a71a23981c23</anchor>
+ <arglist></arglist>
+ </member>
+ <member kind="variable">
+ <type>uint8_t</type>
+ <name>data</name>
+ <anchorfile>structMessage.html</anchorfile>
+ <anchor>dc2ecd460d7b67a67e55993c13f89a22</anchor>
+ <arglist>[25]</arglist>
+ </member>
+ </compound>
+</tagfile>
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+
+
+/**
+ * @file spi_LPC.c
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief SPI, IRQ and pin inicialization function prototypes
+ * A new platform must support this functions.
+ *
+ */
+
+
+#ifndef SPI_LPC_H
+#define SPI_LPC_H
+
+#include "MC1319xdef.h"
+
+#define SPI_SPEED 200 ///< SPI frequency in Hz
+
+void spi_Init(int rx_isr_vect); // inits SPI and hold MC radio in reset state
+uint16_t spi_Read (uint8_t reg); // reads 16 bites from given register
+void spi_Write (uint8_t reg, uint16_t val); // writes 16 bites from given register
+void spi_ReadModifiWrite (uint8_t reg, uint16_t ormask, uint16_t andmask); // reads_modify-writes 16 bites from given register
+void spi_Write_Buf (struct Message *msg); // fill MC transimit buffer
+void spi_Read_Buf (struct Message *msg);
+uint8_t MC_SetChannel(uint8_t channel);
+void disable_IRQ_pin(void);
+void enable_IRQ_pin(void);
+
+#endif
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+/**
+ * @file spi_LPC.c
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief SPI, IRQ and pin inicialization, platform dependent!
+ * Contains support functions for SPI communiacations
+ *
+ */
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <types.h>
+#include "MC1319x.h"
+#include <system_def.h>
+#include "spi.h"
+
+
+/**
+ * Disabling interupt from radio IRQ pin
+ */
+void disable_IRQ_pin(void)
+{
+ VICIntEnClr |= 1<<VIC_EINT3;
+}
+
+/**
+ * Enabling interupt from radio IRQ pin
+ */
+void enable_IRQ_pin(void)
+{
+ VICIntEnable |= 1<<VIC_EINT3;
+}
+
+
+/**
+ * Inits SPI channel to speed given in SPI_SPEED.
+ * Also preset other pins (ATTN,IRQ, TXRXEN, ATTN).
+ * Initiates ISR for IRQ PIn, but it is not enabled.
+ */
+void spi_Init(int rx_isr_vect) // inits SPI and hold MC radio in reset state
+{
+
+ // sets pins for communication
+
+ SET_PIN(PINSEL0, RST, PINSEL_0); // RST as GPIO
+ SET_PIN(PINSEL0, ATTN, PINSEL_0); // ATTN as GPIO
+ SET_PIN(PINSEL0, SCK, PINSEL_1); // SCK as SPI SCK
+ SET_PIN(PINSEL0, MISO, PINSEL_1); // MISO as SPI MISO
+ SET_PIN(PINSEL0, MOSI, PINSEL_1); // MOSI as SPI MOSI
+ SET_PIN(PINSEL0, CE, PINSEL_0); // CE as GPIO
+ SET_PIN(PINSEL0, RXTXEN, PINSEL_0); // RXTXEN as GPIO
+ SET_PIN(PINSEL0, IRQ, PINSEL_3); // IRQ as EINT3
+
+ // setting SPI port
+ // sets MOSI and CLK as output
+
+ S0SPCR = SPCR_MSTR_m ; // Set SPI as Master , CPOl = CPHA =0
+
+ int pom = CPU_APB_HZ / SPI_SPEED ; // Hz;
+ if (pom%2) ++pom ; // align to even number
+ S0SPCCR = pom; // set speed
+
+
+ IO0DIR |= (1<<ATTN)|(1<<RXTXEN)|(1<<RST)| (1<<CE); // sete control bits to output
+
+
+ EXTMODE |= EXTMODE_EXTMODE3_m; // Sets EINT3 to falling edge senstive ***
+ EXTINT = EXTINT_EINT3_m; // clear interrupt
+
+
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (unsigned long)ext_isr; // Nastaveni adresy vektotu preruseni
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = VIC_EINT3 | VIC_ENABLE; // vyber EXTINT3 pro preruseni
+
+}
+
+
+/**
+ * Reads one register in radio
+ * @param reg register to read
+ *
+ * @return value in rgister
+ */
+uint16_t spi_Read (uint8_t reg)
+{
+ uint16_t data =0;
+
+ reg &= 0x3F; // protection before too high value
+
+ CLR(CE);
+
+ S0SPDR = reg | RD;// zapis prvniho byte
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ S0SPDR = 0; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ data = (S0SPDR << 8);
+
+ S0SPDR = 0; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ data |= S0SPDR;
+
+ SET(CE);
+ return data;
+}
+
+
+/**
+ * Write value to one register in radio
+ * @param reg register to write
+ * @param val value to write
+ */
+void spi_Write (uint8_t reg, uint16_t val) // writes 16 bites from given register
+{
+ reg &= 0x3F; // protection before too high value
+
+ CLR(CE);
+
+ S0SPDR = reg | WR;// zapis prvniho byte
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ S0SPDR = (val>>8) & 0xFF; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ S0SPDR = val & 0xFF; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ SET(CE);
+}
+
+
+
+/**
+ * Read recieved data to Message structure
+ *
+ * @param *msg pointer to Messge structure
+ */
+void spi_Read_Buf (struct Message *msg) // write message to MC radio message buffer
+{
+
+ uint8_t i =0;
+ uint8_t dummy =0;
+
+
+ CLR(CE);
+
+ S0SPDR = RX_PKT_RAM | RD; // init write
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+
+
+ S0SPDR = 0x00; // dummy read
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ S0SPDR = 0x00; // dummy read
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ for( i = 0; i < (msg->len - 2); i++)
+ {
+
+ S0SPDR = 0; // cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ dummy = S0SPDR;
+
+ if ((i % 2) == 0) msg->data[i + 1] = dummy;
+ else msg->data[i - 1] = dummy;
+ }
+
+ if((msg->len % 2) ==1)
+ {
+ S0SPDR = 0x00; // dummy read
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ }
+
+ SET(CE);
+}
+
+
+/**
+ * Write messgage to internal radio buffer
+ * @param *msg pointer to Message structure
+ */
+void spi_Write_Buf (struct Message *msg) // write message to MC radio message buffer
+{
+ uint8_t i =0;
+
+ CLR(CE);
+
+ S0SPDR = TX_PKT_RAM | WR; // init write
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+
+ for( i = 0; i < msg->len; i++)
+ {
+ S0SPDR = msg->data[i]; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ }
+
+
+ if((msg->len % 2) ==1)
+ {
+ S0SPDR = 0x00; // dummy write
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ }
+
+ SET(CE);
+}
+
+
+
+
+/**
+ * Read-modify write function for modifiing registers in radio
+ * @param reg register to modify
+ * @param ormask OR mask
+ * @param andmask AND mask
+ */
+void spi_ReadModifiWrite (uint8_t reg, uint16_t ormask, uint16_t andmask) // writes 16 bites from given register
+{
+ uint16_t data =0;
+
+ reg &= 0x3F; // protection before too high value
+
+ CLR(CE);
+
+ S0SPDR = reg | RD;// zapis prvniho byte
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ S0SPDR = 0; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ data = (S0SPDR << 8);
+
+ S0SPDR = 0; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+ data |= S0SPDR;
+
+ SET(CE);
+
+ data &= andmask;
+ data |= ormask;
+
+ CLR(CE);
+
+ S0SPDR = reg | WR;// zapis prvniho byte
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ S0SPDR = (data>>8) & 0xFF; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+
+ S0SPDR = data & 0xFF; // zapis druhyho byte a cteni
+ while((S0SPSR & SPSR_SPIF_m) != SPSR_SPIF_m);
+
+ SET(CE);
+}
--- /dev/null
+//\r
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008\r
+//\r
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering\r
+// License: GNU GPL v.2\r
+//\r
+\r
+/**\r
+ * @file spi_avr.c\r
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008\r
+ * \r
+ * @brief SPI, IRQ and pin inicialization, platform dependent!\r
+ * Contains support functions for SPI communiacations. \r
+ * This portage is not fully ported, some functions are missing.\r
+ * This part is no longer supprted.\r
+ * \r
+ */\r
+\r
+\r
+\r
+#include "MC1319xdef.h"\r
+\r
+\r
+void spi_Init(void) // inits SPI and hold MC radio in reset state\r
+{\r
+ // setting SPI port\r
+ PORTB |= 0xFF; // enables pullups on PORT B\r
+ DDRB = (1<<DD_MOSI)|(1<<DD_SCK); // sets MOSI and CLK as output\r
+ SPCR = (1<<SPR0) | (1<<SPR1) | (1<<MSTR) | (1<<SPE); // enable SPI, set \r
+ //Master mode,clock: fosc/4 , CPOl = CPHA =0\r
+\r
+ // setting PD port\r
+ PORTD = (1<<IRQ) | (1<<CE) | (1<<ATTN); // enables pullups on IRQ and sets CE to HI (continue in nezt row)\r
+ DDRD = (1<<ATTN)|(1<<RXTXEN)|(1<<RST)| (1<<CE); // sete control bits to output \r
+\r
+}\r
+\r
+uint16_t spi_Read (uint8_t reg)\r
+{\r
+ uint16_t data =0;\r
+\r
+ reg &= 0x3F; // protection before too high value\r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = reg | RD;// zapis prvniho byte \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+ SPDR = 0; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ data = (SPDR << 8);\r
+ \r
+ \r
+ SPDR = 0; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ data |= SPDR;\r
+ \r
+ SET(CE);\r
+\r
+ return data;\r
+}\r
+\r
+\r
+\r
+void spi_Write (uint8_t reg, uint16_t val) // writes 16 bites from given register\r
+{\r
+ \r
+ \r
+\r
+ reg &= 0x3F; // protection before too high value\r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = reg | WR;// zapis prvniho byte \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+ SPDR = (val>>8) & 0xFF; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ \r
+ \r
+ \r
+ SPDR = val & 0xFF; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ \r
+ \r
+ SET(CE);\r
+}\r
+\r
+\r
+\r
+void spi_Read_Buf (struct Message *msg) // write message to MC radio message buffer\r
+{\r
+ \r
+ uint8_t i =0;\r
+ uint8_t dummy =0;\r
+ \r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = RX_PKT_RAM | RD; // init write \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+\r
+ SPDR = 0x00; // dummy read\r
+ while((SPSR & 0x80) != 0x80);\r
+ SPDR = 0x00; // dummy read\r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+ for( i = 0; i < (msg->len - 2); i++)\r
+ {\r
+\r
+ SPDR = 0; // cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+ dummy = SPDR;\r
+\r
+ if ((i % 2) == 0) msg->data[i + 1] = dummy;\r
+ else msg->data[i - 1] = dummy;\r
+\r
+\r
+ }\r
+ \r
+ \r
+ if((msg->len % 2) ==1) \r
+ {\r
+ \r
+ SPDR = 0x00; // dummy read\r
+ while((SPSR & 0x80) != 0x80);\r
+ }\r
+ \r
+ SET(CE);\r
+}\r
+\r
+\r
+void spi_Write_Buf (struct Message *msg) // write message to MC radio message buffer\r
+{\r
+ \r
+ uint8_t i =0;\r
+ \r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = TX_PKT_RAM | WR; // init write \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+ for( i = 0; i < msg->len; i++)\r
+ {\r
+\r
+ SPDR = msg->data[i]; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ }\r
+ \r
+ \r
+ if((msg->len % 2) ==1) \r
+ {\r
+ \r
+ SPDR = 0x00; // dummy write\r
+ while((SPSR & 0x80) != 0x80);\r
+ }\r
+ \r
+ SET(CE);\r
+}\r
+\r
+void spi_ReadModifiWrite (uint8_t reg, uint16_t ormask, uint16_t andmask) // writes 16 bites from given register\r
+{ \r
+\r
+ uint16_t data =0;\r
+\r
+ reg &= 0x3F; // protection before too high value\r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = reg | RD;// zapis prvniho byte \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+ SPDR = 0; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ data = (SPDR << 8);\r
+ \r
+ \r
+ SPDR = 0; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ data |= SPDR;\r
+ \r
+ SET(CE);\r
+\r
+ data &= andmask;\r
+ data |= ormask;\r
+\r
+ CLR(CE);\r
+ \r
+ SPDR = reg | WR;// zapis prvniho byte \r
+ while((SPSR & 0x80) != 0x80);\r
+\r
+\r
+ SPDR = (data>>8) & 0xFF; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ \r
+ \r
+ SPDR = data & 0xFF; // zapis druhyho byte a cteni\r
+ while((SPSR & 0x80) != 0x80);\r
+ \r
+ SET(CE);\r
+}\r
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+
+/**
+ * @file uart_minibee.c
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief Uart library - particulary platform dependent
+ *
+ */
+
+
+#include "MC1319xdef.h"
+
+#ifdef LPC
+ #include <uart.h>
+#endif
+
+
+/**
+ * Send one char to uart.
+ */
+void uart_send_char(char val)
+{
+
+#ifdef LPC
+ uart0SendCh(val);
+#endif
+}
+
+/**
+ * Read one char from uart.
+ */
+char uart_get_char(void)
+{
+
+#ifdef LPC
+ return uart0GetCh();
+#endif
+}
+
+/**
+ * Initialize UART - platform dependent
+ */
+void init_uart(void)
+{
+#ifdef LPC
+ init_uart0((int)9600, UART_BITS_8, UART_STOP_BIT_1, UART_PARIT_OFF, 0 );
+#endif
+}
+
+
+/**
+ * Send string to serial output in ASCII code. .
+ * @param data[] string to print
+ */
+void send_rs_str(char data[])
+{
+
+ int i = 0;
+ int j = 0;
+
+ for (j = 0; j < 255; j++)
+ {
+ if(data[j] == 0) break;
+ }
+
+ for (i= 0 ; i < j; i++)
+ {
+ uart_send_char(data[i]);
+ }
+}
+
+/**
+ * Send int value to serial output in ASCII code. Removes unused zeros.
+ * @param val value to print
+ */
+void send_rs_int(int val)
+{
+ char dat[8];
+ int i;
+ int pom = 0;
+
+ for(i = 0; i < 8; i++)
+ {
+ dat[i] = (val & 0xF) + 0x30;
+ if(dat[i] > '9')
+ dat[i] += 7;
+ val >>= 4;
+ }
+
+ for(i = 0; i < 8; i++)
+ {
+ if((pom == 0) & (dat[7-i] == '0'))
+ {
+ if((i == 6) | (i == 7))
+ uart_send_char('0');
+ continue;
+ }
+ pom = 1;
+ uart_send_char(dat[7-i]);
+ }
+
+}
+
+
+
+
--- /dev/null
+//
+// Author: Bc. Jiri Kubias <Jiri.kubias@gmail.com>, (C) 2008
+//
+// Copyright: (c) DCE FEE CTU - Department of Control Engeneering
+// License: GNU GPL v.2
+//
+
+/**
+ * @file uart_minibee.h
+ * @author Bc. Jiri Kubias , DCE FEL CTU 2008
+ *
+ * @brief Uart library - function prototypes
+ *
+ */
+
+#ifndef UART_MINIBEE_H
+#define UART_MINIBEE_H
+
+void uart_send_char(char val);
+char uart_get_char(void);
+void init_uart(void);
+void send_rs_int(int val);
+void send_rs_str(char data[]);
+
+
+
+#endif
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+ifeq ($(BOARD),spejblarm)
+# Other boards do not have enough free ram
+
+bin_PROGRAMS = rama_dam
+rama_dam_SOURCES = rama_dam.c pwm.c
+rama_dam_LIBS = can uart_zen
+link_VARIANTS = mpram
+
+endif
--- /dev/null
+#include "pwm.h"
+
+int PWM_PINSEL[] = {
+ /*nothing*/ 1, /*PWM1*/ 1, 15, 3, 17, /*PWM5*/ 11, /*PWM6*/ 19
+};
+
+uint32_t *PWM_MR[] = {
+ (uint32_t*)&(PWMMR0),
+ (uint32_t*)&(PWMMR1),
+ (uint32_t*)&(PWMMR2),
+ (uint32_t*)&(PWMMR3),
+ (uint32_t*)&(PWMMR4),
+ (uint32_t*)&(PWMMR5),
+ (uint32_t*)&(PWMMR6)
+};
+
+void pwm_channel(int n, int double_edge) {
+ uint32_t bit;
+
+ PWMPCR |= (0x100 | (double_edge && n)) << n;
+ if (n == 5) {
+ PINSEL1 |= 0x00000400;
+ PINSEL1 &= 0xfffff7ff;
+ }
+ else {
+ bit = 1 << PWM_PINSEL[n];
+ PINSEL0 |= bit;
+ bit = ~(bit >> 1);
+ PINSEL0 &= bit;
+ }
+}
+
+void pwm_set(int n, uint32_t when) {
+ *PWM_MR[n] = when;
+ PWMLER |= 1 << n;
+}
+
+void pwm_set_double(int n, uint32_t from, uint32_t to) {
+ *PWM_MR[n-1] = from;
+ *PWM_MR[n] = to;
+ PWMLER |= 0x3 << (n-1);
+}
+
+void pwm_init(uint32_t prescale, uint32_t period) {
+ PWMPR = prescale - 1;
+ PWMMR0 = period - 1;
+ PWMLER |= 0x1;
+ PWMMCR |= 0x00000002;
+ PWMTCR &= ~0x2;
+ PWMTCR |= 0x9;
+}
+
--- /dev/null
+#include <lpc21xx.h>
+#include <types.h>
+
+extern int PWM_PINSEL[];
+extern uint32_t *PWM_MR[];
+
+void pwm_channel(int n, int double_edge);
+void pwm_set(int n, uint32_t when);
+void pwm_set_double(int n, uint32_t from, uint32_t to);
+void pwm_init(uint32_t prescale, uint32_t period);
--- /dev/null
+/********************************************************/
+/* Data Acqusition software for the DAM module */
+/* RAMA UAV control system */
+/* */
+/* ver. 5.3 release */
+/* */
+/* (c) 2006, 2007 Ondrej Spinka, DCE FEE CTU Prague */
+/* */
+/* no animals were harmed during development/testing */
+/* of this software product, except the author himself */
+/********************************************************/
+
+#include <cpu_def.h>
+#include <types.h>
+#include <lpc21xx.h>
+#include <string.h>
+#include <periph/can.h>
+#include <periph/uart_zen.h>
+#include "pwm.h"
+
+/*! @defgroup defines Constants Definitions
+* @{
+*/
+
+/*!\def TRUE
+* Formal definition of logical "TRUE" value.
+*/
+#define TRUE 1
+
+/*!\def WATCHDOG_INIT
+* Watchdog counter initialization/reset value.
+*/
+/* 0x0003D090 corresponds to 100ms reset timeout */
+#define WATCHDOG_INIT 0x0003D090
+
+/*! @defgroup MEMMAP_EXC Exception Mapping Definitions
+* @ingroup defines
+* These constants serve to set the exception mapping either to FLASH (0x01) or RAM (0x02).
+* @{
+*/
+#define MEMMAP_EXC_FLASH 0x01
+#define MEMMAP_EXC_RAM 0x02
+/*! @} */
+
+/*!\def STATUS_LED
+* Defines that status LEDs exist on the target board.
+*/
+#define STATUS_LED
+
+/*! @defgroup led_defines Status LEDs Definitions
+* @ingroup defines
+* These constants define the IO ports and specific bits to manipulate respective status LEDs.
+* @{
+*/
+#ifdef STATUS_LED
+
+#define LED_IMU_PINSEL PINSEL2
+#define LED_IMU_PINSEL_VAL 0xFFFFFFF3
+#define LED_IMU_IODIR IODIR1
+#define LED_IMU_IOSET IOSET1
+#define LED_IMU_IOCLR IOCLR1
+#define LED_IMU_IOBIT 0x00080000
+
+#define LED_GPS_PINSEL PINSEL1
+#define LED_GPS_PINSEL_VAL 0xFFFFCFFF
+#define LED_GPS_IODIR IODIR0
+#define LED_GPS_IOSET IOSET0
+#define LED_GPS_IOCLR IOCLR0
+#define LED_GPS_IOBIT 0x00400000
+
+#define LED_MSH_PINSEL PINSEL1
+#define LED_MSH_PINSEL_VAL 0xFFF3FFFF;
+#define LED_MSH_IODIR IODIR0
+#define LED_MSH_IOSET IOSET0
+#define LED_MSH_IOCLR IOCLR0
+#define LED_MSH_IOBIT 0x00800000
+
+#define LED_ERR_PINSEL PINSEL1
+#define LED_ERR_PINSEL_VAL 0xFFFCFFFF;
+#define LED_ERR_IODIR IODIR0
+#define LED_ERR_IOSET IOSET0
+#define LED_ERR_IOCLR IOCLR0
+#define LED_ERR_IOBIT 0x01000000
+
+#endif
+/*! @} */
+
+/*! @defgroup msh_degauss_defines Magnetic Sensor Hybrid Degauss Pin Definitions
+* @ingroup defines
+* These constants define the IO port and specific bit to drive the MSH degauss pin.
+* @{
+*/
+#define PAL_PINSEL PINSEL1
+#define PAL_PINSEL_VAL 0xFFFCFFFF
+#define PAL_IODIR IODIR0
+#define PAL_IOSET IOSET0
+#define PAL_IOCLR IOCLR0
+#define PAL_IOBIT 0x00200000
+/*! @} */
+
+/*! @defgroup error_tresholds Error Treshold Constants
+* @ingroup defines
+* These constants define the tresholds of number of errors to generate an CAN error message.
+* @{
+*/
+#define IMU_ERROR_TRESHOLD 1024
+#define GPS_ERROR_TRESHOLD_RUN 2048
+#define GPS_ERROR_TRESHOLD_INIT 30720
+/*! @} */
+
+/*! @defgroup error_codes Error Codes
+* @ingroup defines
+* Following constants define the error codes.
+* @{
+*/
+#define NO_ERR 0x00
+#define GENERAL_ERR 0x01
+#define PARITY_ERR 0x02
+#define RANGE_ERR 0x03
+#define FRAME_ERR 0x04
+#define FRAME_ERR_ETX 0x05
+/*! @} */
+
+/*! @defgroup can_id CAN Message IDs
+* @ingroup defines
+* The constants below define respective IDs for the CAN messages.
+* Standard 11-bit IDs are used.
+* @{
+*/
+#define RQ_CAN_ID 0x0014
+
+#define RESET_REQUEST_ID 0x006E
+
+#define FILTER_ROLL_A_ID 0x0070
+#define FILTER_ROLL_B_ID 0x0071
+#define FILTER_PITCH_A_ID 0x0072
+#define FILTER_PITCH_B_ID 0x0073
+#define FILTER_YAW_A_ID 0x0074
+#define FILTER_YAW_B_ID 0x0075
+#define FILTER_ACCEL_X_A_ID 0x0076
+#define FILTER_ACCEL_X_B_ID 0x0077
+#define FILTER_ACCEL_Y_A_ID 0x0078
+#define FILTER_ACCEL_Y_B_ID 0x0079
+#define FILTER_ACCEL_Z_A_ID 0x007A
+#define FILTER_ACCEL_Z_B_ID 0x007B
+#define CAL_SAMPLE_NUM_ID 0x0059
+
+#define IMU_ERR_CAN_ID 0x0002
+#define AR_CAN_ID_ROLL_FILTERED 0x0028
+#define AR_CAN_ID_PITCH_FILTERED 0x0029
+#define AR_CAN_ID_YAW_FILTERED 0x002A
+#define AR_CAN_ID_ROLL 0x00C4
+#define AR_CAN_ID_PITCH 0x01C4
+#define AR_CAN_ID_YAW 0x03C4
+#define AC_CAN_ID_X_FILTERED 0x0053
+#define AC_CAN_ID_Y_FILTERED 0x0054
+#define AC_CAN_ID_Z_FILTERED 0x0055
+#define AC_CAN_ID_X 0x0056
+#define AC_CAN_ID_Y 0x0057
+#define AC_CAN_ID_Z 0x0058
+
+#define GPS_ERR_CAN_ID 0x0004
+#define GPS_ID1 0x0400
+#define GPS_ID2 0x0200
+#define GPS_ID3 0x0180
+#define GPS_ID4 0x0100
+#define GPS_ID5 0x0300
+#define GPS_ID6 0x0500
+#define GPS_ID7 0x0700
+#define GPS_ID8 0x0080
+
+#define MSH_ID_X 0x0020
+#define MSH_ID_Y 0x0040
+#define MSH_ID_Z 0x0060
+/*! @} */
+
+/*! @defgroup timer_settings Timer Settings
+* @ingroup defines
+* The constants below define the timer settings (timer frequency and interrupt number).
+* @{
+*/
+/* 512 Hz */
+#define TIMER_PRESCALER 1
+#define TIMER_PERIOD 19531
+#define ISR_INT_VEC_TIMER 10
+/*! @} */
+
+/*! @defgroup can_settings CAN Settings
+* @ingroup defines
+* The constants below define the CAN settings (baud rate and interrupt number).
+* @{
+*/
+#define CAN_BTR 0x00250000
+#define ISR_INT_VEC_CAN 11
+/*! @} */
+
+/*! @defgroup imu_constants IMU Communication Constants
+* @ingroup defines
+* The constants below define important IMU communication constants,
+* such as message delimiter bytes and out-of-range bit mask.
+* @{
+*/
+#define IMU_MES_DELIMITER_1 0x78
+#define IMU_MES_DELIMITER_2 0x87
+#define IMU_RANGE_MASK 0x3F
+/*! @} */
+
+/*! @defgroup gps_constants GPS Communication Constants
+* @ingroup defines
+* The constants below define important GPS communication constants,
+* such as message header and delimiter bytes and length.
+* @{
+*/
+#define DLE_BYTE 0x10
+#define ETX_BYTE 0x03
+#define ID_POS 0x33
+#define GPS_DATA_LENGTH 0x40
+/*! @} */
+
+/*! @defgroup uart_settings UART Settings
+* @ingroup defines
+* The constants below define the UART settings, such as baud rates, interrupt numbers and buffer lengths.
+* @{
+*/
+#define BAUD_RATE0 38400
+
+/* a bit of dirty work - should be 9600, but 9530 better suits with respect to clock speed */
+#define BAUD_RATE1 9530
+
+#define ISR_INT_VEC_U0 12
+#define ISR_INT_VEC_U1 13
+
+#define BUFF_IMU_LEN 6
+#define BUFF_GPS_LEN 64
+/*! @} */
+
+/*! @defgroup angular_rates_conversion Angular Rates Conversion Constant
+* @ingroup defines
+* @{
+*/
+/*!\def ANGULAR_CONV_64
+* The constant below defines the angular rates conversion constant for 64Hz sampling rate.
+*/
+#define ANGULAR_CONV_64 0.000976563
+
+/*!\def GYRO_OFFSET_FILTERING_TRESHOLD
+* This constant defines the filter initialization treshold.
+*/
+#define GYRO_OFFSET_FILTERING_TRESHOLD 10
+/*! @} */
+
+/*! @defgroup accel_conversion Accelerations Conversion Constant
+* @ingroup defines
+* Accelerations conversion constants
+* @{
+*/
+/*!\def ACCEL_CONV_64
+* This constant is used to convert accelerations suppoted by the IMU from m/s2 into miligs for 64Hz sampling rate.
+*/
+/* ( 1/9.80665 ) * 64 */
+#define ACCEL_CONV_64 6.5261838
+/*! @} */
+
+/*! @defgroup msh_conversion Magnetic Field Intensity Constants
+* @ingroup defines
+* @{
+*/
+/*!\def MSH_CONV
+* AD value-to-mgauss conversion constant
+*/
+#define MSH_CONV 0.91
+
+/*!\def MSH_OFFSET
+* offset constant
+*/
+#define MSH_OFFSET 430
+
+/*!\def BUFF_MSH_LEN
+* Data buffer length
+*/
+#define BUFF_MSH_LEN 32
+/*! @} */
+
+/*! @defgroup filter_settings Filter Settings
+* @ingroup defines
+* The constants below define the polynomial filter coefficients for the roll, pitch and yaw angular rate filters.
+* @{
+*/
+#define MAX_FILTER_LEN 6
+
+#define FILTER_ROLL_A_NUM_FLAG 0x0001
+#define FILTER_ROLL_B_NUM_FLAG 0x0002
+#define FILTER_PITCH_A_NUM_FLAG 0x0004
+#define FILTER_PITCH_B_NUM_FLAG 0x0008
+#define FILTER_YAW_A_NUM_FLAG 0x0010
+#define FILTER_YAW_B_NUM_FLAG 0x0020
+#define FILTER_ACCEL_X_A_NUM_FLAG 0x0040
+#define FILTER_ACCEL_X_B_NUM_FLAG 0x0080
+#define FILTER_ACCEL_Y_A_NUM_FLAG 0x0100
+#define FILTER_ACCEL_Y_B_NUM_FLAG 0x0200
+#define FILTER_ACCEL_Z_A_NUM_FLAG 0x0400
+#define FILTER_ACCEL_Z_B_NUM_FLAG 0x0800
+
+#define FILTER_A_NUM 3
+#define FILTER_B_NUM 3
+
+#define FILTER_COEF_A_1 1.0
+#define FILTER_COEF_A_2 0.462938
+#define FILTER_COEF_A_3 0.2097154
+#define FILTER_COEF_B_1 0.4181633
+#define FILTER_COEF_B_2 0.836327
+#define FILTER_COEF_B_3 0.4181633
+/*! @} */
+/*! @} */
+
+uint8_t reset_req = 0; //!< reset request flag
+
+uint16_t imu_timeout_count = 0; //!< IMU timeout counter
+uint16_t gps_timeout_count = 0; //!< GPS timeout counter
+uint16_t gps_err_treshold = GPS_ERROR_TRESHOLD_INIT; //!< GPS error treshold value (when surpassed, error message is generated)
+uint8_t imu_err_state = 0; //!< IMU error status flag
+uint8_t gps_err_state = 0; //!< GPS error status flag
+
+uint8_t filter_roll_a_num = FILTER_A_NUM; //!< roll filter number of a coefficients
+uint8_t filter_roll_b_num = FILTER_B_NUM; //!< roll filter number of b coefficients
+uint8_t filter_pitch_a_num = FILTER_A_NUM; //!< pitch filter number of a coefficients
+uint8_t filter_pitch_b_num = FILTER_B_NUM; //!< pitch filter number of b coefficients
+uint8_t filter_yaw_a_num = FILTER_A_NUM; //!< yaw filter number of a coefficients
+uint8_t filter_yaw_b_num = FILTER_B_NUM; //!< yaw filter number of b coefficients
+uint8_t filter_accel_x_a_num = FILTER_A_NUM; //!< x-axis acceleration filter number of a coefficients
+uint8_t filter_accel_x_b_num = FILTER_B_NUM; //!< x-axis acceleration filter number of b coefficients
+uint8_t filter_accel_y_a_num = FILTER_A_NUM; //!< y-axis acceleration filter number of a coefficients
+uint8_t filter_accel_y_b_num = FILTER_B_NUM; //!< y-axis acceleration filter number of b coefficients
+uint8_t filter_accel_z_a_num = FILTER_A_NUM; //!< z-axis acceleration filter number of a coefficients
+uint8_t filter_accel_z_b_num = FILTER_B_NUM; //!< z-axis acceleration filter number of b coefficients
+
+uint8_t msh_meas_count = 0; //!< MSH sample counter
+uint8_t msh_degauss_count = 0; //!< MSH degauss (time) counter
+int32_t mg_meas_x[BUFF_MSH_LEN]; //!< x-axis magnetic field intensity sample buffer
+int32_t mg_meas_y[BUFF_MSH_LEN]; //!< y-axis magnetic field intensity sample buffer
+int32_t mg_meas_z[BUFF_MSH_LEN]; //!< z-axis magnetic field intensity sample buffer
+
+uint16_t cal_sample_num; //!< number of IMU calibration samples
+
+double a_roll[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_roll[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< roll filter coeffitients
+double a_pitch[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_pitch[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< pitch filter coeffitients
+double a_yaw[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_yaw[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< yaw filter coeffitients
+double a_accel_x[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_accel_x[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< x-axis acceleration filter coeffitients
+double a_accel_y[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_accel_y[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< y-axis acceleration filter coeffitients
+double a_accel_z[MAX_FILTER_LEN] = {FILTER_COEF_A_1, FILTER_COEF_A_2, FILTER_COEF_A_3, 0, 0, 0}, b_accel_z[MAX_FILTER_LEN] = {FILTER_COEF_B_1, FILTER_COEF_B_2, FILTER_COEF_B_3, 0, 0, 0}; //!< z-axis acceleration filter coeffitients
+
+can_msg_t imu_msg_err = {.id = IMU_ERR_CAN_ID}; //!< IMU CAN error message
+can_msg_t gps_msg_err = {.id = GPS_ERR_CAN_ID}; //!< GPS CAN error message
+
+/*! Timer 0 interrupt handler prototype. */
+void timer_irq_handler ( void ) __attribute__ ( ( interrupt ) );
+
+/*! Timer 0 initialization routine.
+* Takes three arguments:
+* \param prescale unsigned 32-bit int timer prescaler value
+* \param period unsigned 32-bit int timer period value (counter reset occurs on match)
+* \param irq_vect unsigned int timer interrupt number
+*/
+inline void timer_init ( uint32_t prescale, uint32_t period, unsigned irq_vect ) {
+ T0PR = prescale - 1; // set prescaler
+ T0MR1 = period - 1; // set period
+ T0MCR = 0x0003 << 3; // interrupt and counter reset on match1
+ T0EMR = 0x0001 << 6 | 0x2; // set MAT0.1 low on match and high now
+ T0CCR = 0x0000; // no capture
+ T0TCR |= 0x0001; // go!
+
+ ( (uint32_t*) &VICVectAddr0 )[irq_vect] = (uint32_t) timer_irq_handler; // set the interrupt vector
+ ( (uint32_t*) &VICVectCntl0 )[irq_vect] = 0x20 | 4;
+ VICIntEnable = 0x00000010; // enable the timer 0 interrupt
+}
+
+/*! AD convertor initialization function.
+* Takes one argument:
+* \param clk_div unsigned 32-bit int timer prescaler value. Resulting clock speed should be less then or equal to 4.5MHz
+*/
+inline void adc_init ( uint32_t clk_div ) {
+ ADCR = ( ( clk_div & 0x000000FF ) << 8 ) | 0x00200000; // set the clock prescaler and switch the AD convertor on
+}
+
+/*! Watchdog initialization function.
+* Takes one argument:
+* \param init_val unsigned 32-bit int timer initial value.
+*/
+inline void watchdog_init ( uint32_t init_val ) {
+ WDTC = init_val; // timer counter start value
+ WDMOD |= 0x03; // enable watchdog and reset capability
+ WDFEED = 0xAA;
+ WDFEED = 0x55; // feed sequence
+}
+
+/*! Watchdog reset function.
+* Takes no arguments.
+*/
+inline void watchdog_reset ( void ) {
+ WDFEED = 0xAA;
+ WDFEED = 0x55; // feed sequence
+}
+
+/*! Buttleworth filter algorithm.
+* Takes seven arguments:
+* \param sample double new sample
+* \param x_array double pointer to the filter denominator array
+* \param y_array double pointer to the filter nominator array
+* \param a_coef double pointer to the filter denominator coefficients array
+* \param b_coef double pointer to the filter nominator coefficients array
+* \param a_num unsigned 8-bit integer number of a coefficients
+* \param b_num unsigned 8-bit integer number of b coefficients
+*/
+void filter ( double sample, double *x_array, double *y_array, double *a_coef, double *b_coef, uint8_t a_num, uint8_t b_num ) {
+ uint8_t i;
+
+ for ( i = 0; i < ( b_num - 1 ); i++ ) x_array[i] = x_array[i + 1]; // input data buffer shifting
+ x_array[b_num - 1] = sample; // store new samle into the buffer
+
+ for ( i = 0; i < ( a_num - 1 ); i++ ) y_array[i] = y_array[i + 1]; // output data buffer shifting
+ y_array[a_num - 1] = 0; // store 0 at the end
+
+ for ( i = 0; i < b_num; i++ ) y_array[a_num - 1] += b_coef[i] * x_array[b_num - i - 1]; // input polynom computation
+
+ for ( i = 1; i < a_num; i++ ) y_array[a_num - 1] -= a_coef[i] * y_array[a_num - i - 1]; // input polynom computation
+}
+
+/*! Function sending a double number via CAN.
+* Takes two arguments:
+* \param id unsigned 32-bit integer message ID
+* \param num double number to be sent
+*/
+void send_double_can ( uint32_t id, double num ) {
+ can_msg_t msg = {.dlc = 8}; // CAN message
+
+ /* decompose double into 8-bit fields (quartet byte order change) */
+ memcpy ( &msg.data[4], &num, 4 );
+ memcpy ( &msg.data[0], ( ( ( uint8_t * ) &num ) + 4 ), 4 );
+
+ msg.id = id; // set the message ID
+ while ( can_tx_msg ( &msg ) ); // send the CAN message
+}
+
+/*! Function initializing AD conversion and sampling the data.
+* Takes one argument:
+* \param channel AD channel to sample
+* \return Returns sampled value.
+*/
+int32_t read_AD ( int32_t channel ) {
+ int32_t read; // AD read value
+
+ ADCR &= 0xFFFFFF00;
+ ADCR |= channel; // initialize AD channel sample
+ ADCR |= 0x01000000;
+ while ( ! ( ( read = ADDR ) & 0x80000000 ) ); // wait for sample acquisition
+ read &= 0x0000FFC0;
+ read >>= 6; // read and preprocess sample
+
+ return read;
+}
+
+
+/*! Timer 0 interrupt handler.
+* Serves to handle response timeouts of IMU and GPS.
+*/
+void timer_irq_handler ( void ) {
+ static uint16_t blinki = 0; // counter for LED blinking
+
+ if ( !reset_req ) watchdog_reset ( ); // watchdog reset
+
+ mg_meas_x[msh_meas_count] = read_AD ( 0x00000001 ); // store the result into respective buffer
+ mg_meas_y[msh_meas_count] = read_AD ( 0x00000002 ); // store the result into respective buffer
+ mg_meas_z[msh_meas_count] = read_AD ( 0x00000004 ); // store the result into respective buffer
+
+ if ( msh_meas_count < BUFF_MSH_LEN ) msh_meas_count++; // increment the MSH sample counter
+
+ if ( imu_timeout_count++ > IMU_ERROR_TRESHOLD ) { // if IMU is not responding for the preset time
+ imu_err_state = 1;
+ LED_IMU_IOCLR |= LED_IMU_IOBIT; // switch the IMU LED off
+ LED_ERR_IOSET |= LED_ERR_IOBIT; // switch the ERR LED on
+ imu_timeout_count = 0; // reset the IMU time counter
+ imu_msg_err.data[imu_msg_err.dlc++] = GENERAL_ERR; // fill in the error code into the IMU error message structure
+ while ( can_tx_msg ( &imu_msg_err ) ); // send the error message
+ imu_msg_err.dlc = 0; // null the error message
+ }
+
+ if ( gps_timeout_count++ > gps_err_treshold ) { // if GPS is not responding for the preset time
+ gps_err_state = 1;
+ LED_GPS_IOCLR |= LED_GPS_IOBIT; // switch the GPS LED off
+ LED_ERR_IOSET |= LED_ERR_IOBIT; // switch the ERR LED on
+ gps_timeout_count = 0; // reset the GPS time counter
+ gps_msg_err.data[gps_msg_err.dlc++] = GENERAL_ERR; // fill in the error code into the IMU error message structure
+ while ( can_tx_msg ( &gps_msg_err ) ); // send the error message
+ gps_msg_err.dlc = 0; // null the error message
+ }
+
+ if ( blinki++ < 128 ) LED_MSH_IOSET |= LED_MSH_IOBIT; // switch the MSH LED on for 0.25s
+ else LED_MSH_IOCLR |= LED_MSH_IOBIT; // switch the MSH LED off for 0.25s
+ if ( blinki > 256 ) blinki = 0; // after 0.5s, reset the LED blinking counter
+
+ T0IR = 0xFFFFFFFF; // clear the interrupt flag
+ VICVectAddr = 0; // int acknowledge
+}
+
+/*! Function adding coeffitients into the filter coeffitients array.
+* Takes five arguments:
+* \param filter_coef_flag unsigned 16-bit integer pointer filter coeffitient flag
+* \param current_coef_flag unsigned 16-bit integer flag of the filter coeffitient currently being processed
+* \param coef_num unsigned 8-bit integer pointer number of current coeffitient
+* \param filter_array double pointer filter coeffitient array to which the coeffitient will be added
+* \param rx_msg can_msg_t CAN message structure containing the coeffitient
+*/
+void filter_coef_add ( uint16_t *filter_coef_flag, uint16_t current_coef_flag, uint8_t *coef_num, double *filter_array, can_msg_t *rx_msg ) {
+ if ( !( (*filter_coef_flag) & current_coef_flag ) ) { // if first filter ceficient received
+ (*filter_coef_flag) |= current_coef_flag; // set the corresponding flag
+ *coef_num = 0; // and null respective coeficient number
+ }
+
+ if ( *coef_num < MAX_FILTER_LEN ) {
+ memcpy ( &filter_array[*coef_num], &(*rx_msg).data[4], 4 ); // compose double from 8-bit fields, store new coeficient
+ memcpy ( ( ( ( uint8_t * ) &filter_array[(*coef_num)++] ) + 4 ), &(*rx_msg).data[0], 4 ); // and increment the coeficients counter
+ }
+}
+
+/*! CAN Rx message process routine.
+* Serves to handle an incoming CAN message.
+*/
+void can_rx ( void ) {
+ typedef struct { // structure holding non-constant filter_coef_add function params
+ uint16_t current_coef_flag;
+ uint8_t *coef_num;
+ double *filter_array;
+ } filter_param_struct;
+
+ filter_param_struct filter_param[12] = { {FILTER_ROLL_A_NUM_FLAG, &filter_roll_a_num, a_roll}, {FILTER_ROLL_B_NUM_FLAG, &filter_roll_b_num, b_roll}, {FILTER_PITCH_A_NUM_FLAG, &filter_pitch_a_num, a_pitch}, {FILTER_PITCH_B_NUM_FLAG, &filter_pitch_b_num, b_pitch}, {FILTER_YAW_A_NUM_FLAG, &filter_yaw_a_num, a_yaw}, {FILTER_YAW_B_NUM_FLAG, &filter_yaw_b_num, b_yaw}, {FILTER_ACCEL_X_A_NUM_FLAG, &filter_accel_x_a_num, a_accel_x}, {FILTER_ACCEL_X_B_NUM_FLAG, &filter_accel_x_b_num, b_accel_x}, {FILTER_ACCEL_Y_A_NUM_FLAG, &filter_accel_y_a_num, a_accel_y}, {FILTER_ACCEL_Y_B_NUM_FLAG, &filter_accel_y_b_num, b_accel_y}, {FILTER_ACCEL_Z_A_NUM_FLAG, &filter_accel_z_a_num, a_accel_z}, {FILTER_ACCEL_Z_B_NUM_FLAG, &filter_accel_z_b_num, b_accel_z} }; // array of structures holding non-constant filter_coef_add function params for various filters
+
+ static uint16_t filter_coef_flag = 0; // filter coefitients reception flag
+ can_msg_t rx_msg; // received message
+
+ memcpy ( &rx_msg, (void *) &can_rx_msg, sizeof ( can_msg_t ) ); // create a local copy of the received message
+
+ switch ( rx_msg.id ) { // switch according CAN message ID
+ case RESET_REQUEST_ID: // when reset request is received
+ reset_req = TRUE; // set the reset request flag
+ while ( TRUE ); // wait for watchdog reset
+ break;
+
+ case CAL_SAMPLE_NUM_ID: // receive number of calibration samples
+ memcpy ( &cal_sample_num, &rx_msg.data[0], sizeof ( uint16_t ) ); // compose uint16 from 8-bit fields
+ break;
+
+ default: // receive filter coeficients
+ if ( ( rx_msg.id >= FILTER_ROLL_A_ID ) && ( rx_msg.id <= FILTER_ACCEL_Z_B_ID ) ) filter_coef_add ( &filter_coef_flag, filter_param[rx_msg.id - FILTER_ROLL_A_ID].current_coef_flag, filter_param[rx_msg.id - FILTER_ROLL_A_ID].coef_num, filter_param[rx_msg.id - FILTER_ROLL_A_ID].filter_array, &rx_msg ); // if filter coeffitient is received, add it to the respective filter coeffitients array
+ break;
+ }
+
+ can_msg_received = 0; // reset the pending CAN message flag
+}
+
+/*! IMU service routine.
+* Serves to receive and process the IMU datagrams.
+* \param *step unsigned 8-bit int pointer referencing the message processing step.
+*/
+void IMU_service ( uint8_t *step ) {
+ uint8_t count, temp = 0; // auxiliary variables for wait cycle
+ static uint8_t check_imu; // IMU datagram cross-parity computation variable
+ static uint8_t c; // Auxiliary index variable
+ static uint8_t sample_count = 0; // IMU sample counter
+ static uint8_t blinki = 0; // counter variable driving the LED blinking
+ static uint8_t buffer_int16[2]; // receive buffer for a 16-bit integer
+
+ static int16_t buffer_imu[BUFF_IMU_LEN] = {0, 0, 0, 0, 0, 0}; // IMU data buffers
+
+ static uint16_t cal_sample_count = 0; // calibration sample counter
+
+ int32_t msh_read_x; // MSH measurement sum x
+ int32_t msh_read_y; // MSH measurement sum y
+ int32_t msh_read_z; // MSH measurement sum z
+ uint8_t msh_meas_count_local; // local copy of msh_meas_count
+ double msh_val; // MSH sample
+
+ double roll_compensated = 0; // Computed roll rate [64 Hz] with offset compensation
+ double pitch_compensated = 0; // Computed pitch rate [64 Hz] with offset compensation
+ double yaw_compensated = 0; // Computed yaw rate [64 Hz] with offset compensation
+ double accel_x; // Computed x-axis acceleration
+ double accel_y; // Computed y-axis acceleration
+ double accel_z; // Computed z-axis acceleration
+
+ static double roll_offset = 0; // roll gyro offset
+ static double pitch_offset = 0; // pitch gyro offset
+ static double yaw_offset = 0; // yaw gyro offset
+
+ static double x_roll[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_roll[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // roll rate filtering buffer
+ static double x_pitch[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_pitch[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // pitch rate filtering buffer
+ static double x_yaw[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_yaw[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // yaw rate filtering buffer
+ static double x_accel_x[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_accel_x[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // x-axis acceleration filtering buffer
+ static double x_accel_y[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_accel_y[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // y-axis acceleration filtering buffer
+ static double x_accel_z[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}, y_accel_z[MAX_FILTER_LEN] = {0, 0, 0, 0, 0, 0}; // z-axis acceleration filtering buffer
+
+ can_msg_t msg_rq = {.dlc = 0, .id = RQ_CAN_ID}; // time synchronization CAN message
+
+ switch ( *step ) {
+ case 0: if ( read_UART_data ( UART0 ) == IMU_MES_DELIMITER_1 ) ( *step )++; // wait for the first telegram start character
+ break;
+
+ case 1: if ( read_UART_data ( UART0 ) == IMU_MES_DELIMITER_2 ) { // wait for the second telegram start character
+ ( *step )++; // increment the IMU step counter
+
+ if ( ++sample_count > 1 ) while (can_tx_msg(&msg_rq)); // when the second teleram is being received, send the
+ // synchonisation message (IMU running at 64Hz, overall system sampling frequency is 32Hz)
+ } else ( *step ) = 0; // should another character be received, return to the sequence beginning
+
+ break;
+
+ case 2: if ( blinki++ < 32 ) LED_IMU_IOSET |= LED_IMU_IOBIT; // switch the IMU LED on for 0.5s
+ else LED_IMU_IOCLR |= LED_IMU_IOBIT; // switch the IMU LED off for 0.5s
+ if ( blinki > 64 ) blinki = 0; // after 1s, reset the LED blinking counter
+
+ check_imu = IMU_MES_DELIMITER_1; // cross parity initialization
+ check_imu ^= IMU_MES_DELIMITER_2; // cross parity initialization
+
+ c = read_UART_data ( UART0 ); // read the next telegram character
+ check_imu ^= c; // cross parity computation
+
+ if ( c & IMU_RANGE_MASK ) { // when IMU range error is detected, fill in respective error code
+ imu_msg_err.data[imu_msg_err.dlc++] = RANGE_ERR; // into the IMU error message structure
+ while ( can_tx_msg ( &imu_msg_err ) ); // send the error message
+ imu_msg_err.dlc = 0; // null the error message
+ }
+
+ c = 0; // reset c, as it will be used as a cycle counter in the next two steps
+ ( *step )++;
+ break;
+
+ /* read the accelerations and angular velocities */
+ case 3: buffer_int16[0] = read_UART_data ( UART0 ); // read the first part of a 16-bit integer
+ check_imu ^= buffer_int16[0]; // cross parity computation
+ ( *step )++;
+ break;
+
+ case 4: buffer_int16[1] = read_UART_data ( UART0 ); // read the second part of a 16-bit integer
+ check_imu ^= buffer_int16[1]; // cross parity computation
+ memcpy ( &buffer_imu[c], buffer_int16, sizeof ( int16_t ) ); // read the second part of a 16-bit integer
+
+ if ( ++c < 6 ) ( *step )--; else ( *step )++; // when all 6 values are acquired go ahead, or return to the previous step
+ break;
+
+ case 5: c = read_UART_data ( UART0 ); // read the cross parity
+ check_imu ^= c; // this final XOR should give a zero if the parity was right
+
+ if ( check_imu ) { // should the parity be wrong fill in the respective error code
+ imu_msg_err.data[imu_msg_err.dlc++] = PARITY_ERR; // into the IMU error message structure
+ while ( can_tx_msg ( &imu_msg_err ) ); // send the error message
+ imu_msg_err.dlc = 0; // null the error message
+ }
+
+ /* data filtering - roll, pitch and yaw angular rates */
+ filter ( ( ( (double) buffer_imu[0] ) * -ANGULAR_CONV_64 ), x_roll, y_roll, a_roll, b_roll, filter_roll_a_num, filter_roll_b_num );
+ filter ( ( ( (double) buffer_imu[1] ) * -ANGULAR_CONV_64 ), x_pitch, y_pitch, a_pitch, b_pitch, filter_pitch_a_num, filter_pitch_b_num );
+ filter ( ( ( (double) buffer_imu[2] ) * ANGULAR_CONV_64 ), x_yaw, y_yaw, a_yaw, b_yaw, filter_yaw_a_num, filter_yaw_b_num );
+
+ /* gyros offset computation (calibration) */
+ if ( ( cal_sample_count >= GYRO_OFFSET_FILTERING_TRESHOLD ) && ( cal_sample_count < cal_sample_num ) ) { // summarize (cal_sample_num - GYRO_OFFSET_FILTERING_TRESHOLD) samples
+ roll_offset += y_roll[filter_roll_a_num - 1];
+ pitch_offset += y_pitch[filter_pitch_a_num - 1];
+ yaw_offset += y_yaw[filter_yaw_a_num - 1];
+
+ /* ERR LED blinking */
+ if ( blinki < 32 ) LED_ERR_IOSET |= LED_ERR_IOBIT; // switch the ERR LED on for 0.5s
+ else LED_ERR_IOCLR |= LED_ERR_IOBIT; // switch the ERR LED off for 0.5s
+ } else if ( cal_sample_count == cal_sample_num ) { // compute offset mean values
+ roll_offset /= ( (double) ( cal_sample_num - GYRO_OFFSET_FILTERING_TRESHOLD ) );
+ pitch_offset /= ( (double) ( cal_sample_num - GYRO_OFFSET_FILTERING_TRESHOLD ) );
+ yaw_offset /= ( (double) ( cal_sample_num - GYRO_OFFSET_FILTERING_TRESHOLD ) );
+
+ if ( !imu_err_state && !gps_err_state ) LED_ERR_IOCLR |= LED_ERR_IOBIT; // if IMU and GPS are not in the error state switch the ERR LED off
+ else LED_ERR_IOSET |= LED_ERR_IOBIT; // else if IMU or GPS (or both) are in the error state switch the ERR LED on
+ }
+
+ /* filtered roll, pitch and yaw offset compensation */
+ if ( cal_sample_count > cal_sample_num ) {
+ roll_compensated = y_roll[filter_roll_a_num - 1] - roll_offset;
+ pitch_compensated = y_pitch[filter_pitch_a_num - 1] - pitch_offset;
+ yaw_compensated = y_yaw[filter_yaw_a_num - 1] - yaw_offset;
+ }
+
+ if ( cal_sample_count < 0xFFFF ) cal_sample_count++; // increment calibration sample counter
+
+ /* x, y and z acceleration computation */
+ accel_x = ( (double) buffer_imu[4] ) * ACCEL_CONV_64; // convert x-axis acceleration into miligs
+ accel_y = ( (double) buffer_imu[3] ) * ACCEL_CONV_64; // convert y-axis acceleration into miligs
+ accel_z = ( (double) buffer_imu[5] ) * -ACCEL_CONV_64; // convert z-axis acceleration into miligs (*(-1) due to the IMU orientation)
+
+ /* data filtering - x, y and z axes accelerations */
+ filter ( accel_x, x_accel_x, y_accel_x, a_accel_x, b_accel_x, filter_accel_x_a_num, filter_accel_x_b_num );
+ filter ( accel_y, x_accel_y, y_accel_y, a_accel_y, b_accel_y, filter_accel_y_a_num, filter_accel_y_b_num );
+ filter ( accel_z, x_accel_z, y_accel_z, a_accel_z, b_accel_z, filter_accel_z_a_num, filter_accel_z_b_num );
+
+ if ( sample_count > 1 ) { // if the second telegram is received, process the data
+ send_double_can ( AR_CAN_ID_ROLL_FILTERED, roll_compensated ); // send the CAN message containing filtered roll angular velocity
+ send_double_can ( AR_CAN_ID_PITCH_FILTERED, pitch_compensated ); // send the CAN message containing filtered pitch angular velocity
+ send_double_can ( AR_CAN_ID_YAW_FILTERED, yaw_compensated ); // send the CAN message containing filtered yaw angular velocity
+ send_double_can ( AR_CAN_ID_ROLL, ( ( (double) buffer_imu[0] ) * -ANGULAR_CONV_64 ) ); // send the CAN message containing roll angular velocity
+ send_double_can ( AR_CAN_ID_PITCH, ( ( (double) buffer_imu[1] ) * -ANGULAR_CONV_64 ) ); // send the CAN message containing pitch angular velocity
+ send_double_can ( AR_CAN_ID_YAW, ( ( (double) buffer_imu[2] ) * ANGULAR_CONV_64 ) ); // send the CAN message containing yaw angular velocity
+ send_double_can ( AC_CAN_ID_X_FILTERED, y_accel_x[filter_accel_x_a_num - 1] ); // send the CAN message containing filtered x-axis acceleration
+ send_double_can ( AC_CAN_ID_Y_FILTERED, y_accel_y[filter_accel_y_a_num - 1] ); // send the CAN message containing filtered y-axis acceleration
+ send_double_can ( AC_CAN_ID_Z_FILTERED, y_accel_z[filter_accel_z_a_num - 1] ); // send the CAN message containing filtered z-axis acceleration
+ send_double_can ( AC_CAN_ID_X, accel_x ); // send the CAN message containing x-axis acceleration
+ send_double_can ( AC_CAN_ID_Y, accel_y ); // send the CAN message containing y-axis acceleration
+ send_double_can ( AC_CAN_ID_Z, accel_z ); // send the CAN message containing z-axis acceleration
+
+ /* MSH messages composition */
+ msh_read_x = 0; // clear the MSH measure sum x
+ msh_read_y = 0; // clear the MSH measure sum y
+ msh_read_z = 0; // clear the MSH measure sum z
+ msh_meas_count_local = msh_meas_count; // store msh measure counter into a local copy
+ for ( c = 0; c < msh_meas_count_local; c++ ) {
+ msh_read_x += mg_meas_x[c];
+ msh_read_y += mg_meas_y[c]; // compute the sums
+ msh_read_z += mg_meas_z[c];
+ }
+
+ msh_meas_count = 0; // reset the MSH measure counter
+
+ if ( msh_degauss_count++ > 127 ) { // generate the degauss pulse for MSH every 4s
+ PAL_IOCLR |= PAL_IOBIT; // degauss pulse (+)
+ for ( count = 0; count < 60; count++ ) temp++; // delay between pulses
+ PAL_IOSET |= PAL_IOBIT; // degauss pulse (-)
+ msh_degauss_count = 0; // reset degauss timer counter
+ }
+
+ msh_val = ( ( double ) msh_read_x ) / ( ( double ) msh_meas_count_local ); // mean value computation x
+ msh_val /= MSH_CONV; // conversion to mgauss
+ msh_val -= MSH_OFFSET; // offset correction
+ msh_val = -msh_val; // reverse direction to correspond with the vehicle axis orientation
+
+ send_double_can ( MSH_ID_X, msh_val ); // send the CAN message (y magnetic field intensity)
+
+ msh_val = ( ( double ) msh_read_y ) / ( ( double ) msh_meas_count_local ); // mean value computation y
+ msh_val /= MSH_CONV; // conversion to mgauss
+ msh_val -= MSH_OFFSET; // offset correction
+
+ send_double_can ( MSH_ID_Y, msh_val ); // send the CAN message (y magnetic field intensity)
+
+ msh_val = ( ( double ) msh_read_z ) / ( ( double ) msh_meas_count_local ); // mean value computation z
+ msh_val /= MSH_CONV; // conversion to mgauss
+ msh_val -= MSH_OFFSET; // offset correction
+
+ send_double_can ( MSH_ID_Z, msh_val ); // send the CAN message (z magnetic field intensity)
+
+ imu_timeout_count = 0; // reset the IMU timeout counter
+ sample_count = 0; // reset the sample counter
+
+ if ( imu_err_state ) { // if IMU was in error state
+ imu_msg_err.data[imu_msg_err.dlc++] = NO_ERR; // fill in the no error code into the IMU error message structure
+ while ( can_tx_msg ( &imu_msg_err ) ); // send the error message
+ imu_msg_err.dlc = 0; // null the error message
+ LED_ERR_IOCLR |= LED_ERR_IOBIT; // switch the ERR LED off
+ imu_err_state = 0; // turn off the GPS error flag
+ }
+ }
+
+ ( *step ) = 0; // repeat the cycle from the beginning
+ break;
+ }
+}
+
+/*! GPS service routine
+* Serves to receive and process the GPS datagrams.
+* \param *step unsigned 8-bit int pointer referencing the message processing step.
+*/
+void GPS_service ( uint8_t *step ) {
+ uint32_t gps_can_msg_id[8] = {GPS_ID1, GPS_ID2, GPS_ID3, GPS_ID4, GPS_ID5, GPS_ID6, GPS_ID7, GPS_ID8}; // GPS can messages ID array
+ uint8_t i; // cycle counter
+ static uint8_t check_gps; // GPS datagram cross-parity computation variable
+ static uint8_t gps_data_count; // GPS datagram received byte counter
+ static uint8_t dle_data_flag = 0; // Flag variable, signalizing that bit stuffing occured
+ static uint8_t blinki = 0; // counter variable driving the LED blinking
+ static uint8_t buffer_gps[BUFF_GPS_LEN]; // GPS receive buffer
+
+ can_msg_t gps_msg = {.dlc = 8}; // GPS CAN data packet
+
+ switch ( *step ) {
+ case 0: if ( read_UART_data ( UART1 ) == DLE_BYTE ) ( *step )++; // wait for the first telegram start character
+ break;
+
+ case 1: if ( read_UART_data ( UART1 ) == ID_POS ) { // check for the position telegram ID
+ check_gps = ID_POS; // cross parity computation (sum of all telegram characters should be 0)
+ ( *step )++; // go to the next step
+ } else ( *step ) = 0; // if other then position telegram ID is detected, go to the beginning and wait for another telegram
+
+ break;
+
+ case 2: if ( read_UART_data ( UART1 ) == GPS_DATA_LENGTH ) { // check the data message length
+ check_gps += GPS_DATA_LENGTH; // cross parity computation (sum of all telegram characters should be 0)
+
+ if ( blinki++ < 1 ) LED_GPS_IOSET |= LED_GPS_IOBIT; // switch the GPS LED on for 1s
+ else LED_GPS_IOCLR |= LED_GPS_IOBIT; // switch the GPS LED off for 1s
+ if ( blinki > 1 ) blinki = 0; // after 2s, reset the LED blinking counter
+
+ gps_data_count = 0; // reset the GPS Rx data counter
+ ( *step )++; // go to the next step
+ } else ( *step ) = 0; // if wrong data length is detected, go to the beginning and wait for another telegram
+
+ break;
+
+ case 3: buffer_gps[gps_data_count++] = read_UART_data ( UART1 ); // store new GPS data into the GPS data buffer
+
+ if ( ( buffer_gps[gps_data_count - 1] == DLE_BYTE ) && !dle_data_flag ) { // get rid of the DLE byte stuffing
+ gps_data_count--; // shift the data counter back - the stuffed character should be omitted
+ dle_data_flag = 1; // set the DLE stuffing flag
+ } else if ( dle_data_flag ) dle_data_flag = 0; // in the next step, clear the DLE stuffing flag
+
+ if ( !dle_data_flag ) check_gps += buffer_gps[gps_data_count - 1]; // cross parity computation (sum of all telegram characters should be 0)
+
+ if ( gps_data_count == GPS_DATA_LENGTH ) ( *step )++; // if the whole message has been read go to the next step
+ break;
+
+ case 4: dle_data_flag = read_UART_data ( UART1 ); // read the last parity byte
+ check_gps += dle_data_flag; // cross parity computation
+ if ( check_gps ) { // if the parity is wrong fill in the respective error code
+ gps_msg_err.data[gps_msg_err.dlc++] = PARITY_ERR; // into the IMU error message structure
+ while ( can_tx_msg ( &gps_msg_err ) ); // send the error message
+ gps_msg_err.dlc = 0; // null the error message
+ }
+
+ ( *step )++; // follow to the next step
+ break;
+
+ case 5: if ( read_UART_data ( UART1 ) != DLE_BYTE ) { // read the second DLE byte (DLE stuffing). In case it is not received,
+ gps_msg_err.data[gps_msg_err.dlc++] = FRAME_ERR; // fill the respective error code into the IMU error message structure
+ while ( can_tx_msg ( &gps_msg_err ) ); // send the error message
+ gps_msg_err.dlc = 0; // null the error message
+ }
+
+ if ( dle_data_flag != DLE_BYTE ) ( *step )++; else dle_data_flag = 0; // follow to the next step, if DLE stuffing occured repeat the step 5 once more
+ break;
+
+ case 6: if ( read_UART_data ( UART1 ) != ETX_BYTE ) { // the ETX byte should follow...
+ gps_msg_err.data[gps_msg_err.dlc++] = FRAME_ERR_ETX; // in case it does not, fill in the respective error code into the IMU error message structure
+ while ( can_tx_msg ( &gps_msg_err ) ); // send the error message
+ gps_msg_err.dlc = 0; // null the error message
+ }
+
+ ( *step )++; // follow to the next step
+ break;
+
+ /* compose and send the CAN messages containing the GPS data */
+ case 7: for ( i = 0; i < 8; i++ ) {
+ memcpy ( gps_msg.data, &buffer_gps[8 * i], 8 ); // fill in the first data message
+ gps_msg.id = gps_can_msg_id[i]; // set the ID
+ while ( can_tx_msg ( &gps_msg ) ); // send the GPS data packet
+ }
+
+ gps_timeout_count = 0; // reset the GPS timeout counter
+ gps_err_treshold = GPS_ERROR_TRESHOLD_RUN;
+ ( *step ) = 0; // repeat the cycle from the beginning
+
+ if ( gps_err_state ) { // if GPS was in error state
+ gps_msg_err.data[gps_msg_err.dlc++] = NO_ERR; // fill in the no error code into the GPS error message structure
+ while ( can_tx_msg ( &gps_msg_err ) ); // send the error message
+ gps_msg_err.dlc = 0; // null the error message
+ LED_ERR_IOCLR |= LED_ERR_IOBIT; // switch the ERR LED off
+ gps_err_state = 0; // turn off the GPS error flag
+ }
+
+ break;
+ }
+}
+
+/*! Application entry point.
+* This is where the application starts. This routine consists of
+* initialization and an infinite cycle, where pending data are detected and
+* respective service routines called to process them.
+* \return Returns nothing - the program is an infinite cycle.
+*/
+int main ( void ) {
+ uint8_t step_imu = 0; // actual step number in the IMU datagram processing
+ uint8_t step_gps = 0; // actual step number in the GPS datagram processing
+ int count, temp = 0; // auxiliary variables for wait cycle
+
+ VPBDIV = 1; // peripheral clock = CPU clock (10MHz)
+
+ MEMMAP = MEMMAP_EXC_RAM; // map exception handling to RAM
+
+ VICIntEnClr = 0xFFFFFFFF; // init Vector Interrupt Controller
+ VICIntSelect = 0x00000000;
+
+ PAL_PINSEL &= PAL_PINSEL_VAL;
+ PAL_IODIR |= PAL_IOBIT; // set the PAL pin as output and set PAL to 1 (inactive)
+ PAL_IOSET |= PAL_IOBIT;
+
+ LED_IMU_PINSEL &= LED_IMU_PINSEL_VAL;
+ LED_IMU_IODIR |= LED_IMU_IOBIT; // set the IMU LED pin as output and switch the IMU LED off
+ LED_IMU_IOCLR |= LED_IMU_IOBIT;
+
+ LED_GPS_PINSEL &= LED_GPS_PINSEL_VAL;
+ LED_GPS_IODIR |= LED_GPS_IOBIT; // set the GPS LED pin as output and switch the GPS LED off
+ LED_GPS_IOCLR |= LED_GPS_IOBIT;
+
+ LED_MSH_PINSEL &= LED_MSH_PINSEL_VAL;
+ LED_MSH_IODIR |= LED_MSH_IOBIT; // set the MSH LED pin as output and switch the MSH LED off
+ LED_MSH_IOCLR |= LED_MSH_IOBIT;
+
+ LED_ERR_PINSEL &= LED_ERR_PINSEL_VAL;
+ LED_ERR_IODIR |= LED_ERR_IOBIT; // set the ERR LED pin as output and switch the ERR LED on
+ LED_ERR_IOSET |= LED_ERR_IOBIT;
+
+ pwm_channel ( 2, 0 ); // select PWM channel to be used as clock source for Villard
+ pwm_init ( 1, 2000 ); // init PWM
+ pwm_set ( 2, 1000 ); // switch on Villard 5kHz
+
+ can_init ( CAN_BTR, ISR_INT_VEC_CAN, NULL ); // init CAN
+ watchdog_init ( WATCHDOG_INIT ); // watchdog initialization
+
+ for ( count = 0; count < 2500000; count++ ) { // wait for Villard to charge
+ if ( can_msg_received ) can_rx ( ); // when CAN receives new data, call the service routine
+ if ( WDTV < ( WATCHDOG_INIT / 2 ) ) watchdog_reset ( ); // watchdog reset
+ }
+
+ PAL_IOCLR |= PAL_IOBIT; // degauss pulse (+)
+ for ( count = 0; count < 100; count++ ) temp++; // delay between pulses
+ PAL_IOSET |= PAL_IOBIT; // degauss pulse (-)
+
+ LED_ERR_IOCLR |= LED_ERR_IOBIT; // switch the ERR LED off
+
+ adc_init ( 3 ); // init AD convertor (AD clock prescaller 3)
+ UART_init ( UART0, BAUD_RATE0, ISR_INT_VEC_U0 ); // init UART0
+ UART_init ( UART1, BAUD_RATE1, ISR_INT_VEC_U1 ); // init UART1
+ timer_init ( TIMER_PRESCALER, TIMER_PERIOD, ISR_INT_VEC_TIMER ); // init timer 0 - interrupt frequency 1Hz
+
+ /* main infinite cycle - look for new data at both UARTs and CAN */
+ while ( TRUE ) {
+ if ( UART_new_data ( UART0 ) ) IMU_service ( &step_imu ); // when UART0 receives new data, service the IMU
+ if ( UART_new_data ( UART1 ) ) GPS_service ( &step_gps ); // when UART1 receives new data, service the GPS
+ if ( can_msg_received ) can_rx ( ); // when CAN receives new data, call the service routine
+ }
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = shodiny
+shodiny_SOURCES = hodiny.c
+shodiny_LIBS = can
+link_VARIANTS = mpram
--- /dev/null
+/* ustredni hodiny Spejbla */
+
+#include <types.h>
+#include <lpc21xx.h>
+#include <periph/can.h>
+
+#define CANLOAD_ID (*((volatile unsigned long *) 0x40000120))
+
+void timer_irq() __attribute__((interrupt));
+
+void timer_init(uint32_t prescale, uint32_t period) {
+ T0PR = prescale - 1;
+ T0MR1 = period - 1;
+ T0MCR = 0x3<<3; /* interrupt and counter reset on match1 */
+ T0EMR = 0x1<<6 | 0x2; /* set MAT0.1 low on match and high now */
+ T0CCR = 0x0; /* no capture */
+ T0TCR |= 0x1; /* go! */
+}
+
+void timer_init_irq(unsigned irq_vect) {
+ /* set interrupt vector */
+ ((uint32_t*)&VICVectAddr0)[irq_vect] = (uint32_t)timer_irq;
+ ((uint32_t*)&VICVectCntl0)[irq_vect] = 0x20 | 4;
+ /* enable timer int */
+ VICIntEnable = 0x00000010;
+}
+
+can_msg_t msg = {.flags = 0, .dlc = 1};
+uint8_t seq_num = 0;
+
+void timer_irq() {
+ msg.data[0] = seq_num++;
+ while (can_tx_msg(&msg));
+ /* clear int flag */
+ T0IR = 0xffffffff;
+ /* int acknowledge */
+ VICVectAddr = 0;
+}
+
+int main() {
+ /* peripheral clock = CPU clock (10MHz) */
+ VPBDIV = 1;
+ /** map exception handling to RAM **/
+ MEMMAP = 0x2;
+ /* init Vector Interrupt Controller */
+ VICIntEnClr = 0xFFFFFFFF;
+ VICIntSelect = 0x00000000;
+ /* 10MHz VPB, 1000kb/s TSEG1=6, TSEG2=3, SJW= */
+ can_init(0x250000, 14, NULL);
+ msg.id = CANLOAD_ID;
+ /* * */
+ timer_init(10, 4000 /*250Hz*/);
+ timer_init_irq(13);
+ /* jamais fatigue */
+ for (;;);
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = smotor
+smotor_SOURCES = motor.c pwm.c
+smotor_LIBS = can
+link_VARIANTS = mpram
\ No newline at end of file
--- /dev/null
+/** cerveaumotor Spejbla **/
+
+#include <stdlib.h>
+#include <types.h>
+#include <limits.h>
+#include <lpc21xx.h>
+#include <periph/can.h>
+#include <string.h>
+#include "pwm.h"
+
+/* * */
+
+/* CAN message IDs */
+#define CAN_CLOCK_ID 0x401
+//#define CAN_CLOCK_ID 0x481
+#define CAN_CFGMSG_ID 0x4ab
+#define CAN_UNDEF_ID 0xf800
+
+/* unique motor/CAN ID */
+#define CANLOAD_ID (*((volatile unsigned long *) 0x40000120))
+#define MOTOR_ID CANLOAD_ID
+
+/* potentiometer bounds */
+#define POS_MIN 0x060
+#define POS_MAX 0x3a0
+/* reserved value for power-off */
+#define CTRL_OFF 0xffff
+#define CTRL_MAX SHRT_MAX
+
+/* own message for current position signalling */
+can_msg_t tx_msg = {.flags = 0, .dlc = 2};
+
+/* command message ID and index */
+uint16_t cmd_msg_id = CAN_UNDEF_ID, cmd_msg_ndx = 0;
+
+/* command value, current position */
+volatile uint16_t cmd_value = CTRL_OFF, rx_cmd_value = CTRL_OFF,
+ position, pos_data;
+volatile uint8_t tx_request = 0;
+
+/* * */
+
+void timer_irq() __attribute__((interrupt));
+
+void timer_init(uint32_t prescale, uint32_t period) {
+ T0PR = prescale - 1;
+ T0MR1 = period - 1;
+ T0MCR = 0x3<<3; /* interrupt and counter reset on match1 */
+ T0EMR = 0x1<<6 | 0x2; /* set MAT0.1 low on match and high now */
+ T0CCR = 0x0; /* no capture */
+ T0TCR |= 0x1; /* go! */
+}
+
+void timer_init_irq(unsigned irq_vect) {
+ /* set interrupt vector */
+ ((uint32_t*)&VICVectAddr0)[irq_vect] = (uint32_t)timer_irq;
+ ((uint32_t*)&VICVectCntl0)[irq_vect] = 0x20 | 4;
+ /* enable timer int */
+ VICIntEnable = 0x00000010;
+}
+
+void adc_init(unsigned clk_div) {
+ ADCR = 0x01 | ((clk_div&0xff)<<8) | 0x200000;
+ ADCR |= 0x04000000; /* conversion started on falling edge of MAT0.1 */
+}
+
+/* * */
+
+inline void sample() {
+ /* get last position measured (weak point! sampling jitter!) */
+ position = pos_data;
+ /* request transmission of obtained value by idle loop */
+ tx_request = 1;
+}
+
+inline void actuate() {
+ /* set previously received command rx_cmd_value */
+ if (rx_cmd_value == CTRL_OFF) {
+ if (cmd_value != CTRL_OFF) {
+ /* switch H-bridge off */
+ pwm_set(4, 0);
+ pwm_set(6, 0);
+ }
+ }
+ else
+ if (cmd_value == CTRL_OFF) {
+ /* switch H-bridge on */
+
+ }
+ /* set the value */
+ cmd_value = rx_cmd_value;
+}
+
+/* .oOo. * controller * .oOo. */
+
+#define REG_P_GAIN (0.0012 * 15)
+#define REG_P_GAIN_INV ((int16_t)(1.0/REG_P_GAIN))
+inline int16_t regulate(uint16_t w, uint16_t y) {
+ int16_t e = (int16_t)w - (int16_t)y;
+ int32_t m;
+
+ if (e > REG_P_GAIN_INV)
+ return(CTRL_MAX);
+ if (e < -REG_P_GAIN_INV)
+ return(-CTRL_MAX);
+ /* REG_P_GAIN << 1 */
+ m = (int32_t)e*CTRL_MAX;
+ return(m/REG_P_GAIN_INV);
+}
+
+void timer_irq() {
+ int16_t u;
+
+ /* wait for A/D conversion to finish */
+ while ((ADDR&0x80000000) == 0);
+ T0EMR |= 0x2; /* set MAT0.1 high again */
+ pos_data = (ADDR>>6)&0x3ff;
+ if (cmd_value != CTRL_OFF) {
+ /* compute the control */
+ u = regulate(cmd_value, pos_data);
+ /* apply it */
+ if (((pos_data < POS_MIN) && (u < 0)) ||
+ ((pos_data > POS_MAX) && (u > 0))) {
+ /* protect the gear against self-destruction */
+ pwm_set(4, 0);
+ pwm_set(6, 0);
+ }
+ else {
+ if (u > 0) {
+ pwm_set(4, PWMMR0*u/CTRL_MAX);
+ pwm_set(6, 0);
+ }
+ else {
+ pwm_set(4, 0);
+ pwm_set(6, PWMMR0*(-u)/CTRL_MAX);
+ }
+ }
+ }
+ /* clear int flag */
+ T0IR = 0xffffffff;
+ /* int acknowledge */
+ VICVectAddr = 0;
+}
+
+void can_rx(can_msg_t *msg) {
+ can_msg_t rx_msg;
+
+ memcpy(&rx_msg, msg, sizeof(can_msg_t));
+ switch (rx_msg.id) {
+ case CAN_CLOCK_ID:
+ sample();
+ actuate();
+ break;
+ case CAN_CFGMSG_ID:
+ if (((uint16_t*)rx_msg.data)[0] == MOTOR_ID) {
+ cmd_msg_id = ((uint16_t*)rx_msg.data)[1];
+ cmd_msg_ndx = ((uint16_t*)rx_msg.data)[2];
+ }
+ break;
+ default:
+ if (rx_msg.id == cmd_msg_id)
+ rx_cmd_value = ((uint16_t*)rx_msg.data)[cmd_msg_ndx];
+ break;
+ }
+}
+
+int main() {
+ /* peripheral clock = CPU clock (10MHz) */
+ VPBDIV = 1;
+ /** map exception handling to RAM **/
+ MEMMAP = 0x2;
+ /* init Vector Interrupt Controller */
+ VICIntEnClr = 0xFFFFFFFF;
+ VICIntSelect = 0x00000000;
+ /* * */
+ /* 10MHz VPB, 1000kb/s TSEG1=6, TSEG2=3, SJW= */
+ can_init(0x250000, 14, can_rx);
+ tx_msg.id = MOTOR_ID;
+ /***/
+ adc_init(3);
+ pwm_channel(4, 0);
+ pwm_channel(6, 0);
+ pwm_init(1, 500 /*20kHz*/);
+ /* initially, switch H-bridge off */
+ pwm_set(4, 0);
+ pwm_set(6, 0);
+ /* * */
+ timer_init(10, 1000 /*1000Hz*/);
+ timer_init_irq(13);
+ /* jamais fatigue */
+ for (;;)
+ if (tx_request) {
+ *((uint16_t*)tx_msg.data) = position;
+ while (can_tx_msg(&tx_msg));
+ tx_request = 0;
+ }
+}
+
+/* KOHE||, */
--- /dev/null
+#include "pwm.h"
+
+int PWM_PINSEL[] = {
+ /*nothing*/ 1, /*PWM1*/ 1, 15, 3, 17, /*PWM5*/ 11, /*PWM6*/ 19
+};
+
+uint32_t *PWM_MR[] = {
+ (uint32_t*)&(PWMMR0),
+ (uint32_t*)&(PWMMR1),
+ (uint32_t*)&(PWMMR2),
+ (uint32_t*)&(PWMMR3),
+ (uint32_t*)&(PWMMR4),
+ (uint32_t*)&(PWMMR5),
+ (uint32_t*)&(PWMMR6)
+};
+
+void pwm_channel(int n, int double_edge) {
+ uint32_t bit;
+
+ PWMPCR |= (0x100 | (double_edge && n)) << n;
+ if (n == 5) {
+ PINSEL1 |= 0x00000400;
+ PINSEL1 &= 0xfffff7ff;
+ }
+ else {
+ bit = 1 << PWM_PINSEL[n];
+ PINSEL0 |= bit;
+ bit = ~(bit >> 1);
+ PINSEL0 &= bit;
+ }
+}
+
+void pwm_set(int n, uint32_t when) {
+ *PWM_MR[n] = when;
+ PWMLER |= 1 << n;
+}
+
+void pwm_set_double(int n, uint32_t from, uint32_t to) {
+ *PWM_MR[n-1] = from;
+ *PWM_MR[n] = to;
+ PWMLER |= 0x3 << (n-1);
+}
+
+void pwm_init(uint32_t prescale, uint32_t period) {
+ PWMPR = prescale - 1;
+ PWMMR0 = period - 1;
+ PWMLER |= 0x1;
+ PWMMCR |= 0x00000002;
+ PWMTCR &= ~0x2;
+ PWMTCR |= 0x9;
+}
+
--- /dev/null
+#include <lpc21xx.h>
+#include <types.h>
+
+extern int PWM_PINSEL[];
+extern uint32_t *PWM_MR[];
+
+void pwm_channel(int n, int double_edge);
+void pwm_set(int n, uint32_t when);
+void pwm_set_double(int n, uint32_t from, uint32_t to);
+void pwm_init(uint32_t prescale, uint32_t period);
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = test_ARMBoard_pwm
+
+test_ARMBoard_pwm_SOURCES = test_ARMBoard_pwm.c pwm.c
+#test_LIBS = boot_fn
+
+#link_VARIANTS = boot ram bload flash
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (10000000) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+#error Fosc out of range (10MHz-25MHz)\r
+#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+/*
+* C Implementation: pwm
+*
+* Description: configuration of PWM unit
+*
+*
+* Author: LAGARRIGUE <glagarri@etud.insa-toulouse.fr>, (C) 2005
+*
+* Copyright: See COPYING file that comes with this distribution
+*
+*/
+
+
+#include <LPC210x.h>
+#include "config.h"
+#include "pwm.h"
+
+#define MINFREQ (PCLK/(0xFFFFFFFF))
+
+/**
+ * Initializes PWM frequency with match0 register
+ * @param freq frequency in Hz
+ */
+void Init_PWM(int freq)
+{
+ if ((freq <= PCLK) | (freq >= MINFREQ))
+ {
+ PWMPR = 0x00000000; //no prescaler
+ PWMMCR = 0x00000002; // on match with MATCH0 Register, reset the counter
+ PWMMR0 = (int)(PCLK/(freq));
+ }
+
+
+}
+
+/**
+ * Initilizes and sets the duty cycle of the desired pwm channel
+ * @param channel = channel number (1,2,3,4,5,6)
+ * @param duty_cycle = float between 0 and 1
+ */
+void Set_PWM (int channel, float duty_cycle)
+{
+ int Pwmmatch;
+ Pwmmatch = (int) (duty_cycle * PWMMR0);
+
+
+
+ //PINSEL0 |= ...; /* Enable P0.7, 8 and P0.9 as alternate PWM outputs functions*/
+ //PINSEL0 &= ...;
+
+ //PWMPCR = ...; /* single edge control only*/
+
+ //PWMMRX = 0x500; /* set falling edge of PWM channel X */
+
+ //PWMLER = 0x..; /* enable shadow latch for match 1 - 6 */
+
+
+ switch (channel)
+ {
+
+
+ case 1 :
+ PWMMR1 =Pwmmatch;
+ PWMPCR |= 0x0200;
+ PWMLER |= 0x02;
+ PINSEL0 |= 0x00000002;
+ PINSEL0 &= 0xFFFFFFFE;
+ break;
+
+ case 2 :
+ PWMMR2 =Pwmmatch;
+ PWMPCR |= 0x0400;
+ PWMLER |= 0x04;
+ PINSEL0 |= 0x00008000;
+ PINSEL0 &= 0xFFFFBFFF;
+ break;
+
+ case 3 :
+ PWMMR3 =Pwmmatch;
+ PWMPCR |= 0x0800;
+ PWMLER |= 0x08;
+ PINSEL0 |= 0x00000008;
+ PINSEL0 &= 0xFFFFFFFB;
+ break;
+ case 4 :
+ PWMMR4 =Pwmmatch;
+ PWMPCR |= 0x1000;
+ PWMLER |= 0x10;
+ PINSEL0 |= 0x00020000;
+ PINSEL0 &= 0xFFFEFFFF;
+ break;
+
+ case 5 :
+ PWMMR5 =Pwmmatch;
+ PWMPCR |= 0x2000;
+ PWMLER |= 0x20;
+ PINSEL1 |= 0x00000400;
+ PINSEL1 &= 0xFFFFF7FF;
+ break;
+
+ case 6 :
+ PWMMR6 =Pwmmatch;
+ PWMPCR |= 0x4000;
+ PWMLER |= 0x40;
+ PINSEL0 |= 0x00080000;
+ PINSEL0 &= 0xFFFBFFFF;
+ break;
+
+
+ }
+
+}
+
+
+/**
+ * Resets the counter and runs the PWM unit
+ * @param
+ */
+void Run_PWM (void)
+{
+ PWMTCR = 0x2; /* Reset counter and prescaler */
+ PWMTCR = 0x9; /* enable counter and PWM, release counter from reset */
+}
+
+
+/**
+ * Stops PWM unit and resets the timer
+ * @param
+ */
+void Stop_PWM (void)
+{
+ int i;
+ for (i=1 ; i < 7 ; i++)
+ {
+ Set_PWM (i, 0);
+ }
+ PWMTCR = 0x2;
+}
\ No newline at end of file
--- /dev/null
+//
+// pwm.h
+//
+// Description: PWM unit configuration
+//
+//
+// Author: LAGARRIGUE <glagarri@etud.insa-toulouse.fr>, (C) 2005
+//
+// Copyright: See COPYING file that comes with this distribution
+//
+//
+#include <LPC210x.h>
+#include "config.h"
+
+
+#define MINFREQ (PCLK/(0xFFFFFFFF))
+
+void Init_PWM(int freq);
+void Set_PWM (int channel, float duty_cycle);
+void Run_PWM (void);
+void Stop_PWM (void);
--- /dev/null
+ /******************************************************************************/\r
+ /* This file is a test of pwm unit of ARM board.\r
+ It's the first test which works\r
+ The loader works correctly too */\r
+ /******************************************************************************/\r
+ /* */\r
+ /* test_ARMBoard_pwm.c : DC motor control with PWM */\r
+ /* */\r
+ /******************************************************************************/\r
+ \r
+ \r
+ \r
+#include <types.h>\r
+#include <LPC210x.h>\r
+#include "config.h"\r
+#include "pwm.h"\r
+ \r
+ \r
+\r
+ /**\r
+ * * Function Name: lowInit()\r
+ *\r
+ * Description:\r
+ * This function starts up the PLL then sets up the GPIO pins before\r
+ * waiting for the PLL to lock. It finally engages the PLL and\r
+ * returns\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ *\r
+ * \r
+ */\r
+ static void lowInit(void)\r
+{\r
+ // set PLL multiplier & divisor.\r
+ // values computed from config.h\r
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;\r
+ \r
+ // enable PLL\r
+ PLLCON = PLLCON_PLLE;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup the parallel port pin\r
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output\r
+ IOSET = PIO_ONE_BITS; // set the ONEs output\r
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction\r
+ \r
+ // wait for PLL lock\r
+ while (!(PLLSTAT & PLLSTAT_LOCK))\r
+ continue;\r
+ \r
+ // enable & connect PLL\r
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;\r
+ PLLFEED = 0xAA; // Make it happen. These two updates\r
+ PLLFEED = 0x55; // MUST occur in sequence.\r
+ \r
+ // setup & enable the MAM\r
+ MAMTIM = MAMTIM_CYCLES;\r
+ MAMCR = MAMCR_FULL;\r
+ \r
+ // set the peripheral bus speed\r
+ // value computed from config.h\r
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed\r
+}\r
+ \r
+ \r
+ /**\r
+ * Function Name: sysInit()\r
+ *\r
+ * Description:\r
+ * This function is responsible for initializing the program\r
+ * specific hardware\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * void\r
+ * \r
+ */\r
+ \r
+\r
+ static void sysInit(void)\r
+{\r
+ lowInit(); // setup clocks and processor port pins\r
+ \r
+ // set the interrupt controller defaults\r
+#define RAM_RUN\r
+#if defined(RAM_RUN)\r
+ MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM\r
+#elif defined(ROM_RUN)\r
+ MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH\r
+#else\r
+#error RUN_MODE not defined!\r
+#endif\r
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts\r
+ VICIntSelect = 0x00000000; // clear all FIQ selections\r
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()\r
+ \r
+ \r
+}\r
+ \r
+ /**\r
+ * Creates a delay\r
+ * @param d duration (unit not defined yet)\r
+ */\r
+void\r
+ delay(int d)\r
+{\r
+ volatile int x;\r
+ int i;\r
+ for (i = 0; i < 10; i++)\r
+ for(x = d; x; --x)\r
+ ;\r
+}\r
+ \r
+ \r
+\r
+ /**\r
+ * this function has been created to test PWM unit of the ARM Board\r
+ * It has been tested with the DC motor of M.Sojka ;-)\r
+ * One decelerated phase with upward rotation then one accelerated speed phase with backward rotation\r
+ * DC motor pin 2 = PWM2\r
+ * DC motor pin 3 = PWM4\r
+ * DC motor pin 25 = GND\r
+ * @return \r
+ */\r
+ int main() {\r
+ \r
+ int j;\r
+ \r
+ \r
+ sysInit();\r
+ \r
+ Init_PWM(20000);\r
+ Run_PWM();\r
+ Set_PWM(2,0);\r
+ Set_PWM(4,0);\r
+ for (j = 0 ; j < 10 ; j++) \r
+ {\r
+ Set_PWM (4, (9-j)*0.1);\r
+ delay (500000);\r
+ }\r
+ for (j = 0 ; j < 10 ; j++) \r
+ {\r
+ Set_PWM (2, j*0.1);\r
+ delay (500000);\r
+ }\r
+ \r
+ \r
+ Stop_PWM();\r
+ \r
+ while (1) \r
+ { /* Loop forever */\r
+ \r
+ }\r
+ return 0;\r
+ }\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = test_uart
+
+test_uart_SOURCES = uart_test.c uartx.c
+
+# Switch off compiler optimization and debug info.
+#OPTIMIZE=
+#DEBUG=
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides information about the project configuration\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_CONFIG_H\r
+#define INC_CONFIG_H\r
+\r
+#include "types.h"\r
+#include "LPC210x.h"\r
+\r
+// some handy DEFINES\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#ifndef TRUE\r
+#define TRUE !FALSE\r
+#endif\r
+#endif\r
+\r
+#ifndef BIT\r
+#define BIT(n) (1 << (n))\r
+#endif\r
+\r
+// declare functions and values from crt0.S & the linker control file\r
+extern void reset(void);\r
+// extern void exit(void);\r
+extern void abort(void);\r
+// maybe add interrupt vector addresses\r
+\r
+#define HOST_BAUD (115200)\r
+\r
+#define WDOG()\r
+\r
+// PLL setup values are computed within the LPC include file\r
+// It relies upon the following defines\r
+#define FOSC (7372800) // Master Oscillator Freq.\r
+#define PLL_MUL (4) // PLL Multiplier\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+\r
+// Pheripheral Bus Speed Divider\r
+#define PBSD 2 // MUST BE 1, 2, or 4\r
+#define PCLK (CCLK / PBSD) // Pheripheal Bus Clock Freq.\r
+\r
+// Do some value range testing\r
+#if ((FOSC < 10000000) || (FOSC > 25000000))\r
+//#error Fosc out of range (10MHz-25MHz)\r
+//#error correct and recompile\r
+#endif\r
+\r
+#if ((CCLK < 10000000) || (CCLK > 60000000))\r
+#error cclk out of range (10MHz-60MHz)\r
+#error correct PLL_MUL and recompile\r
+#endif\r
+\r
+#if ((FCCO < 150000000) || (FCCO > 320000000))\r
+#error Fcco out of range (156MHz-320MHz)\r
+#error internal algorithm error\r
+#endif\r
+\r
+#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))\r
+#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)\r
+#endif\r
+\r
+// The following are for the Olimex LPC-P2106 TESTER Board\r
+// Port Bit Definitions & Macros: Description - initial conditions\r
+#define TXD0_BIT BIT(0) // used by UART0\r
+#define RXD0_BIT BIT(1) // used by UART0\r
+#define P02_UNUSED_BIT BIT(2) // P0.02 unused - low output\r
+#define P03_UNUSED_BIT BIT(3) // P0.03 unused - low output\r
+#define P04_UNUSED_BIT BIT(4) // P0.04 unused - low output\r
+#define P05_UNUSED_BIT BIT(5) // P0.05 unused - low output\r
+#define P06_UNUSED_BIT BIT(6) // P0.06 unused - low output\r
+#define LED1_BIT BIT(7) // LED 1 - active low output\r
+#define P08_UNUSED_BIT BIT(8) // P0.08 unused - low output\r
+#define P09_UNUSED_BIT BIT(9) // P0.09 unused - low output\r
+#define P10_UNUSED_BIT BIT(10) // P0.10 unused - low output\r
+#define P11_UNUSED_BIT BIT(11) // P0.11 unused - low output\r
+#define P12_UNUSED_BIT BIT(12) // P0.12 unused - low output\r
+#define P13_UNUSED_BIT BIT(13) // P0.13 unused - low output\r
+#define P14_UNUSED_BIT BIT(14) // P0.14 unused - low output\r
+#define P15_UNUSED_BIT BIT(15) // P0.15 unused - low output\r
+#define P16_UNUSED_BIT BIT(16) // P0.16 unused - low output\r
+#define P17_UNUSED_BIT BIT(17) // used by JTAG\r
+#define P18_UNUSED_BIT BIT(18) // used by JTAG\r
+#define P19_UNUSED_BIT BIT(19) // used by JTAG\r
+#define P20_UNUSED_BIT BIT(20) // used by JTAG\r
+#define P21_UNUSED_BIT BIT(21) // used by JTAG\r
+#define P22_UNUSED_BIT BIT(22) // P0.22 unused - low output\r
+#define P23_UNUSED_BIT BIT(23) // P0.23 unused - low output\r
+#define P24_UNUSED_BIT BIT(24) // P0.24 unused - low output\r
+#define P25_UNUSED_BIT BIT(25) // P0.25 unused - low output\r
+#define P26_UNUSED_BIT BIT(26) // P0.26 unused - low output\r
+#define P27_UNUSED_BIT BIT(27) // P0.27 unused - low output\r
+#define P28_UNUSED_BIT BIT(28) // P0.28 unused - low output\r
+#define P29_UNUSED_BIT BIT(29) // P0.29 unused - low output\r
+#define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output\r
+#define SW1_BIT BIT(31) // Switch 1 - active low input\r
+\r
+#define PIO_INPUT_BITS (uint32_t) ( \\r
+ SW1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ZERO_BITS (uint32_t) ( \\r
+ P02_UNUSED_BIT | \\r
+ P03_UNUSED_BIT | \\r
+ P04_UNUSED_BIT | \\r
+ P05_UNUSED_BIT | \\r
+ P06_UNUSED_BIT | \\r
+ P08_UNUSED_BIT | \\r
+ P09_UNUSED_BIT | \\r
+ P10_UNUSED_BIT | \\r
+ P11_UNUSED_BIT | \\r
+ P12_UNUSED_BIT | \\r
+ P13_UNUSED_BIT | \\r
+ P14_UNUSED_BIT | \\r
+ P15_UNUSED_BIT | \\r
+ P16_UNUSED_BIT | \\r
+ P22_UNUSED_BIT | \\r
+ P23_UNUSED_BIT | \\r
+ P24_UNUSED_BIT | \\r
+ P25_UNUSED_BIT | \\r
+ P26_UNUSED_BIT | \\r
+ P27_UNUSED_BIT | \\r
+ P28_UNUSED_BIT | \\r
+ P29_UNUSED_BIT | \\r
+ P30_UNUSED_BIT | \\r
+ 0 )\r
+\r
+#define PIO_ONE_BITS (uint32_t) ( \\r
+ LED1_BIT | \\r
+ 0 )\r
+\r
+#define PIO_OUTPUT_BITS (uint32_t) ( \\r
+ PIO_ZERO_BITS | \\r
+ PIO_ONE_BITS )\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides interface routines to the LPC ARM UARTs.\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ * reduced to see what has to be done for minimum UART-support by mthomas\r
+ *****************************************************************************/\r
+\r
+// #warning "this is a reduced version of the R O Software code"\r
+\r
+#include "uart.h"\r
+\r
+/* on LPC210x: UART0 TX-Pin=P0.2, RX-Pin=P0.1 \r
+ PINSEL0 has to be set to "UART-Function" = Function "01" \r
+ for Pin 0.0 and 0.1 */\r
+ \r
+#define PINSEL_BITPIN0 0\r
+#define PINSEL_BITPIN1 2\r
+// #define PINSEL_BITPIN2 4\r
+#define PINSEL_FIRST_ALT_FUNC 1\r
+// #define PINSEL_SECOND_ALT_FUNC 2\r
+\r
+// Values of Bits 0-3 in PINSEL to activate UART0\r
+#define UART0_PINSEL ((PINSEL_FIRST_ALT_FUNC<<PINSEL_BITPIN0)|(PINSEL_FIRST_ALT_FUNC<<PINSEL_BITPIN1))\r
+// Mask of Bits 0-4\r
+#define UART0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */\r
+\r
+// U0_LCR devisor latch bit \r
+#define UART0_LCR_DLAB 7\r
+\r
+/* baudrate divisor - use UART_BAUD macro\r
+ * mode - see typical modes (uart.h)\r
+ * fmode - see typical fmodes (uart.h)\r
+ * NOTE: uart0Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8); \r
+ */\r
+void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)\r
+{\r
+ // setup Pin Function Select Register (Pin Connect Block) \r
+ // make sure old values of Bits 0-4 are masked out and\r
+ // set them according to UART0-Pin-Selection\r
+/* PCB_PINSEL0 = (PCB_PINSEL0 & ~UART0_PINMASK) | UART0_PINSEL; */\r
+\r
+ U0IER = 0x00; // disable all interrupts\r
+ U0IIR = 0x00; // clear interrupt ID register\r
+ U0LSR = 0x00; // clear line status register\r
+\r
+ // set the baudrate - DLAB must be set to access DLL/DLM\r
+ U0LCR = (1<<UART0_LCR_DLAB); // set divisor latches (DLAB)\r
+ U0DLL = (uint8_t)baud; // set for baud low byte\r
+ U0DLM = (uint8_t)(baud >> 8); // set for baud high byte\r
+ \r
+ // set the number of characters and other\r
+ // user specified operating parameters\r
+ // Databits, Parity, Stopbits - Settings in Line Control Register\r
+ U0LCR = (mode & ~(1<<UART0_LCR_DLAB)); // clear DLAB "on-the-fly"\r
+ // setup FIFO Control Register (fifo-enabled + xx trig) \r
+ U0FCR = fmode;\r
+}\r
+\r
+int uart0Putch(int ch)\r
+{\r
+ while (!(U0LSR & ULSR_THRE)) // wait for TX buffer to empty\r
+ continue; // also either WDOG() or swap()\r
+\r
+ U0THR = (uint8_t)ch; // put char to Transmit Holding Register\r
+ return (uint8_t)ch; // return char ("stdio-compatible"?)\r
+}\r
+\r
+const char *uart0Puts(const char *string)\r
+{\r
+ char ch;\r
+ \r
+ while ((ch = *string)) {\r
+ if (uart0Putch(ch)<0) break;\r
+ string++;\r
+ }\r
+ \r
+ return string;\r
+}\r
+\r
+int uart0TxEmpty(void)\r
+{\r
+ return (U0LSR & (ULSR_THRE | ULSR_TEMT)) == (ULSR_THRE | ULSR_TEMT);\r
+}\r
+\r
+void uart0TxFlush(void)\r
+{\r
+ U0FCR |= UFCR_TX_FIFO_RESET; // clear the TX fifo\r
+}\r
+\r
+\r
+/* Returns: character on success, -1 if no character is available */\r
+int uart0Getch(void)\r
+{\r
+ if (U0LSR & ULSR_RDR) // check if character is available\r
+ return U0RBR; // return character\r
+\r
+ return -1;\r
+}\r
--- /dev/null
+/******************************************************************************\r
+ * based on software from:\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ * \r
+ * reduced to learn what has to be done to enable and use UART0\r
+ *****************************************************************************/\r
+#ifndef INC_UART_H\r
+#define INC_UART_H\r
+\r
+#include <types.h>\r
+#include <LPC210x.h>\r
+\r
+#include "lpcUART.h"\r
+#include "config.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// use the following macros to determine the 'baud' parameter values\r
+// for uart0Init() and uart1Init()\r
+// CAUTION - 'baud' SHOULD ALWAYS BE A CONSTANT or\r
+// a lot of code will be generated.\r
+// Baud-Rate is calculated based on pclk (VPB-clock)\r
+// the devisor must be 16 times the desired baudrate\r
+#define UART_BAUD(baud) (uint16_t)(((FOSC*PLL_MUL/PBSD) / ((baud) * 16.0)) + 0.5)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'baud' settings\r
+#define B1200 UART_BAUD(1200)\r
+#define B9600 UART_BAUD(9600)\r
+#define B19200 UART_BAUD(19200)\r
+#define B38400 UART_BAUD(38400)\r
+#define B57600 UART_BAUD(57600)\r
+#define B115200 UART_BAUD(115200)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'mode' settings\r
+#define UART_8N1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_7N1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_8N2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_7N2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_8E1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_7E1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_8E2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_7E2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_8O1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_7O1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_8O2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+#define UART_7O2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'fmode' settings\r
+#define UART_FIFO_OFF (0x00)\r
+#define UART_FIFO_1 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG1)\r
+#define UART_FIFO_4 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG4)\r
+#define UART_FIFO_8 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG8)\r
+#define UART_FIFO_14 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG14)\r
+\r
+void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode);\r
+int uart0Putch(int ch);\r
+uint16_t uart0Space(void);\r
+const char *uart0Puts(const char *string);\r
+int uart0TxEmpty(void);\r
+void uart0TxFlush(void);\r
+int uart0Getch(void);\r
+\r
+#endif\r
--- /dev/null
+#include <LPC210x.h>
+#include "uartx.h"
+
+
+
+/**
+ * Function Name: lowInit()
+ *
+* Description:
+ * This function starts up the PLL then sets up the GPIO pins before
+ * waiting for the PLL to lock. It finally engages the PLL and
+ * returns
+ *
+* Calling Sequence:
+ * void
+ *
+* Returns:
+ * void
+ *
+ */
+static void lowInit(void)
+{
+ // set PLL multiplier & divisor.
+ // values computed from config.h
+ PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;
+
+ // enable PLL
+ PLLCON = PLLCON_PLLE;
+ PLLFEED = 0xAA; // Make it happen. These two updates
+ PLLFEED = 0x55; // MUST occur in sequence.
+
+ // setup the parallel port pin
+ IOCLR = PIO_ZERO_BITS; // clear the ZEROs output
+ IOSET = PIO_ONE_BITS; // set the ONEs output
+ IODIR = PIO_OUTPUT_BITS; // set the output bit direction
+
+ // wait for PLL lock
+ while (!(PLLSTAT & PLLSTAT_LOCK))
+ continue;
+
+ // enable & connect PLL
+ PLLCON = PLLCON_PLLE | PLLCON_PLLC;
+ PLLFEED = 0xAA; // Make it happen. These two updates
+ PLLFEED = 0x55; // MUST occur in sequence.
+
+ // setup & enable the MAM
+ MAMTIM = MAMTIM_CYCLES;
+ MAMCR = MAMCR_FULL;
+
+ // set the peripheral bus speed
+ // value computed from config.h
+ VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed
+}
+
+
+/**
+ * Function Name: sysInit()
+ *
+* Description:
+ * This function is responsible for initializing the program
+ * specific hardware
+ *
+* Calling Sequence:
+ * void
+ *
+* Returns:
+ * void
+ *
+ */
+static void sysInit(void)
+{
+ lowInit(); // setup clocks and processor port pins
+
+ MEMMAP = 1; // map interrupt vectors space into FLASH
+
+ VICIntEnClear = 0xFFFFFFFF; // clear all interrupts
+ VICIntSelect = 0x00000000; // clear all FIQ selections
+ VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset()
+
+}
+
+
+
+/**
+ * Creates a delay
+ * @param d duration (unit not defined yet)
+ */
+void
+ delay(int d)
+{
+ volatile int x;
+ int i;
+ for (i = 0; i < 10; i++)
+ for(x = d; x; --x)
+ ;
+}
+
+#define NUM_LEDS 4
+static int leds[] = { 0x10000, 0x20000, 0x40000, 0x80000 };
+
+/*////////////////////////////LEDS INITIALISATION///////////////////////*/
+
+/**
+ * Initializes leds.
+ */
+static void ledInit()
+{
+ IODIR |= 0x000F0000; /*leds connected to P0.16 17 18 & 19 should blink*/
+ IOSET = 0x00000000; /* all leds are switched off */
+}
+
+/**
+ * Switches the leds off.
+ * @param led switched off led number. (integer)
+ */
+static void ledOff(int led) /* Ioclr.i =1 => IOset.i cleared */
+{
+ IOCLR = led;
+}
+
+/**
+ * Switches the leds on.
+ * @param led switched on led number. (integer)
+ */
+static void ledOn(int led) /* Ioset.i = 1 => P0.i = 1 */
+{
+ IOSET = led;
+}
+
+
+
+
+/**
+ * this program uses UART1 to print hello as a test word
+ * if everything is correct, leds 0 and 1 should be switched on
+ * then the program ask to type a word and print it continuously (led 0 blinks at each write)
+ * @param
+ * @return
+ */
+int main(void)
+{
+ int i = 0;
+ int written_int_word = -1;
+ char *testword = "hello";
+
+ sysInit();
+
+ ledInit();
+ ledOn(leds[0]);
+
+
+ uartInit(UART_SEL1, B9600 , UART_8N1, UART_FIFO_8);
+
+
+ ledOn(leds[1]);
+
+ uartPutch(UART_SEL1, '\n');
+ uartPuts( UART_SEL1, testword);
+
+ uartPuts( UART_SEL1, "\nPlease write one character:");
+
+ uartPutch(UART_SEL1, '\n');
+ while(written_int_word == -1)
+ written_int_word = uartGetch(UART_SEL1);
+
+
+ while(1)
+ {
+ if (i++ & 1) ledOn(leds[0]);
+ else ledOff(leds[0]);
+ uartPutch(UART_SEL1, written_int_word);
+ delay(200000);
+
+ }
+
+ return 0;
+ }
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides interface routines to the LPC ARM UARTs.\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ * reduced to see what has to be done for minimum UART-support by mthomas\r
+ *****************************************************************************/\r
+\r
+// #warning "this is a reduced version of the R O Software code"\r
+\r
+#include "uartx.h"\r
+\r
+#define UART_LCR_DLAB 7\r
+\r
+/**\r
+ * initializes the desired UART perpipheral\r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ * @param baud Baud rate (see uart.h for the type used - use UART_BAUD macro)\r
+ * @param mode mode - see typical modes (uart.h)\r
+ * @param fmode fmode - see typical fmodes (uart.h)\r
+ * NOTE: uartInit (UART_SEL0,B9600 , UART_8N1, UART_FIFO_8); to use UART0\r
+ */\r
+void uartInit(int uart, uint16_t baud, uint8_t mode, uint8_t fmode)\r
+{\r
+ // setup Pin Function Select Register (Pin Connect Block) \r
+ // make sure old values of Bits 0-4 are masked out and\r
+ // set them according to UART0-Pin-Selectio\r
+ \r
+ \r
+ if (uart == UART_SEL0)\r
+ PINSEL0 |= 0x5;\r
+ \r
+ else if (uart == UART_SEL1)\r
+ PINSEL0 |= 0x50000;\r
+ \r
+ \r
+ \r
+ URET(U0IER) = 0x00; // disable all interrupts\r
+ URET(U0IIR) = 0x00; // clear interrupt ID register\r
+ URET(U0LSR) = 0x00; // clear line status register\r
+\r
+ // set the baudrate - DLAB must be set to access DLL/DLM\r
+\r
+ URET(U0LCR) = (1<<UART_LCR_DLAB); // set divisor latches (DLAB)\r
+ \r
+ URET(U0DLL) = (uint8_t)baud; // set for baud low byte\r
+ URET(U0DLM) = (uint8_t)(baud >> 8); // set for baud high byte\r
+ \r
+ // set the number of characters and other\r
+ // user specified operating parameters\r
+ // Databits, Parity, Stopbits - Settings in Line Control Register\r
+ URET(U0LCR) = (mode & ~(1<<UART_LCR_DLAB)); // clear DLAB "on-the-fly"\r
+ // setup FIFO Control Register (fifo-enabled + xx trig) \r
+ URET(U0FCR) = fmode;\r
+}\r
+\r
+/**\r
+ * prints one character on the desired UART peripheral\r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ * @param ch one character\r
+ * @return return char type: uint8_t\r
+ */\r
+int uartPutch(int uart, int ch)\r
+{\r
+ while (!(URET(U0LSR) & ULSR_THRE)) // wait for TX buffer to empty\r
+ continue; // also either WDOG() or swap()\r
+\r
+ URET(U0THR) = (uint8_t)ch; // put char to Transmit Holding Register\r
+ return (uint8_t)ch; // return char ("stdio-compatible"?)\r
+}\r
+\r
+/**\r
+ * writes a string\r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ * @param string \r
+ * @return \r
+ */\r
+const char *uartPuts(int uart, const char *string)\r
+{\r
+ char ch ;\r
+ \r
+ while ((ch = *string)) {\r
+ if (uartPutch( uart, ch)<0) break;\r
+ string++;\r
+ }\r
+ \r
+ return string;\r
+}\r
+\r
+\r
+/**\r
+ * checks if buffers are empty\r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ * @return 1 if empty ; stg else if not\r
+ */\r
+int uartTxEmpty(int uart)\r
+{\r
+ return (URET(U0LSR) & (ULSR_THRE | ULSR_TEMT)) == (ULSR_THRE | ULSR_TEMT);\r
+}\r
+\r
+/**\r
+ * Clears the TX fifo\r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ */\r
+void uartTxFlush(int uart)\r
+{\r
+ URET(U0FCR) |= UFCR_TX_FIFO_RESET; // clear the TX fifo\r
+}\r
+\r
+\r
+\r
+/**\r
+ * \r
+ * @param uart UART_SEL0 for UART0 and UART_SEL1 for UART1\r
+ * @return character on success, -1 if no character is available\r
+ */\r
+int uartGetch(int uart)\r
+{\r
+ if (URET(U0LSR) & ULSR_RDR) // check if character is available\r
+ return URET(U0RBR); // return character\r
+\r
+ return -1;\r
+}\r
--- /dev/null
+/******************************************************************************\r
+ * generic package for the use of UART0 or UART1\r
+ *In each function the UART in use must be noticed by UART_SEL0 or UART_SEL1\r
+ *\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_UART_H\r
+#define INC_UART_H\r
+\r
+#include <types.h>\r
+#include <LPC210x.h>\r
+\r
+#include "lpcUART.h"\r
+#include "config.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// use the following macros to determine the 'baud' parameter values\r
+// for uartInit()\r
+// CAUTION - 'baud' SHOULD ALWAYS BE A CONSTANT or\r
+// a lot of code will be generated.\r
+// Baud-Rate is calculated based on pclk (VPB-clock)\r
+// the devisor must be 16 times the desired baudrate\r
+#define UART_BAUD(baud) (uint16_t)(((FOSC*PLL_MUL/PBSD) / ((baud) * 16.0)) + 0.5)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'baud' settings\r
+#define B1200 UART_BAUD(1200)\r
+#define B9600 UART_BAUD(9600)\r
+#define B19200 UART_BAUD(19200)\r
+#define B38400 UART_BAUD(38400)\r
+#define B57600 UART_BAUD(57600)\r
+#define B115200 UART_BAUD(115200)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'mode' settings\r
+#define UART_8N1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_7N1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_1)\r
+#define UART_8N2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_7N2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_NO + ULCR_STOP_2)\r
+#define UART_8E1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_7E1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_1)\r
+#define UART_8E2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_7E2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_EVEN + ULCR_STOP_2)\r
+#define UART_8O1 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_7O1 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_1)\r
+#define UART_8O2 (uint8_t)(ULCR_CHAR_8 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+#define UART_7O2 (uint8_t)(ULCR_CHAR_7 + ULCR_PAR_ODD + ULCR_STOP_2)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Definitions for typical UART 'fmode' settings\r
+#define UART_FIFO_OFF (0x00)\r
+#define UART_FIFO_1 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG1)\r
+#define UART_FIFO_4 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG4)\r
+#define UART_FIFO_8 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG8)\r
+#define UART_FIFO_14 (uint8_t)(UFCR_FIFO_ENABLE + UFCR_FIFO_TRIG14)\r
+\r
+\r
+#define UART_SEL0 (0) \r
+#define UART_SEL1 (&U1THR - &U0THR) \r
+#define URET(REG) (*(& REG + uart)) \r
+/* with UART_SEL0 (0) register adresses of UART0*/ \r
+/* UART_SEL1 (&U1THR - &U0THR) offset between UART0 and UART1 regiser adresses*/ \r
+/* URET(REG) (*(& REG + uart)) this function allows add the offset to the register address \r
+ in order to use UART0 if uart = UART_SEL0 \r
+ or UART1 if uart = UART_SEL1 */\r
+\r
+void uartInit(int uart, uint16_t baud, uint8_t mode, uint8_t fmode);\r
+int uartPutch(int uart, int ch);\r
+\r
+\r
+const char *uartPuts( int uart, const char *string);\r
+int uartTxEmpty(int uart);\r
+void uartTxFlush(int uart);\r
+int uartGetch(int uart);\r
+\r
+#endif\r
--- /dev/null
+../common/arch/Makefile
\ No newline at end of file
--- /dev/null
+../common/arch/Makefile.omk
\ No newline at end of file
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = generic mach-$(MACH)
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+#ifndef _ARM_CPU_DEF_H
+#define _ARM_CPU_DEF_H
+
+struct pt_regs {
+ long uregs[18];
+};
+
+#define ARM_cpsr uregs[16]
+#define ARM_pc uregs[15]
+#define ARM_lr uregs[14]
+#define ARM_sp uregs[13]
+#define ARM_ip uregs[12]
+#define ARM_fp uregs[11]
+#define ARM_r10 uregs[10]
+#define ARM_r9 uregs[9]
+#define ARM_r8 uregs[8]
+#define ARM_r7 uregs[7]
+#define ARM_r6 uregs[6]
+#define ARM_r5 uregs[5]
+#define ARM_r4 uregs[4]
+#define ARM_r3 uregs[3]
+#define ARM_r2 uregs[2]
+#define ARM_r1 uregs[1]
+#define ARM_r0 uregs[0]
+#define ARM_ORIG_r0 uregs[17]
+
+struct undef_hook {
+ struct undef_hook *next;
+ unsigned long instr_mask;
+ unsigned long instr_val;
+ unsigned long cpsr_mask;
+ unsigned long cpsr_val;
+ int (*fn)(struct pt_regs *regs, unsigned int instr);
+};
+
+int register_undef_hook(struct undef_hook *hook);
+
+#define NR_IRQS 256
+
+typedef struct irq_handler {
+ void (*handler)(int, void *, struct pt_regs *);
+ unsigned long flags;
+ void *dev_id;
+ const char *devname;
+ struct irq_handler *next;
+ short vectno;
+} irq_handler_t;
+
+#define IRQH_ON_LIST 0x100 /* handler is used */
+
+extern irq_handler_t *irq_array[NR_IRQS];
+extern void *irq_vec[NR_IRQS];
+
+int add_irq_handler(int vectno,irq_handler_t *handler);
+
+int del_irq_handler(int vectno,irq_handler_t *handler);
+
+int test_irq_handler(int vectno,const irq_handler_t *handler);
+
+void irq_redirect2vector(int vectno,struct pt_regs *regs);
+
+/* IRQ handling code */
+
+#define sti() \
+ ({ \
+ unsigned long temp; \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ sti\n" \
+" bic %0, %0, #128\n" \
+" msr cpsr_c, %0" \
+ : "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define cli() \
+ ({ \
+ unsigned long temp; \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ cli\n" \
+" orr %0, %0, #128\n" \
+" msr cpsr_c, %0" \
+ : "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define save_and_cli(flags) \
+ ({ \
+ unsigned long temp; \
+ (void) (&temp == &flags); \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ save_and_cli\n" \
+" orr %1, %0, #128\n" \
+" msr cpsr_c, %1" \
+ : "=r" (flags), "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define save_flags(flags) \
+ ({ \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ save_flags\n" \
+ : "=r" (flags) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define restore_flags(flags) \
+ __asm__ __volatile__( \
+ "msr cpsr_c, %0 @ restore_flags\n" \
+ : \
+ : "r" (flags) \
+ : "memory", "cc")
+
+
+/* FIQ handling code */
+
+#define fiq_sti() \
+ ({ \
+ unsigned long temp; \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ sti\n" \
+" bic %0, %0, #64\n" \
+" msr cpsr_c, %0" \
+ : "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define fiq_cli() \
+ ({ \
+ unsigned long temp; \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ cli\n" \
+" orr %0, %0, #64\n" \
+" msr cpsr_c, %0" \
+ : "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+#define fiq_save_and_cli(flags) \
+ ({ \
+ unsigned long temp; \
+ (void) (&temp == &flags); \
+ __asm__ __volatile__( \
+ "mrs %0, cpsr @ save_and_cli\n" \
+" orr %1, %0, #192\n" \
+" msr cpsr_c, %1" \
+ : "=r" (flags), "=r" (temp) \
+ : \
+ : "memory", "cc"); \
+ })
+
+void __cpu_coherent_range(unsigned long start, unsigned long end);
+
+static inline void flush_icache_range(unsigned long start, unsigned long end)
+{
+ __cpu_coherent_range(start, end);
+}
+
+/* atomic access routines */
+
+//typedef unsigned long atomic_t;
+
+static inline void atomic_clear_mask(unsigned long mask, volatile unsigned long *addr)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ *addr &= ~mask;
+ restore_flags(flags);
+}
+
+static inline void atomic_set_mask(unsigned long mask, volatile unsigned long *addr)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ *addr |= mask;
+ restore_flags(flags);
+}
+
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ *addr |= 1<<nr;
+ restore_flags(flags);
+}
+
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ *addr &= ~(1<<nr);
+ restore_flags(flags);
+}
+
+static inline int test_bit(int nr, volatile unsigned long *addr)
+{
+ return ((*addr) & (1<<nr))?1:0;
+}
+
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long flags;
+ long m=(1<<nr);
+ long r;
+
+ save_and_cli(flags);
+ r=*addr;
+ *addr=r|m;
+ restore_flags(flags);
+ return r&m?1:0;
+}
+
+#define __memory_barrier() \
+ __asm__ __volatile__("": : : "memory")
+
+/*masked fields macros*/
+
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+
+static inline void outb(int port, int val) {
+ *(volatile unsigned char *)(port)=val;
+}
+
+static inline unsigned char inb(int port) {
+ return *(volatile unsigned char *)(port);
+}
+
+#endif /* _ARM_CPU_DEF_H */
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __BIT_TYPES_DEFINED__
+#define __BIT_TYPES_DEFINED__
+
+typedef __u8 uint8_t;
+typedef __s8 int8_t;
+typedef __u16 uint16_t;
+typedef __s16 int16_t;
+typedef __u32 uint32_t;
+typedef __s32 int32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __s64 int64_t;
+typedef __u64 uint64_t;
+#endif
+
+#endif /* !(__BIT_TYPES_DEFINED__) */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef __s8 s8;
+typedef __u8 u8;
+
+typedef __s16 s16;
+typedef __u16 u16;
+
+typedef __s32 s32;
+typedef __u32 u32;
+
+typedef __s64 s64;
+typedef __s64 u64;
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+typedef u32 dma64_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif
+
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = misc
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+include_HEADERS = system_stub.h
+
+lib_LIBRARIES = arch
+
+arch_SOURCES = system_stub.c
+
+lib_obj_SOURCES = system_stub.c
--- /dev/null
+/* Support files for GNU libc. Files in the system namespace go here.
+ Files in the C namespace (ie those that do not start with an
+ underscore) go in .c. */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/fcntl.h>
+#include <stdio.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <errno.h>
+#include <reent.h>
+#include <system_def.h>
+
+/* Register name faking - works in collusion with the linker. */
+register char * stack_ptr asm ("sp");
+
+system_stub_ops_t system_stub_ops;
+
+int
+_read (int file,
+ char * ptr,
+ int len)
+{
+ if(!system_stub_ops.read)
+ return -1;
+ return system_stub_ops.read(file,ptr,len);
+}
+
+int
+_write (int file,
+ char * ptr,
+ int len)
+{
+ if(!system_stub_ops.write)
+ return len;
+ return system_stub_ops.write(file,ptr,len);
+}
+
+
+int
+_lseek (int file,
+ int pos,
+ int dir)
+{
+ if(!system_stub_ops.lseek)
+ return -1;
+ return system_stub_ops.lseek(file,pos,dir);
+}
+
+int
+_open (const char * path,
+ int flags,
+ ...)
+{
+ if(!system_stub_ops.open)
+ return -1;
+ return system_stub_ops.open(path,flags,0);
+}
+
+int
+_close (int file)
+{
+ if(!system_stub_ops.close)
+ return -1;
+ return system_stub_ops.close(file);
+}
+
+typedef int (local_call_t)(void);
+
+void
+_exit (int n)
+{
+ ((local_call_t*)0)();
+ while(1);
+}
+
+int
+_kill (int n, int m)
+{
+ return -1;
+}
+
+int
+_getpid (int n)
+{
+ return 1;
+}
+
+
+caddr_t
+_sbrk (int incr)
+{
+ extern char end asm ("end"); /* Defined by the linker. */
+ static char *heap_end;
+ char * prev_heap_end;
+
+ incr=(incr+3) & ~3;
+
+ if (heap_end == NULL)
+ heap_end = & end;
+
+ prev_heap_end = heap_end;
+
+ if (heap_end + incr > stack_ptr)
+ {
+ /* Some of the libstdc++-v3 tests rely upon detecting
+ out of memory errors, so do not abort here. */
+#if 0
+ extern void abort (void);
+
+ _write (1, "_sbrk: Heap and stack collision\n", 32);
+
+ abort ();
+#else
+ errno = ENOMEM;
+ return (caddr_t) -1;
+#endif
+ }
+
+ heap_end += incr;
+
+ return (caddr_t) prev_heap_end;
+}
+
+int
+_fstat (int file, struct stat * st)
+{
+ return -1;
+}
+
+int _stat (const char *fname, struct stat *st)
+{
+ return -1;
+}
+
+int
+_link (void)
+{
+ return -1;
+}
+
+int
+_unlink (void)
+{
+ return -1;
+}
+
+void
+_raise (void)
+{
+ return;
+}
+
+int
+_gettimeofday (struct timeval * tp, struct timezone * tzp)
+{
+
+ if(tp)
+ {
+ tp->tv_sec = 0;
+ tp->tv_usec = 0;
+ }
+ /* Return fixed data for the timezone. */
+ if (tzp)
+ {
+ tzp->tz_minuteswest = 0;
+ tzp->tz_dsttime = 0;
+ }
+
+ return 0;
+}
+
+/* Return a clock that ticks at 100Hz. */
+clock_t
+_times (struct tms * tp)
+{
+ clock_t timeval = 0;
+
+ if (tp)
+ {
+ tp->tms_utime = timeval; /* user time */
+ tp->tms_stime = 0; /* system time */
+ tp->tms_cutime = 0; /* user time, children */
+ tp->tms_cstime = 0; /* system time, children */
+ }
+
+ return timeval;
+};
+
+
+int
+isatty (int fd)
+{
+ return 1;
+}
+
+int
+_system (const char *s)
+{
+ return -1;
+}
+
+int
+_rename (const char * oldpath, const char * newpath)
+{
+ return -1;
+}
--- /dev/null
+#ifndef _SYSTEM_STUB_H_
+#define _SYSTEM_STUB_H_
+
+#include <types.h>
+
+typedef struct system_stub_ops_t {
+ int (*open)(const char * path, int flags, ...);
+ int (*close)(int file);
+ int (*read)(int file, char * ptr, int len);
+ int (*write)(int file, char * ptr, int len);
+ int (*lseek)(int file, int ptr, int dir);
+} system_stub_ops_t;
+
+extern system_stub_ops_t system_stub_ops;
+
+#endif /* _SYSTEM_DEF_H_ */
--- /dev/null
+#include <cpu_def.h>
+#include <irq_def.h>
+
+static int undef_initialized = 0;
+
+static unsigned long cpu_undef_stack[256];
+
+struct undef_hook *undef_hook_chain = NULL;
+
+static void undef_exception_handler(int excptnum, struct pt_regs *regs)
+{
+ /*unsigned int correction = thumb_mode(regs) ? 2 : 4;*/
+ unsigned int correction = 0;
+ struct undef_hook *hook;
+ void *pc;
+ unsigned long instr;
+
+ regs->ARM_pc -= correction;
+
+ pc = (void *)regs->ARM_pc;
+
+ instr = *(unsigned long *)pc;
+
+ for(hook = undef_hook_chain; hook; hook = hook->next) {
+ if (((instr & hook->instr_mask) == hook->instr_val) &&
+ ((regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val)) {
+ if (hook->fn(regs, instr) == 0) {
+ return;
+ }
+ }
+ }
+
+ for(;;){
+ /* Fatal error */
+ }
+}
+
+int register_undef_hook(struct undef_hook *hook)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+
+ if(!undef_initialized) {
+ set_cpu_exception_handler(ARM_EXCEPTION_UNDEF, (long)undef_exception_handler);
+ set_cpu_exception_stack(ARM_EXCEPTION_UNDEF, (long)((char*)cpu_undef_stack+sizeof(cpu_undef_stack)-8));
+ undef_initialized = 1;
+ }
+
+ hook->next = undef_hook_chain;
+ undef_hook_chain = hook;
+ restore_flags(flags);
+
+ return 0;
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = defines tools libs
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC210x ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC210x_H\r
+#define INC_LPC210x_H\r
+\r
+#define REG_8 volatile unsigned char\r
+#define REG16 volatile unsigned short\r
+#define REG32 volatile unsigned long\r
+\r
+#include "lpcWD.h"\r
+#include "lpcTMR.h"\r
+#include "lpcUART.h"\r
+#include "lpcI2C.h"\r
+#include "lpcSPI.h"\r
+#include "lpcRTC.h"\r
+#include "lpcGPIO.h"\r
+#include "lpcPIN.h"\r
+#include "lpcSCB.h"\r
+#include "lpcVIC.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Watchdog\r
+#define WD ((wdRegs_t *)0xE0000000)\r
+\r
+// Watchdog Registers\r
+#define WDMOD WD->mod /* Watchdog Mode Register */\r
+#define WDTC WD->tc /* Watchdog Time Constant Register */\r
+#define WDFEED WD->feed /* Watchdog Feed Register */\r
+#define WDTV WD->tv /* Watchdog Time Value Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 0\r
+#define TMR0 ((pwmTmrRegs_t *)0xE0004000)\r
+\r
+// Timer 0 Registers\r
+#define T0IR TMR0->ir /* Interrupt Register */\r
+#define T0TCR TMR0->tcr /* Timer Control Register */\r
+#define T0TC TMR0->tc /* Timer Counter */\r
+#define T0PR TMR0->pr /* Prescale Register */\r
+#define T0PC TMR0->pc /* Prescale Counter Register */\r
+#define T0MCR TMR0->mcr /* Match Control Register */\r
+#define T0MR0 TMR0->mr0 /* Match Register 0 */\r
+#define T0MR1 TMR0->mr1 /* Match Register 1 */\r
+#define T0MR2 TMR0->mr2 /* Match Register 2 */\r
+#define T0MR3 TMR0->mr3 /* Match Register 3 */\r
+#define T0CCR TMR0->ccr /* Capture Control Register */\r
+#define T0CR0 TMR0->cr0 /* Capture Register 0 */\r
+#define T0CR1 TMR0->cr1 /* Capture Register 1 */\r
+#define T0CR2 TMR0->cr2 /* Capture Register 2 */\r
+#define T0CR3 TMR0->cr3 /* Capture Register 3 */\r
+#define T0EMR TMR0->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 1\r
+#define TMR1 ((pwmTmrRegs_t *)0xE0008000)\r
+\r
+// Timer 1 Registers\r
+#define T1IR TMR1->ir /* Interrupt Register */\r
+#define T1TCR TMR1->tcr /* Timer Control Register */\r
+#define T1TC TMR1->tc /* Timer Counter */\r
+#define T1PR TMR1->pr /* Prescale Register */\r
+#define T1PC TMR1->pc /* Prescale Counter Register */\r
+#define T1MCR TMR1->mcr /* Match Control Register */\r
+#define T1MR0 TMR1->mr0 /* Match Register 0 */\r
+#define T1MR1 TMR1->mr1 /* Match Register 1 */\r
+#define T1MR2 TMR1->mr2 /* Match Register 2 */\r
+#define T1MR3 TMR1->mr3 /* Match Register 3 */\r
+#define T1CCR TMR1->ccr /* Capture Control Register */\r
+#define T1CR0 TMR1->cr0 /* Capture Register 0 */\r
+#define T1CR1 TMR1->cr1 /* Capture Register 1 */\r
+#define T1CR2 TMR1->cr2 /* Capture Register 2 */\r
+#define T1CR3 TMR1->cr3 /* Capture Register 3 */\r
+#define T1EMR TMR1->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pulse Width Modulator (PWM)\r
+#define PWM ((pwmTmrRegs_t *)0xE0014000)\r
+\r
+// PWM Registers\r
+#define PWMIR PWM->ir /* Interrupt Register */\r
+#define PWMTCR PWM->tcr /* Timer Control Register */\r
+#define PWMTC PWM->tc /* Timer Counter */\r
+#define PWMPR PWM->pr /* Prescale Register */\r
+#define PWMPC PWM->pc /* Prescale Counter Register */\r
+#define PWMMCR PWM->mcr /* Match Control Register */\r
+#define PWMMR0 PWM->mr0 /* Match Register 0 */\r
+#define PWMMR1 PWM->mr1 /* Match Register 1 */\r
+#define PWMMR2 PWM->mr2 /* Match Register 2 */\r
+#define PWMMR3 PWM->mr3 /* Match Register 3 */\r
+#define PWMMR4 PWM->mr4 /* Match Register 4 */\r
+#define PWMMR5 PWM->mr5 /* Match Register 5 */\r
+#define PWMMR6 PWM->mr6 /* Match Register 6 */\r
+#define PWMPCR PWM->pcr /* Control Register */\r
+#define PWMLER PWM->ler /* Latch Enable Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 0 (UART0)\r
+#define UART0 ((uartRegs_t *)0xE000C000)\r
+#define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */\r
+#define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */\r
+\r
+// UART0 Registers\r
+#define U0RBR UART0->rbr /* Receive Buffer Register */\r
+#define U0THR UART0->thr /* Transmit Holding Register */\r
+#define U0IER UART0->ier /* Interrupt Enable Register */\r
+#define U0IIR UART0->iir /* Interrupt ID Register */\r
+#define U0FCR UART0->fcr /* FIFO Control Register */\r
+#define U0LCR UART0->lcr /* Line Control Register */\r
+#define U0LSR UART0->lsr /* Line Status Register */\r
+#define U0SCR UART0->scr /* Scratch Pad Register */\r
+#define U0DLL UART0->dll /* Divisor Latch Register (LSB) */\r
+#define U0DLM UART0->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 1 (UART1)\r
+#define UART1 ((uartRegs_t *)0xE0010000)\r
+#define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */\r
+#define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */\r
+\r
+// UART1 Registers\r
+#define U1RBR UART1->rbr /* Receive Buffer Register */\r
+#define U1THR UART1->thr /* Transmit Holding Register */\r
+#define U1IER UART1->ier /* Interrupt Enable Register */\r
+#define U1IIR UART1->iir /* Interrupt ID Register */\r
+#define U1FCR UART1->fcr /* FIFO Control Register */\r
+#define U1LCR UART1->lcr /* Line Control Register */\r
+#define U1MCR UART1->mcr /* MODEM Control Register */\r
+#define U1LSR UART1->lsr /* Line Status Register */\r
+#define U1MSR UART1->msr /* MODEM Status Register */\r
+#define U1SCR UART1->scr /* Scratch Pad Register */\r
+#define U1DLL UART1->dll /* Divisor Latch Register (LSB) */\r
+#define U1DLM UART1->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// I2C Interface\r
+#define I2C ((i2cRegs_t *)0xE001C000)\r
+\r
+// I2C Registers\r
+#define I2CONSET I2C->conset /* Control Set Register */\r
+#define I2STAT I2C->stat /* Status Register */\r
+#define I2DAT I2C->dat /* Data Register */\r
+#define I2ADR I2C->adr /* Slave Address Register */\r
+#define I2SCLH I2C->sclh /* SCL Duty Cycle Register (high half word) */\r
+#define I2SCLL I2C->scll /* SCL Duty Cycle Register (low half word) */\r
+#define I2CONCLR I2C->conclr /* Control Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Serial Peripheral Interface\r
+#define SPI ((spiRegs_t *)0xE0020000)\r
+\r
+// SPI Registers\r
+#define SPCR SPI->cr /* Control Register */\r
+#define SPSR SPI->sr /* Status Register */\r
+#define SPDR SPI->dr /* Data Register */\r
+#define SPCCR SPI->ccr /* Clock Counter Register */\r
+#define SPINT SPI->flag /* Interrupt Flag Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Real Time Clock\r
+#define RTC ((rtcRegs_t *)0xE0024000)\r
+\r
+// RTC Registers\r
+#define RTCILR RTC->ilr /* Interrupt Location Register */\r
+#define RTCCTC RTC->ctc /* Clock Tick Counter */\r
+#define RTCCCR RTC->ccr /* Clock Control Register */\r
+#define RTCCIIR RTC->ciir /* Counter Increment Interrupt Register */\r
+#define RTCAMR RTC->amr /* Alarm Mask Register */\r
+#define RTCCTIME0 RTC->ctime0 /* Consolidated Time Register 0 */\r
+#define RTCCTIME1 RTC->ctime1 /* Consolidated Time Register 1 */\r
+#define RTCCTIME2 RTC->ctime2 /* Consolidated Time Register 2 */\r
+#define RTCSEC RTC->sec /* Seconds Register */\r
+#define RTCMIN RTC->min /* Minutes Register */\r
+#define RTCHOUR RTC->hour /* Hours Register */\r
+#define RTCDOM RTC->dom /* Day Of Month Register */\r
+#define RTCDOW RTC->dow /* Day Of Week Register */\r
+#define RTCDOY RTC->doy /* Day Of Year Register */\r
+#define RTCMONTH RTC->month /* Months Register */\r
+#define RTCYEAR RTC->year /* Years Register */\r
+#define RTCALSEC RTC->alsec /* Alarm Seconds Register */\r
+#define RTCALMIN RTC->almin /* Alarm Minutes Register */\r
+#define RTCALHOUR RTC->alhour /* Alarm Hours Register */\r
+#define RTCALDOM RTC->aldom /* Alarm Day Of Month Register */\r
+#define RTCALDOW RTC->aldow /* Alarm Day Of Week Register */\r
+#define RTCALDOY RTC->aldoy /* Alarm Day Of Year Register */\r
+#define RTCALMON RTC->almon /* Alarm Months Register */\r
+#define RTCALYEAR RTC->alyear /* Alarm Years Register */\r
+#define RTCPREINT RTC->preint /* Prescale Value Register (integer) */\r
+#define RTCPREFRAC RTC->prefrac /* Prescale Value Register (fraction) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// General Purpose Input/Output\r
+#define GPIO ((gpioRegs_t *)0xE0028000)\r
+\r
+// GPIO Registers\r
+#define IOPIN GPIO->in0 /* Pin Value Register */\r
+#define IOSET GPIO->set0 /* Pin Output Set Register */\r
+#define IODIR GPIO->dir0 /* Pin Direction Register */\r
+#define IOCLR GPIO->clr0 /* Pin Output Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pin Connect Block\r
+#define PINSEL ((pinRegs_t *)0xE002C000)\r
+\r
+// Pin Connect Block Registers\r
+#define PINSEL0 PINSEL->sel0 /* Pin Function Select Register 0 */\r
+#define PINSEL1 PINSEL->sel1 /* Pin Function Select Register 1 */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// System Contol Block\r
+#define SCB ((scbRegs_t *)0xE01FC000)\r
+\r
+// Memory Accelerator Module Registers (MAM)\r
+#define MAMCR SCB->mam.cr /* Control Register */\r
+#define MAMTIM SCB->mam.tim /* Timing Control Register */\r
+\r
+// Memory Mapping Control Register\r
+#define MEMMAP SCB->memmap\r
+\r
+// Phase Locked Loop Registers (PLL)\r
+#define PLLCON SCB->pll.con /* Control Register */\r
+#define PLLCFG SCB->pll.cfg /* Configuration Register */\r
+#define PLLSTAT SCB->pll.stat /* Status Register */\r
+#define PLLFEED SCB->pll.feed /* Feed Register */\r
+\r
+// Power Control Registers\r
+#define PCON SCB->p.con /* Control Register */\r
+#define PCONP SCB->p.conp /* Peripherals Register */\r
+\r
+// VPB Divider Register\r
+#define VPBDIV SCB->vpbdiv\r
+\r
+// External Interrupt Registers\r
+#define EXTINT SCB->ext.flag /* Flag Register */\r
+#define EXTWAKE SCB->ext.wake /* Wakeup Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Vectored Interrupt Controller\r
+#define VIC ((vicRegs_t *)0xFFFFF000)\r
+\r
+// Vectored Interrupt Controller Registers\r
+#define VICIRQStatus VIC->irqStatus /* IRQ Status Register */\r
+#define VICFIQStatus VIC->fiqStatus /* FIQ Status Register */\r
+#define VICRawIntr VIC->rawIntr /* Raw Interrupt Status Register */\r
+#define VICIntSelect VIC->intSelect /* Interrupt Select Register */\r
+#define VICIntEnable VIC->intEnable /* Interrupt Enable Register */\r
+#define VICIntEnClear VIC->intEnClear /* Interrupt Enable Clear Register */\r
+#define VICSoftInt VIC->softInt /* Software Interrupt Register */\r
+#define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */\r
+#define VICProtection VIC->protection /* Protection Enable Register */\r
+#define VICVectAddr VIC->vectAddr /* Vector Address Register */\r
+#define VICDefVectAddr VIC->defVectAddr /* Default Vector Address Register */\r
+#define VICVectAddr0 VIC->vectAddr0 /* Vector Address 0 Register */\r
+#define VICVectAddr1 VIC->vectAddr1 /* Vector Address 1 Register */\r
+#define VICVectAddr2 VIC->vectAddr2 /* Vector Address 2 Register */\r
+#define VICVectAddr3 VIC->vectAddr3 /* Vector Address 3 Register */\r
+#define VICVectAddr4 VIC->vectAddr4 /* Vector Address 4 Register */\r
+#define VICVectAddr5 VIC->vectAddr5 /* Vector Address 5 Register */\r
+#define VICVectAddr6 VIC->vectAddr6 /* Vector Address 6 Register */\r
+#define VICVectAddr7 VIC->vectAddr7 /* Vector Address 7 Register */\r
+#define VICVectAddr8 VIC->vectAddr8 /* Vector Address 8 Register */\r
+#define VICVectAddr9 VIC->vectAddr9 /* Vector Address 9 Register */\r
+#define VICVectAddr10 VIC->vectAddr10 /* Vector Address 10 Register */\r
+#define VICVectAddr11 VIC->vectAddr11 /* Vector Address 11 Register */\r
+#define VICVectAddr12 VIC->vectAddr12 /* Vector Address 12 Register */\r
+#define VICVectAddr13 VIC->vectAddr13 /* Vector Address 13 Register */\r
+#define VICVectAddr14 VIC->vectAddr14 /* Vector Address 14 Register */\r
+#define VICVectAddr15 VIC->vectAddr15 /* Vector Address 15 Register */\r
+#define VICVectCntl0 VIC->vectCntl0 /* Vector Control 0 Register */\r
+#define VICVectCntl1 VIC->vectCntl1 /* Vector Control 1 Register */\r
+#define VICVectCntl2 VIC->vectCntl2 /* Vector Control 2 Register */\r
+#define VICVectCntl3 VIC->vectCntl3 /* Vector Control 3 Register */\r
+#define VICVectCntl4 VIC->vectCntl4 /* Vector Control 4 Register */\r
+#define VICVectCntl5 VIC->vectCntl5 /* Vector Control 5 Register */\r
+#define VICVectCntl6 VIC->vectCntl6 /* Vector Control 6 Register */\r
+#define VICVectCntl7 VIC->vectCntl7 /* Vector Control 7 Register */\r
+#define VICVectCntl8 VIC->vectCntl8 /* Vector Control 8 Register */\r
+#define VICVectCntl9 VIC->vectCntl9 /* Vector Control 9 Register */\r
+#define VICVectCntl10 VIC->vectCntl10 /* Vector Control 10 Register */\r
+#define VICVectCntl11 VIC->vectCntl11 /* Vector Control 11 Register */\r
+#define VICVectCntl12 VIC->vectCntl12 /* Vector Control 12 Register */\r
+#define VICVectCntl13 VIC->vectCntl13 /* Vector Control 13 Register */\r
+#define VICVectCntl14 VIC->vectCntl14 /* Vector Control 14 Register */\r
+#define VICVectCntl15 VIC->vectCntl15 /* Vector Control 15 Register */\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************
+ *
+ * $RCSfile: LPC214x.h,v $
+ * $Revision: 1.4 $
+ *
+ * Header file for Philips LPC214x ARM Processors
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * No guarantees, warrantees, or promises, implied or otherwise.
+ * May be used for hobby or commercial purposes provided copyright
+ * notice remains intact or GPL license is applied.
+ *
+ *****************************************************************************/
+
+#ifndef INC_LPC214x_H
+#define INC_LPC214x_H
+
+///////////////////////////////////////////////////////////////////////////////
+// ISP_RAM2FLASH_BLOCK_SIZE for 210x CPU
+#ifndef ISP_RAM2FLASH_BLOCK_SIZE
+ #define ISP_RAM2FLASH_BLOCK_SIZE 256
+#endif /* ISP_RAM2FLASH_BLOCK_SIZE */
+
+#include "LPC21xx.h"
+
+#include "lpcUSB.h"
+#include "lpcADC-214x.h"
+
+// USB Phase Locked Loop Registers (PLL48)
+#define PLLCON48 SCB->pll48.con /* Control Register */
+#define PLLCFG48 SCB->pll48.cfg /* Configuration Register */
+#define PLLSTAT48 SCB->pll48.stat /* Status Register */
+#define PLLFEED48 SCB->pll48.feed /* Feed Register */
+
+///////////////////////////////////////////////////////////////////////////////
+// USB Device
+
+#define USBIntSt (*(REG32*)0xE01FC1C0) /* USB Interrupt Status (R/W) */
+
+#if 1
+
+#define USB ((usbRegs_t *)0xE0090000)
+
+#define USBDevIntSt USB->DevIntSt
+#define USBDevIntEn USB->DevIntEn
+#define USBDevIntClr USB->DevIntClr
+#define USBDevIntSet USB->DevIntSet
+#define USBDevIntPri USB->DevIntPri
+#define USBEpIntSt USB->EpIntSt
+#define USBEpIntEn USB->EpIntEn
+#define USBEpIntClr USB->EpIntClr
+#define USBEpIntSet USB->EpIntSet
+#define USBEpIntPri USB->EpIntPri
+#define USBReEp USB->ReEp
+#define USBEpInd USB->EpInd
+#define USBMaxPSize USB->MaxPSize
+#define USBRxData USB->RxData
+#define USBRxPLen USB->RxPLen
+#define USBTxData USB->TxData
+#define USBTxPLen USB->TxPLen
+#define USBCtrl USB->Ctrl
+#define USBCmdCode USB->CmdCode
+#define USBCmdData USB->CmdData
+#define USBDMARSt USB->DMARSt
+#define USBDMARClr USB->DMARClr
+#define USBDMARSet USB->DMARSet
+#define USBUDCAH USB->UDCAH
+#define USBEpDMASt USB->EpDMASt
+#define USBEpDMAEn USB->EpDMAEn
+#define USBEpDMADis USB->EpDMADis
+#define USBDMAIntSt USB->DMAIntSt
+#define USBDMAIntEn USB->DMAIntEn
+#define USBEoTIntSt USB->EoTIntSt
+#define USBEoTIntClr USB->EoTIntClr
+#define USBEoTIntSet USB->EoTIntSet
+#define USBNDDRIntSt USB->NDDRIntSt
+#define USBNDDRIntClr USB->NDDRIntClr
+#define USBNDDRIntSet USB->NDDRIntSet
+#define USBSysErrIntSt USB->SysErrIntSt
+#define USBSysErrIntClr USB->SysErrIntClr
+#define USBSysErrIntSet USB->SysErrIntSet
+#define USB_MODULE_ID USB->MODULE_ID
+# else
+
+#define USB_REGS_BASE 0xE0090000
+
+#define USBDevIntSt (*(REG32*)(USB_REGS_BASE+USBDevIntSt_o))
+#define USBDevIntEn (*(REG32*)(USB_REGS_BASE+USBDevIntEn_o))
+#define USBDevIntClr (*(REG32*)(USB_REGS_BASE+USBDevIntClr_o))
+#define USBDevIntSet (*(REG32*)(USB_REGS_BASE+USBDevIntSet_o))
+#define USBDevIntPri (*(REG_8*)(USB_REGS_BASE+USBDevIntPri_o))
+#define USBEpIntSt (*(REG32*)(USB_REGS_BASE+USBEpIntSt_o))
+#define USBEpIntEn (*(REG32*)(USB_REGS_BASE+USBEpIntEn_o))
+#define USBEpIntClr (*(REG32*)(USB_REGS_BASE+USBEpIntClr_o))
+#define USBEpIntSet (*(REG32*)(USB_REGS_BASE+USBEpIntSet_o))
+#define USBEpIntPri (*(REG32*)(USB_REGS_BASE+USBEpIntPri_o))
+#define USBReEp (*(REG32*)(USB_REGS_BASE+USBReEp_o))
+#define USBEpInd (*(REG32*)(USB_REGS_BASE+USBEpInd_o))
+#define USBMaxPSize (*(REG32*)(USB_REGS_BASE+USBMaxPSize_o))
+#define USBRxData (*(REG32*)(USB_REGS_BASE+USBRxData_o))
+#define USBRxPLen (*(REG32*)(USB_REGS_BASE+USBRxPLen_o))
+#define USBTxData (*(REG32*)(USB_REGS_BASE+USBTxData_o))
+#define USBTxPLen (*(REG32*)(USB_REGS_BASE+USBTxPLen_o))
+#define USBCtrl (*(REG32*)(USB_REGS_BASE+USBCtrl_o))
+#define USBCmdCode (*(REG32*)(USB_REGS_BASE+USBCmdCode_o))
+#define USBCmdData (*(REG32*)(USB_REGS_BASE+USBCmdData_o))
+#define USBDMARSt (*(REG32*)(USB_REGS_BASE+USBDMARSt_o))
+#define USBDMARClr (*(REG32*)(USB_REGS_BASE+USBDMARClr_o))
+#define USBDMARSet (*(REG32*)(USB_REGS_BASE+USBDMARSet_o))
+#define USBUDCAH (*(REG32*)(USB_REGS_BASE+USBUDCAH_o))
+#define USBEpDMASt (*(REG32*)(USB_REGS_BASE+USBEpDMASt_o))
+#define USBEpDMAEn (*(REG32*)(USB_REGS_BASE+USBEpDMAEn_o))
+#define USBEpDMADis (*(REG32*)(USB_REGS_BASE+USBEpDMADis_o))
+#define USBDMAIntSt (*(REG32*)(USB_REGS_BASE+USBDMAIntSt_o))
+#define USBDMAIntEn (*(REG32*)(USB_REGS_BASE+USBDMAIntEn_o))
+#define USBEoTIntSt (*(REG32*)(USB_REGS_BASE+USBEoTIntSt_o))
+#define USBEoTIntClr (*(REG32*)(USB_REGS_BASE+USBEoTIntClr_o))
+#define USBEoTIntSet (*(REG32*)(USB_REGS_BASE+USBEoTIntSet_o))
+#define USBNDDRIntSt (*(REG32*)(USB_REGS_BASE+USBNDDRIntSt_o))
+#define USBNDDRIntClr (*(REG32*)(USB_REGS_BASE+USBNDDRIntClr_o))
+#define USBNDDRIntSet (*(REG32*)(USB_REGS_BASE+USBNDDRIntSet_o))
+#define USBSysErrIntSt (*(REG32*)(USB_REGS_BASE+USBSysErrIntSt_o))
+#define USBSysErrIntClr (*(REG32*)(USB_REGS_BASE+USBSysErrIntClr_o))
+#define USBSysErrIntSet (*(REG32*)(USB_REGS_BASE+USBSysErrIntSet_o))
+#define USB_MODULE_ID (*(REG32*)(USB_REGS_BASE+USB_MODULE_ID_o))
+
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////
+// A/D Converter
+#define ADC0 ((adc214xRegs_t *)0xE0034000)
+
+#define AD0CR ADC0->cr // Control Register
+#define AD0GDR ADC0->gdr // Global Data Register
+#define AD0GSR ADC0->gsr // Global Start Register
+#define AD0INTEN ADC0->inten // Interrupt Enable Register
+#define AD0DR0 ADC0->dr0 // Channel 0 Data Register
+#define AD0DR1 ADC0->dr1 // Channel 1 Data Register
+#define AD0DR2 ADC0->dr2 // Channel 2 Data Register
+#define AD0DR3 ADC0->dr3 // Channel 3 Data Register
+#define AD0DR4 ADC0->dr4 // Channel 4 Data Register
+#define AD0DR5 ADC0->dr5 // Channel 5 Data Register
+#define AD0DR6 ADC0->dr6 // Channel 6 Data Register
+#define AD0DR7 ADC0->dr7 // Channel 7 Data Register
+#define AD0STAT ADC0->stat // Status Register
+
+#define ADC1 ((adc214xRegs_t *)0xE0060000)
+
+#define AD1CR ADC0->cr // Control Register
+#define AD1GDR ADC0->gdr // Global Data Register
+#define AD1GSR ADC0->gsr // Global Start Register
+#define AD1INTEN ADC0->inten // Interrupt Enable Register
+#define AD1DR0 ADC0->dr0 // Channel 0 Data Register
+#define AD1DR1 ADC0->dr1 // Channel 1 Data Register
+#define AD1DR2 ADC0->dr2 // Channel 2 Data Register
+#define AD1DR3 ADC0->dr3 // Channel 3 Data Register
+#define AD1DR4 ADC0->dr4 // Channel 4 Data Register
+#define AD1DR5 ADC0->dr5 // Channel 5 Data Register
+#define AD1DR6 ADC0->dr6 // Channel 6 Data Register
+#define AD1DR7 ADC0->dr7 // Channel 7 Data Register
+#define AD1STAT ADC0->stat // Status Register
+
+
+#endif /*INC_LPC21xx_H*/
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC21xx ARM Processors \r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC21xx_H\r
+#define INC_LPC21xx_H\r
+\r
+#define REG_8 volatile unsigned char\r
+#define REG16 volatile unsigned short\r
+#define REG32 volatile unsigned long\r
+\r
+#include "lpcWD.h"\r
+#include "lpcTMR.h"\r
+#include "lpcUART.h"\r
+#include "lpcI2C.h"\r
+#include "lpcSPI.h"\r
+#include "lpcRTC.h"\r
+#include "lpcGPIO.h"\r
+#include "lpcPIN.h"\r
+#include "lpcADC.h"\r
+#include "lpcSCB.h"\r
+#include "lpcVIC.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Watchdog\r
+#define WD ((wdRegs_t *)0xE0000000)\r
+\r
+// Watchdog Registers\r
+#define WDMOD WD->mod /* Watchdog Mode Register */\r
+#define WDTC WD->tc /* Watchdog Time Constant Register */\r
+#define WDFEED WD->feed /* Watchdog Feed Register */\r
+#define WDTV WD->tv /* Watchdog Time Value Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 0\r
+#define TMR0 ((pwmTmrRegs_t *)0xE0004000)\r
+\r
+// Timer 0 Registers\r
+#define T0IR TMR0->ir /* Interrupt Register */\r
+#define T0TCR TMR0->tcr /* Timer Control Register */\r
+#define T0TC TMR0->tc /* Timer Counter */\r
+#define T0PR TMR0->pr /* Prescale Register */\r
+#define T0PC TMR0->pc /* Prescale Counter Register */\r
+#define T0MCR TMR0->mcr /* Match Control Register */\r
+#define T0MR0 TMR0->mr0 /* Match Register 0 */\r
+#define T0MR1 TMR0->mr1 /* Match Register 1 */\r
+#define T0MR2 TMR0->mr2 /* Match Register 2 */\r
+#define T0MR3 TMR0->mr3 /* Match Register 3 */\r
+#define T0CCR TMR0->ccr /* Capture Control Register */\r
+#define T0CR0 TMR0->cr0 /* Capture Register 0 */\r
+#define T0CR1 TMR0->cr1 /* Capture Register 1 */\r
+#define T0CR2 TMR0->cr2 /* Capture Register 2 */\r
+#define T0CR3 TMR0->cr3 /* Capture Register 3 */\r
+#define T0EMR TMR0->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 1\r
+#define TMR1 ((pwmTmrRegs_t *)0xE0008000)\r
+\r
+// Timer 1 Registers\r
+#define T1IR TMR1->ir /* Interrupt Register */\r
+#define T1TCR TMR1->tcr /* Timer Control Register */\r
+#define T1TC TMR1->tc /* Timer Counter */\r
+#define T1PR TMR1->pr /* Prescale Register */\r
+#define T1PC TMR1->pc /* Prescale Counter Register */\r
+#define T1MCR TMR1->mcr /* Match Control Register */\r
+#define T1MR0 TMR1->mr0 /* Match Register 0 */\r
+#define T1MR1 TMR1->mr1 /* Match Register 1 */\r
+#define T1MR2 TMR1->mr2 /* Match Register 2 */\r
+#define T1MR3 TMR1->mr3 /* Match Register 3 */\r
+#define T1CCR TMR1->ccr /* Capture Control Register */\r
+#define T1CR0 TMR1->cr0 /* Capture Register 0 */\r
+#define T1CR1 TMR1->cr1 /* Capture Register 1 */\r
+#define T1CR2 TMR1->cr2 /* Capture Register 2 */\r
+#define T1CR3 TMR1->cr3 /* Capture Register 3 */\r
+#define T1EMR TMR1->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pulse Width Modulator (PWM)\r
+#define PWM ((pwmTmrRegs_t *)0xE0014000)\r
+\r
+// PWM Registers\r
+#define PWMIR PWM->ir /* Interrupt Register */\r
+#define PWMTCR PWM->tcr /* Timer Control Register */\r
+#define PWMTC PWM->tc /* Timer Counter */\r
+#define PWMPR PWM->pr /* Prescale Register */\r
+#define PWMPC PWM->pc /* Prescale Counter Register */\r
+#define PWMMCR PWM->mcr /* Match Control Register */\r
+#define PWMMR0 PWM->mr0 /* Match Register 0 */\r
+#define PWMMR1 PWM->mr1 /* Match Register 1 */\r
+#define PWMMR2 PWM->mr2 /* Match Register 2 */\r
+#define PWMMR3 PWM->mr3 /* Match Register 3 */\r
+#define PWMMR4 PWM->mr4 /* Match Register 4 */\r
+#define PWMMR5 PWM->mr5 /* Match Register 5 */\r
+#define PWMMR6 PWM->mr6 /* Match Register 6 */\r
+#define PWMPCR PWM->pcr /* Control Register */\r
+#define PWMLER PWM->ler /* Latch Enable Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 0 (UART0)\r
+#define UART0 ((uartRegs_t *)0xE000C000)\r
+#define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */\r
+#define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */\r
+\r
+// UART0 Registers\r
+#define U0RBR UART0->rbr /* Receive Buffer Register */\r
+#define U0THR UART0->thr /* Transmit Holding Register */\r
+#define U0IER UART0->ier /* Interrupt Enable Register */\r
+#define U0IIR UART0->iir /* Interrupt ID Register */\r
+#define U0FCR UART0->fcr /* FIFO Control Register */\r
+#define U0LCR UART0->lcr /* Line Control Register */\r
+#define U0LSR UART0->lsr /* Line Status Register */\r
+#define U0SCR UART0->scr /* Scratch Pad Register */\r
+#define U0DLL UART0->dll /* Divisor Latch Register (LSB) */\r
+#define U0DLM UART0->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 1 (UART1)\r
+#define UART1 ((uartRegs_t *)0xE0010000)\r
+#define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */\r
+#define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */\r
+\r
+// UART1 Registers\r
+#define U1RBR UART1->rbr /* Receive Buffer Register */\r
+#define U1THR UART1->thr /* Transmit Holding Register */\r
+#define U1IER UART1->ier /* Interrupt Enable Register */\r
+#define U1IIR UART1->iir /* Interrupt ID Register */\r
+#define U1FCR UART1->fcr /* FIFO Control Register */\r
+#define U1LCR UART1->lcr /* Line Control Register */\r
+#define U1MCR UART1->mcr /* MODEM Control Register */\r
+#define U1LSR UART1->lsr /* Line Status Register */\r
+#define U1MSR UART1->msr /* MODEM Status Register */\r
+#define U1SCR UART1->scr /* Scratch Pad Register */\r
+#define U1DLL UART1->dll /* Divisor Latch Register (LSB) */\r
+#define U1DLM UART1->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// I2C Interface\r
+#define I2C ((i2cRegs_t *)0xE001C000)\r
+\r
+// I2C Registers\r
+#define I2CONSET I2C->conset /* Control Set Register */\r
+#define I2STAT I2C->stat /* Status Register */\r
+#define I2DAT I2C->dat /* Data Register */\r
+#define I2ADR I2C->adr /* Slave Address Register */\r
+#define I2SCLH I2C->sclh /* SCL Duty Cycle Register (high half word) */\r
+#define I2SCLL I2C->scll /* SCL Duty Cycle Register (low half word) */\r
+#define I2CONCLR I2C->conclr /* Control Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Serial Peripheral Interface 0 (SPI0)\r
+#define SPI0 ((spiRegs_t *)0xE0020000)\r
+\r
+// SPI0 Registers\r
+#define S0SPCR SPI0->cr /* Control Register */\r
+#define S0SPSR SPI0->sr /* Status Register */\r
+#define S0SPDR SPI0->dr /* Data Register */\r
+#define S0SPCCR SPI0->ccr /* Clock Counter Register */\r
+#define S0SPINT SPI0->flag /* Interrupt Flag Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Serial Peripheral Interface 1 (SPI1)\r
+#define SPI1 ((spiRegs_t *)0xE0030000)\r
+\r
+// SPI1 Registers\r
+#define S1SPCR SPI1->cr /* Control Register */\r
+#define S1SPSR SPI1->sr /* Status Register */\r
+#define S1SPDR SPI1->dr /* Data Register */\r
+#define S1SPCCR SPI1->ccr /* Clock Counter Register */\r
+#define S1SPINT SPI1->flag /* Interrupt Flag Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Real Time Clock\r
+#define RTC ((rtcRegs_t *)0xE0024000)\r
+\r
+// RTC Registers\r
+#define RTCILR RTC->ilr /* Interrupt Location Register */\r
+#define RTCCTC RTC->ctc /* Clock Tick Counter */\r
+#define RTCCCR RTC->ccr /* Clock Control Register */\r
+#define RTCCIIR RTC->ciir /* Counter Increment Interrupt Register */\r
+#define RTCAMR RTC->amr /* Alarm Mask Register */\r
+#define RTCCTIME0 RTC->ctime0 /* Consolidated Time Register 0 */\r
+#define RTCCTIME1 RTC->ctime1 /* Consolidated Time Register 1 */\r
+#define RTCCTIME2 RTC->ctime2 /* Consolidated Time Register 2 */\r
+#define RTCSEC RTC->sec /* Seconds Register */\r
+#define RTCMIN RTC->min /* Minutes Register */\r
+#define RTCHOUR RTC->hour /* Hours Register */\r
+#define RTCDOM RTC->dom /* Day Of Month Register */\r
+#define RTCDOW RTC->dow /* Day Of Week Register */\r
+#define RTCDOY RTC->doy /* Day Of Year Register */\r
+#define RTCMONTH RTC->month /* Months Register */\r
+#define RTCYEAR RTC->year /* Years Register */\r
+#define RTCALSEC RTC->alsec /* Alarm Seconds Register */\r
+#define RTCALMIN RTC->almin /* Alarm Minutes Register */\r
+#define RTCALHOUR RTC->alhour /* Alarm Hours Register */\r
+#define RTCALDOM RTC->aldom /* Alarm Day Of Month Register */\r
+#define RTCALDOW RTC->aldow /* Alarm Day Of Week Register */\r
+#define RTCALDOY RTC->aldoy /* Alarm Day Of Year Register */\r
+#define RTCALMON RTC->almon /* Alarm Months Register */\r
+#define RTCALYEAR RTC->alyear /* Alarm Years Register */\r
+#define RTCPREINT RTC->preint /* Prescale Value Register (integer) */\r
+#define RTCPREFRAC RTC->prefrac /* Prescale Value Register (fraction) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// General Purpose Input/Output\r
+#define GPIO ((gpioRegs_t *)0xE0028000)\r
+\r
+// GPIO Registers\r
+#define IO0PIN GPIO->in0 /* P0 Pin Value Register */\r
+#define IO0SET GPIO->set0 /* P0 Pin Output Set Register */\r
+#define IO0DIR GPIO->dir0 /* P0 Pin Direction Register */\r
+#define IO0CLR GPIO->clr0 /* P0 Pin Output Clear Register */\r
+#define IO1PIN GPIO->in1 /* P1 Pin Value Register */\r
+#define IO1SET GPIO->set1 /* P1 Pin Output Set Register */\r
+#define IO1DIR GPIO->dir1 /* P1 Pin Direction Register */\r
+#define IO1CLR GPIO->clr1 /* P1 Pin Output Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pin Connect Block\r
+#define PINSEL ((pinRegs_t *)0xE002C000)\r
+\r
+// Pin Connect Block Registers\r
+#define PINSEL0 PINSEL->sel0 /* Pin Function Select Register 0 */\r
+#define PINSEL1 PINSEL->sel1 /* Pin Function Select Register 1 */\r
+#define PINSEL2 PINSEL->sel2 /* Pin Function Select Register 2 */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// A/D Converter\r
+#define ADC ((adcRegs_t *)0xE0034000)\r
+\r
+// A/D Converter Registers\r
+#define ADCR ADC->cr /* Control Register */\r
+#define ADDR ADC->dr /* Data Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// System Contol Block\r
+#define SCB ((scbRegs_t *)0xE01FC000)\r
+\r
+// Memory Accelerator Module Registers (MAM)\r
+#define MAMCR SCB->mam.cr /* Control Register */\r
+#define MAMTIM SCB->mam.tim /* Timing Control Register */\r
+\r
+// Memory Mapping Control Register\r
+#define MEMMAP SCB->memmap\r
+\r
+// Phase Locked Loop Registers (PLL)\r
+#define PLLCON SCB->pll.con /* Control Register */\r
+#define PLLCFG SCB->pll.cfg /* Configuration Register */\r
+#define PLLSTAT SCB->pll.stat /* Status Register */\r
+#define PLLFEED SCB->pll.feed /* Feed Register */\r
+\r
+// Power Control Registers\r
+#define PCON SCB->p.con /* Control Register */\r
+#define PCONP SCB->p.conp /* Peripherals Register */\r
+\r
+// VPB Divider Register\r
+#define VPBDIV SCB->vpbdiv\r
+\r
+// External Interrupt Registers\r
+#define EXTINT SCB->ext.flag /* Flag Register */\r
+#define EXTWAKE SCB->ext.wake /* Wakeup Register */\r
+#define EXTMODE SCB->ext.mode /* Mode Register */\r
+#define EXTPOLAR SCB->ext.polar /* Polarity Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Vectored Interrupt Controller\r
+#define VIC ((vicRegs_t *)0xFFFFF000)\r
+\r
+// Vectored Interrupt Controller Registers\r
+#define VICIRQStatus VIC->irqStatus /* IRQ Status Register */\r
+#define VICFIQStatus VIC->fiqStatus /* FIQ Status Register */\r
+#define VICRawIntr VIC->rawIntr /* Raw Interrupt Status Register */\r
+#define VICIntSelect VIC->intSelect /* Interrupt Select Register */\r
+#define VICIntEnable VIC->intEnable /* Interrupt Enable Register */\r
+#define VICIntEnClear VIC->intEnClear /* Interrupt Enable Clear Register */\r
+#define VICSoftInt VIC->softInt /* Software Interrupt Register */\r
+#define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */\r
+#define VICProtection VIC->protection /* Protection Enable Register */\r
+#define VICVectAddr VIC->vectAddr /* Vector Address Register */\r
+#define VICDefVectAddr VIC->defVectAddr /* Default Vector Address Register */\r
+#define VICVectAddr0 VIC->vectAddr0 /* Vector Address 0 Register */\r
+#define VICVectAddr1 VIC->vectAddr1 /* Vector Address 1 Register */\r
+#define VICVectAddr2 VIC->vectAddr2 /* Vector Address 2 Register */\r
+#define VICVectAddr3 VIC->vectAddr3 /* Vector Address 3 Register */\r
+#define VICVectAddr4 VIC->vectAddr4 /* Vector Address 4 Register */\r
+#define VICVectAddr5 VIC->vectAddr5 /* Vector Address 5 Register */\r
+#define VICVectAddr6 VIC->vectAddr6 /* Vector Address 6 Register */\r
+#define VICVectAddr7 VIC->vectAddr7 /* Vector Address 7 Register */\r
+#define VICVectAddr8 VIC->vectAddr8 /* Vector Address 8 Register */\r
+#define VICVectAddr9 VIC->vectAddr9 /* Vector Address 9 Register */\r
+#define VICVectAddr10 VIC->vectAddr10 /* Vector Address 10 Register */\r
+#define VICVectAddr11 VIC->vectAddr11 /* Vector Address 11 Register */\r
+#define VICVectAddr12 VIC->vectAddr12 /* Vector Address 12 Register */\r
+#define VICVectAddr13 VIC->vectAddr13 /* Vector Address 13 Register */\r
+#define VICVectAddr14 VIC->vectAddr14 /* Vector Address 14 Register */\r
+#define VICVectAddr15 VIC->vectAddr15 /* Vector Address 15 Register */\r
+#define VICVectCntl0 VIC->vectCntl0 /* Vector Control 0 Register */\r
+#define VICVectCntl1 VIC->vectCntl1 /* Vector Control 1 Register */\r
+#define VICVectCntl2 VIC->vectCntl2 /* Vector Control 2 Register */\r
+#define VICVectCntl3 VIC->vectCntl3 /* Vector Control 3 Register */\r
+#define VICVectCntl4 VIC->vectCntl4 /* Vector Control 4 Register */\r
+#define VICVectCntl5 VIC->vectCntl5 /* Vector Control 5 Register */\r
+#define VICVectCntl6 VIC->vectCntl6 /* Vector Control 6 Register */\r
+#define VICVectCntl7 VIC->vectCntl7 /* Vector Control 7 Register */\r
+#define VICVectCntl8 VIC->vectCntl8 /* Vector Control 8 Register */\r
+#define VICVectCntl9 VIC->vectCntl9 /* Vector Control 9 Register */\r
+#define VICVectCntl10 VIC->vectCntl10 /* Vector Control 10 Register */\r
+#define VICVectCntl11 VIC->vectCntl11 /* Vector Control 11 Register */\r
+#define VICVectCntl12 VIC->vectCntl12 /* Vector Control 12 Register */\r
+#define VICVectCntl13 VIC->vectCntl13 /* Vector Control 13 Register */\r
+#define VICVectCntl14 VIC->vectCntl14 /* Vector Control 14 Register */\r
+#define VICVectCntl15 VIC->vectCntl15 /* Vector Control 15 Register */\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC22xx ARM Processors \r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC22xx_H\r
+#define INC_LPC22xx_H\r
+\r
+#define REG_8 volatile unsigned char\r
+#define REG16 volatile unsigned short\r
+#define REG32 volatile unsigned long\r
+\r
+#include "lpcWD.h"\r
+#include "lpcTMR.h"\r
+#include "lpcUART.h"\r
+#include "lpcI2C.h"\r
+#include "lpcSPI.h"\r
+#include "lpcRTC.h"\r
+#include "lpcGPIO.h"\r
+#include "lpcPIN.h"\r
+#include "lpcADC.h"\r
+#include "lpcSCB.h"\r
+#include "lpcEMC.h"\r
+#include "lpcVIC.h"\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Watchdog\r
+#define WD ((wdRegs_t *)0xE0000000)\r
+\r
+// Watchdog Registers\r
+#define WDMOD WD->mod /* Watchdog Mode Register */\r
+#define WDTC WD->tc /* Watchdog Time Constant Register */\r
+#define WDFEED WD->feed /* Watchdog Feed Register */\r
+#define WDTV WD->tv /* Watchdog Time Value Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 0\r
+#define TMR0 ((pwmTmrRegs_t *)0xE0004000)\r
+\r
+// Timer 0 Registers\r
+#define T0IR TMR0->ir /* Interrupt Register */\r
+#define T0TCR TMR0->tcr /* Timer Control Register */\r
+#define T0TC TMR0->tc /* Timer Counter */\r
+#define T0PR TMR0->pr /* Prescale Register */\r
+#define T0PC TMR0->pc /* Prescale Counter Register */\r
+#define T0MCR TMR0->mcr /* Match Control Register */\r
+#define T0MR0 TMR0->mr0 /* Match Register 0 */\r
+#define T0MR1 TMR0->mr1 /* Match Register 1 */\r
+#define T0MR2 TMR0->mr2 /* Match Register 2 */\r
+#define T0MR3 TMR0->mr3 /* Match Register 3 */\r
+#define T0CCR TMR0->ccr /* Capture Control Register */\r
+#define T0CR0 TMR0->cr0 /* Capture Register 0 */\r
+#define T0CR1 TMR0->cr1 /* Capture Register 1 */\r
+#define T0CR2 TMR0->cr2 /* Capture Register 2 */\r
+#define T0CR3 TMR0->cr3 /* Capture Register 3 */\r
+#define T0EMR TMR0->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Timer 1\r
+#define TMR1 ((pwmTmrRegs_t *)0xE0008000)\r
+\r
+// Timer 1 Registers\r
+#define T1IR TMR1->ir /* Interrupt Register */\r
+#define T1TCR TMR1->tcr /* Timer Control Register */\r
+#define T1TC TMR1->tc /* Timer Counter */\r
+#define T1PR TMR1->pr /* Prescale Register */\r
+#define T1PC TMR1->pc /* Prescale Counter Register */\r
+#define T1MCR TMR1->mcr /* Match Control Register */\r
+#define T1MR0 TMR1->mr0 /* Match Register 0 */\r
+#define T1MR1 TMR1->mr1 /* Match Register 1 */\r
+#define T1MR2 TMR1->mr2 /* Match Register 2 */\r
+#define T1MR3 TMR1->mr3 /* Match Register 3 */\r
+#define T1CCR TMR1->ccr /* Capture Control Register */\r
+#define T1CR0 TMR1->cr0 /* Capture Register 0 */\r
+#define T1CR1 TMR1->cr1 /* Capture Register 1 */\r
+#define T1CR2 TMR1->cr2 /* Capture Register 2 */\r
+#define T1CR3 TMR1->cr3 /* Capture Register 3 */\r
+#define T1EMR TMR1->emr /* External Match Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pulse Width Modulator (PWM)\r
+#define PWM ((pwmTmrRegs_t *)0xE0014000)\r
+\r
+// PWM Registers\r
+#define PWMIR PWM->ir /* Interrupt Register */\r
+#define PWMTCR PWM->tcr /* Timer Control Register */\r
+#define PWMTC PWM->tc /* Timer Counter */\r
+#define PWMPR PWM->pr /* Prescale Register */\r
+#define PWMPC PWM->pc /* Prescale Counter Register */\r
+#define PWMMCR PWM->mcr /* Match Control Register */\r
+#define PWMMR0 PWM->mr0 /* Match Register 0 */\r
+#define PWMMR1 PWM->mr1 /* Match Register 1 */\r
+#define PWMMR2 PWM->mr2 /* Match Register 2 */\r
+#define PWMMR3 PWM->mr3 /* Match Register 3 */\r
+#define PWMMR4 PWM->mr4 /* Match Register 4 */\r
+#define PWMMR5 PWM->mr5 /* Match Register 5 */\r
+#define PWMMR6 PWM->mr6 /* Match Register 6 */\r
+#define PWMPCR PWM->pcr /* Control Register */\r
+#define PWMLER PWM->ler /* Latch Enable Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 0 (UART0)\r
+#define UART0 ((uartRegs_t *)0xE000C000)\r
+#define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */\r
+#define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */\r
+\r
+// UART0 Registers\r
+#define U0RBR UART0->rbr /* Receive Buffer Register */\r
+#define U0THR UART0->thr /* Transmit Holding Register */\r
+#define U0IER UART0->ier /* Interrupt Enable Register */\r
+#define U0IIR UART0->iir /* Interrupt ID Register */\r
+#define U0FCR UART0->fcr /* FIFO Control Register */\r
+#define U0LCR UART0->lcr /* Line Control Register */\r
+#define U0LSR UART0->lsr /* Line Status Register */\r
+#define U0SCR UART0->scr /* Scratch Pad Register */\r
+#define U0DLL UART0->dll /* Divisor Latch Register (LSB) */\r
+#define U0DLM UART0->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Universal Asynchronous Receiver Transmitter 1 (UART1)\r
+#define UART1 ((uartRegs_t *)0xE0010000)\r
+#define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */\r
+#define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */\r
+\r
+// UART1 Registers\r
+#define U1RBR UART1->rbr /* Receive Buffer Register */\r
+#define U1THR UART1->thr /* Transmit Holding Register */\r
+#define U1IER UART1->ier /* Interrupt Enable Register */\r
+#define U1IIR UART1->iir /* Interrupt ID Register */\r
+#define U1FCR UART1->fcr /* FIFO Control Register */\r
+#define U1LCR UART1->lcr /* Line Control Register */\r
+#define U1MCR UART1->mcr /* MODEM Control Register */\r
+#define U1LSR UART1->lsr /* Line Status Register */\r
+#define U1MSR UART1->msr /* MODEM Status Register */\r
+#define U1SCR UART1->scr /* Scratch Pad Register */\r
+#define U1DLL UART1->dll /* Divisor Latch Register (LSB) */\r
+#define U1DLM UART1->dlm /* Divisor Latch Register (MSB) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// I2C Interface\r
+#define I2C ((i2cRegs_t *)0xE001C000)\r
+\r
+// I2C Registers\r
+#define I2CONSET I2C->conset /* Control Set Register */\r
+#define I2STAT I2C->stat /* Status Register */\r
+#define I2DAT I2C->dat /* Data Register */\r
+#define I2ADR I2C->adr /* Slave Address Register */\r
+#define I2SCLH I2C->sclh /* SCL Duty Cycle Register (high half word) */\r
+#define I2SCLL I2C->scll /* SCL Duty Cycle Register (low half word) */\r
+#define I2CONCLR I2C->conclr /* Control Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Serial Peripheral Interface 0 (SPI0)\r
+#define SPI0 ((spiRegs_t *)0xE0020000)\r
+\r
+// SPI0 Registers\r
+#define S0SPCR SPI0->cr /* Control Register */\r
+#define S0SPSR SPI0->sr /* Status Register */\r
+#define S0SPDR SPI0->dr /* Data Register */\r
+#define S0SPCCR SPI0->ccr /* Clock Counter Register */\r
+#define S0SPINT SPI0->flag /* Interrupt Flag Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Serial Peripheral Interface 1 (SPI1)\r
+#define SPI1 ((spiRegs_t *)0xE0030000)\r
+\r
+// SPI1 Registers\r
+#define S1SPCR SPI1->cr /* Control Register */\r
+#define S1SPSR SPI1->sr /* Status Register */\r
+#define S1SPDR SPI1->dr /* Data Register */\r
+#define S1SPCCR SPI1->ccr /* Clock Counter Register */\r
+#define S1SPINT SPI1->flag /* Interrupt Flag Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Real Time Clock\r
+#define RTC ((rtcRegs_t *)0xE0024000)\r
+\r
+// RTC Registers\r
+#define RTCILR RTC->ilr /* Interrupt Location Register */\r
+#define RTCCTC RTC->ctc /* Clock Tick Counter */\r
+#define RTCCCR RTC->ccr /* Clock Control Register */\r
+#define RTCCIIR RTC->ciir /* Counter Increment Interrupt Register */\r
+#define RTCAMR RTC->amr /* Alarm Mask Register */\r
+#define RTCCTIME0 RTC->ctime0 /* Consolidated Time Register 0 */\r
+#define RTCCTIME1 RTC->ctime1 /* Consolidated Time Register 1 */\r
+#define RTCCTIME2 RTC->ctime2 /* Consolidated Time Register 2 */\r
+#define RTCSEC RTC->sec /* Seconds Register */\r
+#define RTCMIN RTC->min /* Minutes Register */\r
+#define RTCHOUR RTC->hour /* Hours Register */\r
+#define RTCDOM RTC->dom /* Day Of Month Register */\r
+#define RTCDOW RTC->dow /* Day Of Week Register */\r
+#define RTCDOY RTC->doy /* Day Of Year Register */\r
+#define RTCMONTH RTC->month /* Months Register */\r
+#define RTCYEAR RTC->year /* Years Register */\r
+#define RTCALSEC RTC->alsec /* Alarm Seconds Register */\r
+#define RTCALMIN RTC->almin /* Alarm Minutes Register */\r
+#define RTCALHOUR RTC->alhour /* Alarm Hours Register */\r
+#define RTCALDOM RTC->aldom /* Alarm Day Of Month Register */\r
+#define RTCALDOW RTC->aldow /* Alarm Day Of Week Register */\r
+#define RTCALDOY RTC->aldoy /* Alarm Day Of Year Register */\r
+#define RTCALMON RTC->almon /* Alarm Months Register */\r
+#define RTCALYEAR RTC->alyear /* Alarm Years Register */\r
+#define RTCPREINT RTC->preint /* Prescale Value Register (integer) */\r
+#define RTCPREFRAC RTC->prefrac /* Prescale Value Register (fraction) */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// General Purpose Input/Output\r
+#define GPIO ((gpioRegs_t *)0xE0028000)\r
+\r
+// GPIO Registers\r
+#define IO0PIN GPIO->in0 /* P0 Pin Value Register */\r
+#define IO0SET GPIO->set0 /* P0 Pin Output Set Register */\r
+#define IO0DIR GPIO->dir0 /* P0 Pin Direction Register */\r
+#define IO0CLR GPIO->clr0 /* P0 Pin Output Clear Register */\r
+#define IO1PIN GPIO->in1 /* P1 Pin Value Register */\r
+#define IO1SET GPIO->set1 /* P1 Pin Output Set Register */\r
+#define IO1DIR GPIO->dir1 /* P1 Pin Direction Register */\r
+#define IO1CLR GPIO->clr1 /* P1 Pin Output Clear Register */\r
+#define IO2PIN GPIO->in2 /* P2 Pin Value Register */\r
+#define IO2SET GPIO->set2 /* P2 Pin Output Set Register */\r
+#define IO2DIR GPIO->dir2 /* P2 Pin Direction Register */\r
+#define IO2CLR GPIO->clr2 /* P2 Pin Output Clear Register */\r
+#define IO3PIN GPIO->in3 /* P3 Pin Value Register */\r
+#define IO3SET GPIO->set3 /* P3 Pin Output Set Register */\r
+#define IO3DIR GPIO->dir3 /* P3 Pin Direction Register */\r
+#define IO3CLR GPIO->clr3 /* P3 Pin Output Clear Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Pin Connect Block\r
+#define PINSEL ((pinRegs_t *)0xE002C000)\r
+\r
+// Pin Connect Block Registers\r
+#define PINSEL0 PINSEL->sel0 /* Pin Function Select Register 0 */\r
+#define PINSEL1 PINSEL->sel1 /* Pin Function Select Register 1 */\r
+#define PINSEL2 PINSEL->sel2 /* Pin Function Select Register 2 */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// A/D Converter\r
+#define ADC ((adcRegs_t *)0xE0034000)\r
+\r
+// A/D Converter Registers\r
+#define ADCR ADC->cr /* Control Register */\r
+#define ADDR ADC->dr /* Data Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// System Contol Block\r
+#define SCB ((scbRegs_t *)0xE01FC000)\r
+\r
+// Memory Accelerator Module Registers (MAM)\r
+#define MAMCR SCB->mam.cr /* Control Register */\r
+#define MAMTIM SCB->mam.tim /* Timing Control Register */\r
+\r
+// Memory Mapping Control Register\r
+#define MEMMAP SCB->memmap\r
+\r
+// Phase Locked Loop Registers (PLL)\r
+#define PLLCON SCB->pll.con /* Control Register */\r
+#define PLLCFG SCB->pll.cfg /* Configuration Register */\r
+#define PLLSTAT SCB->pll.stat /* Status Register */\r
+#define PLLFEED SCB->pll.feed /* Feed Register */\r
+\r
+// Power Control Registers\r
+#define PCON SCB->p.con /* Control Register */\r
+#define PCONP SCB->p.conp /* Peripherals Register */\r
+\r
+// VPB Divider Register\r
+#define VPBDIV SCB->vpbdiv\r
+\r
+// External Interrupt Registers\r
+#define EXTINT SCB->ext.flag /* Flag Register */\r
+#define EXTWAKE SCB->ext.wake /* Wakeup Register */\r
+#define EXTMODE SCB->ext.mode /* Mode Register */\r
+#define EXTPOLAR SCB->ext.polar /* Polarity Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// External Memory Controller (EMC)\r
+#define EMC ((volatile emcRegs_t *)0xFFE00000)\r
+\r
+// External Memory Controller Registers\r
+#define BCFG0 EMC->bcfg0 /* Bank 0 Configuration Register */\r
+#define BCFG1 EMC->bcfg1 /* Bank 1 Configuration Register */\r
+#define BCFG2 EMC->bcfg2 /* Bank 2 Configuration Register */\r
+#define BCFG3 EMC->bcfg3 /* Bank 3 Configuration Register */\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// Vectored Interrupt Controller\r
+#define VIC ((vicRegs_t *)0xFFFFF000)\r
+\r
+// Vectored Interrupt Controller Registers\r
+#define VICIRQStatus VIC->irqStatus /* IRQ Status Register */\r
+#define VICFIQStatus VIC->fiqStatus /* FIQ Status Register */\r
+#define VICRawIntr VIC->rawIntr /* Raw Interrupt Status Register */\r
+#define VICIntSelect VIC->intSelect /* Interrupt Select Register */\r
+#define VICIntEnable VIC->intEnable /* Interrupt Enable Register */\r
+#define VICIntEnClear VIC->intEnClear /* Interrupt Enable Clear Register */\r
+#define VICSoftInt VIC->softInt /* Software Interrupt Register */\r
+#define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */\r
+#define VICProtection VIC->protection /* Protection Enable Register */\r
+#define VICVectAddr VIC->vectAddr /* Vector Address Register */\r
+#define VICDefVectAddr VIC->defVectAddr /* Default Vector Address Register */\r
+#define VICVectAddr0 VIC->vectAddr0 /* Vector Address 0 Register */\r
+#define VICVectAddr1 VIC->vectAddr1 /* Vector Address 1 Register */\r
+#define VICVectAddr2 VIC->vectAddr2 /* Vector Address 2 Register */\r
+#define VICVectAddr3 VIC->vectAddr3 /* Vector Address 3 Register */\r
+#define VICVectAddr4 VIC->vectAddr4 /* Vector Address 4 Register */\r
+#define VICVectAddr5 VIC->vectAddr5 /* Vector Address 5 Register */\r
+#define VICVectAddr6 VIC->vectAddr6 /* Vector Address 6 Register */\r
+#define VICVectAddr7 VIC->vectAddr7 /* Vector Address 7 Register */\r
+#define VICVectAddr8 VIC->vectAddr8 /* Vector Address 8 Register */\r
+#define VICVectAddr9 VIC->vectAddr9 /* Vector Address 9 Register */\r
+#define VICVectAddr10 VIC->vectAddr10 /* Vector Address 10 Register */\r
+#define VICVectAddr11 VIC->vectAddr11 /* Vector Address 11 Register */\r
+#define VICVectAddr12 VIC->vectAddr12 /* Vector Address 12 Register */\r
+#define VICVectAddr13 VIC->vectAddr13 /* Vector Address 13 Register */\r
+#define VICVectAddr14 VIC->vectAddr14 /* Vector Address 14 Register */\r
+#define VICVectAddr15 VIC->vectAddr15 /* Vector Address 15 Register */\r
+#define VICVectCntl0 VIC->vectCntl0 /* Vector Control 0 Register */\r
+#define VICVectCntl1 VIC->vectCntl1 /* Vector Control 1 Register */\r
+#define VICVectCntl2 VIC->vectCntl2 /* Vector Control 2 Register */\r
+#define VICVectCntl3 VIC->vectCntl3 /* Vector Control 3 Register */\r
+#define VICVectCntl4 VIC->vectCntl4 /* Vector Control 4 Register */\r
+#define VICVectCntl5 VIC->vectCntl5 /* Vector Control 5 Register */\r
+#define VICVectCntl6 VIC->vectCntl6 /* Vector Control 6 Register */\r
+#define VICVectCntl7 VIC->vectCntl7 /* Vector Control 7 Register */\r
+#define VICVectCntl8 VIC->vectCntl8 /* Vector Control 8 Register */\r
+#define VICVectCntl9 VIC->vectCntl9 /* Vector Control 9 Register */\r
+#define VICVectCntl10 VIC->vectCntl10 /* Vector Control 10 Register */\r
+#define VICVectCntl11 VIC->vectCntl11 /* Vector Control 11 Register */\r
+#define VICVectCntl12 VIC->vectCntl12 /* Vector Control 12 Register */\r
+#define VICVectCntl13 VIC->vectCntl13 /* Vector Control 13 Register */\r
+#define VICVectCntl14 VIC->vectCntl14 /* Vector Control 14 Register */\r
+#define VICVectCntl15 VIC->vectCntl15 /* Vector Control 15 Register */\r
+\r
+#endif\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * This module provides the interface definitions for setting up and\r
+ * controlling the various interrupt modes present on the ARM processor.\r
+ * Copyright 2004, R O SoftWare\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_ARM_VIC_H\r
+#define INC_ARM_VIC_H\r
+\r
+/******************************************************************************\r
+ *\r
+ * MACRO Name: ISR_ENTRY()\r
+ *\r
+ * Description:\r
+ * This MACRO is used upon entry to an ISR. The current version of\r
+ * the gcc compiler for ARM does not produce correct code for\r
+ * interrupt routines to operate properly with THUMB code. The MACRO\r
+ * performs the following steps:\r
+ *\r
+ * 1 - Adjust address at which execution should resume after servicing\r
+ * ISR to compensate for IRQ entry\r
+ * 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.\r
+ * 3 - Get the status of the interrupted program is in SPSR.\r
+ * 4 - Push it onto the IRQ stack as well.\r
+ *\r
+ *****************************************************************************/\r
+#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \\r
+ " stmfd sp!,{r0-r12,lr}\n" \\r
+ " mrs r1, spsr\n" \\r
+ " stmfd sp!,{r1}")\r
+\r
+/******************************************************************************\r
+ *\r
+ * MACRO Name: ISR_EXIT()\r
+ *\r
+ * Description:\r
+ * This MACRO is used to exit an ISR. The current version of the gcc\r
+ * compiler for ARM does not produce correct code for interrupt\r
+ * routines to operate properly with THUMB code. The MACRO performs\r
+ * the following steps:\r
+ *\r
+ * 1 - Recover SPSR value from stack \r
+ * 2 - and restore its value \r
+ * 3 - Pop the return address & the saved general registers from\r
+ * the IRQ stack & return\r
+ *\r
+ *****************************************************************************/\r
+#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \\r
+ " msr spsr_c,r1\n" \\r
+ " ldmfd sp!,{r0-r12,pc}^")\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: disableIRQ()\r
+ *\r
+ * Description:\r
+ * This function sets the IRQ disable bit in the status register\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned disableIRQ(void);\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: enableIRQ()\r
+ *\r
+ * Description:\r
+ * This function clears the IRQ disable bit in the status register\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned enableIRQ(void);\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: restoreIRQ()\r
+ *\r
+ * Description:\r
+ * This function restores the IRQ disable bit in the status register\r
+ * to the value contained within passed oldCPSR\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned restoreIRQ(unsigned oldCPSR);\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: disableFIQ()\r
+ *\r
+ * Description:\r
+ * This function sets the FIQ disable bit in the status register\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned disableFIQ(void);\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: enableFIQ()\r
+ *\r
+ * Description:\r
+ * This function clears the FIQ disable bit in the status register\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned enableFIQ(void);\r
+\r
+/******************************************************************************\r
+ *\r
+ * Function Name: restoreIRQ()\r
+ *\r
+ * Description:\r
+ * This function restores the FIQ disable bit in the status register\r
+ * to the value contained within passed oldCPSR\r
+ *\r
+ * Calling Sequence: \r
+ * void\r
+ *\r
+ * Returns:\r
+ * previous value of CPSR\r
+ *\r
+ *****************************************************************************/\r
+unsigned restoreFIQ(unsigned oldCPSR);\r
+\r
+#endif\r
--- /dev/null
+/***********************************************************************/\r
+/* This file is part of the uVision/ARM development tools */\r
+/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */\r
+/***********************************************************************/\r
+/* */\r
+/* LPC21XX.H: Header file for Philips LPC2114 / LPC2119 */\r
+/* LPC2124 / LPC2129 */\r
+/* LPC2194 */\r
+/* */\r
+/***********************************************************************/\r
+\r
+#ifndef __LPC21xx_H\r
+#define __LPC21xx_H\r
+\r
+/* Vectored Interrupt Controller (VIC) */\r
+#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))\r
+#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))\r
+#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))\r
+#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))\r
+#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))\r
+#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))\r
+#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))\r
+#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C))\r
+#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))\r
+#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))\r
+#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))\r
+#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))\r
+#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))\r
+#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))\r
+#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))\r
+#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))\r
+#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))\r
+#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))\r
+#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))\r
+#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))\r
+#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))\r
+#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))\r
+#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))\r
+#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))\r
+#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))\r
+#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))\r
+#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))\r
+#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))\r
+#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))\r
+#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))\r
+#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))\r
+#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))\r
+#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))\r
+#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))\r
+#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))\r
+#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))\r
+#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))\r
+#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))\r
+#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))\r
+#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))\r
+#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))\r
+#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))\r
+#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))\r
+\r
+/* Pin Connect Block */\r
+#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))\r
+#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))\r
+#define PINSEL2 (*((volatile unsigned long *) 0xE002C014))\r
+\r
+/* General Purpose Input/Output (GPIO) */\r
+#define IOPIN0 (*((volatile unsigned long *) 0xE0028000))\r
+#define IOSET0 (*((volatile unsigned long *) 0xE0028004))\r
+#define IODIR0 (*((volatile unsigned long *) 0xE0028008))\r
+#define IOCLR0 (*((volatile unsigned long *) 0xE002800C))\r
+#define IOPIN1 (*((volatile unsigned long *) 0xE0028010))\r
+#define IOSET1 (*((volatile unsigned long *) 0xE0028014))\r
+#define IODIR1 (*((volatile unsigned long *) 0xE0028018))\r
+#define IOCLR1 (*((volatile unsigned long *) 0xE002801C))\r
+#define IO0PIN (*((volatile unsigned long *) 0xE0028000))\r
+#define IO0SET (*((volatile unsigned long *) 0xE0028004))\r
+#define IO0DIR (*((volatile unsigned long *) 0xE0028008))\r
+#define IO0CLR (*((volatile unsigned long *) 0xE002800C))\r
+#define IO1PIN (*((volatile unsigned long *) 0xE0028010))\r
+#define IO1SET (*((volatile unsigned long *) 0xE0028014))\r
+#define IO1DIR (*((volatile unsigned long *) 0xE0028018))\r
+#define IO1CLR (*((volatile unsigned long *) 0xE002801C))\r
+\r
+/* Memory Accelerator Module (MAM) */\r
+#define MAMCR (*((volatile unsigned char *) 0xE01FC000))\r
+#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))\r
+#define MEMMAP (*((volatile unsigned char *) 0xE01FC040))\r
+\r
+/* Phase Locked Loop (PLL) */\r
+#define PLLCON (*((volatile unsigned char *) 0xE01FC080))\r
+#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))\r
+#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))\r
+#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))\r
+\r
+/* VPB Divider */\r
+#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))\r
+\r
+/* Power Control */\r
+#define PCON (*((volatile unsigned char *) 0xE01FC0C0))\r
+#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))\r
+\r
+/* External Interrupts */\r
+#define EXTINT (*((volatile unsigned char *) 0xE01FC140))\r
+#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))\r
+#define EXTMODE (*((volatile unsigned char *) 0xE01FC148))\r
+#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C))\r
+\r
+/* Timer 0 */\r
+#define T0IR (*((volatile unsigned long *) 0xE0004000))\r
+#define T0TCR (*((volatile unsigned long *) 0xE0004004))\r
+#define T0TC (*((volatile unsigned long *) 0xE0004008))\r
+#define T0PR (*((volatile unsigned long *) 0xE000400C))\r
+#define T0PC (*((volatile unsigned long *) 0xE0004010))\r
+#define T0MCR (*((volatile unsigned long *) 0xE0004014))\r
+#define T0MR0 (*((volatile unsigned long *) 0xE0004018))\r
+#define T0MR1 (*((volatile unsigned long *) 0xE000401C))\r
+#define T0MR2 (*((volatile unsigned long *) 0xE0004020))\r
+#define T0MR3 (*((volatile unsigned long *) 0xE0004024))\r
+#define T0CCR (*((volatile unsigned long *) 0xE0004028))\r
+#define T0CR0 (*((volatile unsigned long *) 0xE000402C))\r
+#define T0CR1 (*((volatile unsigned long *) 0xE0004030))\r
+#define T0CR2 (*((volatile unsigned long *) 0xE0004034))\r
+#define T0CR3 (*((volatile unsigned long *) 0xE0004038))\r
+#define T0EMR (*((volatile unsigned long *) 0xE000403C))\r
+\r
+/* Timer 1 */\r
+#define T1IR (*((volatile unsigned long *) 0xE0008000))\r
+#define T1TCR (*((volatile unsigned long *) 0xE0008004))\r
+#define T1TC (*((volatile unsigned long *) 0xE0008008))\r
+#define T1PR (*((volatile unsigned long *) 0xE000800C))\r
+#define T1PC (*((volatile unsigned long *) 0xE0008010))\r
+#define T1MCR (*((volatile unsigned long *) 0xE0008014))\r
+#define T1MR0 (*((volatile unsigned long *) 0xE0008018))\r
+#define T1MR1 (*((volatile unsigned long *) 0xE000801C))\r
+#define T1MR2 (*((volatile unsigned long *) 0xE0008020))\r
+#define T1MR3 (*((volatile unsigned long *) 0xE0008024))\r
+#define T1CCR (*((volatile unsigned long *) 0xE0008028))\r
+#define T1CR0 (*((volatile unsigned long *) 0xE000802C))\r
+#define T1CR1 (*((volatile unsigned long *) 0xE0008030))\r
+#define T1CR2 (*((volatile unsigned long *) 0xE0008034))\r
+#define T1CR3 (*((volatile unsigned long *) 0xE0008038))\r
+#define T1EMR (*((volatile unsigned long *) 0xE000803C))\r
+\r
+/* Pulse Width Modulator (PWM) */\r
+#define PWMIR (*((volatile unsigned long *) 0xE0014000))\r
+#define PWMTCR (*((volatile unsigned long *) 0xE0014004))\r
+#define PWMTC (*((volatile unsigned long *) 0xE0014008))\r
+#define PWMPR (*((volatile unsigned long *) 0xE001400C))\r
+#define PWMPC (*((volatile unsigned long *) 0xE0014010))\r
+#define PWMMCR (*((volatile unsigned long *) 0xE0014014))\r
+#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))\r
+#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))\r
+#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))\r
+#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))\r
+#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))\r
+#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))\r
+#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))\r
+#define PWMCCR (*((volatile unsigned long *) 0xE0014028))\r
+#define PWMCR0 (*((volatile unsigned long *) 0xE001402C))\r
+#define PWMCR1 (*((volatile unsigned long *) 0xE0014030))\r
+#define PWMCR2 (*((volatile unsigned long *) 0xE0014034))\r
+#define PWMCR3 (*((volatile unsigned long *) 0xE0014038))\r
+#define PWMEMR (*((volatile unsigned long *) 0xE001403C))\r
+#define PWMPCR (*((volatile unsigned long *) 0xE001404C))\r
+#define PWMLER (*((volatile unsigned long *) 0xE0014050))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define U0RBR (*((volatile unsigned char *) 0xE000C000))\r
+#define U0THR (*((volatile unsigned char *) 0xE000C000))\r
+#define U0IER (*((volatile unsigned char *) 0xE000C004))\r
+#define U0IIR (*((volatile unsigned char *) 0xE000C008))\r
+#define U0FCR (*((volatile unsigned char *) 0xE000C008))\r
+#define U0LCR (*((volatile unsigned char *) 0xE000C00C))\r
+#define U0MCR (*((volatile unsigned char *) 0xE000C010))\r
+#define U0LSR (*((volatile unsigned char *) 0xE000C014))\r
+#define U0MSR (*((volatile unsigned char *) 0xE000C018))\r
+#define U0SCR (*((volatile unsigned char *) 0xE000C01C))\r
+#define U0DLL (*((volatile unsigned char *) 0xE000C000))\r
+#define U0DLM (*((volatile unsigned char *) 0xE000C004))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define U1RBR (*((volatile unsigned char *) 0xE0010000))\r
+#define U1THR (*((volatile unsigned char *) 0xE0010000))\r
+#define U1IER (*((volatile unsigned char *) 0xE0010004))\r
+#define U1IIR (*((volatile unsigned char *) 0xE0010008))\r
+#define U1FCR (*((volatile unsigned char *) 0xE0010008))\r
+#define U1LCR (*((volatile unsigned char *) 0xE001000C))\r
+#define U1MCR (*((volatile unsigned char *) 0xE0010010))\r
+#define U1LSR (*((volatile unsigned char *) 0xE0010014))\r
+#define U1MSR (*((volatile unsigned char *) 0xE0010018))\r
+#define U1SCR (*((volatile unsigned char *) 0xE001001C))\r
+#define U1DLL (*((volatile unsigned char *) 0xE0010000))\r
+#define U1DLM (*((volatile unsigned char *) 0xE0010004))\r
+\r
+/* I2C Interface */\r
+#define I2CONSET (*((volatile unsigned char *) 0xE001C000))\r
+#define I2STAT (*((volatile unsigned char *) 0xE001C004))\r
+#define I2DAT (*((volatile unsigned char *) 0xE001C008))\r
+#define I2ADR (*((volatile unsigned char *) 0xE001C00C))\r
+#define I2SCLH (*((volatile unsigned short*) 0xE001C010))\r
+#define I2SCLL (*((volatile unsigned short*) 0xE001C014))\r
+#define I2CONCLR (*((volatile unsigned char *) 0xE001C018))\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define S0SPCR (*((volatile unsigned char *) 0xE0020000))\r
+#define S0SPSR (*((volatile unsigned char *) 0xE0020004))\r
+#define S0SPDR (*((volatile unsigned char *) 0xE0020008))\r
+#define S0SPCCR (*((volatile unsigned char *) 0xE002000C))\r
+#define S0SPTCR (*((volatile unsigned char *) 0xE0020010))\r
+#define S0SPTSR (*((volatile unsigned char *) 0xE0020014))\r
+#define S0SPTOR (*((volatile unsigned char *) 0xE0020018))\r
+#define S0SPINT (*((volatile unsigned char *) 0xE002001C))\r
+\r
+/* SPI1 (Serial Peripheral Interface 1) */\r
+#define S1SPCR (*((volatile unsigned char *) 0xE0030000))\r
+#define S1SPSR (*((volatile unsigned char *) 0xE0030004))\r
+#define S1SPDR (*((volatile unsigned char *) 0xE0030008))\r
+#define S1SPCCR (*((volatile unsigned char *) 0xE003000C))\r
+#define S1SPTCR (*((volatile unsigned char *) 0xE0030010))\r
+#define S1SPTSR (*((volatile unsigned char *) 0xE0030014))\r
+#define S1SPTOR (*((volatile unsigned char *) 0xE0030018))\r
+#define S1SPINT (*((volatile unsigned char *) 0xE003001C))\r
+\r
+/* Real Time Clock */\r
+#define ILR (*((volatile unsigned char *) 0xE0024000))\r
+#define CTC (*((volatile unsigned short*) 0xE0024004))\r
+#define CCR (*((volatile unsigned char *) 0xE0024008))\r
+#define CIIR (*((volatile unsigned char *) 0xE002400C))\r
+#define AMR (*((volatile unsigned char *) 0xE0024010))\r
+#define CTIME0 (*((volatile unsigned long *) 0xE0024014))\r
+#define CTIME1 (*((volatile unsigned long *) 0xE0024018))\r
+#define CTIME2 (*((volatile unsigned long *) 0xE002401C))\r
+#define SEC (*((volatile unsigned char *) 0xE0024020))\r
+#define MIN (*((volatile unsigned char *) 0xE0024024))\r
+#define HOUR (*((volatile unsigned char *) 0xE0024028))\r
+#define DOM (*((volatile unsigned char *) 0xE002402C))\r
+#define DOW (*((volatile unsigned char *) 0xE0024030))\r
+#define DOY (*((volatile unsigned short*) 0xE0024034))\r
+#define MONTH (*((volatile unsigned char *) 0xE0024038))\r
+#define YEAR (*((volatile unsigned short*) 0xE002403C))\r
+#define ALSEC (*((volatile unsigned char *) 0xE0024060))\r
+#define ALMIN (*((volatile unsigned char *) 0xE0024064))\r
+#define ALHOUR (*((volatile unsigned char *) 0xE0024068))\r
+#define ALDOM (*((volatile unsigned char *) 0xE002406C))\r
+#define ALDOW (*((volatile unsigned char *) 0xE0024070))\r
+#define ALDOY (*((volatile unsigned short*) 0xE0024074))\r
+#define ALMON (*((volatile unsigned char *) 0xE0024078))\r
+#define ALYEAR (*((volatile unsigned short*) 0xE002407C))\r
+#define PREINT (*((volatile unsigned short*) 0xE0024080))\r
+#define PREFRAC (*((volatile unsigned short*) 0xE0024084))\r
+\r
+/* A/D Converter */\r
+#define ADCR (*((volatile unsigned long *) 0xE0034000))\r
+#define ADDR (*((volatile unsigned long *) 0xE0034004))\r
+\r
+/* CAN Acceptance Filter RAM */\r
+#define AFRAM (*((volatile unsigned long *) 0xE0038000))\r
+\r
+/* CAN Acceptance Filter */\r
+#define AFMR (*((volatile unsigned long *) 0xE003C000))\r
+#define SFF_sa (*((volatile unsigned long *) 0xE003C004))\r
+#define SFF_GRP_sa (*((volatile unsigned long *) 0xE003C008))\r
+#define EFF_sa (*((volatile unsigned long *) 0xE003C00C))\r
+#define EFF_GRP_sa (*((volatile unsigned long *) 0xE003C010))\r
+#define ENDofTable (*((volatile unsigned long *) 0xE003C014))\r
+#define LUTerrAd (*((volatile unsigned long *) 0xE003C018))\r
+#define LUTerr (*((volatile unsigned long *) 0xE003C01C))\r
+\r
+/* CAN Central Registers */\r
+#define CANTxSR (*((volatile unsigned long *) 0xE0040000))\r
+#define CANRxSR (*((volatile unsigned long *) 0xE0040004))\r
+#define CANMSR (*((volatile unsigned long *) 0xE0040008))\r
+\r
+/* CAN Controller 1 (CAN1) */\r
+#define C1MOD (*((volatile unsigned long *) 0xE0044000))\r
+#define C1CMR (*((volatile unsigned long *) 0xE0044004))\r
+#define C1GSR (*((volatile unsigned long *) 0xE0044008))\r
+#define C1ICR (*((volatile unsigned long *) 0xE004400C))\r
+#define C1IER (*((volatile unsigned long *) 0xE0044010))\r
+#define C1BTR (*((volatile unsigned long *) 0xE0044014))\r
+#define C1EWL (*((volatile unsigned long *) 0xE0044018))\r
+#define C1SR (*((volatile unsigned long *) 0xE004401C))\r
+#define C1RFS (*((volatile unsigned long *) 0xE0044020))\r
+#define C1RID (*((volatile unsigned long *) 0xE0044024))\r
+#define C1RDA (*((volatile unsigned long *) 0xE0044028))\r
+#define C1RDB (*((volatile unsigned long *) 0xE004402C))\r
+#define C1TFI1 (*((volatile unsigned long *) 0xE0044030))\r
+#define C1TID1 (*((volatile unsigned long *) 0xE0044034))\r
+#define C1TDA1 (*((volatile unsigned long *) 0xE0044038))\r
+#define C1TDB1 (*((volatile unsigned long *) 0xE004403C))\r
+#define C1TFI2 (*((volatile unsigned long *) 0xE0044040))\r
+#define C1TID2 (*((volatile unsigned long *) 0xE0044044))\r
+#define C1TDA2 (*((volatile unsigned long *) 0xE0044048))\r
+#define C1TDB2 (*((volatile unsigned long *) 0xE004404C))\r
+#define C1TFI3 (*((volatile unsigned long *) 0xE0044050))\r
+#define C1TID3 (*((volatile unsigned long *) 0xE0044054))\r
+#define C1TDA3 (*((volatile unsigned long *) 0xE0044058))\r
+#define C1TDB3 (*((volatile unsigned long *) 0xE004405C))\r
+\r
+/* CAN Controller 2 (CAN2) */\r
+#define C2MOD (*((volatile unsigned long *) 0xE0048000))\r
+#define C2CMR (*((volatile unsigned long *) 0xE0048004))\r
+#define C2GSR (*((volatile unsigned long *) 0xE0048008))\r
+#define C2ICR (*((volatile unsigned long *) 0xE004800C))\r
+#define C2IER (*((volatile unsigned long *) 0xE0048010))\r
+#define C2BTR (*((volatile unsigned long *) 0xE0048014))\r
+#define C2EWL (*((volatile unsigned long *) 0xE0048018))\r
+#define C2SR (*((volatile unsigned long *) 0xE004801C))\r
+#define C2RFS (*((volatile unsigned long *) 0xE0048020))\r
+#define C2RID (*((volatile unsigned long *) 0xE0048024))\r
+#define C2RDA (*((volatile unsigned long *) 0xE0048028))\r
+#define C2RDB (*((volatile unsigned long *) 0xE004802C))\r
+#define C2TFI1 (*((volatile unsigned long *) 0xE0048030))\r
+#define C2TID1 (*((volatile unsigned long *) 0xE0048034))\r
+#define C2TDA1 (*((volatile unsigned long *) 0xE0048038))\r
+#define C2TDB1 (*((volatile unsigned long *) 0xE004803C))\r
+#define C2TFI2 (*((volatile unsigned long *) 0xE0048040))\r
+#define C2TID2 (*((volatile unsigned long *) 0xE0048044))\r
+#define C2TDA2 (*((volatile unsigned long *) 0xE0048048))\r
+#define C2TDB2 (*((volatile unsigned long *) 0xE004804C))\r
+#define C2TFI3 (*((volatile unsigned long *) 0xE0048050))\r
+#define C2TID3 (*((volatile unsigned long *) 0xE0048054))\r
+#define C2TDA3 (*((volatile unsigned long *) 0xE0048058))\r
+#define C2TDB3 (*((volatile unsigned long *) 0xE004805C))\r
+\r
+/* CAN Controller 3 (CAN3) */\r
+#define C3MOD (*((volatile unsigned long *) 0xE004C000))\r
+#define C3CMR (*((volatile unsigned long *) 0xE004C004))\r
+#define C3GSR (*((volatile unsigned long *) 0xE004C008))\r
+#define C3ICR (*((volatile unsigned long *) 0xE004C00C))\r
+#define C3IER (*((volatile unsigned long *) 0xE004C010))\r
+#define C3BTR (*((volatile unsigned long *) 0xE004C014))\r
+#define C3EWL (*((volatile unsigned long *) 0xE004C018))\r
+#define C3SR (*((volatile unsigned long *) 0xE004C01C))\r
+#define C3RFS (*((volatile unsigned long *) 0xE004C020))\r
+#define C3RID (*((volatile unsigned long *) 0xE004C024))\r
+#define C3RDA (*((volatile unsigned long *) 0xE004C028))\r
+#define C3RDB (*((volatile unsigned long *) 0xE004C02C))\r
+#define C3TFI1 (*((volatile unsigned long *) 0xE004C030))\r
+#define C3TID1 (*((volatile unsigned long *) 0xE004C034))\r
+#define C3TDA1 (*((volatile unsigned long *) 0xE004C038))\r
+#define C3TDB1 (*((volatile unsigned long *) 0xE004C03C))\r
+#define C3TFI2 (*((volatile unsigned long *) 0xE004C040))\r
+#define C3TID2 (*((volatile unsigned long *) 0xE004C044))\r
+#define C3TDA2 (*((volatile unsigned long *) 0xE004C048))\r
+#define C3TDB2 (*((volatile unsigned long *) 0xE004C04C))\r
+#define C3TFI3 (*((volatile unsigned long *) 0xE004C050))\r
+#define C3TID3 (*((volatile unsigned long *) 0xE004C054))\r
+#define C3TDA3 (*((volatile unsigned long *) 0xE004C058))\r
+#define C3TDB3 (*((volatile unsigned long *) 0xE004C05C))\r
+\r
+/* CAN Controller 4 (CAN4) */\r
+#define C4MOD (*((volatile unsigned long *) 0xE0050000))\r
+#define C4CMR (*((volatile unsigned long *) 0xE0050004))\r
+#define C4GSR (*((volatile unsigned long *) 0xE0050008))\r
+#define C4ICR (*((volatile unsigned long *) 0xE005000C))\r
+#define C4IER (*((volatile unsigned long *) 0xE0050010))\r
+#define C4BTR (*((volatile unsigned long *) 0xE0050014))\r
+#define C4EWL (*((volatile unsigned long *) 0xE0050018))\r
+#define C4SR (*((volatile unsigned long *) 0xE005001C))\r
+#define C4RFS (*((volatile unsigned long *) 0xE0050020))\r
+#define C4RID (*((volatile unsigned long *) 0xE0050024))\r
+#define C4RDA (*((volatile unsigned long *) 0xE0050028))\r
+#define C4RDB (*((volatile unsigned long *) 0xE005002C))\r
+#define C4TFI1 (*((volatile unsigned long *) 0xE0050030))\r
+#define C4TID1 (*((volatile unsigned long *) 0xE0050034))\r
+#define C4TDA1 (*((volatile unsigned long *) 0xE0050038))\r
+#define C4TDB1 (*((volatile unsigned long *) 0xE005003C))\r
+#define C4TFI2 (*((volatile unsigned long *) 0xE0050040))\r
+#define C4TID2 (*((volatile unsigned long *) 0xE0050044))\r
+#define C4TDA2 (*((volatile unsigned long *) 0xE0050048))\r
+#define C4TDB2 (*((volatile unsigned long *) 0xE005004C))\r
+#define C4TFI3 (*((volatile unsigned long *) 0xE0050050))\r
+#define C4TID3 (*((volatile unsigned long *) 0xE0050054))\r
+#define C4TDA3 (*((volatile unsigned long *) 0xE0050058))\r
+#define C4TDB3 (*((volatile unsigned long *) 0xE005005C))\r
+\r
+/* Watchdog */\r
+#define WDMOD (*((volatile unsigned char *) 0xE0000000))\r
+#define WDTC (*((volatile unsigned long *) 0xE0000004))\r
+#define WDFEED (*((volatile unsigned char *) 0xE0000008))\r
+#define WDTV (*((volatile unsigned long *) 0xE000000C))\r
+\r
+\r
+//------------------------- added by Jiri Kubias DCE CVUT -----------------------\r
+\r
+// GPIO section, mask for PINSEL\r
+ #define PINSEL_0 0x0l\r
+ #define PINSEL_1 0x1l\r
+ #define PINSEL_2 0x2l\r
+ #define PINSEL_3 0x3l\r
+ \r
+\r
+// ADC section\r
+ \r
+ #define ADC_CR_ADC0_m (1<<0)\r
+ #define ADC_CR_ADC1_m (1<<1)\r
+ #define ADC_CR_ADC2_m (1<<2)\r
+ #define ADC_CR_ADC3_m (1<<3)\r
+ #define ADC_CR_BURST (1<<16)\r
+ #define ADC_CR_CLK_DIV_1_m (1<<8) // this nuber should be multipied sampe \r
+ // requested divisor 5 ---- clk_div = 4 * ADC_CR_CLK_DIV_1\r
+ #define ADC_CR_CLK_DIV_m(X) ((X-1)<<8) // not tested\r
+ #define ADC_CR_CLKS_11_m (0<<17)\r
+ #define ADC_CR_CLKS_10_m (1<<17)\r
+ #define ADC_CR_CLKS_9_m (2<<17)\r
+ #define ADC_CR_CLKS_8_m (3<<17)\r
+ #define ADC_CR_CLKS_7_m (4<<17)\r
+ #define ADC_CR_CLKS_6_m (5<<17)\r
+ #define ADC_CR_CLKS_5_m (6<<17)\r
+ #define ADC_CR_CLKS_4_m (7<<17)\r
+ #define ADC_CR_PDN_ON_m (1<<21)\r
+ #define ADC_CR_START_OFF_m (0<<24)\r
+ #define ADC_CR_START_NOW_m (1<<24)\r
+ #define ADC_CR_START_P016_m (2<<24)\r
+ #define ADC_CR_START_P022_m (3<<24)\r
+ #define ADC_CR_START_MAT01_m (4<<24)\r
+ #define ADC_CR_START_MAT03_m (5<<24)\r
+ #define ADC_CR_START_MAT10_m (6<<24)\r
+ #define ADC_CR_START_MAT11_m (7<<24)\r
+ #define ADC_CR_EDGE_RISING_m (0<<27)\r
+ #define ADC_CR_EDGE_FALLING_m (1<<27)\r
+\r
+\r
+// PWM section\r
+ // mask for PWMIR\r
+ #define PWMIR_IR_PWM0_m (0x01l << 0)\r
+ #define PWMIR_IR_PWM1_m (0x01l << 1)\r
+ #define PWMIR_IR_PWM2_m (0x01l << 2)\r
+ #define PWMIR_IR_PWM3_m (0x01l << 3)\r
+ #define PWMIR_IR_PWM4_m (0x01l << 8)\r
+ #define PWMIR_IR_PWM5_m (0x01l << 9)\r
+ #define PWMIR_IR_PWM6_m (0x01l << 10)\r
+\r
+ // mask for PWMTCR\r
+ #define PWMTCR_CE_m (0x01l << 0)\r
+ #define PWMTCR_CR_m (0x01l << 1)\r
+ #define PWMTCR_EN_m (0x01l << 3)\r
+\r
+ // mask for PWMMCR\r
+ #define PWMMCR_PWMMR0I_m (0x01l << 0)\r
+ #define PWMMCR_PWMMR0R_m (0x01l << 1)\r
+ #define PWMMCR_PWMMR0S_m (0x01l << 2)\r
+ #define PWMMCR_PWMMR1I_m (0x01l << 3)\r
+ #define PWMMCR_PWMMR1R_m (0x01l << 4)\r
+ #define PWMMCR_PWMMR1S_m (0x01l << 5)\r
+ #define PWMMCR_PWMMR2I_m (0x01l << 6)\r
+ #define PWMMCR_PWMMR2R_m (0x01l << 7)\r
+ #define PWMMCR_PWMMR2S_m (0x01l << 8)\r
+ #define PWMMCR_PWMMR3I_m (0x01l << 9)\r
+ #define PWMMCR_PWMMR3R_m (0x01l << 10)\r
+ #define PWMMCR_PWMMR3S_m (0x01l << 11)\r
+ #define PWMMCR_PWMMR4I_m (0x01l << 12)\r
+ #define PWMMCR_PWMMR4R_m (0x01l << 13)\r
+ #define PWMMCR_PWMMR4S_m (0x01l << 14)\r
+ #define PWMMCR_PWMMR5I_m (0x01l << 15)\r
+ #define PWMMCR_PWMMR5R_m (0x01l << 16)\r
+ #define PWMMCR_PWMMR5S_m (0x01l << 17)\r
+ #define PWMMCR_PWMMR6I_m (0x01l << 18)\r
+ #define PWMMCR_PWMMR6R_m (0x01l << 19)\r
+ #define PWMMCR_PWMMR6S_m (0x01l << 20)\r
+\r
+ // mask for PWMPCR\r
+ #define PWMPCR_PWMSEL2_m (0x01l << 2)\r
+ #define PWMPCR_PWMSEL3_m (0x01l << 3)\r
+ #define PWMPCR_PWMSEL4_m (0x01l << 4)\r
+ #define PWMPCR_PWMSEL5_m (0x01l << 5)\r
+ #define PWMPCR_PWMSEL6_m (0x01l << 6)\r
+ #define PWMPCR_PWMENA1_m (0x01l << 9)\r
+ #define PWMPCR_PWMENA2_m (0x01l << 10)\r
+ #define PWMPCR_PWMENA3_m (0x01l << 11)\r
+ #define PWMPCR_PWMENA4_m (0x01l << 12)\r
+ #define PWMPCR_PWMENA5_m (0x01l << 13)\r
+ #define PWMPCR_PWMENA6_m (0x01l << 14)\r
+ \r
+ // mask for PWMLER\r
+\r
+ #define PWMLER_LA0_m (0x01l << 0)\r
+ #define PWMLER_LA1_m (0x01l << 1)\r
+ #define PWMLER_LA2_m (0x01l << 2)\r
+ #define PWMLER_LA3_m (0x01l << 3)\r
+ #define PWMLER_LA4_m (0x01l << 4)\r
+ #define PWMLER_LA5_m (0x01l << 5)\r
+ #define PWMLER_LA6_m (0x01l << 6)\r
+ \r
+\r
+// SPI section\r
+ // mask for SPCR\r
+ #define SPCR_BIT_EN_m (1<<2)\r
+ #define SPCR_CPHA_m (1<<3)\r
+ #define SPCR_CPOL_m (1<<4)\r
+ #define SPCR_MSTR_m (1<<5)\r
+ #define SPCR_LSBF_m (1<<6)\r
+ #define SPCR_SPIE_m (1<<7)\r
+ #define SPCR_BITS_8_m (8<<8)\r
+ #define SPCR_BITS_9_m (9<<8)\r
+ #define SPCR_BITS_10_m (10<<8)\r
+ #define SPCR_BITS_11_m (11<<8)\r
+ #define SPCR_BITS_12_m (12<<8)\r
+ #define SPCR_BITS_13_m (13<<8)\r
+ #define SPCR_BITS_14_m (14<<8)\r
+ #define SPCR_BITS_15_m (15<<8)\r
+ #define SPCR_BITS_16_m (0<<8)\r
+\r
+ // mask for SPSR\r
+ #define SPSR_ABRT_m (1<<3)\r
+ #define SPSR_MODF_m (1<<4)\r
+ #define SPSR_ROVR_m (1<<5)\r
+ #define SPSR_WCOL_m (1<<6)\r
+ #define SPSR_SPIF_m (1<<7)\r
+\r
+\r
+// VIC Channel Assignments\r
+ #define VIC_WDT 0\r
+ #define VIC_TIMER0 4\r
+ #define VIC_TIMER1 5\r
+ #define VIC_UART0 6\r
+ #define VIC_UART1 7\r
+ #define VIC_PWM 8\r
+ #define VIC_PWM0 8\r
+ #define VIC_I2C 9\r
+ #define VIC_SPI 10\r
+ #define VIC_SPI0 10\r
+ #define VIC_SPI1 11\r
+ #define VIC_PLL 12\r
+ #define VIC_RTC 13\r
+ #define VIC_EINT0 14\r
+ #define VIC_EINT1 15\r
+ #define VIC_EINT2 16\r
+ #define VIC_EINT3 17\r
+ #define VIC_ENABLE 0x20\r
+\r
+\r
+// EXTINT\r
+ //EXTINT part\r
+ #define EXTINT_EINT0_m (1<<0)\r
+ #define EXTINT_EINT1_m (1<<1)\r
+ #define EXTINT_EINT2_m (1<<2)\r
+ #define EXTINT_EINT3_m (1<<3) \r
+\r
+ //EXTWAKE part \r
+ #define EXTWAKE_EXTWAKE0_m (1<<0)\r
+ #define EXTWAKE_EXTWAKE1_m (1<<1)\r
+ #define EXTWAKE_EXTWAKE2_m (1<<2)\r
+ #define EXTWAKE_EXTWAKE3_m (1<<3)\r
+\r
+ //EXTMODE part \r
+ #define EXTMODE_EXTMODE0_m (1<<0)\r
+ #define EXTMODE_EXTMODE1_m (1<<1)\r
+ #define EXTMODE_EXTMODE2_m (1<<2)\r
+ #define EXTMODE_EXTMODE3_m (1<<3)\r
+\r
+ //EXTPOLAR part \r
+ #define EXTPOLAR_EXTPOLAR0_m (1<<0)\r
+ #define EXTPOLAR_EXTPOLAR1_m (1<<1)\r
+ #define EXTPOLAR_EXTPOLAR2_m (1<<2)\r
+ #define EXTPOLAR_EXTPOLAR3_m (1<<3)\r
+\r
+\r
+// set pin macro\r
+#define SET_PIN(GATE,PIN,VAL) \\r
+{ GATE &= ~(PINSEL_3 << (PIN<<1)); \\r
+ GATE |= (VAL << (PIN<<1)); \\r
+}\r
+\r
+\r
+#ifdef __GNUC__\r
+/* For Keil compatibility */\r
+#define __irq __attribute__((interrupt))\r
+#endif\r
+\r
+#endif // __LPC21xx_H\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_ADC_H\r
+#define INC_LPC_ADC_H\r
+\r
+// A/D Converter Registers\r
+typedef struct\r
+{\r
+ REG32 cr; // Control Register\r
+ REG32 dr; // Data Register\r
+} adcRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_EMC_H\r
+#define INC_LPC_EMC_H\r
+\r
+// External Memory Controller Registers\r
+typedef struct\r
+{\r
+ REG32 bcfg0; // Bank 0 Configuration Register\r
+ REG32 bcfg1; // Bank 1 Configuration Register\r
+ REG32 bcfg2; // Bank 2 Configuration Register\r
+ REG32 bcfg3; // Bank 3 Configuration Register\r
+} emcRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_GPIO_H\r
+#define INC_LPC_GPIO_H\r
+\r
+// General Purpose Input/Output Registers (GPIO)\r
+typedef struct\r
+{\r
+ REG32 in0; // P0 Pin Value Register\r
+ REG32 set0; // P0 Pin Output Set Register\r
+ REG32 dir0; // P0 Pin Direction Register\r
+ REG32 clr0; // P0 Pin Output Clear Register\r
+ REG32 in1; // P1 Pin Value Register\r
+ REG32 set1; // P1 Pin Output Set Register\r
+ REG32 dir1; // P1 Pin Direction Register\r
+ REG32 clr1; // P1 Pin Output Clear Register\r
+ REG32 in2; // P2 Pin Value Register\r
+ REG32 set2; // P2 Pin Output Set Register\r
+ REG32 dir2; // P2 Pin Direction Register\r
+ REG32 clr2; // P2 Pin Output Clear Register\r
+ REG32 in3; // P3 Pin Value Register\r
+ REG32 set3; // P3 Pin Output Set Register\r
+ REG32 dir3; // P3 Pin Direction Register\r
+ REG32 clr3; // P3 Pin Output Clear Register\r
+} gpioRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_I2C_H\r
+#define INC_LPC_I2C_H\r
+\r
+// I2C Interface Registers\r
+typedef struct\r
+{\r
+ REG_8 conset; // Control Set Register\r
+ REG_8 _pad0[3];\r
+ REG_8 stat; // Status Register\r
+ REG_8 _pad1[3];\r
+ REG_8 dat; // Data Register\r
+ REG_8 _pad2[3];\r
+ REG_8 adr; // Slave Address Register\r
+ REG_8 _pad3[3];\r
+ REG16 sclh; // SCL Duty Cycle Register (high half word)\r
+ REG16 _pad4;\r
+ REG16 scll; // SCL Duty Cycle Register (low half word)\r
+ REG16 _pad5;\r
+ REG_8 conclr; // Control Clear Register\r
+ REG_8 _pad6[3];\r
+} i2cRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_PIN_H\r
+#define INC_LPC_PIN_H\r
+\r
+// Pin Connect Block Registers\r
+typedef struct\r
+{\r
+ REG32 sel0; // Pin Function Select Register 0\r
+ REG32 sel1; // Pin Function Select Register 1\r
+ REG32 _pad[3];\r
+ REG32 sel2; // Pin Function Select Register 2\r
+} pinRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_RTC_H\r
+#define INC_LPC_RTC_H\r
+\r
+typedef struct\r
+{\r
+ REG_8 ilr; // Interrupt Location Register\r
+ REG_8 _pad0[3];\r
+ REG16 ctc; // Clock Tick Counter\r
+ REG16 _pad1;\r
+ REG_8 ccr; // Clock Control Register\r
+ REG_8 _pad2[3];\r
+ REG_8 ciir; // Counter Increment Interrupt Register\r
+ REG_8 _pad3[3];\r
+ REG_8 amr; // Alarm Mask Register\r
+ REG_8 _pad4[3];\r
+ REG32 ctime0; // Consolidated Time Register 0\r
+ REG32 ctime1; // Consolidated Time Register 1\r
+ REG32 ctime2; // Consolidated Time Register 2\r
+ REG_8 sec; // Seconds Register\r
+ REG_8 _pad5[3];\r
+ REG_8 min; // Minutes Register\r
+ REG_8 _pad6[3];\r
+ REG_8 hour; // Hours Register\r
+ REG_8 _pad7[3];\r
+ REG_8 dom; // Day Of Month Register\r
+ REG_8 _pad8[3];\r
+ REG_8 dow; // Day Of Week Register\r
+ REG_8 _pad9[3];\r
+ REG16 doy; // Day Of Year Register\r
+ REG16 _pad10;\r
+ REG_8 month; // Months Register\r
+ REG_8 _pad11[3];\r
+ REG16 year; // Years Register\r
+ REG32 _pad12[8];\r
+ REG_8 alsec; // Alarm Seconds Register\r
+ REG_8 _pad13[3];\r
+ REG_8 almin; // Alarm Minutes Register\r
+ REG_8 _pad14[3];\r
+ REG_8 alhour; // Alarm Hours Register\r
+ REG_8 _pad15[3];\r
+ REG_8 aldom; // Alarm Day Of Month Register\r
+ REG_8 _pad16[3];\r
+ REG_8 aldow; // Alarm Day Of Week Register\r
+ REG_8 _pad17[3];\r
+ REG16 aldoy; // Alarm Day Of Year Register\r
+ REG16 _pad18;\r
+ REG_8 almon; // Alarm Months Register\r
+ REG_8 _pad19[3];\r
+ REG16 alyear; // Alarm Years Register\r
+ REG16 _pad20;\r
+ REG16 preint; // Prescale Value Register (integer)\r
+ REG16 _pad21;\r
+ REG16 prefrac; // Prescale Value Register (fraction)\r
+ REG16 _pad22;\r
+} rtcRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_SCB_H\r
+#define INC_LPC_SCB_H\r
+\r
+// System Control Block Registers\r
+typedef struct\r
+{\r
+ // Memory Accelerator Module Registers (MAM)\r
+ struct\r
+ {\r
+ REG_8 cr; // Control Register\r
+ REG_8 _pad0[3];\r
+ REG_8 tim; // Timing Control Register\r
+ REG32 _pad1[14];\r
+ } mam;\r
+\r
+ // Memory Mapping Control Register\r
+ REG_8 memmap;\r
+ REG32 _pad0[15];\r
+\r
+ // Phase Locked Loop Registers (PLL)\r
+ struct\r
+ {\r
+ REG_8 con; // Control Register\r
+ REG_8 _pad0[3];\r
+ REG_8 cfg; // Configuration Register\r
+ REG_8 _pad1[3];\r
+ REG16 stat; // Status Register\r
+ REG16 _pad2;\r
+ REG_8 feed; // Feed Register\r
+ REG32 _pad3[12];\r
+ } pll;\r
+\r
+ // Power Control Registers\r
+ struct\r
+ {\r
+ REG_8 con; // Control Register\r
+ REG_8 _pad0[3];\r
+ REG32 conp; // Peripherals Register\r
+ REG32 _pad1[14];\r
+ } p;\r
+\r
+ // VPB Divider Register\r
+ REG_8 vpbdiv;\r
+ REG32 _pad1[15];\r
+\r
+ // External Interrupt Registers\r
+ struct\r
+ {\r
+ REG_8 flag; // Flag Register\r
+ REG_8 _pad0[3];\r
+ REG_8 wake; // Wakeup Register\r
+ REG_8 _pad1[3];\r
+ REG_8 mode; // Mode Register\r
+ REG_8 _pad2[3];\r
+ REG_8 polar; // Polarity Register\r
+ REG32 _pad3[12];\r
+ } ext;\r
+} scbRegs_t;\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// MAM defines\r
+#define MAMCR_OFF 0\r
+#define MAMCR_PART 1\r
+#define MAMCR_FULL 2\r
+\r
+#define MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000)\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// MEMMAP defines\r
+#define MEMMAP_BBLK 0 // Interrupt Vectors in Boot Block\r
+#define MEMMAP_FLASH 1 // Interrupt Vectors in Flash\r
+#define MEMMAP_SRAM 2 // Interrupt Vectors in SRAM\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// PLL defines & computations\r
+// Compute the value of PLL_DIV and test range validity\r
+// FOSC & PLL_MUL should be defined in project configuration file (config.h)\r
+#ifndef CCLK\r
+#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.\r
+#endif\r
+\r
+#define FCCO_MAX (320000000) // Max CC Osc Freq.\r
+#define PLL_DIV (FCCO_MAX / (2 * CCLK)) // PLL Divider\r
+#define FCCO (FOSC * PLL_MUL * 2 * PLL_DIV) // CC Osc. Freq.\r
+\r
+// PLLCON Register Bit Definitions\r
+#define PLLCON_PLLE (1 << 0) // PLL Enable\r
+#define PLLCON_PLLC (1 << 1) // PLL Connect\r
+\r
+// PLLCFG Register Bit Definitions\r
+#define PLLCFG_MSEL ((PLL_MUL - 1) << 0) // PLL Multiplier\r
+#define PLLCFG_PSEL ((PLL_DIV - 1) << 5) // PLL Divider\r
+\r
+// PLLSTAT Register Bit Definitions\r
+#define PLLSTAT_LOCK (1 << 10) // PLL Lock Status Bit\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// VPBDIV defines & computations\r
+#define VPBDIV_VALUE (PBSD & 0x03) // VPBDIV value\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_SPI_H\r
+#define INC_LPC_SPI_H\r
+\r
+// Serial Peripheral Interface Registers (SPI)\r
+typedef struct\r
+{\r
+ REG_8 cr; // Control Register\r
+ REG_8 _pad0[3];\r
+ REG_8 sr; // Status Register\r
+ REG_8 _pad1[3];\r
+ REG_8 dr; // Data Register\r
+ REG_8 _pad2[3];\r
+ REG_8 ccr; // Clock Counter Register\r
+ REG_8 _pad3[3];\r
+ REG_8 tcr; // Test Control Register\r
+ REG_8 _pad4[3];\r
+ REG_8 tsr; // Test Status Register\r
+ REG_8 _pad5[3];\r
+ REG_8 tor; // Test Observe Register\r
+ REG_8 _pad6[3];\r
+ REG_8 flag; // Interrupt Flag Register\r
+ REG_8 _pad7[3];\r
+} spiRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_TMR_H\r
+#define INC_LPC_TMR_H\r
+\r
+// Timer & PWM Registers\r
+typedef struct\r
+{\r
+ REG32 ir; // Interrupt Register\r
+ REG32 tcr; // Timer Control Register\r
+ REG32 tc; // Timer Counter\r
+ REG32 pr; // Prescale Register\r
+ REG32 pc; // Prescale Counter Register\r
+ REG32 mcr; // Match Control Register\r
+ REG32 mr0; // Match Register 0\r
+ REG32 mr1; // Match Register 1\r
+ REG32 mr2; // Match Register 2\r
+ REG32 mr3; // Match Register 3\r
+ REG32 ccr; // Capture Control Register\r
+ REG32 cr0; // Capture Register 0\r
+ REG32 cr1; // Capture Register 1\r
+ REG32 cr2; // Capture Register 2\r
+ REG32 cr3; // Capture Register 3\r
+ REG32 emr; // External Match Register\r
+ REG32 mr4; // Match Register 4\r
+ REG32 mr5; // Match Register 5\r
+ REG32 mr6; // Match Register 6\r
+ REG32 pcr; // Control Register\r
+ REG32 ler; // Latch Enable Register\r
+} pwmTmrRegs_t;\r
+\r
+// Timer Interrupt Register Bit Definitions\r
+#define TIR_MR0I (1 << 0) // Interrupt flag for match channel 0\r
+#define TIR_MR1I (1 << 1) // Interrupt flag for match channel 1\r
+#define TIR_MR2I (1 << 2) // Interrupt flag for match channel 2\r
+#define TIR_MR3I (1 << 3) // Interrupt flag for match channel 3\r
+#define TIR_CR0I (1 << 4) // Interrupt flag for capture channel 0 event\r
+#define TIR_CR1I (1 << 5) // Interrupt flag for capture channel 1 event\r
+#define TIR_CR2I (1 << 6) // Interrupt flag for capture channel 2 event\r
+#define TIR_CR3I (1 << 7) // Interrupt flag for capture channel 3 event\r
+\r
+// PWM Interrupt Register Bit Definitions\r
+#define PWMIR_MR0I (1 << 0) // Interrupt flag for match channel 0\r
+#define PWMIR_MR1I (1 << 1) // Interrupt flag for match channel 1\r
+#define PWMIR_MR2I (1 << 2) // Interrupt flag for match channel 2\r
+#define PWMIR_MR3I (1 << 3) // Interrupt flag for match channel 3\r
+#define PWMIR_MR4I (1 << 8) // Interrupt flag for match channel 4\r
+#define PWMIR_MR5I (1 << 9) // Interrupt flag for match channel 5\r
+#define PWMIR_MR6I (1 << 10) // Interrupt flag for match channel 6\r
+#define PWMIR_MASK (0x070F)\r
+\r
+// Timer Control Register Bit Definitions\r
+#define TCR_ENABLE (1 << 0)\r
+#define TCR_RESET (1 << 1)\r
+\r
+// PWM Control Register Bit Definitions\r
+#define PWMCR_ENABLE (1 << 0)\r
+#define PWMCR_RESET (1 << 1)\r
+\r
+// Timer Match Control Register Bit Definitions\r
+#define TMCR_MR0_I (1 << 0) // Enable Interrupt when MR0 matches TC\r
+#define TMCR_MR0_R (1 << 1) // Enable Reset of TC upon MR0 match\r
+#define TMCR_MR0_S (1 << 2) // Enable Stop of TC upon MR0 match\r
+#define TMCR_MR1_I (1 << 3) // Enable Interrupt when MR1 matches TC\r
+#define TMCR_MR1_R (1 << 4) // Enable Reset of TC upon MR1 match\r
+#define TMCR_MR1_S (1 << 5) // Enable Stop of TC upon MR1 match\r
+#define TMCR_MR2_I (1 << 6) // Enable Interrupt when MR2 matches TC\r
+#define TMCR_MR2_R (1 << 7) // Enable Reset of TC upon MR2 match\r
+#define TMCR_MR2_S (1 << 8) // Enable Stop of TC upon MR2 match\r
+#define TMCR_MR3_I (1 << 9) // Enable Interrupt when MR3 matches TC\r
+#define TMCR_MR3_R (1 << 10) // Enable Reset of TC upon MR3 match\r
+#define TMCR_MR3_S (1 << 11) // Enable Stop of TC upon MR3 match\r
+\r
+// Timer Capture Control Register Bit Definitions\r
+#define TCCR_CR0_R (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0\r
+#define TCCR_CR0_F (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0\r
+#define TCCR_CR0_I (1 << 2) // Enable Interrupt on load of CR0\r
+#define TCCR_CR1_R (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1\r
+#define TCCR_CR1_F (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1\r
+#define TCCR_CR1_I (1 << 5) // Enable Interrupt on load of CR1\r
+#define TCCR_CR2_R (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2\r
+#define TCCR_CR2_F (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2\r
+#define TCCR_CR2_I (1 << 8) // Enable Interrupt on load of CR2\r
+#define TCCR_CR3_R (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3\r
+#define TCCR_CR3_F (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3\r
+#define TCCR_CR3_I (1 << 11) // Enable Interrupt on load of CR3\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_UART_H\r
+#define INC_LPC_UART_H\r
+\r
+// Universal Asynchronous Receiver Transmitter Registers\r
+typedef struct\r
+{\r
+ union\r
+ {\r
+ REG_8 rbr; // Receive Buffer Register\r
+ REG_8 thr; // Transmit Holding Register\r
+ REG_8 dll; // Divisor Latch Register (LSB)\r
+ REG_8 _pad0[4];\r
+ };\r
+\r
+ union\r
+ {\r
+ REG_8 ier; // Interrupt Enable Register\r
+ REG_8 dlm; // Divisor Latch Register (MSB)\r
+ REG_8 _pad1[4];\r
+ };\r
+\r
+ union\r
+ {\r
+ REG_8 iir; // Interrupt ID Register\r
+ REG_8 fcr; // FIFO Control Register\r
+ REG_8 _pad2[4];\r
+ };\r
+\r
+ REG_8 lcr; // Line Control Registe\r
+ REG_8 _pad3[3];\r
+ REG_8 mcr; // MODEM Control Register\r
+ REG_8 _pad4[3];\r
+ REG_8 lsr; // Line Status Register\r
+ REG_8 _pad5[3];\r
+ REG_8 msr; // MODEM Status Register\r
+ REG_8 _pad6[3];\r
+ REG_8 scr; // Scratch Pad Register\r
+ REG_8 _pad7[3];\r
+} uartRegs_t;\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+// UART defines\r
+\r
+// Interrupt Enable Register bit definitions\r
+#define UIER_ERBFI (1 << 0) // Enable Receive Data Available Interrupt\r
+#define UIER_ETBEI (1 << 1) // Enable Transmit Holding Register Empty Interrupt\r
+#define UIER_ELSI (1 << 2) // Enable Receive Line Status Interrupt\r
+#define UIER_EDSSI (1 << 3) // Enable MODEM Status Interrupt\r
+\r
+// Interrupt ID Register bit definitions\r
+#define UIIR_NO_INT (1 << 0) // NO INTERRUPTS PENDING\r
+#define UIIR_MS_INT (0 << 1) // MODEM Status\r
+#define UIIR_THRE_INT (1 << 1) // Transmit Holding Register Empty\r
+#define UIIR_RDA_INT (2 << 1) // Receive Data Available\r
+#define UIIR_RLS_INT (3 << 1) // Receive Line Status\r
+#define UIIR_CTI_INT (6 << 1) // Character Timeout Indicator\r
+#define UIIR_ID_MASK 0x0E\r
+\r
+// FIFO Control Register bit definitions\r
+#define UFCR_FIFO_ENABLE (1 << 0) // FIFO Enable\r
+#define UFCR_RX_FIFO_RESET (1 << 1) // Reset Receive FIFO\r
+#define UFCR_TX_FIFO_RESET (1 << 2) // Reset Transmit FIFO\r
+#define UFCR_FIFO_TRIG1 (0 << 6) // Trigger @ 1 character in FIFO\r
+#define UFCR_FIFO_TRIG4 (1 << 6) // Trigger @ 4 characters in FIFO\r
+#define UFCR_FIFO_TRIG8 (2 << 6) // Trigger @ 8 characters in FIFO\r
+#define UFCR_FIFO_TRIG14 (3 << 6) // Trigger @ 14 characters in FIFO\r
+\r
+// Line Control Register bit definitions\r
+#define ULCR_CHAR_5 (0 << 0) // 5-bit character length\r
+#define ULCR_CHAR_6 (1 << 0) // 6-bit character length\r
+#define ULCR_CHAR_7 (2 << 0) // 7-bit character length\r
+#define ULCR_CHAR_8 (3 << 0) // 8-bit character length\r
+#define ULCR_STOP_1 (0 << 2) // 1 stop bit\r
+#define ULCR_STOP_2 (1 << 2) // 2 stop bits\r
+#define ULCR_PAR_NO (0 << 3) // No Parity\r
+#define ULCR_PAR_ODD (1 << 3) // Odd Parity\r
+#define ULCR_PAR_EVEN (3 << 3) // Even Parity\r
+#define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity\r
+#define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty\r
+#define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition\r
+#define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access\r
+\r
+// Modem Control Register bit definitions\r
+#define UMCR_DTR (1 << 0) // Data Terminal Ready\r
+#define UMCR_RTS (1 << 1) // Request To Send\r
+#define UMCR_LB (1 << 4) // Loopback\r
+\r
+// Line Status Register bit definitions\r
+#define ULSR_RDR (1 << 0) // Receive Data Ready\r
+#define ULSR_OE (1 << 1) // Overrun Error\r
+#define ULSR_PE (1 << 2) // Parity Error\r
+#define ULSR_FE (1 << 3) // Framing Error\r
+#define ULSR_BI (1 << 4) // Break Interrupt\r
+#define ULSR_THRE (1 << 5) // Transmit Holding Register Empty\r
+#define ULSR_TEMT (1 << 6) // Transmitter Empty\r
+#define ULSR_RXFE (1 << 7) // Error in Receive FIFO\r
+#define ULSR_ERR_MASK 0x1E\r
+\r
+// Modem Status Register bit definitions\r
+#define UMSR_DCTS (1 << 0) // Delta Clear To Send\r
+#define UMSR_DDSR (1 << 1) // Delta Data Set Ready\r
+#define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator\r
+#define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect\r
+#define UMSR_CTS (1 << 4) // Clear To Send\r
+#define UMSR_DSR (1 << 5) // Data Set Ready\r
+#define UMSR_RI (1 << 6) // Ring Indicator\r
+#define UMSR_DCD (1 << 7) // Data Carrier Detect\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************
+ *
+ * $RCSfile: lpcUSB.h,v $
+ * $Revision: 1.3 $
+ *
+ * Header file for Philips LPC214x USB enabled ARM Processors
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * No guarantees, warrantees, or promises, implied or otherwise.
+ * May be used for hobby or commercial purposes provided copyright
+ * notice remains intact or GPL license is applied.
+ *
+ *****************************************************************************/
+
+/* USBIntSt - USB Interrupt Status (R/W) */
+#define USB_INT_REQ_LP (1<<0) /*Low priority interrupt line status (RO) */
+#define USB_INT_REQ_HP (1<<1) /*High priority interrupt line status. (RO) */
+#define USB_INT_REQ_DMA (1<<2) /*DMA interrupt line status. This bit is read only. (LPC2146/8 only) 0*/
+#define USB_need_clock (1<<8) /*USB need clock indicator*/
+#define USB_EN_USB_INTS (1<<31) /*Enable all USB interrupts*/
+
+/* Device interrupt registers */
+#define USBDevIntSt_o 0x0000 /* USB Device Interrupt Status (RO) */
+#define USBDevIntEn_o 0x0004 /* USB Device Interrupt Enable (R/W) */
+#define USBDevIntClr_o 0x0008 /* USB Device Interrupt Clear (WO) */
+#define USBDevIntSet_o 0x000C /* USB Device Interrupt Set (WO) */
+#define USBDevInt_FRAME (1<<0) /*Frame interrupt @1kHz for ISO transfers*/
+#define USBDevInt_EP_FAST (1<<1) /*Fast interrupt transfer for the endpoint*/
+#define USBDevInt_EP_SLOW (1<<2) /*Slow interrupt transfer for the endpoint*/
+#define USBDevInt_DEV_STAT (1<<3) /*USB Bus reset, USB suspend change or Connect occured*/
+#define USBDevInt_CCEMTY (1<<4) /*Command code register is empty/ready for CMD*/
+#define USBDevInt_CDFULL (1<<5) /*Command data register is full/data available*/
+#define USBDevInt_RxENDPKT (1<<6) /*Current packet in the FIFO is transferred to the CPU*/
+#define USBDevInt_TxENDPKT (1<<7) /*TxPacket bytes written to FIFO*/
+#define USBDevInt_EP_RLZED (1<<8) /*Endpoints realized after Maxpacket size update*/
+#define USBDevInt_ERR_INT (1<<9) /*Error Interrupt - Use Read Error Status Command 0xFB*/
+
+#define USBDevIntPri_o 0x002C /* USB Device Interrupt Priority (WO) */
+#define USBDevIntPri_FRAME (1<<0) /*0/1 FRAME int routed to the low/high priority interrupt line*/
+#define USBDevIntPri_EP_FAST (1<<1) /*0/1 EP_FAST int routed to the low/high priority line*/
+
+/* Endpoint interrupt registers - bits corresponds to EP0 to EP31 */
+#define USBEpIntSt_o 0x0030 /* USB Endpoint Interrupt Status (RO) */
+#define USBEpIntEn_o 0x0034 /* USB Endpoint Interrupt Enable (R/W) */
+#define USBEpIntClr_o 0x0038 /* USB Endpoint Interrupt Clear (WO) */
+#define USBEpIntSet_o 0x003C /* USB Endpoint Interrupt Set (WO) */
+#define USBEpIntPri_o 0x0040 /* USB Endpoint Priority (WO) */
+/* Endpoint realization registers */
+#define USBReEp_o 0x0044 /* USB Realize Endpoint (R/W) */
+#define USBEpInd_o 0x0048 /* USB Endpoint Index (WO) */
+#define USBEpInd_Ind 0x001F /* Index for subsequent USBMaxPSize (WO) */
+#define USBMaxPSize_o 0x004C /* USB MaxPacketSize (R/W) */
+#define USBMaxPSize_Size 0x03FF /* The maximum packet size value */
+/* USB transfer registers */
+#define USBRxData_o 0x0018 /* USB Receive Data (RO) */
+#define USBRxPLen_o 0x0020 /* USB Receive Packet Length (RO) */
+#define USBRxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be read from RAM*/
+#define USBRxPLen_DV (1<<10) /*Data valid. 0 only for error ISO packet*/
+#define USBRxPLen_PKT_RDY (1<<11) /*Packet length valid and packet is ready for reading*/
+#define USBTxData_o 0x001C /* USB Transmit Data (WO) */
+#define USBTxPLen_o 0x0024 /* USB Transmit Packet Length (WO) */
+#define USBTxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be written to the EP_RAM*/
+#define USBCtrl_o 0x0028 /* USB Control (R/W) */
+#define USBCtrl_RD_EN (1<<0) /*Read mode control*/
+#define USBCtrl_WR_EN (1<<1) /*Write mode control*/
+#define USBCtrl_LOG_ENDPOINT 0x003C /*Logical Endpoint number*/
+/* Command registers */
+#define USBCmdCode_o 0x0010 /* USB Command Code (WO) */
+#define USBCmdCode_CMD_PHASE 0x0000FF00 /*The command phase*/
+#define USBCmdCode_CMD_CODE 0x00FF0000 /*The code for the command*/
+#define USBCmdData_o 0x0014 /* USB Command Data (RO) */
+/* DMA registers (LPC2146/8 only) */
+#define USBDMARSt_o 0x0050 /* USB DMA Request Status (RO) */
+#define USBDMARClr_o 0x0054 /* USB DMA Request Clear (WO) */
+#define USBDMARSet_o 0x0058 /* USB DMA Request Set (WO) */
+#define USBUDCAH_o 0x0080 /* USB UDCA Head (R/W) has to be aligned to 128 bytes */
+#define USBEpDMASt_o 0x0084 /* USB Endpoint DMA Status (RO) */
+#define USBEpDMAEn_o 0x0088 /* USB Endpoint DMA Enable (WO) */
+#define USBEpDMADis_o 0x008C /* USB Endpoint DMA Disable (WO) */
+#define USBDMAIntSt_o 0x0090 /* USB DMA Interrupt Status (RO) */
+#define USBDMAIntEn_o 0x0094 /* USB DMA Interrupt Enable (R/W) */
+#define USBDMAInt_EoT (1<<0) /*End of Transfer Interrupt bit, 1 if USBEoTIntSt != 0*/
+#define USBDMAInt_New_DD_Rq (1<<1) /* New DD Request Interrupt bit, 1 if USBNDDRIntSt != 0*/
+#define USBDMAInt_SysError (1<<2) /*System Error Interrupt bit, 1 if USBSysErrIntSt != 0*/
+#define USBEoTIntSt_o 0x00A0 /* USB End of Transfer Interrupt Status (RO) */
+#define USBEoTIntClr_o 0x00A4 /* USB End of Transfer Interrupt Clear (WO) */
+#define USBEoTIntSet_o 0x00A8 /* USB End of Transfer Interrupt Set (WO) */
+#define USBNDDRIntSt_o 0x00AC /* USB New DD Request Interrupt Status (RO) */
+#define USBNDDRIntClr_o 0x00B0 /* USB New DD Request Interrupt Clear (WO) */
+#define USBNDDRIntSet_o 0x00B4 /* USB New DD Request Interrupt Set (WO) */
+#define USBSysErrIntSt_o 0x00B8 /* USB System Error Interrupt Status (RO) */
+#define USBSysErrIntClr_o 0x00BC /* USB System Error Interrupt Clear (WO) */
+#define USBSysErrIntSet_o 0x00C0 /* USB System Error Interrupt Set (WO) */
+#define USB_MODULE_ID_o 0x00FC /* USB Module ID */
+
+/* Command Codes */
+#define USB_CMD_SET_ADDR 0x00D00500
+#define USB_CMD_CFG_DEV 0x00D80500
+#define USB_CMD_SET_MODE 0x00F30500
+#define USB_CMD_RD_FRAME 0x00F50500
+#define USB_DAT_RD_FRAME 0x00F50200
+#define USB_CMD_RD_TEST 0x00FD0500
+#define USB_DAT_RD_TEST 0x00FD0200
+#define USB_CMD_SET_DEV_STAT 0x00FE0500
+#define USB_CMD_GET_DEV_STAT 0x00FE0500
+#define USB_DAT_GET_DEV_STAT 0x00FE0200
+#define USB_CMD_GET_ERR_CODE 0x00FF0500
+#define USB_DAT_GET_ERR_CODE 0x00FF0200
+#define USB_CMD_RD_ERR_STAT 0x00FB0500
+#define USB_DAT_RD_ERR_STAT 0x00FB0200
+#define USB_DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
+#define USB_CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
+#define USB_DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
+#define USB_CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
+#define USB_DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
+#define USB_CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
+#define USB_CMD_CLR_BUF 0x00F20500
+#define USB_DAT_CLR_BUF 0x00F20200
+#define USB_CMD_VALID_BUF 0x00FA0500
+
+/* Device Address Register Definitions */
+#define USBC_DEV_ADDR_MASK 0x7F
+#define USBC_DEV_EN 0x80
+
+/* Device Configure Register Definitions */
+#define USBC_CONF_DEVICE 0x01
+
+/* Device Mode Register Definitions */
+#define USBC_AP_CLK 0x01
+#define USBC_INAK_CI 0x02
+#define USBC_INAK_CO 0x04
+#define USBC_INAK_II 0x08
+#define USBC_INAK_IO 0x10
+#define USBC_INAK_BI 0x20
+#define USBC_INAK_BO 0x40
+
+/* Device Status Register Definitions */
+#define USBC_DEV_CON 0x01
+#define USBC_DEV_CON_CH 0x02
+#define USBC_DEV_SUS 0x04
+#define USBC_DEV_SUS_CH 0x08
+#define USBC_DEV_RST 0x10
+
+/* Error Code Register Definitions */
+#define USBC_ERR_EC_MASK 0x0F
+#define USBC_ERR_EA 0x10
+
+/* Error Status Register Definitions */
+#define USBC_ERR_PID 0x01
+#define USBC_ERR_UEPKT 0x02
+#define USBC_ERR_DCRC 0x04
+#define USBC_ERR_TIMOUT 0x08
+#define USBC_ERR_EOP 0x10
+#define USBC_ERR_B_OVRN 0x20
+#define USBC_ERR_BTSTF 0x40
+#define USBC_ERR_TGL 0x80
+
+/* Endpoint Select Register Definitions */
+#define USBC_EP_SEL_F 0x01
+#define USBC_EP_SEL_ST 0x02
+#define USBC_EP_SEL_STP 0x04
+#define USBC_EP_SEL_PO 0x08
+#define USBC_EP_SEL_EPN 0x10
+#define USBC_EP_SEL_B_1_FULL 0x20
+#define USBC_EP_SEL_B_2_FULL 0x40
+
+/* Endpoint Status Register Definitions */
+#define USBC_EP_STAT_ST 0x01
+#define USBC_EP_STAT_DA 0x20
+#define USBC_EP_STAT_RF_MO 0x40
+#define USBC_EP_STAT_CND_ST 0x80
+
+/* Clear Buffer Register Definitions */
+#define USBC_CLR_BUF_PO 0x01
+
+typedef struct
+{
+/* Device interrupt registers */
+ REG32 DevIntSt; /* USB Device Interrupt Status (RO) 0000 */
+ REG32 DevIntEn; /* USB Device Interrupt Enable (R/W) 0004 */
+ REG32 DevIntClr; /* USB Device Interrupt Clear (WO) 0008 */
+ REG32 DevIntSet; /* USB Device Interrupt Set (WO) 000C */
+/* Command registers */
+ REG32 CmdCode; /* USB Command Code (WO) 0010 */
+ REG32 CmdData; /* USB Command Data (RO) 0014 */
+/* USB transfer registers */
+ REG32 RxData; /* USB Receive Data (RO) 0018 */
+ REG32 TxData; /* USB Transmit Data (WO) 001C */
+ REG32 RxPLen; /* USB Receive Packet Length (RO) 0020 */
+ REG32 TxPLen; /* USB Transmit Packet Length (WO) 0024 */
+ REG32 Ctrl; /* USB Control (R/W) 0028 */
+/* Device interrupt priority register */
+ REG_8 USBDevIntPri; /* USB Device Interrupt Priority (WO) 002C */
+ REG_8 _pad0[3];
+/* Endpoint interrupt registers */
+ REG32 EpIntSt; /* USB Endpoint Interrupt Status (RO) 0030 */
+ REG32 EpIntEn; /* USB Endpoint Interrupt Enable (R/W) 0034 */
+ REG32 EpIntClr; /* USB Endpoint Interrupt Clear (WO) 0038 */
+ REG32 EpIntSet; /* USB Endpoint Interrupt Set (WO) 003C */
+ REG32 EpIntPri; /* USB Endpoint Priority (WO) 0040 */
+/* Endpoint realization registers */
+ REG32 ReEp; /* USB Realize Endpoint (R/W) 0044 */
+ REG32 EpInd; /* USB Endpoint Index (WO) 0048 */
+ REG32 MaxPSize; /* USB MaxPacketSize (R/W) 004C */
+/* DMA registers (LPC2146/8 only) */
+ REG32 DMARSt; /* USB DMA Request Status (RO) 0050 */
+ REG32 DMARClr; /* USB DMA Request Clear (WO) 0054 */
+ REG32 DMARSet; /* USB DMA Request Set (WO) 0058 */
+ REG32 _pad1[9];
+ REG32 UDCAH; /* USB UDCA Head (R/W) 0080 */
+ REG32 EpDMASt; /* USB Endpoint DMA Status (RO) 0084 */
+ REG32 EpDMAEn; /* USB Endpoint DMA Enable (WO) 0088 */
+ REG32 EpDMADis; /* USB Endpoint DMA Disable (WO) 008C */
+ REG32 DMAIntSt; /* USB DMA Interrupt Status (RO) 0090 */
+ REG32 DMAIntEn; /* USB DMA Interrupt Enable (R/W) 0094 */
+ REG32 _pad2[2];
+ REG32 EoTIntSt; /* USB End of Transfer Interrupt Status (RO) 00A0 */
+ REG32 EoTIntClr; /* USB End of Transfer Interrupt Clear (WO) 00A4 */
+ REG32 EoTIntSet; /* USB End of Transfer Interrupt Set (WO) 00A8 */
+ REG32 NDDRIntSt; /* USB New DD Request Interrupt Status (RO) 00AC */
+ REG32 NDDRIntClr; /* USB New DD Request Interrupt Clear (WO) 00B0 */
+ REG32 NDDRIntSet; /* USB New DD Request Interrupt Set (WO) 00B4 */
+ REG32 SysErrIntSt; /* USB System Error Interrupt Status (RO) 00B8 */
+ REG32 SysErrIntClr; /* USB System Error Interrupt Clear (WO) 00BC */
+ REG32 SysErrIntSet; /* USB System Error Interrupt Set (WO) 00C0 */
+ REG32 _pad3[0xE];
+ REG32 MODULE_ID; /* Module ID (RO) 00FC */
+} usbRegs_t;
+
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_VIC_H\r
+#define INC_LPC_VIC_H\r
+\r
+// Vectored Interrupt Controller Registers (VIC)\r
+typedef struct\r
+{\r
+ REG32 irqStatus; // IRQ Status Register\r
+ REG32 fiqStatus; // FIQ Status Register\r
+ REG32 rawIntr; // Raw Interrupt Status Register\r
+ REG32 intSelect; // Interrupt Select Register\r
+ REG32 intEnable; // Interrupt Enable Register\r
+ REG32 intEnClear; // Interrupt Enable Clear Register\r
+ REG32 softInt; // Software Interrupt Register\r
+ REG32 softIntClear; // Software Interrupt Clear Register\r
+ REG32 protection; // Protection Enable Register\r
+ REG32 _pad0[3];\r
+ REG32 vectAddr; // Vector Address Register\r
+ REG32 defVectAddr; // Default Vector Address Register\r
+ REG32 _pad1[50];\r
+ REG32 vectAddr0; // Vector Address 0 Register\r
+ REG32 vectAddr1; // Vector Address 1 Register\r
+ REG32 vectAddr2; // Vector Address 2 Register\r
+ REG32 vectAddr3; // Vector Address 3 Register\r
+ REG32 vectAddr4; // Vector Address 4 Register\r
+ REG32 vectAddr5; // Vector Address 5 Register\r
+ REG32 vectAddr6; // Vector Address 6 Register\r
+ REG32 vectAddr7; // Vector Address 7 Register\r
+ REG32 vectAddr8; // Vector Address 8 Register\r
+ REG32 vectAddr9; // Vector Address 9 Register\r
+ REG32 vectAddr10; // Vector Address 10 Register\r
+ REG32 vectAddr11; // Vector Address 11 Register\r
+ REG32 vectAddr12; // Vector Address 12 Register\r
+ REG32 vectAddr13; // Vector Address 13 Register\r
+ REG32 vectAddr14; // Vector Address 14 Register\r
+ REG32 vectAddr15; // Vector Address 15 Register\r
+ REG32 _pad2[48];\r
+ REG32 vectCntl0; // Vector Control 0 Register\r
+ REG32 vectCntl1; // Vector Control 1 Register\r
+ REG32 vectCntl2; // Vector Control 2 Register\r
+ REG32 vectCntl3; // Vector Control 3 Register\r
+ REG32 vectCntl4; // Vector Control 4 Register\r
+ REG32 vectCntl5; // Vector Control 5 Register\r
+ REG32 vectCntl6; // Vector Control 6 Register\r
+ REG32 vectCntl7; // Vector Control 7 Register\r
+ REG32 vectCntl8; // Vector Control 8 Register\r
+ REG32 vectCntl9; // Vector Control 9 Register\r
+ REG32 vectCntl10; // Vector Control 10 Register\r
+ REG32 vectCntl11; // Vector Control 11 Register\r
+ REG32 vectCntl12; // Vector Control 12 Register\r
+ REG32 vectCntl13; // Vector Control 13 Register\r
+ REG32 vectCntl14; // Vector Control 14 Register\r
+ REG32 vectCntl15; // Vector Control 15 Register\r
+} vicRegs_t;\r
+\r
+// VIC Channel Assignments\r
+#define VIC_WDT 0\r
+#define VIC_TIMER0 4\r
+#define VIC_TIMER1 5\r
+#define VIC_UART0 6\r
+#define VIC_UART1 7\r
+#define VIC_PWM 8\r
+#define VIC_PWM0 8\r
+#define VIC_I2C 9\r
+#define VIC_SPI 10\r
+#define VIC_SPI0 10\r
+#define VIC_SPI1 11\r
+#define VIC_PLL 12\r
+#define VIC_RTC 13\r
+#define VIC_EINT0 14\r
+#define VIC_EINT1 15\r
+#define VIC_EINT2 16\r
+#define VIC_EINT3 17\r
+#define VIC_ADC 18\r
+\r
+// Vector Control Register bit definitions\r
+#define VIC_ENABLE (1 << 5)\r
+\r
+// Convert Channel Number to Bit Value\r
+#define VIC_BIT(chan) (1 << (chan))\r
+\r
+#endif\r
+\r
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * $RCSfile: $\r
+ * $Revision: $\r
+ *\r
+ * Header file for Philips LPC ARM Processors.\r
+ * Copyright 2004 R O SoftWare\r
+ *\r
+ * No guarantees, warrantees, or promises, implied or otherwise.\r
+ * May be used for hobby or commercial purposes provided copyright\r
+ * notice remains intact.\r
+ *\r
+ *****************************************************************************/\r
+#ifndef INC_LPC_WD_H\r
+#define INC_LPC_WD_H\r
+\r
+// Watchdog Registers\r
+typedef struct\r
+{\r
+ REG_8 mod; // Watchdog Mode Register\r
+ REG_8 _pad0[3];\r
+ REG32 tc; // Watchdog Time Constant Register\r
+ REG_8 feed; // Watchdog Feed Register\r
+ REG32 tv; // Watchdog Time Value Register\r
+} wdRegs_t;\r
+\r
+#endif\r
--- /dev/null
+/**************************** dev_cntrl.h *******************************/\r
+/* Copyright 2003/12/28 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Provides definitions and prototypes for device drivers to run with */\r
+/* newlib. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 dev_cntrl.h 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+\r
+#ifndef DEV_CNTRL__H\r
+#define DEV_CNTRL__H\r
+\r
+#include <reent.h>\r
+\r
+ /* Structure used to define a device driver. */\r
+struct device_table_entry {\r
+ const char *name; /* Device name. */\r
+\r
+ /* Device open method. */\r
+ int (*open)(struct _reent *r,const char *name, int flags, int mode);\r
+\r
+ /* Device close method. */\r
+ int (*close)(struct _reent *r,int file);\r
+\r
+ /* Device read method. */\r
+ _ssize_t (*read)(struct _reent *r,int file, void *ptr, size_t len);\r
+\r
+ /* Device write method. */\r
+ _ssize_t (*write)(struct _reent *r,int file, const void *ptr, size_t len);\r
+\r
+ /* Device ioctl method (controls device operating parameters. */\r
+ int (*ioctl)(struct _reent *r, int file, unsigned long request, void *ptr);\r
+ };\r
+\r
+ /* List of devices. Newlib adapatation uses this to determine */\r
+ /* what devices are available and how to control them. List */\r
+ /* is terminated by a null pointer entry. */\r
+ /* Note: Entries 0, 1, 2 are reserved to address stdin, */\r
+ /* stdout and stderr. These must be able to work from a */\r
+ /* standard open w/o needing further setup if they are to be */\r
+ /* transparent, alternatively they must be setup before any I/O */\r
+ /* is done. */\r
+extern const struct device_table_entry *device_table[];\r
+\r
+ /* Macros to split file number into two pieces. The low order */\r
+ /* 8 bits are used to index the specific device being addressed */\r
+ /* (hopefully 256 devices is an unreasonbly large limit). The */\r
+ /* remaining bits are used in a device specific fashion to */\r
+ /* allow each device driver to address multiple devices or */\r
+ /* files. */\r
+#define DEVICE(x) ((x) & 0xFF)\r
+ /*lint -emacro(702,SUB_FILE) right shift of signed qty */\r
+#define SUB_FILE(x) ((x) >> 8) \r
+\r
+ /**** Existing device drivers that may be used. ****/\r
+extern const struct device_table_entry com1; /* UART0. */\r
+extern const struct device_table_entry sys; /* SYS -- Essentially */\r
+ /* a dummy. */\r
+#endif /* DEV_CNTRL__H */\r
--- /dev/null
+/**************************** errno_lpc.h *******************************/\r
+/* Copyright 2003/12/29 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Errno definitions specific to this newlib port. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 errno_lpc.h 30-Dec-2003,10:34:14,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+\r
+#ifndef ERRNO_LPC__H\r
+#define ERRNO_LPC__H\r
+\r
+#define ELPC_CANT 2001 /* Can't preform requested operation. */\r
+#define ELPC_OOR 2002 /* Argument out of range. */\r
+#define ELPC_INTERNAL 2003 /* Internal error encounterd. */\r
+\r
+#endif /*ERRNO_LPC__H*/\r
--- /dev/null
+/**************************** lpc210x.h *********************************/\r
+/* Copyright 2003/12/29 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Register definitions for LPC2104/LPC2105/LPC2106. Works with the */\r
+/* appropriate link script to set up the register addresses. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 lpc210x.h 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* 2 lpc210x.h 17-Jan-2004,14:18:12,`RADSETT' Correct title line.\r
+* TLIB revision history ends.\r
+*/\r
+\r
+/* lint -library*/\r
+#ifndef LPC210X__H\r
+#define LPC210X__H\r
+\r
+/* WD */\r
+extern volatile unsigned char WDMOD;\r
+extern volatile unsigned int WDTC;\r
+extern volatile unsigned char WDFEED;\r
+extern volatile const unsigned int WDTV;\r
+\r
+/* TIMER 0 */\r
+\r
+extern volatile unsigned char T0IR;\r
+extern volatile unsigned char T0TCR;\r
+extern volatile unsigned int T0TC;\r
+extern volatile unsigned int T0PR;\r
+extern volatile unsigned int T0PC;\r
+extern volatile unsigned short T0MCR;\r
+extern volatile unsigned int T0MR0;\r
+extern volatile unsigned int T0MR1;\r
+extern volatile unsigned int T0MR2;\r
+extern volatile unsigned int T0MR3;\r
+extern volatile unsigned short T0CCR;\r
+extern volatile const unsigned int T0CR0;\r
+extern volatile const unsigned int T0CR1;\r
+extern volatile const unsigned int T0CR2;\r
+extern volatile unsigned short T0EMR;\r
+\r
+/* TIMER 1 */\r
+\r
+extern volatile unsigned char T1IR;\r
+extern volatile unsigned char T1TCR;\r
+extern volatile unsigned int T1TC;\r
+extern volatile unsigned int T1PR;\r
+extern volatile unsigned int T1PC;\r
+extern volatile unsigned short T1MCR;\r
+extern volatile unsigned int T1MR0;\r
+extern volatile unsigned int T1MR1;\r
+extern volatile unsigned int T1MR2;\r
+extern volatile unsigned int T1MR3;\r
+extern volatile unsigned short T1CCR;\r
+extern volatile const unsigned int T1CR0;\r
+extern volatile const unsigned int T1CR1;\r
+extern volatile const unsigned int T1CR2;\r
+extern volatile const unsigned int T1CR3;\r
+extern volatile unsigned short T1EMR;\r
+\r
+/* UART 0 */\r
+\r
+extern volatile const unsigned char U0RBR;\r
+extern volatile unsigned char U0THR;\r
+extern volatile unsigned char U0DLL;\r
+extern volatile unsigned char U0IER;\r
+extern volatile unsigned char U0DLM;\r
+extern volatile const unsigned char U0IIR;\r
+extern volatile unsigned char U0FCR;\r
+extern volatile unsigned char U0LCR;\r
+extern volatile const unsigned char U0LSR;\r
+extern volatile unsigned char U0SCR;\r
+\r
+/* UART 1 */\r
+\r
+extern volatile const unsigned char U1RBR;\r
+extern volatile unsigned char U1THR;\r
+extern volatile unsigned char U1DLL;\r
+extern volatile unsigned char U1IER;\r
+extern volatile unsigned char U1DLM;\r
+extern volatile const unsigned char U1IIR;\r
+extern volatile unsigned char U1FCR;\r
+extern volatile unsigned char U1LCR;\r
+extern volatile unsigned char U1MCR;\r
+extern volatile const unsigned char U1LSR;\r
+extern volatile const unsigned char U1MSR;\r
+extern volatile unsigned char U1SCR;\r
+\r
+/* PWM */\r
+\r
+extern volatile unsigned short PWMIR;\r
+extern volatile unsigned char PWMTCR;\r
+extern volatile unsigned int PWMTC;\r
+extern volatile unsigned int PWMPR;\r
+extern volatile unsigned int PWMPC;\r
+extern volatile unsigned int PWMMCR;\r
+extern volatile unsigned int PWMMR0;\r
+extern volatile unsigned int PWMMR1;\r
+extern volatile unsigned int PWMMR2;\r
+extern volatile unsigned int PWMMR3;\r
+extern volatile unsigned int PWMMR4;\r
+extern volatile unsigned int PWMMR5;\r
+extern volatile unsigned int PWMMR6;\r
+extern volatile unsigned short PWMPCR;\r
+extern volatile unsigned char PWMLER;\r
+\r
+/* IIC */\r
+\r
+extern volatile unsigned char I2CONSET;\r
+extern volatile const unsigned char I2STAT;\r
+extern volatile unsigned char I2DAT;\r
+extern volatile unsigned char I2ADR;\r
+extern volatile unsigned short I2SCLH;\r
+extern volatile unsigned short I2SCLL;\r
+extern volatile unsigned char I2CONCLR;\r
+\r
+/* SPI */\r
+\r
+extern volatile unsigned char SPCR;\r
+extern volatile const unsigned char SPSR;\r
+extern volatile unsigned char SPPR;\r
+extern volatile unsigned char SPCCR;\r
+extern volatile unsigned char SPINT;\r
+\r
+/* RTC */\r
+\r
+extern volatile unsigned char ILR;\r
+extern volatile const unsigned char CTC;\r
+extern volatile unsigned char CCR;\r
+extern volatile unsigned char CIIR;\r
+extern volatile unsigned char AMR;\r
+extern volatile unsigned int CTIME0;\r
+extern volatile unsigned int CTIME1;\r
+extern volatile unsigned int CTIME2;\r
+extern volatile unsigned char SEC;\r
+extern volatile unsigned char MINUTE; /* MIN conflicts with linker */\r
+extern volatile unsigned char HOUR;\r
+extern volatile unsigned char DOM;\r
+extern volatile unsigned char DOW;\r
+extern volatile unsigned short DOY;\r
+extern volatile unsigned MONTH;\r
+extern volatile unsigned short YEAR;\r
+extern volatile unsigned char ALSEC;\r
+extern volatile unsigned char ALMIN;\r
+extern volatile unsigned char ALHOUR;\r
+extern volatile unsigned char ALDOM;\r
+extern volatile unsigned char ALDOW;\r
+extern volatile unsigned short ALDOY;\r
+extern volatile unsigned char ALMON;\r
+extern volatile unsigned short ALYEAR;\r
+extern volatile unsigned short PREINT;\r
+extern volatile unsigned short PREFRAC;\r
+\r
+/* GPIO */\r
+\r
+extern volatile const unsigned int IOPIN;\r
+extern unsigned int IODIR;\r
+extern volatile unsigned int IOCLR;\r
+extern volatile unsigned int IOSET;\r
+\r
+/* PIN CONNECT BLOCK */\r
+\r
+extern unsigned int PINSEL0;\r
+extern unsigned int PINSEL1;\r
+\r
+\r
+/* SYSTEM CONTROL BLOCK */\r
+ /* MAM */\r
+\r
+extern unsigned char MAMCR;\r
+extern unsigned char MAMTIM;\r
+\r
+\r
+extern unsigned char MEMAP;\r
+\r
+ /* PLL */\r
+\r
+extern volatile unsigned char PLLCON;\r
+extern volatile unsigned char PLLCFG;\r
+extern volatile const unsigned short PLLSTAT;\r
+extern volatile unsigned char PLLFEED;\r
+\r
+ /* POWER CONTROL */\r
+\r
+extern volatile unsigned char PCON;\r
+extern volatile unsigned short PCONP;\r
+\r
+ /* VPB */\r
+\r
+extern volatile unsigned char VPBDIV;\r
+\r
+ /* EXTERNAL INTERUPT/WAKE */\r
+\r
+extern volatile unsigned char EXTINT;\r
+extern volatile unsigned char EXTWAKE;\r
+\r
+#endif /* LPC210X__H */\r
--- /dev/null
+/**************************** lpc2119.h *********************************/\r
+/* Copyright 2004/06/15 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* Register definitions for LPC2119/LPC2129/LPC2194/LPC2292/LPC2294. */\r
+/* Works with the appropriate link script to set up the register */\r
+/* addresses. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 lpc2119.h 16-Jul-2004,11:49:34,`RADSETT' Original archived version.\r
+* TLIB revision history ends.\r
+*/\r
+\r
+/* lint -library*/\r
+#ifndef LPC2119__H\r
+#define LPC2119__H\r
+\r
+/* WD */\r
+extern volatile unsigned char WDMOD;\r
+extern volatile unsigned int WDTC;\r
+extern volatile unsigned char WDFEED;\r
+extern volatile const unsigned int WDTV;\r
+\r
+/* TIMER 0 */\r
+\r
+extern volatile unsigned char T0IR;\r
+extern volatile unsigned char T0TCR;\r
+extern volatile unsigned int T0TC;\r
+extern volatile unsigned int T0PR;\r
+extern volatile unsigned int T0PC;\r
+extern volatile unsigned short T0MCR;\r
+extern volatile unsigned int T0MR0;\r
+extern volatile unsigned int T0MR1;\r
+extern volatile unsigned int T0MR2;\r
+extern volatile unsigned int T0MR3;\r
+extern volatile unsigned short T0CCR;\r
+extern volatile const unsigned int T0CR0;\r
+extern volatile const unsigned int T0CR1;\r
+extern volatile const unsigned int T0CR2;\r
+extern volatile unsigned short T0EMR;\r
+\r
+/* TIMER 1 */\r
+\r
+extern volatile unsigned char T1IR;\r
+extern volatile unsigned char T1TCR;\r
+extern volatile unsigned int T1TC;\r
+extern volatile unsigned int T1PR;\r
+extern volatile unsigned int T1PC;\r
+extern volatile unsigned short T1MCR;\r
+extern volatile unsigned int T1MR0;\r
+extern volatile unsigned int T1MR1;\r
+extern volatile unsigned int T1MR2;\r
+extern volatile unsigned int T1MR3;\r
+extern volatile unsigned short T1CCR;\r
+extern volatile const unsigned int T1CR0;\r
+extern volatile const unsigned int T1CR1;\r
+extern volatile const unsigned int T1CR2;\r
+extern volatile const unsigned int T1CR3;\r
+extern volatile unsigned short T1EMR;\r
+\r
+/* UART 0 */\r
+\r
+extern volatile const unsigned char U0RBR;\r
+extern volatile unsigned char U0THR;\r
+extern volatile unsigned char U0DLL;\r
+extern volatile unsigned char U0IER;\r
+extern volatile unsigned char U0DLM;\r
+extern volatile const unsigned char U0IIR;\r
+extern volatile unsigned char U0FCR;\r
+extern volatile unsigned char U0LCR;\r
+extern volatile const unsigned char U0LSR;\r
+extern volatile unsigned char U0SCR;\r
+\r
+/* UART 1 */\r
+\r
+extern volatile const unsigned char U1RBR;\r
+extern volatile unsigned char U1THR;\r
+extern volatile unsigned char U1DLL;\r
+extern volatile unsigned char U1IER;\r
+extern volatile unsigned char U1DLM;\r
+extern volatile const unsigned char U1IIR;\r
+extern volatile unsigned char U1FCR;\r
+extern volatile unsigned char U1LCR;\r
+extern volatile unsigned char U1MCR;\r
+extern volatile const unsigned char U1LSR;\r
+extern volatile const unsigned char U1MSR;\r
+extern volatile unsigned char U1SCR;\r
+\r
+/* PWM */\r
+\r
+extern volatile unsigned short PWMIR;\r
+extern volatile unsigned char PWMTCR;\r
+extern volatile unsigned int PWMTC;\r
+extern volatile unsigned int PWMPR;\r
+extern volatile unsigned int PWMPC;\r
+extern volatile unsigned int PWMMCR;\r
+extern volatile unsigned int PWMMR0;\r
+extern volatile unsigned int PWMMR1;\r
+extern volatile unsigned int PWMMR2;\r
+extern volatile unsigned int PWMMR3;\r
+extern volatile unsigned int PWMMR4;\r
+extern volatile unsigned int PWMMR5;\r
+extern volatile unsigned int PWMMR6;\r
+extern volatile unsigned short PWMPCR;\r
+extern volatile unsigned char PWMLER;\r
+\r
+/* IIC */\r
+\r
+extern volatile unsigned char I2CONSET;\r
+extern volatile const unsigned char I2STAT;\r
+extern volatile unsigned char I2DAT;\r
+extern volatile unsigned char I2ADR;\r
+extern volatile unsigned short I2SCLH;\r
+extern volatile unsigned short I2SCLL;\r
+extern volatile unsigned char I2CONCLR;\r
+\r
+/* SPI/SPI0 */\r
+\r
+extern volatile unsigned char S0PCR;\r
+extern volatile const unsigned char S0PSR;\r
+extern volatile unsigned char S0PPR;\r
+extern volatile unsigned char S0PCCR;\r
+extern volatile unsigned char S0PINT;\r
+\r
+ /* Synonyms for compatibility with the 210x series. */\r
+extern volatile unsigned char SPCR;\r
+extern volatile const unsigned char SPSR;\r
+extern volatile unsigned char SPPR;\r
+extern volatile unsigned char SPCCR;\r
+extern volatile unsigned char SPINT;\r
+\r
+/* RTC */\r
+\r
+extern volatile unsigned char ILR;\r
+extern volatile const unsigned char CTC;\r
+extern volatile unsigned char CCR;\r
+extern volatile unsigned char CIIR;\r
+extern volatile unsigned char AMR;\r
+extern volatile unsigned int CTIME0;\r
+extern volatile unsigned int CTIME1;\r
+extern volatile unsigned int CTIME2;\r
+extern volatile unsigned char SEC;\r
+extern volatile unsigned char MINUTE; /* MIN conflicts with linker */\r
+extern volatile unsigned char HOUR;\r
+extern volatile unsigned char DOM;\r
+extern volatile unsigned char DOW;\r
+extern volatile unsigned short DOY;\r
+extern volatile unsigned MONTH;\r
+extern volatile unsigned short YEAR;\r
+extern volatile unsigned char ALSEC;\r
+extern volatile unsigned char ALMIN;\r
+extern volatile unsigned char ALHOUR;\r
+extern volatile unsigned char ALDOM;\r
+extern volatile unsigned char ALDOW;\r
+extern volatile unsigned short ALDOY;\r
+extern volatile unsigned char ALMON;\r
+extern volatile unsigned short ALYEAR;\r
+extern volatile unsigned short PREINT;\r
+extern volatile unsigned short PREFRAC;\r
+\r
+/* GPIO PORT0 */\r
+\r
+extern volatile const unsigned int IO0PIN;\r
+extern unsigned int IO0DIR;\r
+extern volatile unsigned int IO0CLR;\r
+extern volatile unsigned int IO0SET;\r
+\r
+ /* Synonyms for compatibility with the 210x series. */\r
+extern volatile const unsigned int IOPIN;\r
+extern unsigned int IODIR;\r
+extern volatile unsigned int IOCLR;\r
+extern volatile unsigned int IOSET;\r
+\r
+/* GPIO PORT1 */\r
+\r
+extern volatile const unsigned int IO1PIN;\r
+extern unsigned int IO1DIR;\r
+extern volatile unsigned int IO1CLR;\r
+extern volatile unsigned int IO1SET;\r
+\r
+/* GPIO PORT2 */\r
+\r
+extern volatile const unsigned int IO2PIN;\r
+extern unsigned int IO2DIR;\r
+extern volatile unsigned int IO2CLR;\r
+extern volatile unsigned int IO2SET;\r
+\r
+/* GPIO PORT3 */\r
+\r
+extern volatile const unsigned int IO3PIN;\r
+extern unsigned int IO3DIR;\r
+extern volatile unsigned int IO3CLR;\r
+extern volatile unsigned int IO3SET;\r
+\r
+/* PIN CONNECT BLOCK */\r
+\r
+extern unsigned int PINSEL0;\r
+extern unsigned int PINSEL1;\r
+extern unsigned int PINSEL2;\r
+\r
+/* SPI1 */\r
+\r
+extern volatile unsigned char S1PCR;\r
+extern volatile const unsigned char S1PSR;\r
+extern volatile unsigned char S1PPR;\r
+extern volatile unsigned char S1PCCR;\r
+extern volatile unsigned char S1PINT;\r
+\r
+/* ADC */\r
+\r
+ /* Renamed from AD... to prevent ld conflict. */\r
+extern volatile unsigned int A2DCR;\r
+extern volatile unsigned int A2DDR;\r
+\r
+/* CAN */\r
+\r
+extern volatile unsigned int CAN_RECV[0x200];\r
+extern volatile unsigned int AFMR;\r
+extern volatile unsigned int SFF_sa;\r
+extern volatile unsigned int SFF_GRP_sa;\r
+extern volatile unsigned int EFF_sa;\r
+extern volatile unsigned int EFF_GRP_sa;\r
+extern volatile unsigned int ENDofTable;\r
+extern const volatile unsigned int LUTerrAd;\r
+extern const volatile unsigned int LUTerr;\r
+extern const volatile unsigned int CANTxSR;\r
+extern const volatile unsigned int CANRxSR;\r
+extern const volatile unsigned int CANMSR;\r
+\r
+/* CAN1 Interface */\r
+\r
+extern volatile unsigned int C1MOD;\r
+extern volatile unsigned int C1CMR;\r
+extern const volatile unsigned int C1GSR;\r
+extern const volatile unsigned int C1ICR;\r
+extern volatile unsigned int C1IER;\r
+extern volatile unsigned int C1BTR;\r
+extern volatile unsigned int C1EWL;\r
+extern const volatile unsigned int C1SR;\r
+extern volatile unsigned int C1RFS;\r
+extern volatile unsigned int C1RID;\r
+extern volatile unsigned int C1RDA;\r
+extern volatile unsigned int C1RDB;\r
+extern volatile unsigned int C1TFI1;\r
+extern volatile unsigned int C1TID1;\r
+extern volatile unsigned int C1TDA1;\r
+extern volatile unsigned int C1TDB1;\r
+extern volatile unsigned int C1TFI2;\r
+extern volatile unsigned int C1TID2;\r
+extern volatile unsigned int C1TDA2;\r
+extern volatile unsigned int C1TDB2;\r
+extern volatile unsigned int C1TFI3;\r
+extern volatile unsigned int C1TID3;\r
+extern volatile unsigned int C1TDA3;\r
+extern volatile unsigned int C1TDB3;\r
+\r
+/* CAN2 Interface */\r
+\r
+extern volatile unsigned int C2MOD;\r
+extern volatile unsigned int C2CMR;\r
+extern const volatile unsigned int C2GSR;\r
+extern const volatile unsigned int C2ICR;\r
+extern volatile unsigned int C2IER;\r
+extern volatile unsigned int C2BTR;\r
+extern volatile unsigned int C2EWL;\r
+extern const volatile unsigned int C2SR;\r
+extern volatile unsigned int C2RFS;\r
+extern volatile unsigned int C2RID;\r
+extern volatile unsigned int C2RDA;\r
+extern volatile unsigned int C2RDB;\r
+extern volatile unsigned int C2TFI1;\r
+extern volatile unsigned int C2TID1;\r
+extern volatile unsigned int C2TDA1;\r
+extern volatile unsigned int C2TDB1;\r
+extern volatile unsigned int C2TFI2;\r
+extern volatile unsigned int C2TID2;\r
+extern volatile unsigned int C2TDA2;\r
+extern volatile unsigned int C2TDB2;\r
+extern volatile unsigned int C2TFI3;\r
+extern volatile unsigned int C2TID3;\r
+extern volatile unsigned int C2TDA3;\r
+extern volatile unsigned int C2TDB3;\r
+\r
+/* CAN3 Interface */\r
+\r
+extern volatile unsigned int C3MOD;\r
+extern volatile unsigned int C3CMR;\r
+extern const volatile unsigned int C3GSR;\r
+extern const volatile unsigned int C3ICR;\r
+extern volatile unsigned int C3IER;\r
+extern volatile unsigned int C3BTR;\r
+extern volatile unsigned int C3EWL;\r
+extern const volatile unsigned int C3SR;\r
+extern volatile unsigned int C3RFS;\r
+extern volatile unsigned int C3RID;\r
+extern volatile unsigned int C3RDA;\r
+extern volatile unsigned int C3RDB;\r
+extern volatile unsigned int C3TFI1;\r
+extern volatile unsigned int C3TID1;\r
+extern volatile unsigned int C3TDA1;\r
+extern volatile unsigned int C3TDB1;\r
+extern volatile unsigned int C3TFI2;\r
+extern volatile unsigned int C3TID2;\r
+extern volatile unsigned int C3TDA2;\r
+extern volatile unsigned int C3TDB2;\r
+extern volatile unsigned int C3TFI3;\r
+extern volatile unsigned int C3TID3;\r
+extern volatile unsigned int C3TDA3;\r
+extern volatile unsigned int C3TDB3;\r
+\r
+/* CAN4 Interface */\r
+\r
+extern volatile unsigned int C4MOD;\r
+extern volatile unsigned int C4CMR;\r
+extern const volatile unsigned int C4GSR;\r
+extern const volatile unsigned int C4ICR;\r
+extern volatile unsigned int C4IER;\r
+extern volatile unsigned int C4BTR;\r
+extern volatile unsigned int C4EWL;\r
+extern const volatile unsigned int C4SR;\r
+extern volatile unsigned int C4RFS;\r
+extern volatile unsigned int C4RID;\r
+extern volatile unsigned int C4RDA;\r
+extern volatile unsigned int C4RDB;\r
+extern volatile unsigned int C4TFI1;\r
+extern volatile unsigned int C4TID1;\r
+extern volatile unsigned int C4TDA1;\r
+extern volatile unsigned int C4TDB1;\r
+extern volatile unsigned int C4TFI2;\r
+extern volatile unsigned int C4TID2;\r
+extern volatile unsigned int C4TDA2;\r
+extern volatile unsigned int C4TDB2;\r
+extern volatile unsigned int C4TFI3;\r
+extern volatile unsigned int C4TID3;\r
+extern volatile unsigned int C4TDA3;\r
+extern volatile unsigned int C4TDB3;\r
+\r
+/* SYSTEM CONTROL BLOCK */\r
+ /* MAM */\r
+\r
+extern unsigned char MAMCR;\r
+extern unsigned char MAMTIM;\r
+\r
+\r
+extern unsigned char MEMAP;\r
+\r
+ /* PLL */\r
+\r
+extern volatile unsigned char PLLCON;\r
+extern volatile unsigned char PLLCFG;\r
+extern volatile const unsigned short PLLSTAT;\r
+extern volatile unsigned char PLLFEED;\r
+\r
+ /* POWER CONTROL */\r
+\r
+extern volatile unsigned char PCON;\r
+extern volatile unsigned short PCONP;\r
+\r
+ /* VPB */\r
+\r
+extern volatile unsigned char VPBDIV;\r
+\r
+ /* EXTERNAL INTERUPT/WAKE */\r
+\r
+extern volatile unsigned char EXTINT;\r
+extern volatile unsigned char EXTWAKE;\r
+extern volatile unsigned char EXTMODE;\r
+extern volatile unsigned char EXTPOLAR;\r
+\r
+/* External Memory Controller- EMC */\r
+\r
+extern volatile unsigned int BCFG0;\r
+extern volatile unsigned int BCFG1;\r
+extern volatile unsigned int BCFG2;\r
+extern volatile unsigned int BCFG3;\r
+\r
+\r
+/* Vector Interrupt Controller (VIC) */\r
+\r
+extern volatile const unsigned int VICIRQStatus;\r
+extern volatile const unsigned int VICFIQStatus;\r
+extern volatile const unsigned int VICRawIntr;\r
+extern volatile unsigned int VICIntSelect;\r
+extern volatile unsigned int VICIntEnable;\r
+extern volatile unsigned int VICIntEnClr;\r
+extern volatile unsigned int VICSoftInt;\r
+extern volatile unsigned int VICSoftIntClear;\r
+extern volatile unsigned int VICProtection;\r
+extern void (* volatile VICVectAddrRead)( void);\r
+extern void (* volatile VICDefVectAddr)( void);\r
+extern void (* volatile VICVectAddr[16])(void);\r
+extern volatile unsigned int VICVectCntl[16];\r
+\r
+ /* The list of interrupts is variant specific so it's */\r
+ /* included here rather than in lpc_sys.h */\r
+\r
+ /* List of interrupt sources. */\r
+#define WDT ((INTERRUPT_SOURCE)0u) /* Watchdog timer. */\r
+#define SW ((INTERRUPT_SOURCE)1u) /* Software interrupt. */\r
+#define DBGCOMMRX ((INTERRUPT_SOURCE)2u) /* Debug comm receive. */\r
+#define DBGCOMMTX ((INTERRUPT_SOURCE)3u) /* Debug comm transmit.*/\r
+#define TIMER0 ((INTERRUPT_SOURCE)4u) /* Timer # 0. */\r
+#define TIMER1 ((INTERRUPT_SOURCE)5u) /* Timer # 1. */\r
+#define UART0 ((INTERRUPT_SOURCE)6u) /* UART # 0. */\r
+#define UART1 ((INTERRUPT_SOURCE)7u) /* UART # 1. */\r
+#define PWM0 ((INTERRUPT_SOURCE)8u) /* PWM. */\r
+#define I2C ((INTERRUPT_SOURCE)9u) /* IIC. */\r
+#define SPI ((INTERRUPT_SOURCE)10u) /* SPI 0. */\r
+#define SPI0 ((INTERRUPT_SOURCE)10u) /* SPI 0. */\r
+#define SPI1 ((INTERRUPT_SOURCE)11u) /* SPI 1. */\r
+#define PLL ((INTERRUPT_SOURCE)12u) /* PLL. */\r
+#define RTC ((INTERRUPT_SOURCE)13u) /* Real time clock. */\r
+#define EINT0 ((INTERRUPT_SOURCE)14u) /* External int # 0. */\r
+#define EINT1 ((INTERRUPT_SOURCE)15u) /* External int # 1. */\r
+#define EINT2 ((INTERRUPT_SOURCE)16u) /* External int # 2. */\r
+#define EINT3 ((INTERRUPT_SOURCE)17u) /* External int # 3. */\r
+#define AD ((INTERRUPT_SOURCE)18u) /* A/D Convertor. */\r
+#define CANACCFILT ((INTERRUPT_SOURCE)19u) /* CAN and Acceptance */\r
+ /* Filter. */\r
+#define CAN1TX ((INTERRUPT_SOURCE)20u) /* CAN 1 Tx. */\r
+#define CAN2TX ((INTERRUPT_SOURCE)21u) /* CAN 2 Tx. */\r
+#define CAN3TX ((INTERRUPT_SOURCE)22u) /* CAN 3 Tx. */\r
+#define CAN4TX ((INTERRUPT_SOURCE)23u) /* CAN 4 Tx. */\r
+#define CAN1RX ((INTERRUPT_SOURCE)26u) /* CAN 1 Rx. */\r
+#define CAN2RX ((INTERRUPT_SOURCE)27u) /* CAN 2 Rx. */\r
+#define CAN3RX ((INTERRUPT_SOURCE)28u) /* CAN 3 Rx. */\r
+#define CAN4RX ((INTERRUPT_SOURCE)29u) /* CAN 4 Rx. */\r
+\r
+#define MAX_INTERRUPT_SOURCE ((INTERRUPT_SOURCE)30u) /* End of the list.*/\r
+\r
+#endif /* LPC2119__H */\r
--- /dev/null
+/***********************************************************************/\r
+/* This file is part of the uVision/ARM development tools */\r
+/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */\r
+/***********************************************************************/\r
+/* */\r
+/* LPC21XX.H: Header file for Philips LPC2114 / LPC2119 */\r
+/* LPC2124 / LPC2129 */\r
+/* LPC2194 */\r
+/* */\r
+/***********************************************************************/\r
+\r
+#ifndef __LPC21xx_H\r
+#define __LPC21xx_H\r
+\r
+/* Vectored Interrupt Controller (VIC) */\r
+#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))\r
+#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))\r
+#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))\r
+#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))\r
+#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))\r
+#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))\r
+#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))\r
+#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C))\r
+#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))\r
+#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))\r
+#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))\r
+#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))\r
+#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))\r
+#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))\r
+#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))\r
+#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))\r
+#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))\r
+#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))\r
+#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))\r
+#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))\r
+#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))\r
+#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))\r
+#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))\r
+#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))\r
+#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))\r
+#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))\r
+#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))\r
+#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))\r
+#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))\r
+#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))\r
+#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))\r
+#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))\r
+#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))\r
+#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))\r
+#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))\r
+#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))\r
+#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))\r
+#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))\r
+#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))\r
+#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))\r
+#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))\r
+#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))\r
+#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))\r
+\r
+/* Pin Connect Block */\r
+#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))\r
+#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))\r
+#define PINSEL2 (*((volatile unsigned long *) 0xE002C014))\r
+\r
+/* General Purpose Input/Output (GPIO) */\r
+#define IOPIN0 (*((volatile unsigned long *) 0xE0028000))\r
+#define IOSET0 (*((volatile unsigned long *) 0xE0028004))\r
+#define IODIR0 (*((volatile unsigned long *) 0xE0028008))\r
+#define IOCLR0 (*((volatile unsigned long *) 0xE002800C))\r
+#define IOPIN1 (*((volatile unsigned long *) 0xE0028010))\r
+#define IOSET1 (*((volatile unsigned long *) 0xE0028014))\r
+#define IODIR1 (*((volatile unsigned long *) 0xE0028018))\r
+#define IOCLR1 (*((volatile unsigned long *) 0xE002801C))\r
+\r
+/* Memory Accelerator Module (MAM) */\r
+#define MAMCR (*((volatile unsigned char *) 0xE01FC000))\r
+#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))\r
+#define MEMMAP (*((volatile unsigned char *) 0xE01FC040))\r
+\r
+/* Phase Locked Loop (PLL) */\r
+#define PLLCON (*((volatile unsigned char *) 0xE01FC080))\r
+#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))\r
+#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))\r
+#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))\r
+\r
+/* VPB Divider */\r
+#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))\r
+\r
+/* Power Control */\r
+#define PCON (*((volatile unsigned char *) 0xE01FC0C0))\r
+#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))\r
+\r
+/* External Interrupts */\r
+#define EXTINT (*((volatile unsigned char *) 0xE01FC140))\r
+#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))\r
+#define EXTMODE (*((volatile unsigned char *) 0xE01FC148))\r
+#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C))\r
+\r
+/* Timer 0 */\r
+#define T0IR (*((volatile unsigned long *) 0xE0004000))\r
+#define T0TCR (*((volatile unsigned long *) 0xE0004004))\r
+#define T0TC (*((volatile unsigned long *) 0xE0004008))\r
+#define T0PR (*((volatile unsigned long *) 0xE000400C))\r
+#define T0PC (*((volatile unsigned long *) 0xE0004010))\r
+#define T0MCR (*((volatile unsigned long *) 0xE0004014))\r
+#define T0MR0 (*((volatile unsigned long *) 0xE0004018))\r
+#define T0MR1 (*((volatile unsigned long *) 0xE000401C))\r
+#define T0MR2 (*((volatile unsigned long *) 0xE0004020))\r
+#define T0MR3 (*((volatile unsigned long *) 0xE0004024))\r
+#define T0CCR (*((volatile unsigned long *) 0xE0004028))\r
+#define T0CR0 (*((volatile unsigned long *) 0xE000402C))\r
+#define T0CR1 (*((volatile unsigned long *) 0xE0004030))\r
+#define T0CR2 (*((volatile unsigned long *) 0xE0004034))\r
+#define T0CR3 (*((volatile unsigned long *) 0xE0004038))\r
+#define T0EMR (*((volatile unsigned long *) 0xE000403C))\r
+\r
+/* Timer 1 */\r
+#define T1IR (*((volatile unsigned long *) 0xE0008000))\r
+#define T1TCR (*((volatile unsigned long *) 0xE0008004))\r
+#define T1TC (*((volatile unsigned long *) 0xE0008008))\r
+#define T1PR (*((volatile unsigned long *) 0xE000800C))\r
+#define T1PC (*((volatile unsigned long *) 0xE0008010))\r
+#define T1MCR (*((volatile unsigned long *) 0xE0008014))\r
+#define T1MR0 (*((volatile unsigned long *) 0xE0008018))\r
+#define T1MR1 (*((volatile unsigned long *) 0xE000801C))\r
+#define T1MR2 (*((volatile unsigned long *) 0xE0008020))\r
+#define T1MR3 (*((volatile unsigned long *) 0xE0008024))\r
+#define T1CCR (*((volatile unsigned long *) 0xE0008028))\r
+#define T1CR0 (*((volatile unsigned long *) 0xE000802C))\r
+#define T1CR1 (*((volatile unsigned long *) 0xE0008030))\r
+#define T1CR2 (*((volatile unsigned long *) 0xE0008034))\r
+#define T1CR3 (*((volatile unsigned long *) 0xE0008038))\r
+#define T1EMR (*((volatile unsigned long *) 0xE000803C))\r
+\r
+/* Pulse Width Modulator (PWM) */\r
+#define PWMIR (*((volatile unsigned long *) 0xE0014000))\r
+#define PWMTCR (*((volatile unsigned long *) 0xE0014004))\r
+#define PWMTC (*((volatile unsigned long *) 0xE0014008))\r
+#define PWMPR (*((volatile unsigned long *) 0xE001400C))\r
+#define PWMPC (*((volatile unsigned long *) 0xE0014010))\r
+#define PWMMCR (*((volatile unsigned long *) 0xE0014014))\r
+#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))\r
+#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))\r
+#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))\r
+#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))\r
+#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))\r
+#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))\r
+#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))\r
+#define PWMCCR (*((volatile unsigned long *) 0xE0014028))\r
+#define PWMCR0 (*((volatile unsigned long *) 0xE001402C))\r
+#define PWMCR1 (*((volatile unsigned long *) 0xE0014030))\r
+#define PWMCR2 (*((volatile unsigned long *) 0xE0014034))\r
+#define PWMCR3 (*((volatile unsigned long *) 0xE0014038))\r
+#define PWMEMR (*((volatile unsigned long *) 0xE001403C))\r
+#define PWMPCR (*((volatile unsigned long *) 0xE001404C))\r
+#define PWMLER (*((volatile unsigned long *) 0xE0014050))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define U0RBR (*((volatile unsigned char *) 0xE000C000))\r
+#define U0THR (*((volatile unsigned char *) 0xE000C000))\r
+#define U0IER (*((volatile unsigned char *) 0xE000C004))\r
+#define U0IIR (*((volatile unsigned char *) 0xE000C008))\r
+#define U0FCR (*((volatile unsigned char *) 0xE000C008))\r
+#define U0LCR (*((volatile unsigned char *) 0xE000C00C))\r
+#define U0MCR (*((volatile unsigned char *) 0xE000C010))\r
+#define U0LSR (*((volatile unsigned char *) 0xE000C014))\r
+#define U0MSR (*((volatile unsigned char *) 0xE000C018))\r
+#define U0SCR (*((volatile unsigned char *) 0xE000C01C))\r
+#define U0DLL (*((volatile unsigned char *) 0xE000C000))\r
+#define U0DLM (*((volatile unsigned char *) 0xE000C004))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define U1RBR (*((volatile unsigned char *) 0xE0010000))\r
+#define U1THR (*((volatile unsigned char *) 0xE0010000))\r
+#define U1IER (*((volatile unsigned char *) 0xE0010004))\r
+#define U1IIR (*((volatile unsigned char *) 0xE0010008))\r
+#define U1FCR (*((volatile unsigned char *) 0xE0010008))\r
+#define U1LCR (*((volatile unsigned char *) 0xE001000C))\r
+#define U1MCR (*((volatile unsigned char *) 0xE0010010))\r
+#define U1LSR (*((volatile unsigned char *) 0xE0010014))\r
+#define U1MSR (*((volatile unsigned char *) 0xE0010018))\r
+#define U1SCR (*((volatile unsigned char *) 0xE001001C))\r
+#define U1DLL (*((volatile unsigned char *) 0xE0010000))\r
+#define U1DLM (*((volatile unsigned char *) 0xE0010004))\r
+\r
+/* I2C Interface */\r
+#define I2CONSET (*((volatile unsigned char *) 0xE001C000))\r
+#define I2STAT (*((volatile unsigned char *) 0xE001C004))\r
+#define I2DAT (*((volatile unsigned char *) 0xE001C008))\r
+#define I2ADR (*((volatile unsigned char *) 0xE001C00C))\r
+#define I2SCLH (*((volatile unsigned short*) 0xE001C010))\r
+#define I2SCLL (*((volatile unsigned short*) 0xE001C014))\r
+#define I2CONCLR (*((volatile unsigned char *) 0xE001C018))\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define S0SPCR (*((volatile unsigned char *) 0xE0020000))\r
+#define S0SPSR (*((volatile unsigned char *) 0xE0020004))\r
+#define S0SPDR (*((volatile unsigned char *) 0xE0020008))\r
+#define S0SPCCR (*((volatile unsigned char *) 0xE002000C))\r
+#define S0SPTCR (*((volatile unsigned char *) 0xE0020010))\r
+#define S0SPTSR (*((volatile unsigned char *) 0xE0020014))\r
+#define S0SPTOR (*((volatile unsigned char *) 0xE0020018))\r
+#define S0SPINT (*((volatile unsigned char *) 0xE002001C))\r
+\r
+/* SPI1 (Serial Peripheral Interface 1) */\r
+#define S1SPCR (*((volatile unsigned char *) 0xE0030000))\r
+#define S1SPSR (*((volatile unsigned char *) 0xE0030004))\r
+#define S1SPDR (*((volatile unsigned char *) 0xE0030008))\r
+#define S1SPCCR (*((volatile unsigned char *) 0xE003000C))\r
+#define S1SPTCR (*((volatile unsigned char *) 0xE0030010))\r
+#define S1SPTSR (*((volatile unsigned char *) 0xE0030014))\r
+#define S1SPTOR (*((volatile unsigned char *) 0xE0030018))\r
+#define S1SPINT (*((volatile unsigned char *) 0xE003001C))\r
+\r
+/* Real Time Clock */\r
+#define ILR (*((volatile unsigned char *) 0xE0024000))\r
+#define CTC (*((volatile unsigned short*) 0xE0024004))\r
+#define CCR (*((volatile unsigned char *) 0xE0024008))\r
+#define CIIR (*((volatile unsigned char *) 0xE002400C))\r
+#define AMR (*((volatile unsigned char *) 0xE0024010))\r
+#define CTIME0 (*((volatile unsigned long *) 0xE0024014))\r
+#define CTIME1 (*((volatile unsigned long *) 0xE0024018))\r
+#define CTIME2 (*((volatile unsigned long *) 0xE002401C))\r
+#define SEC (*((volatile unsigned char *) 0xE0024020))\r
+#define MIN (*((volatile unsigned char *) 0xE0024024))\r
+#define HOUR (*((volatile unsigned char *) 0xE0024028))\r
+#define DOM (*((volatile unsigned char *) 0xE002402C))\r
+#define DOW (*((volatile unsigned char *) 0xE0024030))\r
+#define DOY (*((volatile unsigned short*) 0xE0024034))\r
+#define MONTH (*((volatile unsigned char *) 0xE0024038))\r
+#define YEAR (*((volatile unsigned short*) 0xE002403C))\r
+#define ALSEC (*((volatile unsigned char *) 0xE0024060))\r
+#define ALMIN (*((volatile unsigned char *) 0xE0024064))\r
+#define ALHOUR (*((volatile unsigned char *) 0xE0024068))\r
+#define ALDOM (*((volatile unsigned char *) 0xE002406C))\r
+#define ALDOW (*((volatile unsigned char *) 0xE0024070))\r
+#define ALDOY (*((volatile unsigned short*) 0xE0024074))\r
+#define ALMON (*((volatile unsigned char *) 0xE0024078))\r
+#define ALYEAR (*((volatile unsigned short*) 0xE002407C))\r
+#define PREINT (*((volatile unsigned short*) 0xE0024080))\r
+#define PREFRAC (*((volatile unsigned short*) 0xE0024084))\r
+\r
+/* A/D Converter */\r
+#define ADCR (*((volatile unsigned long *) 0xE0034000))\r
+#define ADDR (*((volatile unsigned long *) 0xE0034004))\r
+\r
+/* CAN Acceptance Filter RAM */\r
+#define AFRAM (*((volatile unsigned long *) 0xE0038000))\r
+\r
+/* CAN Acceptance Filter */\r
+#define AFMR (*((volatile unsigned long *) 0xE003C000))\r
+#define SFF_sa (*((volatile unsigned long *) 0xE003C004))\r
+#define SFF_GRP_sa (*((volatile unsigned long *) 0xE003C008))\r
+#define EFF_sa (*((volatile unsigned long *) 0xE003C00C))\r
+#define EFF_GRP_sa (*((volatile unsigned long *) 0xE003C010))\r
+#define ENDofTable (*((volatile unsigned long *) 0xE003C014))\r
+#define LUTerrAd (*((volatile unsigned long *) 0xE003C018))\r
+#define LUTerr (*((volatile unsigned long *) 0xE003C01C))\r
+\r
+/* CAN Central Registers */\r
+#define CANTxSR (*((volatile unsigned long *) 0xE0040000))\r
+#define CANRxSR (*((volatile unsigned long *) 0xE0040004))\r
+#define CANMSR (*((volatile unsigned long *) 0xE0040008))\r
+\r
+/* CAN Controller 1 (CAN1) */\r
+#define C1MOD (*((volatile unsigned long *) 0xE0044000))\r
+#define C1CMR (*((volatile unsigned long *) 0xE0044004))\r
+#define C1GSR (*((volatile unsigned long *) 0xE0044008))\r
+#define C1ICR (*((volatile unsigned long *) 0xE004400C))\r
+#define C1IER (*((volatile unsigned long *) 0xE0044010))\r
+#define C1BTR (*((volatile unsigned long *) 0xE0044014))\r
+#define C1EWL (*((volatile unsigned long *) 0xE0044018))\r
+#define C1SR (*((volatile unsigned long *) 0xE004401C))\r
+#define C1RFS (*((volatile unsigned long *) 0xE0044020))\r
+#define C1RID (*((volatile unsigned long *) 0xE0044024))\r
+#define C1RDA (*((volatile unsigned long *) 0xE0044028))\r
+#define C1RDB (*((volatile unsigned long *) 0xE004402C))\r
+#define C1TFI1 (*((volatile unsigned long *) 0xE0044030))\r
+#define C1TID1 (*((volatile unsigned long *) 0xE0044034))\r
+#define C1TDA1 (*((volatile unsigned long *) 0xE0044038))\r
+#define C1TDB1 (*((volatile unsigned long *) 0xE004403C))\r
+#define C1TFI2 (*((volatile unsigned long *) 0xE0044040))\r
+#define C1TID2 (*((volatile unsigned long *) 0xE0044044))\r
+#define C1TDA2 (*((volatile unsigned long *) 0xE0044048))\r
+#define C1TDB2 (*((volatile unsigned long *) 0xE004404C))\r
+#define C1TFI3 (*((volatile unsigned long *) 0xE0044050))\r
+#define C1TID3 (*((volatile unsigned long *) 0xE0044054))\r
+#define C1TDA3 (*((volatile unsigned long *) 0xE0044058))\r
+#define C1TDB3 (*((volatile unsigned long *) 0xE004405C))\r
+\r
+/* CAN Controller 2 (CAN2) */\r
+#define C2MOD (*((volatile unsigned long *) 0xE0048000))\r
+#define C2CMR (*((volatile unsigned long *) 0xE0048004))\r
+#define C2GSR (*((volatile unsigned long *) 0xE0048008))\r
+#define C2ICR (*((volatile unsigned long *) 0xE004800C))\r
+#define C2IER (*((volatile unsigned long *) 0xE0048010))\r
+#define C2BTR (*((volatile unsigned long *) 0xE0048014))\r
+#define C2EWL (*((volatile unsigned long *) 0xE0048018))\r
+#define C2SR (*((volatile unsigned long *) 0xE004801C))\r
+#define C2RFS (*((volatile unsigned long *) 0xE0048020))\r
+#define C2RID (*((volatile unsigned long *) 0xE0048024))\r
+#define C2RDA (*((volatile unsigned long *) 0xE0048028))\r
+#define C2RDB (*((volatile unsigned long *) 0xE004802C))\r
+#define C2TFI1 (*((volatile unsigned long *) 0xE0048030))\r
+#define C2TID1 (*((volatile unsigned long *) 0xE0048034))\r
+#define C2TDA1 (*((volatile unsigned long *) 0xE0048038))\r
+#define C2TDB1 (*((volatile unsigned long *) 0xE004803C))\r
+#define C2TFI2 (*((volatile unsigned long *) 0xE0048040))\r
+#define C2TID2 (*((volatile unsigned long *) 0xE0048044))\r
+#define C2TDA2 (*((volatile unsigned long *) 0xE0048048))\r
+#define C2TDB2 (*((volatile unsigned long *) 0xE004804C))\r
+#define C2TFI3 (*((volatile unsigned long *) 0xE0048050))\r
+#define C2TID3 (*((volatile unsigned long *) 0xE0048054))\r
+#define C2TDA3 (*((volatile unsigned long *) 0xE0048058))\r
+#define C2TDB3 (*((volatile unsigned long *) 0xE004805C))\r
+\r
+/* CAN Controller 3 (CAN3) */\r
+#define C3MOD (*((volatile unsigned long *) 0xE004C000))\r
+#define C3CMR (*((volatile unsigned long *) 0xE004C004))\r
+#define C3GSR (*((volatile unsigned long *) 0xE004C008))\r
+#define C3ICR (*((volatile unsigned long *) 0xE004C00C))\r
+#define C3IER (*((volatile unsigned long *) 0xE004C010))\r
+#define C3BTR (*((volatile unsigned long *) 0xE004C014))\r
+#define C3EWL (*((volatile unsigned long *) 0xE004C018))\r
+#define C3SR (*((volatile unsigned long *) 0xE004C01C))\r
+#define C3RFS (*((volatile unsigned long *) 0xE004C020))\r
+#define C3RID (*((volatile unsigned long *) 0xE004C024))\r
+#define C3RDA (*((volatile unsigned long *) 0xE004C028))\r
+#define C3RDB (*((volatile unsigned long *) 0xE004C02C))\r
+#define C3TFI1 (*((volatile unsigned long *) 0xE004C030))\r
+#define C3TID1 (*((volatile unsigned long *) 0xE004C034))\r
+#define C3TDA1 (*((volatile unsigned long *) 0xE004C038))\r
+#define C3TDB1 (*((volatile unsigned long *) 0xE004C03C))\r
+#define C3TFI2 (*((volatile unsigned long *) 0xE004C040))\r
+#define C3TID2 (*((volatile unsigned long *) 0xE004C044))\r
+#define C3TDA2 (*((volatile unsigned long *) 0xE004C048))\r
+#define C3TDB2 (*((volatile unsigned long *) 0xE004C04C))\r
+#define C3TFI3 (*((volatile unsigned long *) 0xE004C050))\r
+#define C3TID3 (*((volatile unsigned long *) 0xE004C054))\r
+#define C3TDA3 (*((volatile unsigned long *) 0xE004C058))\r
+#define C3TDB3 (*((volatile unsigned long *) 0xE004C05C))\r
+\r
+/* CAN Controller 4 (CAN4) */\r
+#define C4MOD (*((volatile unsigned long *) 0xE0050000))\r
+#define C4CMR (*((volatile unsigned long *) 0xE0050004))\r
+#define C4GSR (*((volatile unsigned long *) 0xE0050008))\r
+#define C4ICR (*((volatile unsigned long *) 0xE005000C))\r
+#define C4IER (*((volatile unsigned long *) 0xE0050010))\r
+#define C4BTR (*((volatile unsigned long *) 0xE0050014))\r
+#define C4EWL (*((volatile unsigned long *) 0xE0050018))\r
+#define C4SR (*((volatile unsigned long *) 0xE005001C))\r
+#define C4RFS (*((volatile unsigned long *) 0xE0050020))\r
+#define C4RID (*((volatile unsigned long *) 0xE0050024))\r
+#define C4RDA (*((volatile unsigned long *) 0xE0050028))\r
+#define C4RDB (*((volatile unsigned long *) 0xE005002C))\r
+#define C4TFI1 (*((volatile unsigned long *) 0xE0050030))\r
+#define C4TID1 (*((volatile unsigned long *) 0xE0050034))\r
+#define C4TDA1 (*((volatile unsigned long *) 0xE0050038))\r
+#define C4TDB1 (*((volatile unsigned long *) 0xE005003C))\r
+#define C4TFI2 (*((volatile unsigned long *) 0xE0050040))\r
+#define C4TID2 (*((volatile unsigned long *) 0xE0050044))\r
+#define C4TDA2 (*((volatile unsigned long *) 0xE0050048))\r
+#define C4TDB2 (*((volatile unsigned long *) 0xE005004C))\r
+#define C4TFI3 (*((volatile unsigned long *) 0xE0050050))\r
+#define C4TID3 (*((volatile unsigned long *) 0xE0050054))\r
+#define C4TDA3 (*((volatile unsigned long *) 0xE0050058))\r
+#define C4TDB3 (*((volatile unsigned long *) 0xE005005C))\r
+\r
+/* Watchdog */\r
+#define WDMOD (*((volatile unsigned char *) 0xE0000000))\r
+#define WDTC (*((volatile unsigned long *) 0xE0000004))\r
+#define WDFEED (*((volatile unsigned char *) 0xE0000008))\r
+#define WDTV (*((volatile unsigned long *) 0xE000000C))\r
+\r
+#endif // __LPC21xx_H\r
--- /dev/null
+/**************************** lpc_ioctl.h *******************************/\r
+/* Copyright 2003/12/29 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* I/O control. Routines, enums and structures to support device */\r
+/* control. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 lpc_ioctl.h 30-Dec-2003,10:34:14,`RADSETT' First archival version.\r
+* TLIB revision history ends.\r
+*/\r
+#ifndef LPC_IOCTL__H\r
+#define LPC_IOCTL__H\r
+\r
+ /**** Request defintions. These define the requested actions.****/\r
+#define UART_SETUP (0x2100uL)\r
+\r
+\r
+ /**** UART Defintions. ****/\r
+\r
+ \r
+#define UART_STOP_BITS_2 (4u) /* Sets to provide 2 stop bits */\r
+#define UART_STOP_BITS_1 (0u) /* Sets to provide 1 stop bit */\r
+\r
+ \r
+#define UART_PARITY_NONE (0u) /* Set to parity None */\r
+#define UART_PARITY_ODD (8u) /* Set to parity Odd */\r
+#define UART_PARITY_EVEN (0x18u) /* Set to parity Even */\r
+#define UART_PARITY_STICK1 (0x28u) /* Set to parity stuck on */\r
+#define UART_PARITY_STICK0 (0x38u) /* Set to parity stuck off */\r
+\r
+#define UART_WORD_LEN_5 (0u) /* 5 bit serial byte. */\r
+#define UART_WORD_LEN_6 (1u) /* 6 bit serial byte. */\r
+#define UART_WORD_LEN_7 (2u) /* 7 bit serial byte. */\r
+#define UART_WORD_LEN_8 (3u) /* 8 bit serial byte. */\r
+\r
+ /* serial_param -- structure to pass with ioctl request */\r
+ /* UART_SETUP to control the serial line characteristics. */\r
+struct serial_param {\r
+ unsigned long baud;\r
+ unsigned int length;\r
+ unsigned int parity;\r
+ unsigned int stop;\r
+ };\r
+\r
+\r
+\r
+/************************** _ioctl_r ************************************/\r
+/* Support function. Device specific control. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* int fd -- number referring to the open file. Generally */\r
+/* obtained from a corresponding call to open. */\r
+/* unsigned long request -- Number to indicate the request being made */\r
+/* of the driver. */\r
+/* void *ptr -- pointer to data that is either used by or */\r
+/* set by the driver. Varies by request. */\r
+/* Returns 0 if successful, otherwise errno will be set to indicate */\r
+/* the source of the error. */\r
+int _ioctl_r( struct _reent *r, int fd, unsigned long request, void *ptr);\r
+\r
+/************************** ioctl ***************************************/\r
+/* Support function. Device specific control. A shell to convert */\r
+/* requests into a re-entrant form. */\r
+/* int fd -- number referring to the open file. Generally */\r
+/* obtained from a corresponding call to open. */\r
+/* unsigned long request -- Number to indicate the request being made */\r
+/* of the driver. */\r
+/* void *ptr -- pointer to data that is either used by or */\r
+/* set by the driver. Varies by request. */\r
+/* Returns 0 if successful, otherwise errno will be set to indicate */\r
+/* the source of the error. */\r
+int ioctl( int fd, unsigned long request, void *ptr);\r
+\r
+#endif /* LPC_IOCTL__H */\r
+\r
--- /dev/null
+/**************************** lpc_sys.h *********************************/\r
+/* Copyright 2003/12/29 Aeolus Development */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* 1. Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* 2. Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the*/\r
+/* documentation and/or other materials provided with the */\r
+/* distribution. */\r
+/* 3. The name of the Aeolus Development or its contributors may not be */\r
+/* used to endorse or promote products derived from this software */\r
+/* without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* */\r
+/* System control. Basic support that doesn't really fit as part of a */\r
+/* device driver. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 lpc_sys.h 30-Dec-2003,10:34:12,`RADSETT' First archival version.\r
+* 2 lpc_sys.h 17-Jan-2004,16:04:06,`RADSETT' Correct title line.\r
+* 3 lpc_sys.h 29-Jan-2004,11:28:14,`RADSETT' Update Prototypes.\r
+* Add MinimumAchievableWait prototype.\r
+* Spelling corrections\r
+* TLIB revision history ends.\r
+*/\r
+/*lint -library*/\r
+#ifndef LPC_SYS__H\r
+#define LPC_SYS__H\r
+\r
+#include <reent.h>\r
+\r
+ /**** Structures & enums. ****/\r
+\r
+typedef enum { /* Enumerates the possible VPB clock dividers */\r
+ VPB_DIV1, /* VPB clock = CPU clock */\r
+ VPB_DIV2, /* VPB clock = CPU clock / 2 */\r
+ VPB_DIV4 /* VPB clock = CPU clock / 4 */\r
+ } VPB_param;\r
+\r
+typedef enum { /* Enumerates MAM modes. */\r
+ MAM_disabled, /* MAM disabled. */\r
+ MAM_part_enable, /* MAM partially enabled. */\r
+ MAM_full_enable /* MAM fully enabled. */\r
+ } MAM_CONTROL;\r
+\r
+/********************* ActualSpeed **************************************/\r
+/* ActualSpeed -- Returns the operating speed of the CPU. Relies on */\r
+/* earlier call to set native oscillator speed correctly. */\r
+unsigned long ActualSpeed( void);\r
+\r
+/********************* GetUs ********************************************/\r
+/* GetUs -- Get the current time in uS. */\r
+unsigned long long GetUs( void);\r
+\r
+/********************* MinimumAchievableWait ****************************/\r
+/* MinimumAchievableWait -- Get the shotest wait we can do. */\r
+unsigned int MinimumAchievableWait(void);\r
+\r
+/********************* SetDesiredSpeed **********************************/\r
+/* SetDesiredSpeed -- Set the cpu to desired frequency. Relies on */\r
+/* earlier call to set native oscillator speed correctly. Returns 0 */\r
+/* if successful. desired_speed is set to actual speed obtained on */\r
+/* return. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned long desired_speed -- CPU operating frequency in kHz. */\r
+/* Returns 0 if successful. errno will be set on error. */\r
+int SetDesiredSpeed( struct _reent *r, unsigned long desired_speed);\r
+\r
+/********************* SetMAM *******************************************/\r
+/* SetMAM -- Set up the MAM. Minimal error checking, not much more */\r
+/* than a wrapper around the register. Returns 0 if successful, */\r
+/* something else. Sets errno in case of an error. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned int cycle_time -- number of cycles to access the flash. */\r
+/* MAM_CONTROL ctrl -- Mode to place MAM in. One of: */\r
+/* MAM_disabled, MAM_part_enable, or */\r
+/* MAM_full_enable. */\r
+/* Returns 0 if successful. Additional error/sanity checks are possible*/\r
+int SetMAM( struct _reent *r, unsigned int cycle_time, MAM_CONTROL ctrl);\r
+\r
+/********************* SetNativeSpeed ***********************************/\r
+/* SetNativeSpeed -- Set the oscillator frequency for the external */\r
+/* oscillator. This is used to inform the routines that deal with cpu */\r
+/* frequencies what the starting point is. Any error here will be */\r
+/* multiplied later. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* unsigned long speed -- external oscillator/crystal frequency in kHz.*/\r
+/* Note: There is no way to determine or verify this value so we have */\r
+/* to trust the caller to get it right. */\r
+/* Returns 0 if successful. */\r
+int SetNativeSpeed( struct _reent *r, unsigned long speed);\r
+\r
+/********************* StartClock ***************************************/\r
+/* StartClock -- Starts up the clock used for internal timing. */\r
+/* Attempts to match the desired clock speed (CLOCK_SPEED) and */\r
+/* initializes timing_scale_factor to a compensating scale. Returns 0 */\r
+/* if successful, otherwise error code will be retained in errno. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* Note: Should be called only after all clocks have been set up. */\r
+/* Otherwise time scale will not be correct. */\r
+/* Returns 0 if successful. */\r
+int StartClock( struct _reent *r);\r
+\r
+/********************* VPBControl ***************************************/\r
+/* VPBControl -- Control the clock divider on the peripheral bus. */\r
+/* Returns the actual divider in ptr (requested is also passed in ptr. */\r
+/* struct _reent *r -- re-entrancy structure, used by newlib to */\r
+/* support multiple threads of operation. */\r
+/* VPB_parm p -- requested VPB to CPU freq rate. */\r
+/* Returns 0 if successful. */\r
+int VPBControl( struct _reent *r, VPB_param p);\r
+\r
+/********************* VPBRate ******************************************/\r
+/* VPBRate -- Finds and returns the rate of the clock on the */\r
+/* peripheral bus (in Hz). */\r
+unsigned long VPBRate( void);\r
+\r
+/********************* UsToCounts ***************************************/\r
+/* UsToCounts -- converts to internal units in counts from uS. Other */\r
+/* Modules use this counter for a timebase so this needs to be */\r
+/* available to them. */\r
+/* unsigned int us -- microseconds to convert to counts. */\r
+/* Returns number of counts corresponding to us. Saturates on */\r
+/* overflow so for large time periods it is possible to get a result */\r
+/* lower than requested. */\r
+unsigned int UsToCounts( unsigned int us);\r
+\r
+/********************* WaitUs *******************************************/\r
+/* WaitUs -- Wait for 'wait_time' us */\r
+/* unsigned int wait_time -- microseconds to convert to counts. */\r
+/* Will break wait into multiple waits if needed to avoid saturation. */\r
+void WaitUs( unsigned int wait_time);\r
+\r
+#endif /* LPC_SYS__H */\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = boot can uart_zen uart-nozen ldscripts
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_obj_SOURCES = crt0.S crt0flash.S initarray.c
+lib_obj_SOURCES += startup.S # for canld - FIXME: replace by the crt0flash above
+
+
--- /dev/null
+ .global main // int main(void)\r
+\r
+ .global _etext // -> .data initial values in ROM\r
+ .global _data // -> .data area in RAM\r
+ .global _edata // end of .data area\r
+ .global __bss_start // -> .bss area in RAM\r
+ .global __bss_end__ // end of .bss area\r
+ .global _stack // top of stack\r
+\r
+// Stack Sizes\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000080\r
+ .set SVC_STACK_SIZE, 0x00000004\r
+\r
+// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs\r
+ .set MODE_USR, 0x10 // User Mode\r
+ .set MODE_FIQ, 0x11 // FIQ Mode\r
+ .set MODE_IRQ, 0x12 // IRQ Mode\r
+ .set MODE_SVC, 0x13 // Supervisor Mode\r
+ .set MODE_ABT, 0x17 // Abort Mode\r
+ .set MODE_UND, 0x1B // Undefined Mode\r
+ .set MODE_SYS, 0x1F // System Mode\r
+\r
+ .equ I_BIT, 0x80 // when I bit is set, IRQ is disabled\r
+ .equ F_BIT, 0x40 // when F bit is set, FIQ is disabled\r
+\r
+ .section .ivec, "xa"\r
+// .text\r
+ .code 32\r
+ .align 2\r
+\r
+ .global _boot\r
+ .func _boot\r
+_boot:\r
+\r
+// Runtime Interrupt Vectors\r
+// -------------------------\r
+Vectors:\r
+ b _start // reset - _start\r
+ ldr pc,_undf // undefined - _undf\r
+ ldr pc,_swi // SWI - _swi\r
+ ldr pc,_pabt // program abort - _pabt\r
+ ldr pc,_dabt // data abort - _dabt\r
+ nop // reserved\r
+ ldr pc,[pc,#-0xFF0] // IRQ - read the VIC\r
+ ldr pc,_fiq // FIQ - _fiq\r
+\r
+// Use this group for development\r
+_undf: .word __undf // undefined\r
+_swi: .word __swi // SWI\r
+_pabt: .word __pabt // program abort\r
+_dabt: .word __dabt // data abort\r
+_irq: .word __irq // IRQ\r
+_fiq: .word __fiq // FIQ\r
+\r
+__undf: b . // undefined\r
+__swi: b . // SWI\r
+__pabt: b . // program abort\r
+__dabt: b . // data abort\r
+__irq: b . // IRQ\r
+__fiq: b . // FIQ\r
+ .size _boot, . - _boot\r
+ .endfunc\r
+\r
+ .text\r
+// Setup the operating mode & stack.\r
+// ---------------------------------\r
+ .global _start, start, _mainCRTStartup\r
+ .func _start\r
+\r
+_start:\r
+start:\r
+_mainCRTStartup:\r
+\r
+// Initialize Interrupt System\r
+// - Set stack location for each mode\r
+// - Leave in System Mode with Interrupts Disabled\r
+// -----------------------------------------------\r
+ ldr r0,=_stack\r
+ msr CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode\r
+ mov sp,r0\r
+ sub r0,r0,#UND_STACK_SIZE\r
+ msr CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode\r
+ mov sp,r0\r
+ sub r0,r0,#ABT_STACK_SIZE\r
+ msr CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode\r
+ mov sp,r0\r
+ sub r0,r0,#FIQ_STACK_SIZE\r
+ msr CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode\r
+ mov sp,r0\r
+ sub r0,r0,#IRQ_STACK_SIZE\r
+ msr CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode\r
+ mov sp,r0\r
+ sub r0,r0,#SVC_STACK_SIZE\r
+ msr CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode\r
+ mov sp,r0\r
+\r
+// Enable interrupts\r
+ msr CPSR_c,#MODE_SVC // Supervisor Mode -- recommended by our\r
+ // guru Pavel Pisa\r
+\r
+// Copy initialized data to its execution address in RAM\r
+// -----------------------------------------------------\r
+#ifdef ROM_RUN\r
+ ldr r1,=_etext // -> ROM data start\r
+ ldr r2,=_data // -> data start\r
+ ldr r3,=_edata // -> end of data\r
+1: cmp r2,r3 // check if data to move\r
+ ldrlo r0,[r1],#4 // copy it\r
+ strlo r0,[r2],#4\r
+ blo 1b // loop until done\r
+#endif\r
+// Clear .bss\r
+// ----------\r
+ mov r0,#0 // get a zero\r
+ ldr r1,=__bss_start // -> bss start\r
+ ldr r2,=__bss_end__ // -> bss end\r
+2: cmp r1,r2 // check if data to clear\r
+ strlo r0,[r1],#4 // clear 4 bytes\r
+ blo 2b // loop until done\r
+\r
+// Call init functions in .init_array section (only if __libc_init_array exists)\r
+ .weak __libc_init_array\r
+ ldr r3,=__libc_init_array\r
+ cmp r3, #0\r
+ movne lr, pc\r
+ movne pc, r3\r
+\r
+// Call main program: main(0)\r
+// --------------------------\r
+ mov r0,#0 // no arguments (argc = 0)\r
+ mov r1,r0\r
+ mov r2,r0\r
+ mov fp,r0 // null frame pointer\r
+ mov r7,r0 // null frame pointer for thumb\r
+ ldr r10,=main\r
+ mov lr,pc\r
+ bx r10 // enter main()\r
+\r
+ .size _start, . - _start\r
+ .endfunc\r
+\r
+ .global _reset, reset, exit, abort\r
+ .func _reset\r
+_reset:\r
+reset:\r
+exit:\r
+abort:\r
+ b . // loop until reset\r
+\r
+ .size _reset, . - _reset\r
+ .endfunc\r
+\r
+ .end\r
--- /dev/null
+ .global main // int main(void)\r
+\r
+ .global _etext // -> .data initial values in ROM\r
+ .global _data // -> .data area in RAM\r
+ .global _edata // end of .data area\r
+ .global __bss_start // -> .bss area in RAM\r
+ .global __bss_end__ // end of .bss area\r
+ .global _stack // top of stack\r
+\r
+// Stack Sizes\r
+ .set UND_STACK_SIZE, 0x00000004\r
+ .set ABT_STACK_SIZE, 0x00000004\r
+ .set FIQ_STACK_SIZE, 0x00000004\r
+ .set IRQ_STACK_SIZE, 0X00000080\r
+ .set SVC_STACK_SIZE, 0x00000004\r
+\r
+// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs\r
+ .set MODE_USR, 0x10 // User Mode\r
+ .set MODE_FIQ, 0x11 // FIQ Mode\r
+ .set MODE_IRQ, 0x12 // IRQ Mode\r
+ .set MODE_SVC, 0x13 // Supervisor Mode\r
+ .set MODE_ABT, 0x17 // Abort Mode\r
+ .set MODE_UND, 0x1B // Undefined Mode\r
+ .set MODE_SYS, 0x1F // System Mode\r
+\r
+ .equ I_BIT, 0x80 // when I bit is set, IRQ is disabled\r
+ .equ F_BIT, 0x40 // when F bit is set, FIQ is disabled\r
+\r
+ .section .ivec, "xa"\r
+// .text\r
+ .code 32\r
+ .align 2\r
+\r
+ .global _boot\r
+ .func _boot\r
+_boot:\r
+\r
+// Runtime Interrupt Vectors\r
+// -------------------------\r
+Vectors:\r
+ b _start // reset - _start\r
+ ldr pc,_undf // undefined - _undf\r
+ ldr pc,_swi // SWI - _swi\r
+ ldr pc,_pabt // program abort - _pabt\r
+ ldr pc,_dabt // data abort - _dabt\r
+ nop // reserved\r
+ ldr pc,[pc,#-0xFF0] // IRQ - read the VIC\r
+ ldr pc,_fiq // FIQ - _fiq\r
+\r
+// Use this group for development\r
+_undf: .word __undf // undefined\r
+_swi: .word __swi // SWI\r
+_pabt: .word __pabt // program abort\r
+_dabt: .word __dabt // data abort\r
+_irq: .word __irq // IRQ\r
+_fiq: .word __fiq // FIQ\r
+\r
+__undf: b . // undefined\r
+__swi: b . // SWI\r
+__pabt: b . // program abort\r
+__dabt: b . // data abort\r
+__irq: b . // IRQ\r
+__fiq: b . // FIQ\r
+ .size _boot, . - _boot\r
+ .endfunc\r
+\r
+ .text\r
+// Setup the operating mode & stack.\r
+// ---------------------------------\r
+ .global _start, start, _mainCRTStartup\r
+ .func _start\r
+\r
+_start:\r
+start:\r
+_mainCRTStartup:\r
+\r
+// Initialize Interrupt System\r
+// - Set stack location for each mode\r
+// - Leave in System Mode with Interrupts Disabled\r
+// -----------------------------------------------\r
+ ldr r0,=_stack\r
+ msr CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode\r
+ mov sp,r0\r
+ sub r0,r0,#UND_STACK_SIZE\r
+ msr CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode\r
+ mov sp,r0\r
+ sub r0,r0,#ABT_STACK_SIZE\r
+ msr CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode\r
+ mov sp,r0\r
+ sub r0,r0,#FIQ_STACK_SIZE\r
+ msr CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode\r
+ mov sp,r0\r
+ sub r0,r0,#IRQ_STACK_SIZE\r
+ msr CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode\r
+ mov sp,r0\r
+ sub r0,r0,#SVC_STACK_SIZE\r
+ msr CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode\r
+ mov sp,r0\r
+\r
+// Enable interrupts\r
+ msr CPSR_c,#MODE_SVC // Supervisor Mode -- recommended by our\r
+ // guru Pavel Pisa\r
+\r
+// Copy initialized data to its execution address in RAM\r
+// -----------------------------------------------------\r
+#define ROM_RUN\r
+#ifdef ROM_RUN\r
+ ldr r1,=_etext // -> ROM data start\r
+ ldr r2,=_data // -> data start\r
+ ldr r3,=_edata // -> end of data\r
+1: cmp r2,r3 // check if data to move\r
+ ldrlo r0,[r1],#4 // copy it\r
+ strlo r0,[r2],#4\r
+ blo 1b // loop until done\r
+#endif\r
+// Clear .bss\r
+// ----------\r
+ mov r0,#0 // get a zero\r
+ ldr r1,=__bss_start // -> bss start\r
+ ldr r2,=__bss_end__ // -> bss end\r
+2: cmp r1,r2 // check if data to clear\r
+ strlo r0,[r1],#4 // clear 4 bytes\r
+ blo 2b // loop until done\r
+\r
+// Call init functions in .init_array section (only if __libc_init_array exists)\r
+ .weak __libc_init_array\r
+ ldr r3,=__libc_init_array\r
+ cmp r3, #0\r
+ movne lr, pc\r
+ movne pc, r3\r
+\r
+// Call main program: main(0)\r
+// --------------------------\r
+ mov r0,#0 // no arguments (argc = 0)\r
+ mov r1,r0\r
+ mov r2,r0\r
+ mov fp,r0 // null frame pointer\r
+ mov r7,r0 // null frame pointer for thumb\r
+ ldr r10,=main\r
+ mov lr,pc\r
+ bx r10 // enter main()\r
+\r
+ .size _start, . - _start\r
+ .endfunc\r
+\r
+ .global _reset, reset, exit, abort\r
+ .func _reset\r
+_reset:\r
+reset:\r
+exit:\r
+abort:\r
+ b . // loop until reset\r
+\r
+ .size _reset, . - _reset\r
+ .endfunc\r
+\r
+ .end\r
--- /dev/null
+#\r
+# RAM/ISP\r
+#\r
+\r
+ .equ Mode_USR, 0x10\r
+ .equ Mode_FIQ, 0x11\r
+ .equ Mode_IRQ, 0x12\r
+ .equ Mode_SVC, 0x13\r
+ .equ Mode_ABT, 0x17\r
+ .equ Mode_UND, 0x1B\r
+ .equ Mode_SYS, 0x1F\r
+\r
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+ .equ Top_Stack, 0x40003ffc\r
+ .equ UND_Stack_Size, 0x00000004\r
+ .equ SVC_Stack_Size, 0x00000004\r
+ .equ ABT_Stack_Size, 0x00000004\r
+ .equ FIQ_Stack_Size, 0x00000004\r
+ .equ IRQ_Stack_Size, 0x00000200\r
+ .equ USR_Stack_Size, 0x00001000\r
+\r
+# -*-\r
+# -x-X-x-\r
+# -*-\r
+ .section .ivec, "xa"\r
+ .global _boot\r
+ .func _boot\r
+\r
+_boot: \r
+# Exception Vectors\r
+vectors: LDR PC, Reset_Addr \r
+ LDR PC, Undef_Addr\r
+ LDR PC, SWI_Addr\r
+ LDR PC, PAbt_Addr\r
+ LDR PC, DAbt_Addr\r
+ NOP /* Reserved Vector */\r
+# LDR PC, IRQ_Addr\r
+ LDR PC, [PC, #-0x0FF0] /* Vector from VicVectAddr */\r
+ LDR PC, FIQ_Addr\r
+\r
+Reset_Addr: .word _start\r
+Undef_Addr: .word Undef_Handler\r
+SWI_Addr: .word SWI_Handler\r
+PAbt_Addr: .word PAbt_Handler\r
+DAbt_Addr: .word DAbt_Handler\r
+ .word 0 /* Reserved Address */\r
+IRQ_Addr: .word IRQ_Handler\r
+FIQ_Addr: .word FIQ_Handler\r
+\r
+Undef_Handler: B Undef_Handler\r
+SWI_Handler: B SWI_Handler\r
+PAbt_Handler: B PAbt_Handler\r
+DAbt_Handler: B DAbt_Handler\r
+IRQ_Handler: B IRQ_Handler\r
+FIQ_Handler: B FIQ_Handler\r
+\r
+ .endfunc\r
+\r
+# -*-\r
+# program entry point\r
+# -*-\r
+\r
+ .text\r
+ .global _start, start\r
+ .func _start\r
+_start:\r
+\r
+# Initialise Interrupt System\r
+# ...\r
+\r
+# Setup Stack for each mode\r
+\r
+ LDR R0, =Top_Stack\r
+\r
+# Enter Undefined Instruction Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_UND|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #UND_Stack_Size\r
+\r
+# Enter Abort Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #ABT_Stack_Size\r
+\r
+# Enter FIQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #FIQ_Stack_Size\r
+\r
+# Enter IRQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #IRQ_Stack_Size\r
+\r
+# Enter Supervisor Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #SVC_Stack_Size\r
+\r
+# Enter User Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_USR\r
+ MOV SP, R0\r
+\r
+# Setup a default Stack Limit (when compiled with "-mapcs-stack-check")\r
+ SUB SL, SP, #USR_Stack_Size\r
+\r
+.if 0\r
+# Relocate .data section (Copy from ROM to RAM)\r
+ LDR R1, =_etext\r
+ LDR R2, =_data\r
+ LDR R3, =_edata\r
+LoopRel: CMP R2, R3\r
+ LDRLO R0, [R1], #4\r
+ STRLO R0, [R2], #4\r
+ BLO LoopRel\r
+.endif /*0*/\r
+\r
+# Clear .bss section (Zero init)\r
+ MOV R0, #0\r
+ LDR R1, =__bss_start__\r
+ LDR R2, =__bss_end__\r
+LoopZI: CMP R1, R2\r
+ STRLO R0, [R1], #4\r
+ BLO LoopZI\r
+\r
+# Enter the C code\r
+ ADR LR, __main_exit\r
+ LDR R0, =main\r
+ BX R0\r
+\r
+__main_exit: B __main_exit\r
+\r
+\r
+ .size _startup, . - _startup\r
+ .endfunc\r
+\r
+\r
+ .end\r
--- /dev/null
+/*
+ * Copyright (C) 2004 CodeSourcery, LLC
+ *
+ * Permission to use, copy, modify, and distribute this file
+ * for any purpose is hereby granted without fee, provided that
+ * the above copyright notice and this notice appears in all
+ * copies.
+ *
+ * This file is distributed WITHOUT ANY WARRANTY; without even the implied
+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#include <sys/types.h>
+
+/* Handle ELF .init_array sections. */
+
+/* These magic symbols are provided by the linker. */
+extern void (*__init_array_start []) (void) __attribute__((weak));
+extern void (*__init_array_end []) (void) __attribute__((weak));
+
+/* /\* Iterate over all the init routines. *\/ */
+/* void */
+/* __libc_init_array (void) */
+/* { */
+/* void (*func)(void); */
+
+/* for (func = (void (*)(void))__init_array_start; */
+/* func < (void (*)(void))__init_array_end; */
+/* func++) { */
+/* (*func)(); */
+/* } */
+/* } */
+
+/* Iterate over all the init routines. */
+void
+__libc_init_array (void)
+{
+ size_t count;
+ size_t i;
+
+ count = __init_array_end - __init_array_start;
+ for (i = 0; i < count; i++)
+ __init_array_start[i] ();
+}
--- /dev/null
+#/***********************************************************************/\r
+#/* This file is part of the uVision/ARM development tools */\r
+#/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */\r
+#/***********************************************************************/\r
+#/* */\r
+#/* STARTUP.S: Startup file for the Blinky Example */\r
+#/* */\r
+#/***********************************************************************/\r
+\r
+\r
+/* \r
+//*** <<< Use Configuration Wizard in Context Menu >>> *** \r
+*/\r
+\r
+\r
+# *** Startup Code (executed after Reset) ***\r
+\r
+\r
+# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs\r
+\r
+ .equ Mode_USR, 0x10\r
+ .equ Mode_FIQ, 0x11\r
+ .equ Mode_IRQ, 0x12\r
+ .equ Mode_SVC, 0x13\r
+ .equ Mode_ABT, 0x17\r
+ .equ Mode_UND, 0x1B\r
+ .equ Mode_SYS, 0x1F\r
+\r
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */\r
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */\r
+\r
+\r
+/*\r
+// <h> Stack Configuration\r
+// <o> Top of Stack Address <0x0-0xFFFFFFFF>\r
+// <h> Stack Sizes (in Bytes)\r
+// <o1> Undefined Mode <0x0-0xFFFFFFFF>\r
+// <o2> Supervisor Mode <0x0-0xFFFFFFFF>\r
+// <o3> Abort Mode <0x0-0xFFFFFFFF>\r
+// <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF>\r
+// <o5> Interrupt Mode <0x0-0xFFFFFFFF>\r
+// <o6> User/System Mode <0x0-0xFFFFFFFF>\r
+// </h>\r
+// </h>\r
+*/\r
+ .equ Top_Stack, 0x40000200\r
+ .equ UND_Stack_Size, 0x00000004\r
+ .equ SVC_Stack_Size, 0x00000004\r
+ .equ ABT_Stack_Size, 0x00000004\r
+ .equ FIQ_Stack_Size, 0x00000004\r
+ .equ IRQ_Stack_Size, 0x00000020\r
+ .equ USR_Stack_Size, 0x00000060\r
+\r
+\r
+# Phase Locked Loop (PLL) definitions\r
+ .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */\r
+ .equ PLLCON_OFS, 0x00 /* PLL Control Offset*/\r
+ .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */\r
+ .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */\r
+ .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */\r
+ .equ PLLCON_PLLE, (1<<0) /* PLL Enable */\r
+ .equ PLLCON_PLLC, (1<<1) /* PLL Connect */\r
+ .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */\r
+ .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */\r
+ .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */\r
+\r
+/*\r
+// <e> PLL Setup\r
+// <o1.0..4> MSEL: PLL Multiplier Selection\r
+// <1-32><#-1>\r
+// <i> M Value\r
+// <o1.5..6> PSEL: PLL Divider Selection\r
+// <0=> 1 <1=> 2 <2=> 4 <3=> 8\r
+// <i> P Value\r
+// </e>\r
+*/\r
+ .equ PLL_SETUP, 1\r
+ .equ PLLCFG_Val, 0x00000024\r
+\r
+\r
+# Memory Accelerator Module (MAM) definitions\r
+ .equ MAM_BASE, 0xE01FC000 /* MAM Base Address */\r
+ .equ MAMCR_OFS, 0x00 /* MAM Control Offset*/\r
+ .equ MAMTIM_OFS, 0x04 /* MAM Timing Offset */\r
+\r
+/*\r
+// <e> MAM Setup\r
+// <o1.0..1> MAM Control\r
+// <0=> Disabled\r
+// <1=> Partially Enabled\r
+// <2=> Fully Enabled\r
+// <i> Mode\r
+// <o2.0..2> MAM Timing\r
+// <0=> Reserved <1=> 1 <2=> 2 <3=> 3\r
+// <4=> 4 <5=> 5 <6=> 6 <7=> 7\r
+// <i> Fetch Cycles\r
+// </e>\r
+*/\r
+ .equ MAM_SETUP, 1\r
+ .equ MAMCR_Val, 0x00000002\r
+ .equ MAMTIM_Val, 0x00000004\r
+\r
+\r
+# Starupt Code must be linked first at Address at which it expects to run.\r
+\r
+ .text\r
+// .arm\r
+\r
+ .global _startup\r
+ .func _startup\r
+_startup:\r
+\r
+\r
+# Exception Vectors\r
+# Mapped to Address 0.\r
+# Absolute addressing mode must be used.\r
+# Dummy Handlers are implemented as infinite loops which can be modified.\r
+\r
+Vectors: LDR PC, Reset_Addr \r
+ LDR PC, Undef_Addr\r
+ LDR PC, SWI_Addr\r
+ LDR PC, PAbt_Addr\r
+ LDR PC, DAbt_Addr\r
+ NOP /* Reserved Vector */\r
+# LDR PC, IRQ_Addr\r
+ LDR PC, [PC, #-0x0FF0] /* Vector from VicVectAddr */\r
+ LDR PC, FIQ_Addr\r
+\r
+Reset_Addr: .word Reset_Handler\r
+Undef_Addr: .word Undef_Handler\r
+SWI_Addr: .word SWI_Handler\r
+PAbt_Addr: .word PAbt_Handler\r
+DAbt_Addr: .word DAbt_Handler\r
+ .word 0 /* Reserved Address */\r
+IRQ_Addr: .word IRQ_Handler\r
+FIQ_Addr: .word FIQ_Handler\r
+\r
+Undef_Handler: B Undef_Handler\r
+SWI_Handler: B SWI_Handler\r
+PAbt_Handler: B PAbt_Handler\r
+DAbt_Handler: B DAbt_Handler\r
+IRQ_Handler: B IRQ_Handler\r
+FIQ_Handler: B FIQ_Handler\r
+\r
+\r
+# Reset Handler\r
+\r
+Reset_Handler: \r
+\r
+.if 0\r
+.if PLL_SETUP\r
+ LDR R0, =PLL_BASE\r
+ MOV R1, #0xAA\r
+ MOV R2, #0x55\r
+\r
+# Configure and Enable PLL\r
+ MOV R3, #PLLCFG_Val\r
+ STR R3, [R0, #PLLCFG_OFS] \r
+ MOV R3, #PLLCON_PLLE\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+\r
+# Wait until PLL Locked\r
+PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]\r
+ ANDS R3, R3, #PLLSTAT_PLOCK\r
+ BEQ PLL_Loop\r
+\r
+# Switch to PLL Clock\r
+ MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+.endif\r
+\r
+\r
+.if MAM_SETUP\r
+ LDR R0, =MAM_BASE\r
+ MOV R1, #MAMTIM_Val\r
+ STR R1, [R0, #MAMTIM_OFS] \r
+ MOV R1, #MAMCR_Val\r
+ STR R1, [R0, #MAMCR_OFS] \r
+.endif\r
+\r
+\r
+# Memory Mapping (when Interrupt Vectors are in RAM)\r
+ .equ MEMMAP, 0xE01FC040 /* Memory Mapping Control */\r
+.ifdef RAM_INTVEC\r
+ LDR R0, =MEMMAP\r
+ MOV R1, #2\r
+ STR R1, [R0]\r
+.endif\r
+.endif /* 0 */\r
+\r
+\r
+# Initialise Interrupt System\r
+# ...\r
+\r
+\r
+# Setup Stack for each mode\r
+\r
+ LDR R0, =Top_Stack\r
+\r
+# Enter Undefined Instruction Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_UND|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #UND_Stack_Size\r
+\r
+# Enter Abort Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #ABT_Stack_Size\r
+\r
+# Enter FIQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #FIQ_Stack_Size\r
+\r
+# Enter IRQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #IRQ_Stack_Size\r
+\r
+# Enter Supervisor Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #SVC_Stack_Size\r
+\r
+# Enter User Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_USR\r
+ MOV SP, R0\r
+\r
+# Setup a default Stack Limit (when compiled with "-mapcs-stack-check")\r
+ SUB SL, SP, #USR_Stack_Size\r
+\r
+\r
+# Relocate .data section (Copy from ROM to RAM)\r
+ LDR R1, =_etext\r
+ LDR R2, =_data\r
+ LDR R3, =_edata\r
+LoopRel: CMP R2, R3\r
+ LDRLO R0, [R1], #4\r
+ STRLO R0, [R2], #4\r
+ BLO LoopRel\r
+\r
+\r
+# Clear .bss section (Zero init)\r
+ MOV R0, #0\r
+ LDR R1, =__bss_start__\r
+ LDR R2, =__bss_end__\r
+LoopZI: CMP R1, R2\r
+ STRLO R0, [R1], #4\r
+ BLO LoopZI\r
+\r
+\r
+# Enter the C code\r
+ ADR LR, __main_exit\r
+ LDR R0, =main\r
+ BX R0\r
+\r
+__main_exit: B __main_exit\r
+\r
+\r
+ .size _startup, . - _startup\r
+ .endfunc\r
+\r
+\r
+ .end\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LIBRARIES = can
+
+can_SOURCES = can.c can_baud.c
+
+nobase_include_HEADERS = periph/can.h
--- /dev/null
+#include <string.h>
+#include <periph/can.h>
+
+volatile int can_msg_received = 0;
+volatile can_msg_t can_rx_msg;
+
+/* default receive interrupt handler */
+void can_rx_isr() __attribute__((interrupt));
+
+/* private global variables */
+can_rx_callback can_rx_cb;
+
+void can_init(uint32_t btr, unsigned rx_isr_vect, can_rx_callback rx_cb) {
+ /* enable CAN1 Rx pin */
+ PINSEL1 |= 0x00040000;
+ PINSEL1 &= 0xfff7ffff;
+ /* receive all messages, no filtering */
+ AFMR = 0x2;
+ /* reset mode */
+ C1MOD = 0x1;
+ /* -- addition from lpc2000 maillist msg #3052: */
+ C1CMR = 0x0e; //Clear receive buffer, data overrun, abort tx
+ /* -- end of addition */
+ C1IER = 0x0;
+ C1GSR = 0x0;
+ /* set baudrate & timing */
+ C1BTR = btr;
+ /* register Rx handler */
+ can_rx_cb = rx_cb;
+ /* set interrupt vector */
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (uint32_t)can_rx_isr;
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x20 | 26;
+ /* enable Rx int */
+ VICIntEnable = 0x04000000;
+ C1IER = 0x1;
+ /* normal (operating) mode */
+ C1MOD = 0x0;
+#if 0
+ /* LPC2119 CAN.5 erratum workaround */
+ C1TFI1 = 0x00000000;
+ C1TID1 = 0x0;
+ C1CMR = 0x23;
+#endif
+}
+
+void can_off() {
+ can_rx_cb = NULL;
+ /* disable Rx int */
+ VICIntEnClr = 0x04000000;
+ C1IER = 0x0;
+ /* abort transmission */
+ C1CMR = 0x2;
+ /* switch off the CAN controller */
+ C1MOD = 0x1;
+}
+
+void can_rx_isr() {
+ can_rx_msg.flags = C1RFS;
+ can_rx_msg.dlc = (can_rx_msg.flags>>16) & 0xf;
+ can_rx_msg.id = C1RID;
+ memcpy((void *) can_rx_msg.data, (void *) &C1RDA, sizeof(uint32_t));
+ memcpy((void *) &can_rx_msg.data[4], (void *) &C1RDB, sizeof(uint32_t));
+ can_msg_received = 1;
+ if (can_rx_cb != NULL)
+ can_rx_cb((can_msg_t*)&can_rx_msg);
+ /* release Rx buffer */
+ C1CMR = 0x4;
+ /* int acknowledge */
+ VICVectAddr = 0;
+}
+
+int can_tx_msg(can_msg_t *tx_msg) {
+ uint32_t *data = (uint32_t*)tx_msg->data;
+
+ /* check, if buffer is ready (previous Tx completed) */
+ if ((C1SR & 0x4) == 0)
+ return -1; /* busy */
+ C1TFI1 = (tx_msg->flags & 0xc0000000) |
+ ((tx_msg->dlc<<16) & 0x000f0000);
+ C1TID1 = tx_msg->id;
+ C1TDA1 = data[0];
+ C1TDB1 = data[1];
+ /* start transmission */
+ C1CMR = 0x21;
+ return 0; /* OK */
+}
+
+/*EOF*/
--- /dev/null
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Philips LPC2129 CAN Example
+//
+// Description
+// -----------
+// This example demonstrates setup of CAN module
+//
+// Author : Jiri Kubias DCE CVUT
+// Modified : 13.03.08: added Autobaud calc. Jiri Kubias DCE CVUT
+//
+// Prereq: startcfg.h startcfg.h types.h
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+#include <periph/can.h>
+#include <system_def.h>
+
+//#include "types.h"
+
+//volatile int can_msg_received = 0;
+//volatile can_msg_t can_rx_msg;
+
+/* default receive interrupt handler */
+//void can_rx_isr() __attribute__((interrupt));
+
+/* private global variables */
+//uint32_t *can_rx_msg_data = (uint32_t*)can_rx_msg.data;
+//can_rx_callback can_rx_cb;
+
+
+
+//void can_init(uint32_t bitrate, unsigned rx_isr_vect, can_rx_callback rx_cb)
+void can_init_baudrate(uint32_t baudrate, unsigned rx_isr_vect, can_rx_callback rx_cb)
+{
+ uint32_t tseg1, tseg2, i, quanta, best, sjw, divider, clk, q, btr_calc, diff;
+
+ best = 0xFFFFFFFF;
+ quanta = 0;
+
+
+ clk = CPU_APB_HZ;//get_apb_speed() * 1000; FIXME convert to system_def.h CPU_APB_HZ
+
+ for ( i = 8 ; i <= 25 ; i++){
+ int q = baudrate * i;
+ divider = clk / q;
+
+ btr_calc = clk / (i * divider);
+
+ if(btr_calc > baudrate) diff = btr_calc - baudrate;
+ else diff = baudrate - btr_calc;
+
+ if (diff < best) {
+ best = diff;
+ quanta = i;
+ }
+ }
+
+ q = baudrate * quanta;
+ divider = (clk + q/2) / q;
+
+ tseg1 = ((quanta * 70) / 100); // this is tseg1
+ tseg2 = quanta - tseg1; //(quanta[i] - ((quanta[i] * 70) / 100)); // this is Tseg2
+
+ tseg1 -= 1;
+ tseg2 -= 1;
+ divider -= 1;
+
+
+ if (tseg2 < 5)
+ sjw = tseg2 -1;
+ else
+ sjw = 4;
+
+
+ // TODO samling point
+
+
+ /* enable CAN1 Rx pin */
+ PINSEL1 |= 0x00040000;
+ PINSEL1 &= 0xfff7ffff;
+
+ /* receive all messages, no filtering */
+ AFMR = 0x2;
+
+ /* reset mode */
+ C1MOD = 0x1;
+
+ /* -- addition from lpc2000 maillist msg #3052: */
+ C1CMR = 0x0e; //Clear receive buffer, data overrun, abort tx
+
+ /* -- end of addition */
+ C1IER = 0x0;
+ C1GSR = 0x0;
+
+ /* set baudrate & timing */
+
+ C1BTR = divider | (tseg1 << 16) \
+ | (tseg2 << 20) | (sjw<<14);
+
+ /* register Rx handler */
+ can_rx_cb = rx_cb;
+
+ /* set interrupt vector */
+ ((uint32_t*)&VICVectAddr0)[rx_isr_vect] = (uint32_t)can_rx_isr;
+ ((uint32_t*)&VICVectCntl0)[rx_isr_vect] = 0x20 | 26;
+
+ /* enable Rx int */
+ VICIntEnable = 0x04000000;
+ C1IER = 0x1;
+
+ /* normal (operating) mode */
+ C1MOD = 0x0;
+
+ #if 0
+ /* LPC2119 CAN.5 erratum workaround */
+ C1TFI1 = 0x00000000;
+ C1TID1 = 0x0;
+ C1CMR = 0x23;
+ #endif
+}
+
+
+
+/*EOF*/
--- /dev/null
+#include <stdlib.h>
+#include <types.h>
+#include <lpc21xx.h>
+
+typedef struct _can_msg_t {
+#define CAN_MSG_RTR 0x40000000
+#define CAN_MSG_EXTID 0x80000000
+ uint32_t flags;
+ unsigned short dlc;
+ uint32_t id;
+ unsigned char data[8];
+} can_msg_t;
+
+typedef void (*can_rx_callback)(can_msg_t *msg);
+
+/* private global variables */
+can_rx_callback can_rx_cb;
+
+/* public global variables */
+extern volatile int can_msg_received;
+extern volatile can_msg_t can_rx_msg;
+
+/* function prototypes */
+void can_init(uint32_t btr, unsigned rx_isr_vect, can_rx_callback rx_cb); // Marek Peca function btr is register
+
+void can_init_baudrate(uint32_t baudrate, unsigned rx_isr_vect, can_rx_callback rx_cb); // Jiri Kubias function auto baudrate calculation
+void can_off();
+int can_tx_msg(can_msg_t *tx_msg);
+
+void can_rx_isr();
+
+/*EOF*/
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
--- /dev/null
+/***********************************************************************/\r
+/* This file is part of the ARM Compiler package */\r
+/* Copyright KEIL ELEKTRONIK GmbH 1992-2004 */\r
+/***********************************************************************/\r
+/* */\r
+/* TARGET.LD: Linker Script File */\r
+/* */\r
+/***********************************************************************/\r
+\r
+\r
+/*\r
+//*** <<< Use Configuration Wizard in Context Menu >>> *** \r
+*/\r
+\r
+\r
+/*\r
+// <h> Memory Configuration\r
+// <h> Code (Read Only)\r
+// <o> Start <0x0-0xFFFFFFFF>\r
+// <o1> Size <0x0-0xFFFFFFFF>\r
+// </h>\r
+// <h> Data (Read/Write)\r
+// <o2> Start <0x0-0xFFFFFFFF>\r
+// <o3> Size <0x0-0xFFFFFFFF>\r
+// </h>\r
+// </h>\r
+*/\r
+\r
+/* Memory Definitions */\r
+\r
+MEMORY\r
+{\r
+ CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x0003E000\r
+ /*DATA (rw) : ORIGIN = 0x40000000, LENGTH = 0x00004000*/\r
+ DATA (rw) : ORIGIN = 0x40000120, LENGTH = 0x00000050\r
+}\r
+\r
+STARTUP(startup.o)\r
+\r
+/* Section Definitions */\r
+\r
+SECTIONS\r
+{\r
+\r
+ /* first section is .text which is used for code */\r
+\r
+ .text :\r
+ {\r
+ *startup.o (.text) /* Startup code */\r
+ *(.text) /* remaining code */\r
+\r
+ *(.glue_7t) *(.glue_7)\r
+\r
+ } >CODE =0\r
+\r
+ . = ALIGN(4);\r
+\r
+ /* .rodata section which is used for read-only data (constants) */\r
+\r
+ .rodata :\r
+ {\r
+ *(.rodata)\r
+ } >CODE\r
+\r
+ . = ALIGN(4);\r
+\r
+ _etext = . ;\r
+ PROVIDE (etext = .);\r
+\r
+ /* .data section which is used for initialized data */\r
+\r
+ .data : AT (_etext)\r
+ {\r
+ _data = . ;\r
+ /* *!*!*!* */\r
+ PROVIDE (canload_id = .);\r
+ . += 4;\r
+ /* *!*!*!* */\r
+ *(.data)\r
+ SORT(CONSTRUCTORS)\r
+ } >DATA\r
+ . = ALIGN(4);\r
+\r
+ _edata = . ;\r
+ PROVIDE (edata = .);\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+\r
+ .bss :\r
+ {\r
+ __bss_start = . ;\r
+ __bss_start__ = . ;\r
+ *(.bss)\r
+ *(COMMON)\r
+ } >DATA\r
+ . = ALIGN(4);\r
+ __bss_end__ = . ;\r
+ __bss_end__ = . ;\r
+\r
+ _end = .;\r
+ PROVIDE (end = .);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+lpc21xx.ld-mpflash
\ No newline at end of file
--- /dev/null
+/***********************************************************************/\r
+/* This file is part of the ARM Compiler package */\r
+/* Copyright KEIL ELEKTRONIK GmbH 1992-2004 */\r
+/***********************************************************************/\r
+/* */\r
+/* TARGET.LD: Linker Script File */\r
+/* */\r
+/***********************************************************************/\r
+\r
+\r
+/*\r
+//*** <<< Use Configuration Wizard in Context Menu >>> *** \r
+*/\r
+\r
+STACK_SIZE = 0x400;\r
+\r
+/*\r
+// <h> Memory Configuration\r
+// <h> Code (Read Only)\r
+// <o> Start <0x0-0xFFFFFFFF>\r
+// <o1> Size <0x0-0xFFFFFFFF>\r
+// </h>\r
+// <h> Data (Read/Write)\r
+// <o2> Start <0x0-0xFFFFFFFF>\r
+// <o3> Size <0x0-0xFFFFFFFF>\r
+// </h>\r
+// </h>\r
+*/\r
+\r
+/* Memory Definitions */\r
+\r
+MEMORY\r
+{\r
+ CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x0003E000\r
+ DATA (rw) : ORIGIN = 0x40000000, LENGTH = 0x00004000\r
+}\r
+\r
+STARTUP(crt0flash.o)\r
+INCLUDE board.ld /* Allow to INPUT board specific files */\r
+\r
+/* Section Definitions */\r
+\r
+SECTIONS\r
+{\r
+ .ivec :\r
+ {\r
+ *(.ivec) /* interrupt entry points */\r
+ } > CODE\r
+\r
+ /* first section is .text which is used for code */\r
+ .text :\r
+ {\r
+ *crt0flash.o (.text) /* Startup code */\r
+ *(.text) /* remaining code */\r
+\r
+ *(.glue_7t) *(.glue_7)\r
+\r
+ } >CODE =0\r
+\r
+ . = ALIGN(4);\r
+\r
+ /* .init_array - pointers to functions called before main */\r
+ PROVIDE (__init_array_start = .);\r
+ .init_array :\r
+ {\r
+ *(.init_array)\r
+ } >CODE =0\r
+ PROVIDE (__init_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /* .rodata section which is used for read-only data (constants) */\r
+\r
+ .rodata :\r
+ {\r
+ *(.rodata)\r
+ } >CODE\r
+\r
+ . = ALIGN(4);\r
+\r
+ _etext = . ;\r
+ PROVIDE (etext = .);\r
+\r
+ /* .data section which is used for initialized data */\r
+\r
+ .data : AT (_etext)\r
+ {\r
+ _data = . ;\r
+ /* *!*!*!* */\r
+ PROVIDE (canload_id = .);\r
+ . += 4;\r
+ /* *!*!*!* */\r
+ *(.data)\r
+ SORT(CONSTRUCTORS)\r
+ } >DATA\r
+ . = ALIGN(4);\r
+\r
+ _edata = . ;\r
+ PROVIDE (edata = .);\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+\r
+ .bss :\r
+ {\r
+ __bss_start = . ;\r
+ __bss_start__ = . ;\r
+ *(.bss)\r
+ *(COMMON)\r
+ } >DATA\r
+ . = ALIGN(4);\r
+ __bss_end__ = . ;\r
+ __bss_end__ = . ;\r
+\r
+ .stack ALIGN(256) :\r
+ {\r
+ . += STACK_SIZE;\r
+ PROVIDE (_stack = .);\r
+ } > DATA\r
+\r
+ _end = .;\r
+ PROVIDE (end = .);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+/***\r
+ * LPC21xx RAM with <0x40000120;0x40000200) hole\r
+ * used by ISP or CAN bootloader\r
+ ***/\r
+\r
+STARTUP(crt0.o)\r
+INCLUDE board.ld /* Allow to INPUT board specific files */\r
+\r
+ENTRY(_start)\r
+STACK_SIZE = 0x400;\r
+\r
+/* Memory Definitions */\r
+MEMORY\r
+{\r
+ RAML (rw) : ORIGIN = 0x40000000, LENGTH = 0x00000120\r
+ RAMH (rw) : ORIGIN = 0x40000200, LENGTH = 0x00004000\r
+}\r
+\r
+/* Section Definitions */\r
+\r
+SECTIONS\r
+{\r
+ .ivec :\r
+ {\r
+ *(.ivec) /* interrupt entry points */\r
+ } > RAML\r
+\r
+ /* first section is .text which is used for code */\r
+ .text :\r
+ {\r
+ *crt0.o (.text) /* Startup code */\r
+ *(.text) /* remaining code */\r
+\r
+ *(.rodata) /* read-only data (constants) */\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } > RAMH\r
+\r
+ . = ALIGN(4);\r
+ _etext = . ;\r
+ PROVIDE (etext = .);\r
+\r
+ /* .init_array - pointers to functions called before main */\r
+ PROVIDE (__init_array_start = .);\r
+ .init_array :\r
+ {\r
+ *(.init_array)\r
+ } >RAMH =0\r
+ PROVIDE (__init_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /* .data section which is used for initialized data */\r
+ .data :\r
+ {\r
+ _data = .;\r
+ *(.data)\r
+ . = ALIGN(4);\r
+ } > RAMH\r
+\r
+ _edata = . ;\r
+ PROVIDE (edata = .);\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ __bss_start = . ;\r
+ __bss_start__ = . ;\r
+ *(.bss)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ } > RAMH\r
+\r
+ . = ALIGN(4);\r
+ __bss_end__ = . ;\r
+ PROVIDE (__bss_end = .);\r
+\r
+ .stack ALIGN(256) :\r
+ {\r
+ . += STACK_SIZE;\r
+ PROVIDE (_stack = .);\r
+ } > RAMH\r
+\r
+ _end = . ;\r
+ PROVIDE (end = .);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+lpc21xx.ld-mpram
\ No newline at end of file
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* RAMISP.ld: Linker Script File - for use with serial line boo loader*/\r
+/* */\r
+/***********************************************************************/\r
+ENTRY(_start)\r
+STACK_SIZE = 0x400;\r
+\r
+/* Memory Definitions */\r
+MEMORY\r
+{\r
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000\r
+ RAMBEG (rw) : ORIGIN = 0x40000000, LENGTH = 0x00000120\r
+ RAMISP (r) : ORIGIN = 0x40000120, LENGTH = 0x000000E0\r
+ RAMREST (rw) : ORIGIN = 0x40000200, LENGTH = 0x0000FE00\r
+}\r
+\r
+STARTUP(crt0.o)\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ /* first section is .text which is used for code */\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+/* LONG( ((ABSOLUTE( _start ) - . - 8) >> 2) + 0xea000000 ) /* B _start */\r
+ *(.text) /* remaining code */\r
+ *(.rodata) /* read-only data (constants) */\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ _etext = . ;\r
+ PROVIDE (etext = .);\r
+\r
+ .ivec :\r
+ {\r
+ *(.ivec) /* remaining code */\r
+ } > RAMBEG\r
+ \r
+ /* .data section which is used for initialized data */\r
+ .data :\r
+ {\r
+ _data = .;\r
+ *(.data)\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ _edata = . ;\r
+ PROVIDE (edata = .);\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ __bss_start = . ;\r
+ __bss_start__ = . ;\r
+ *(.bss)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ __bss_end__ = . ;\r
+ PROVIDE (__bss_end = .);\r
+\r
+ .stack ALIGN(256) :\r
+ {\r
+ . += STACK_SIZE;\r
+ PROVIDE (_stack = .);\r
+ } > RAMREST\r
+\r
+ _end = . ;\r
+ PROVIDE (end = .);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+bin_PROGRAMS = uart_noz
+
+uart_noz_SOURCES = main.c
+uart_noz_LIBS = uart_nozen
+
+
+lib_LIBRARIES = uart_nozen
+uart_nozen_SOURCES = uart_nozen.c
+
+include_HEADERS = uart_nozen.h
--- /dev/null
+
+
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <errno.h>
+#include <periph/can.h>
+#include <system_def.h>
+#include <string.h>
+#include <deb_led.h>
+#include "uart_nozen.h"
+
+
+
+
+#define CAN_SPEED 1000000
+
+#define CAN_ISR 0
+#define SERVO_ISR 1
+#define UART0_ISR 3
+#define UART1_ISR 4
+
+
+
+void dummy_wait(void)
+{
+ int i = 1000000;
+ while(--i);
+}
+
+
+
+void init_perip(void) // inicializace periferii mikroprocesoru
+{
+ UART_init( UART0,UART0_ISR, 19200, UART_BITS_8, UART_STOP_BIT_1, UART_PARIT_OFF, 0);
+ UART_init( UART1,UART1_ISR, 115100, UART_BITS_8, UART_STOP_BIT_1, UART_PARIT_OFF, 0);
+}
+
+
+
+int main (void)
+{
+
+// sample use
+ init_perip(); // sys init MCU
+
+
+
+
+ while(1)
+ {
+ while (UART_new_data(UART1))
+ {
+ write_UART_data( UART0, read_UART_data(UART1));
+ }
+
+ while (UART_new_data(UART0))
+ {
+ write_UART_data( UART1, read_UART_data(UART0));
+ }
+ __deb_led_on(LEDG);
+ dummy_wait();
+ __deb_led_off(LEDG);
+ __deb_led_off(LEDY);
+ dummy_wait();
+ }
+}
+
+
+
--- /dev/null
+/********************************************************/
+/* ZEN UART library for LPC ARM */
+/* */
+/* ver. 3.0 release */
+/* */
+/* (c) 2006, 2007 Ondrej Spinka, DCE FEE CTU Prague */
+/* modified by Jiri Kubias 2008, DCE FEE CTU Prague */
+/* */
+/* no animals were harmed during development/testing */
+/* of this software product, except the author himself */
+/* */
+/* you may use this library for whatever purpose you */
+/* like, safe for satanistic rituals. */
+/********************************************************/
+
+
+#include <system_def.h>
+#include "uart_nozen.h"
+
+/*! @defgroup defines Constants Definitions
+* @{
+*/
+
+/*!\def RX_MASK
+* Interrupt identification mask.
+*/
+#define RX_MASK 0x0E
+
+/*!\def RX_INT
+* Receive data available mask.
+*/
+#define RX_INT 0x04
+
+/*!\def TX_EMPTY
+* Transmitter holding register empty mask.
+*/
+#define TX_EMPTY 0x20
+
+/*!\def UART_REG_OFFSET
+* Makro for register address computation according respective UART number.
+*/
+#define UART_REG_ADDR(base_reg, dev_num) ( *( (volatile char *) ( ( (volatile void *) &base_reg ) + ( (dev_num) * UART1_OFFSET ) ) ) )
+/*! @} */
+
+#define UART_DLAB 0x80 // FIXME
+
+volatile uint8_t err_flag[2] = {0, 0}, new_data_flag[2] = {0, 0}, over_flag[2] = {0, 0}; //!< UART0 and UART1 error flags, new data flags and buffer overflow flags
+volatile uint8_t i_w[2] = {0, 0}, i_r[2] = {0, 0}; //!< UART0 and UART1 read and write buffer indexes
+uint8_t buff[2][UART_BUFF_LEN]; //!< UART0 and UART1 data buffers
+
+/*! UART0 interrupt handler prototype */
+void UART0_irq ( void ) __attribute__ ( ( interrupt ) );
+
+/*! UART1 interrupt handler prototype */
+void UART1_irq ( void ) __attribute__ ( ( interrupt ) );
+
+/*! UART interrupt service routine.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+*/
+void UART_isr ( uint8_t uart_num ) {
+ if ( i_w[uart_num] > UART_BUFF_LEN - 1 ) i_w[uart_num] = 0; // when buffer is full, start overwriting oldest data
+
+ err_flag[uart_num] = UART_REG_ADDR ( U0LSR, uart_num ) & 0x8E; // check the line status
+
+ if ( ( UART_REG_ADDR ( U0IIR, uart_num ) & RX_MASK ) == RX_INT ) { // if Rx data ready IRQ is pending
+ buff[uart_num][i_w[uart_num]++] = UART_REG_ADDR ( U0RBR, uart_num ); // store new character into the receive buffer
+ new_data_flag[uart_num] = 1; // set the new data flag
+ }
+
+ if ( i_w[uart_num] == i_r[uart_num] ) { // when round buffer is full
+ i_r[uart_num]++; // shift the oldest byte pointer
+ over_flag[uart_num] = 1; // set the data overwrite flag
+ }
+
+ VICVectAddr = 0; // int acknowledge
+}
+
+/*! UART0 Rx interrupt service rutine.
+* This rutine might be modified according user demands.
+*/
+void UART0_irq ( void ) {
+ UART_isr ( UART0 );
+}
+
+/*! UART1 Rx interrupt service rutine.
+* This rutine might be modified according user demands.
+*/
+void UART1_irq ( void ) {
+ UART_isr ( UART1 );
+}
+
+/*! UART initialization function.
+* Takes three arguments:
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \param baud_rate unsigned 32-bit int baud rate in bps
+* \param rx_isr_vect unsigned 32-bit int interrupt vector number
+*/
+void UART_init ( uint8_t uart_num, unsigned rx_isr_vect, uint32_t baud_rate ,uint8_t bits, uint8_t stopbit, uint8_t parit_en, char parit_mode )
+ {
+ uint16_t divisor = (CPU_VPB_HZ + (baud_rate * 16)/2) / (baud_rate * 16); // baud divisor computation
+
+
+ PINSEL0 &= ( 0xFFFFFFF0 - ( uart_num * 0xEFFF1 ) ); //enable UART functionality on respective processor pins
+ PINSEL0 |= ( 0x00000005 + ( uart_num * 0x4FFFB ) );
+ UART_REG_ADDR ( U0LCR, uart_num ) = UART_DLAB | bits | stopbit | parit_en | parit_mode; //0x83; // 8-bit data, no parity, set DLAB = 1
+ UART_REG_ADDR ( U0DLL, uart_num ) = *(uint8_t *) &divisor; // write divisor lo-byte
+ UART_REG_ADDR ( U0DLM, uart_num ) = *( ( (uint8_t *) &divisor ) + 1 ); // write divisor hi-byte
+ UART_REG_ADDR ( U0LCR, uart_num ) &= 0x7F; // clear DLAB
+ UART_REG_ADDR ( U0FCR, uart_num ) = 0x01; // enable UART FIFO, interrupt level 1 byte - this might be modified by the user
+ UART_REG_ADDR ( U0IER, uart_num ) = 0x01; // enable RBR interrupt
+
+ if ( !uart_num ) ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART0_irq; // if UART0 register UART0 interrupt handler
+ else ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART1_irq; // else register UART1 interrupt handler
+
+ ( ( uint32_t * ) &VICVectCntl0 )[rx_isr_vect] = 0x20 | ( 6 + uart_num ); // enable IRQ slot, set UART interrupt number
+ VICIntEnable = ( ( uart_num + 1 ) * 0x00000040 ); //enable UART IRQ
+}
+
+/*! Data read function.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns readed character (unsigned 8-bit int).
+*/
+uint8_t read_UART_data ( uint8_t uart_num ) {
+ uint8_t data; // readed data byte
+
+ while ( !new_data_flag[uart_num] ); // wait for new Rx data
+
+ if ( i_r[uart_num] > UART_BUFF_LEN - 1 ) i_r[uart_num] = 0; // when top of the buffer is reached, return the read pointer to 0
+ data = buff[uart_num][i_r[uart_num]++]; // read new data from the data buffer
+ if ( i_r[uart_num] == i_w[uart_num] ) new_data_flag[uart_num] = 0; // when all data was read clear the new data flag
+
+ return data; // return new data byte
+}
+
+/*! Determine possible UART transmission errors.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns error code (0 no errors, -1 UART error, -2 incoming data buffer overrun).
+*/
+int8_t UART_test_err ( uint8_t uart_num ) {
+ if ( err_flag[uart_num] ) { // check the UART0 error flag
+ err_flag[uart_num] = 0; // reset the UART0 error flag
+ return -1; // return error code
+ }
+
+ if ( over_flag[uart_num] ) { // check the UART0 incoming data buffer overrun flag
+ over_flag[uart_num] = 0; // reset the UART0 incoming data buffer overrun flag
+ return -2; // return error code
+ }
+
+ return 0; // no errors
+}
+
+/*! Determine whether new data wait in the UART round buffer.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns 1 if there are unreaded data in the incoming data buffer, 0 otherwise.
+*/
+inline uint8_t UART_new_data ( uint8_t uart_num ) {
+ return new_data_flag[uart_num]; // return UART new data flag
+}
+
+/*! Data write function.
+* Takes two arguments:
+* \param uart_num unsigned 8-bit UART number (0 or 1)
+* \param data unsigned 8-bit int byte (character) to send
+*/
+void write_UART_data ( uint8_t uart_num, uint8_t data ) {
+ while ( !( UART_REG_ADDR ( U0LSR, uart_num ) & TX_EMPTY ) ); // wait for the transmitter holding register emptying
+ UART_REG_ADDR ( U0THR, uart_num ) = data; // write the data byte to the transmitter holding register
+}
--- /dev/null
+/********************************************************/
+/* NOZEN UART library for LPC ARM */
+/* */
+/* ver. 3.0 release */
+/* */
+/* (c) 2006, 2007 Ondrej Spinka, DCE FEE CTU Prague */
+/* modified by Jiri Kubias 2008, DCE FEE CTU Prague */
+/* */
+/* no animals were harmed during development/testing */
+/* of this software product, except the author himself */
+/* */
+/* you may use this library for whatever purpose you */
+/* like, safe for satanistic rituals. */
+/********************************************************/
+
+#include <types.h>
+#include <lpc21xx.h>
+
+
+/*! @defgroup defines Constants Definitions
+* @{
+*/
+
+/*!\def SYSTEM_CLK
+* System clock frequency in Hz.
+*/
+// #define SYSTEM_CLK 10000000
+
+/*!\def UART_BUFF_LEN
+* Incomming data buffer length.
+*/
+#ifndef UART_BUFF_LEN
+#define UART_BUFF_LEN 64
+#endif
+
+/*!\def UART_BITS
+* Number of bits.
+*/
+#define UART_BITS_5 0x0
+#define UART_BITS_6 0x1
+#define UART_BITS_7 0x2
+#define UART_BITS_8 0x3
+
+/*!\def UART_BITS
+* Number of stopbits.
+*/
+#define UART_STOP_BIT_1 (0x0 << 2)
+#define UART_STOP_BIT_2 (0x1 << 2)
+
+/*!\def UART_BITS
+* UART parits.
+*/
+#define UART_PARIT_ENA (0x1 << 3)
+#define UART_PARIT_OFF (0x0 << 3)
+#define UART_PARIT_ODD (0x0 << 4)
+#define UART_PARIT_EVEN (0x1 << 4)
+#define UART_PARIT_FORCE_1 (0x2 << 4)
+#define UART_PARIT_FORCE_0 (0x3 << 4)
+/*! @} */
+
+/*!\def UART1_OFFSET
+* UART1 address offset.
+*/
+#define UART1_OFFSET 0x4000
+
+/*!\def UART0
+* UART0 number.
+*/
+#define UART0 0
+
+/*!\def UART1
+* UART1 number.
+*/
+#define UART1 1
+/*! @} */
+
+/*! @defgroup prototypes Function Prototypes
+* @{
+*/
+
+/*! UART initialization function.
+* Takes three arguments:
+* \param uart_num unsigned 8-bit int UART device number
+* \param baud_rate unsigned 32-bit int baud rate in bps
+* \param rx_isr_vect unsigned 32-bit int interrupt vector number
+* \param bits unsigned 8-bit int number of transmited bits
+* \param stopbit unsigned 8bit int number of stop
+* \param parit_en unsigned 8-bit enable or dislable parity generator
+* \param parit_mode unsigned 8-bit selects type of parity (if parit_en is ON)
+*/
+void UART_init ( uint8_t uart_num, unsigned rx_isr_vect, uint32_t baud_rate ,uint8_t bits, uint8_t stopbit, uint8_t parit_en, char parit_mode);
+
+
+/*! Data read function.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns readed character (unsigned 8-bit int).
+*/
+uint8_t read_UART_data ( uint8_t uart_num );
+
+/*! Determine possible UART transmission errors.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns error code (0 no errors, -1 UART error, -2 incoming data buffer overrun).
+*/
+int8_t UART_test_err ( uint8_t uart_num );
+
+/*! Determine whether new data wait in the UART round buffer.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns 1 if there are unreaded data in the incoming data buffer, 0 otherwise.
+*/
+inline uint8_t UART_new_data ( uint8_t uart_num );
+
+/*! Data write function.
+* Takes two arguments:
+* \param uart_num unsigned 8-bit UART number (0 or 1)
+* \param data unsigned 8-bit int byte (character) to send
+*/
+void write_UART_data ( uint8_t uart_num, uint8_t data );
+/*! @} */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LIBRARIES = uart_zen
+
+uart_zen_SOURCES = uart_zen.c
+
+nobase_include_HEADERS = periph/uart_zen.h
--- /dev/null
+/********************************************************/
+/* ZEN UART library for LPC ARM */
+/* */
+/* ver. 3.0 release */
+/* */
+/* (c) 2006, 2007 Ondrej Spinka, DCE FEE CTU Prague */
+/* */
+/* no animals were harmed during development/testing */
+/* of this software product, except the author himself */
+/* */
+/* you may use this library for whatever purpose you */
+/* like, safe for satanistic rituals. */
+/********************************************************/
+
+#include <types.h>
+#include <lpc21xx.h>
+
+/*! @defgroup defines Constants Definitions
+* @{
+*/
+
+/*!\def SYSTEM_CLK
+* System clock frequency in Hz.
+*/
+#define SYSTEM_CLK 10000000
+
+/*!\def UART_BUFF_LEN
+* Incomming data buffer length.
+*/
+#define UART_BUFF_LEN 64
+/*! @} */
+
+/*!\def UART1_OFFSET
+* UART1 address offset.
+*/
+#define UART1_OFFSET 0x4000
+
+/*!\def UART0
+* UART0 number.
+*/
+#define UART0 0
+
+/*!\def UART1
+* UART1 number.
+*/
+#define UART1 1
+/*! @} */
+
+/*! @defgroup prototypes Function Prototypes
+* @{
+*/
+
+/*! UART initialization function.
+* Takes three arguments:
+* \param uart_num unsigned 8-bit int UART device number
+* \param baud_rate unsigned 32-bit int baud rate in bps
+* \param rx_isr_vect unsigned 32-bit int interrupt vector number
+*/
+void UART_init ( uint8_t uart_num, uint32_t baud_rate, unsigned rx_isr_vect );
+
+/*! Data read function.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns readed character (unsigned 8-bit int).
+*/
+uint8_t read_UART_data ( uint8_t uart_num );
+
+/*! Determine possible UART transmission errors.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns error code (0 no errors, -1 UART error, -2 incoming data buffer overrun).
+*/
+int8_t UART_test_err ( uint8_t uart_num );
+
+/*! Determine whether new data wait in the UART round buffer.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns 1 if there are unreaded data in the incoming data buffer, 0 otherwise.
+*/
+inline uint8_t UART_new_data ( uint8_t uart_num );
+
+/*! Data write function.
+* Takes two arguments:
+* \param uart_num unsigned 8-bit UART number (0 or 1)
+* \param data unsigned 8-bit int byte (character) to send
+*/
+void write_UART_data ( uint8_t uart_num, uint8_t data );
+/*! @} */
--- /dev/null
+/********************************************************/
+/* ZEN UART library for LPC ARM */
+/* */
+/* ver. 3.0 release */
+/* */
+/* (c) 2006, 2007 Ondrej Spinka, DCE FEE CTU Prague */
+/* modified: 2008 Jiri Kubias DCE FEE CTU */
+/* - fixed baudrate computing */
+/* */
+/* no animals were harmed during development/testing */
+/* of this software product, except the author himself */
+/* */
+/* you may use this library for whatever purpose you */
+/* like, safe for satanistic rituals. */
+/********************************************************/
+
+#include <periph/uart_zen.h>
+
+/*! @defgroup defines Constants Definitions
+* @{
+*/
+
+/*!\def RX_MASK
+* Interrupt identification mask.
+*/
+#define RX_MASK 0x0E
+
+/*!\def RX_INT
+* Receive data available mask.
+*/
+#define RX_INT 0x04
+
+/*!\def TX_EMPTY
+* Transmitter holding register empty mask.
+*/
+#define TX_EMPTY 0x20
+
+/*!\def UART_REG_OFFSET
+* Makro for register address computation according respective UART number.
+*/
+#define UART_REG_ADDR(base_reg, dev_num) ( *( (volatile char *) ( ( (volatile void *) &base_reg ) + ( (dev_num) * UART1_OFFSET ) ) ) )
+/*! @} */
+
+volatile uint8_t err_flag[2] = {0, 0}, new_data_flag[2] = {0, 0}, over_flag[2] = {0, 0}; //!< UART0 and UART1 error flags, new data flags and buffer overflow flags
+volatile uint8_t i_w[2] = {0, 0}, i_r[2] = {0, 0}; //!< UART0 and UART1 read and write buffer indexes
+uint8_t buff[2][UART_BUFF_LEN]; //!< UART0 and UART1 data buffers
+
+/*! UART0 interrupt handler prototype */
+void UART0_irq ( void ) __attribute__ ( ( interrupt ) );
+
+/*! UART1 interrupt handler prototype */
+void UART1_irq ( void ) __attribute__ ( ( interrupt ) );
+
+/*! UART interrupt service routine.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+*/
+void UART_isr ( uint8_t uart_num ) {
+ if ( i_w[uart_num] > UART_BUFF_LEN - 1 ) i_w[uart_num] = 0; // when buffer is full, start overwriting oldest data
+
+ err_flag[uart_num] = UART_REG_ADDR ( U0LSR, uart_num ) & 0x8E; // check the line status
+
+ if ( ( UART_REG_ADDR ( U0IIR, uart_num ) & RX_MASK ) == RX_INT ) { // if Rx data ready IRQ is pending
+ buff[uart_num][i_w[uart_num]++] = UART_REG_ADDR ( U0RBR, uart_num ); // store new character into the receive buffer
+ new_data_flag[uart_num] = 1; // set the new data flag
+ }
+
+ if ( i_w[uart_num] == i_r[uart_num] ) { // when round buffer is full
+ i_r[uart_num]++; // shift the oldest byte pointer
+ over_flag[uart_num] = 1; // set the data overwrite flag
+ }
+
+ VICVectAddr = 0; // int acknowledge
+}
+
+/*! UART0 Rx interrupt service rutine.
+* This rutine might be modified according user demands.
+*/
+void UART0_irq ( void ) {
+ UART_isr ( UART0 );
+}
+
+/*! UART1 Rx interrupt service rutine.
+* This rutine might be modified according user demands.
+*/
+void UART1_irq ( void ) {
+ UART_isr ( UART1 );
+}
+
+/*! UART initialization function.
+* Takes three arguments:
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \param baud_rate unsigned 32-bit int baud rate in bps
+* \param rx_isr_vect unsigned 32-bit int interrupt vector number
+*/
+void UART_init ( uint8_t uart_num, uint32_t baud_rate, unsigned rx_isr_vect ) {
+
+ uint16_t divisor = (SYSTEM_CLK + (baud_rate * 16)/2) / (baud_rate * 16); // baud divisor computation
+
+
+ PINSEL0 &= ( 0xFFFFFFF0 - ( uart_num * 0xEFFF1 ) ); //enable UART functionality on respective processor pins
+ PINSEL0 |= ( 0x00000005 + ( uart_num * 0x4FFFB ) );
+ UART_REG_ADDR ( U0LCR, uart_num ) = 0x83; // 8-bit data, no parity, set DLAB = 1
+ UART_REG_ADDR ( U0DLL, uart_num ) = *(uint8_t *) &divisor; // write divisor lo-byte
+ UART_REG_ADDR ( U0DLM, uart_num ) = *( ( (uint8_t *) &divisor ) + 1 ); // write divisor hi-byte
+ UART_REG_ADDR ( U0LCR, uart_num ) &= 0x7F; // clear DLAB
+ UART_REG_ADDR ( U0FCR, uart_num ) = 0x01; // enable UART FIFO, interrupt level 1 byte - this might be modified by the user
+ UART_REG_ADDR ( U0IER, uart_num ) = 0x01; // enable RBR interrupt
+
+ if ( !uart_num ) ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART0_irq; // if UART0 register UART0 interrupt handler
+ else ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART1_irq; // else register UART1 interrupt handler
+
+ ( ( uint32_t * ) &VICVectCntl0 )[rx_isr_vect] = 0x20 | ( 6 + uart_num ); // enable IRQ slot, set UART interrupt number
+ VICIntEnable = ( ( uart_num + 1 ) * 0x00000040 ); //enable UART IRQ
+}
+
+/*! Data read function.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns readed character (unsigned 8-bit int).
+*/
+uint8_t read_UART_data ( uint8_t uart_num ) {
+ uint8_t data; // readed data byte
+
+ while ( !new_data_flag[uart_num] ); // wait for new Rx data
+
+ if ( i_r[uart_num] > UART_BUFF_LEN - 1 ) i_r[uart_num] = 0; // when top of the buffer is reached, return the read pointer to 0
+ data = buff[uart_num][i_r[uart_num]++]; // read new data from the data buffer
+ if ( i_r[uart_num] == i_w[uart_num] ) new_data_flag[uart_num] = 0; // when all data was read clear the new data flag
+
+ return data; // return new data byte
+}
+
+/*! Determine possible UART transmission errors.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns error code (0 no errors, -1 UART error, -2 incoming data buffer overrun).
+*/
+int8_t UART_test_err ( uint8_t uart_num ) {
+ if ( err_flag[uart_num] ) { // check the UART0 error flag
+ err_flag[uart_num] = 0; // reset the UART0 error flag
+ return -1; // return error code
+ }
+
+ if ( over_flag[uart_num] ) { // check the UART0 incoming data buffer overrun flag
+ over_flag[uart_num] = 0; // reset the UART0 incoming data buffer overrun flag
+ return -2; // return error code
+ }
+
+ return 0; // no errors
+}
+
+/*! Determine whether new data wait in the UART round buffer.
+* \param uart_num unsigned 8-bit int UART number (0 or 1)
+* \return Returns 1 if there are unreaded data in the incoming data buffer, 0 otherwise.
+*/
+inline uint8_t UART_new_data ( uint8_t uart_num ) {
+ return new_data_flag[uart_num]; // return UART new data flag
+}
+
+/*! Data write function.
+* Takes two arguments:
+* \param uart_num unsigned 8-bit UART number (0 or 1)
+* \param data unsigned 8-bit int byte (character) to send
+*/
+void write_UART_data ( uint8_t uart_num, uint8_t data ) {
+ while ( !( UART_REG_ADDR ( U0LSR, uart_num ) & TX_EMPTY ) ); // wait for the transmitter holding register emptying
+ UART_REG_ADDR ( U0THR, uart_num ) = data; // write the data byte to the transmitter holding register
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+SUBDIRS = lpc21isp tolpc
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+utils_PROGRAMS = lpc21isp
+
+lpc21isp_SOURCES = lpc21isp.c
+
+# Override LOADLIBES from config.target (if specified)
+LOADLIBES=
--- /dev/null
+/******************************************************************************
+
+Project: Portable command line ISP for Philips LPC2000 family
+ and Analog Devices ADUC70xx
+
+Filename: lpc21isp.c
+
+Compiler: Microsoft VC 6/7, GCC Cygwin, GCC Linux
+
+Autor: Martin Maurer (Martin.Maurer@clibb.de)
+
+Copyright: (c) Martin Maurer 2003-2005, All rights reserved
+Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com
+
+Version: 1.27
+
+Change-History:
+
+ 1.00 2004-01-08 Initial Version, tested for MSVC6/7 and GCC under Cygwin
+ 1.01 2004-01-10 Porting to Linux (at least compiling must work)
+ 1.02 2004-01-10 Implemented conversion intel hex format -> binary
+ 1.03 2004-01-25 Preparation to upload to public website
+ 1.04 2004-02-12 Merged in bugfixes by Soeren Gust
+ 1.05 2004-03-14 Implement printing of error codes as text / strings
+ 1.06 2004-03-09 Merged in bugfixes by Charles Manning:
+ The '?' sychronisation does not reliably respond to the first '?'.
+ I added some retries.
+ The LPC2106 sometimes responds to the '?' by echoing them back.
+ This sometimes causes an attempt to match "?Synchonized".
+ Added code to strip off any leading '?'s.
+ Timeouts were too long.
+ Change from RTS/CTS to no flow control.
+ Done because many/most people will use only 3-wire comms.
+ Added some progress tracing.
+ 1.07 2004-03-14 Implement handling of control lines for easier booting
+ 1.08 2004-04-01 Bugfix for upload problem
+ 1.09 2004-04-03 Redesign of upload routine
+ Now always 180 byte blocks are uploaded, to prevent
+ small junks in uuencoding
+ 1.10 2004-04-03 Clear buffers before sending commands to LPC21xx,
+ this prevents synchronizing errors when previously loaded
+ program does a lot of output, so FIFO of PC runs full
+ 1.11 2004-04-03 Small optimization for controlling reset line
+ otherwise termonly starts LPC twice, free PC buffers
+ 1.12 2004-04-04 Add switch to enable logging terminal output to lpc21isp.log
+ 1.13 2004-05-19 Merged in improvement by Charles Manning:
+ Instead of exiting the wrong hex file size is corrected
+ 1.14 2004-07-07 Merged in improvement by Alex Holden:
+ Remove little/big endian dependancy
+ 1.15 2004-09-27 Temporary improvement by Cyril Holweck:
+ Removed test (data echoed = data transmited) on the main
+ data transfert, since this was the biggest failure
+ reason and is covered by checksome anyway.
+ Added COMPILE_FOR_LPC21, to have target dump it's own
+ memory to stdout.
+ 1.16 2004-10-09 Merged in bugfix / improvement by Sinelnikov Evgeny
+ I found out that Linux and Windows serial port initialization
+ are different with pinouts states. My board don't get
+ reset signal at first cycle of DTR pinout moving.
+ And I add this moving to initalization cycle.
+ 1.17 2004-10-21 Changes by Cyril Holweck
+ Divide main, take out the real programming function, that can
+ also be used by a target to copy its own code to another.
+ 1.18 2004-10-26 Changes by Cyril Holweck
+ Added a "G 0 A\r\n" at end of programming to run code.
+ 1.19 2004-11-03 Changes by Robert Adsett
+ Add support for Analog Devices.
+ Separate file load from programming.
+ Change from a debug on/off flag to debug level
+ Remove if(debug) tests and replace with DebugPrintf
+ statements.
+ Change serial I/O and timing so that the system
+ dependancies are isolated to a few portability functions.
+ Add support for binary serial I/O.
+ Add doxygen support.
+ 1.20 2004-11-07 Preparation for multiport booting (factory support)
+ 1.21 2004-11-08 Bugfix from Robert Adsett
+ BinaryLength was not initialized
+ 1.22 2004-11-08 Changes from Cyril Holweck / Evgeny Sinelnikov
+ Forgotten IspEnvironment-> and bugfixes if COMPILE_FOR_LINUX
+ If COMPILE_FOR_LPC21, PhilipsDownload() 'acts as' main():
+ - it should not be static and should return int.
+ - no sub-function can use exit() but only return()
+ Use 'char' instead of 'byte' ;)
+ 1.23 2005-01-16 Build in automatic detection of LPC chiptype
+ (needed for 256 KByte support)
+ 1.24B 2005-06-02 Changes by Thiadmer Riemersma: completed support for other
+ chip types (LPC213x series and others).
+ 1.24C 2005-06-11 Changes by Thiadmer Riemersma: added the device ID codes for
+ chip types LPC2131 and LPC2132.
+ 1.25 2005-06-19 Martin Maurer: Setup more parameters in DCB,
+ otherwise wrong code is downloaded (only Windows and Cygwin)
+ when a previous program has changed these parameters
+ Check exact string of "G 0 A\r\n0\r\n" instead of whole received buffer,
+ to prevent checking of already received by program start
+ (error on running program, but reports CMD_SUCCESS)
+ Add ifdefs for all baudrates (needed only for high baudrate,
+ which seem to be not available on Macs...)
+ 1.26 2005-06-26 Martin Maurer:
+ Correct check again: "G 0 A\r\n0\r\n" is cutted, because of reboot
+ (error on running program, but reports CMD_SUCCESS)
+ 1.27 2005-06-29 Martin Maurer:
+ Add LPC chip ID's (thanks to Robert from Philips) for
+ missing LPC213x and upcoming new LPC214x chips
+ (currently untested, because i don't have access to these chips,
+ please give me feedback !)
+
+******************************************************************************/
+
+#define VERSION_STR "1.27"
+
+#if defined(_WIN32) && !defined(__CYGWIN__)
+ #define COMPILE_FOR_WINDOWS
+ #define COMPILED_FOR ("Windows")
+#elif defined(__CYGWIN__)
+ #define COMPILE_FOR_CYGWIN
+ #define COMPILED_FOR ("Cygwin")
+#elif defined(__arm__) || defined(__thumb__)
+ #define COMPILE_FOR_LPC21
+ #define COMPILED_FOR ("ARM")
+ #define printf iprintf
+#else
+ #define COMPILE_FOR_LINUX
+ #define COMPILED_FOR ("Linux")
+#endif
+
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+#include <windows.h>
+#include <io.h>
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_WINDOWS
+#include <conio.h>
+#endif // defined COMPILE_FOR_WINDOWS
+
+#if defined COMPILE_FOR_LINUX
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <string.h>
+#include <strings.h>
+#include <sys/ioctl.h>
+#endif // defined COMPILE_FOR_LINUX
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+#include <termios.h>
+#include <unistd.h> // for read and return value of lseek
+#include <sys/time.h> // for select_time
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+
+#include <ctype.h> // isdigit()
+#include <stdio.h> // stdout
+#include <stdarg.h>
+#include <time.h>
+
+#if defined COMPILE_FOR_LPC21
+#include <stdlib.h>
+#include <string.h>
+#include "lpc_ioctl.h"
+#endif
+
+#if !defined COMPILE_FOR_LPC21
+#include <fcntl.h>
+#endif
+
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif // O_BINARY
+
+#ifndef DWORD
+#define DWORD unsigned long
+#endif // DWORD
+
+#if defined COMPILE_FOR_LINUX
+#define stricmp strcasecmp
+#endif // defined COMPILE_FOR_LINUX
+
+typedef unsigned char BINARY; /**< data type used for microcontroller
+ * memory image. */
+
+/*
+debug levels
+0 - very quiet - Nothing gets printed at this level
+1 - quiet - Only error messages should be printed
+2 - indicate progress - Add progress messages
+3 - first level debug - Major level tracing
+4 - second level debug - Add detailed debugging
+5 - log comm's - log serial I/O
+*/
+
+typedef enum
+{
+ PHILIPS_ARM,
+ ANALOG_DEVICES_ARM
+} TARGET;
+
+typedef struct
+{
+ unsigned long id;
+ unsigned Product;
+ unsigned FlashSize; /* in kiB, for informational purposes only */
+ unsigned RAMSize; /* in kiB, for informational purposes only */
+ unsigned FlashSectors; /* total number of sectors */
+ unsigned MaxCopySize; /* maximum size that can be copied to Flash in a single command */
+ int *SectorTable; /* pointer to a sector table with the sector sizes */
+} LPC_DEVICE_TYPE;
+
+typedef struct
+{
+
+#if !defined COMPILE_FOR_LPC21
+ TARGET micro; /**< The type of micro that will be
+ * programmed. */
+ int debug_level;
+ unsigned char TerminalAfterUpload;
+ unsigned char TerminalOnly;
+ unsigned char DetectOnly;
+ int DetectedDevice; /* index in LPCtypes[] array */
+ unsigned char FormatHex;
+ unsigned char ControlLines;
+ unsigned char LogFile;
+ char *input_file; /**< Name of the file to get input from. */
+ char *serial_port; /**< Name of the serial port to use to
+ * communicate with the microcontroller.
+ * Read from the command line. */
+ char *baud_rate; /**< Baud rate to use on the serial
+ * port communicating with the
+ * microcontroller. Read from the
+ * command line. */
+#endif // !defined COMPILE_FOR_LPC21
+
+ char *StringOscillator; /**< Holds representation of oscillator
+ * speed from the command line. */
+ BINARY *BinaryContent; /**< Binary image of the */
+ /* microcontroller's memory. */
+ unsigned long BinaryLength;
+
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+ HANDLE hCom;
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_LPC21
+ int fdCom;
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_LPC21
+
+#if defined COMPILE_FOR_LINUX
+ struct termios oldtio, newtio;
+#endif // defined COMPILE_FOR_LINUX
+
+ unsigned serial_timeout_count; /**< Local used to track
+ * timeouts on serial port read. */
+
+} ISP_ENVIRONMENT;
+
+static int debug_level = 2;
+
+static void DumpString(int level, const void *s, size_t size, const char *fmt, ...);
+static void SendComPort(ISP_ENVIRONMENT *IspEnvironment, const char *s);
+static void ReceiveComPort(ISP_ENVIRONMENT *IspEnvironment, void *Answer, unsigned long MaxSize, unsigned long *RealSize, unsigned long WantedNr0x0A,unsigned timeOutMilliseconds);
+static void DebugPrintf( int level, const char *fmt, ...);
+static void PhilipsOutputErrorMessage(unsigned char ErrorNumber);
+static unsigned char GetErrorNumber(const char *Answer);
+static void SerialTimeoutSet(ISP_ENVIRONMENT *IspEnvironment, unsigned timeout_milliseconds);
+static void SerialTimeoutTick(ISP_ENVIRONMENT *IspEnvironment);
+static int SerialTimeoutCheck(ISP_ENVIRONMENT *IspEnvironment);
+
+#if !defined COMPILE_FOR_LPC21
+static void ClearSerialPortBuffers(ISP_ENVIRONMENT *IspEnvironment);
+static void ControlModemLines(ISP_ENVIRONMENT *IspEnvironment, unsigned char DTR, unsigned char RTS);
+static unsigned char Ascii2Hex(unsigned char c);
+#endif
+
+static int SectorTable_210x[] = { 8192, 8192, 8192, 8192, 8192, 8192, 8192, 8192,
+ 8192, 8192, 8192, 8192, 8192, 8192, 8192 };
+static int SectorTable_211x[] = { 8192, 8192, 8192, 8192, 8192, 8192, 8192, 8192,
+ 8192, 8192, 8192, 8192, 8192, 8192, 8192, };
+static int SectorTable_212x[] = { 8192, 8192, 8192, 8192, 8192, 8192, 8192, 8192,
+ 65536, 65536, 8192, 8192, 8192, 8192, 8192, 8192,
+ 8192 };
+static int SectorTable_213x[] = { 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096,
+ 32768, 32768, 32768, 32768, 32768, 32768, 32768, 32768,
+ 32768, 32768, 32768, 32768, 32768, 32768, 4096, 4096,
+ 4096, 4096, 4096 };
+static LPC_DEVICE_TYPE LPCtypes[] =
+{
+ { 0, 0, 0 }, /* unknown */
+ { 0xFFF0FF12, 2104, 128, 16, 15, 8192, SectorTable_210x },
+ { 0xFFF0FF22, 2105, 128, 32, 15, 8192, SectorTable_210x },
+ { 0xFFF0FF32, 2106, 128, 64, 15, 8192, SectorTable_210x },
+ { 0x0101FF12, 2114, 128, 16, 15, 8192, SectorTable_211x },
+ { 0x0201FF12, 2119, 128, 16, 15, 8192, SectorTable_211x },
+ { 0x0101FF13, 2124, 256, 16, 17, 8192, SectorTable_212x },
+ { 0x0201FF13, 2129, 256, 16, 17, 8192, SectorTable_212x },
+ { 0x0002FF01, 2131, 32, 8, 8, 4096, SectorTable_213x },
+ { 0x0002FF11, 2132, 64, 16, 9, 4096, SectorTable_213x },
+ { 0x0002FF12, 2134, 128, 16, 11, 4096, SectorTable_213x },
+ { 0x0002FF23, 2136, 256, 32, 15, 4096, SectorTable_213x },
+ { 0x0002FF25, 2138, 512, 32, 27, 4096, SectorTable_213x },
+ { 0x0402FF01, 2141, 32, 8, 8, 4096, SectorTable_213x },
+ { 0x0402FF11, 2142, 64, 16, 9, 4096, SectorTable_213x },
+ { 0x0402FF12, 2144, 128, 16, 11, 4096, SectorTable_213x },
+ { 0x0402FF23, 2146, 256, 40, 15, 4096, SectorTable_213x },
+ { 0x0402FF25, 2148, 512, 40, 27, 4096, SectorTable_213x },
+ { 0x0301FF13, 2194, 256, 16, 0, 8192, SectorTable_212x },
+ { 0x0301FF12, 2210, 0, 16, 0, 8192, SectorTable_211x }, /* table is a "don't care" */
+ { 0x0401FF12, 2212, 128, 16, 15, 8192, SectorTable_211x },
+ { 0x0601FF13, 2214, 256, 16, 17, 8192, SectorTable_212x },
+ /* 2290; same id as the LPC2210 */
+ { 0x0401FF13, 2292, 256, 16, 0, 8192, SectorTable_212x },
+ { 0x0501FF13, 2294, 256, 16, 0, 8192, SectorTable_212x },
+};
+
+/************* Portability layer. Serial and console I/O differences */
+/* are taken care of here. */
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+static int kbhit( void);
+static int getch( void);
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX
+static void Sleep(unsigned long MilliSeconds);
+#endif // defined COMPILE_FOR_LINUX
+
+
+
+#if !defined COMPILE_FOR_LPC21
+static void OpenSerialPort(ISP_ENVIRONMENT *IspEnvironment)
+{
+ // Open COM-Port (different between Windows and Linux)
+
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+ DCB dcb;
+ COMMTIMEOUTS commtimeouts;
+
+ IspEnvironment->hCom = CreateFile(IspEnvironment->serial_port, GENERIC_READ | GENERIC_WRITE,0,NULL,OPEN_EXISTING,FILE_ATTRIBUTE_NORMAL,NULL);
+
+ if(IspEnvironment->hCom == INVALID_HANDLE_VALUE)
+ {
+ DebugPrintf( 1, "Can't open COM-Port %s ! - Error: %ld\n", IspEnvironment->serial_port, GetLastError());
+ exit(2);
+ }
+
+ DebugPrintf( 3, "COM-Port %s opened...\n", IspEnvironment->serial_port);
+
+ GetCommState(IspEnvironment->hCom, &dcb);
+ dcb.BaudRate = atol(IspEnvironment->baud_rate);
+ dcb.ByteSize = 8;
+ dcb.StopBits = ONESTOPBIT;
+ dcb.Parity = NOPARITY;
+ dcb.fDtrControl = DTR_CONTROL_DISABLE;
+ dcb.fOutX = FALSE;
+ dcb.fInX = FALSE;
+ dcb.fNull = FALSE;
+ dcb.fRtsControl = RTS_CONTROL_DISABLE;
+ if(SetCommState(IspEnvironment->hCom, &dcb) == 0)
+ {
+ DebugPrintf( 1, "Can't set baudrate %s ! - Error: %ld", IspEnvironment->baud_rate, GetLastError());
+ exit(3);
+ }
+
+ SetCommMask(IspEnvironment->hCom,EV_RXCHAR | EV_TXEMPTY);
+
+ commtimeouts.ReadIntervalTimeout = MAXDWORD;
+ commtimeouts.ReadTotalTimeoutMultiplier = 0;
+ commtimeouts.ReadTotalTimeoutConstant = 1;
+ commtimeouts.WriteTotalTimeoutMultiplier = 0;
+ commtimeouts.WriteTotalTimeoutConstant = 0;
+ SetCommTimeouts(IspEnvironment->hCom, &commtimeouts);
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX
+
+ IspEnvironment->fdCom = open(IspEnvironment->serial_port, O_RDWR | O_NOCTTY | O_NONBLOCK );
+
+ if(IspEnvironment->fdCom < 0)
+ {
+ DebugPrintf( 1, "Can't open COM-Port %s !\n", IspEnvironment->serial_port);
+ exit(2);
+ }
+
+ DebugPrintf( 3, "COM-Port %s opened...\n", IspEnvironment->serial_port);
+
+ /* clear input & output buffers, then switch to "blocking mode" */
+ tcflush(IspEnvironment->fdCom, TCOFLUSH);
+ tcflush(IspEnvironment->fdCom, TCIFLUSH);
+ fcntl(IspEnvironment->fdCom, F_SETFL, fcntl(IspEnvironment->fdCom, F_GETFL) & ~O_NONBLOCK);
+
+ tcgetattr(IspEnvironment->fdCom, &IspEnvironment->oldtio); /* save current port settings */
+
+ bzero(&IspEnvironment->newtio, sizeof(IspEnvironment->newtio));
+ IspEnvironment->newtio.c_cflag = CS8 | CLOCAL | CREAD;
+
+ switch(atol(IspEnvironment->baud_rate))
+ {
+#ifdef B1152000
+ case 1152000: IspEnvironment->newtio.c_cflag |= B1152000; break;
+#endif // B1152000
+#ifdef B576000
+ case 576000: IspEnvironment->newtio.c_cflag |= B576000; break;
+#endif // B576000
+#ifdef B230400
+ case 230400: IspEnvironment->newtio.c_cflag |= B230400; break;
+#endif // B230400
+#ifdef B115200
+ case 115200: IspEnvironment->newtio.c_cflag |= B115200; break;
+#endif // B115200
+#ifdef B57600
+ case 57600: IspEnvironment->newtio.c_cflag |= B57600; break;
+#endif // B57600
+#ifdef B38400
+ case 38400: IspEnvironment->newtio.c_cflag |= B38400; break;
+#endif // B38400
+#ifdef B19200
+ case 19200: IspEnvironment->newtio.c_cflag |= B19200; break;
+#endif // B19200
+#ifdef B9600
+ case 9600: IspEnvironment->newtio.c_cflag |= B9600; break;
+#endif // B9600
+#ifdef B4800
+ case 4800: IspEnvironment->newtio.c_cflag |= B4800; break;
+#endif // B4800
+#ifdef B2400
+ case 2400: IspEnvironment->newtio.c_cflag |= B2400; break;
+#endif // B2400
+#ifdef B1200
+ case 1200: IspEnvironment->newtio.c_cflag |= B1200; break;
+#endif // B1200
+#ifdef B600
+ case 600: IspEnvironment->newtio.c_cflag |= B600; break;
+#endif // B600
+#ifdef B300
+ case 300: IspEnvironment->newtio.c_cflag |= B300; break;
+#endif // B300
+ default:
+ {
+ DebugPrintf( 1, "unknown baudrate %s\n", IspEnvironment->baud_rate);
+ exit(3);
+ }
+ }
+
+ IspEnvironment->newtio.c_iflag = IGNPAR | IGNBRK | IXON | IXOFF;
+ IspEnvironment->newtio.c_oflag = 0;
+
+ /* set input mode (non-canonical, no echo,...) */
+ IspEnvironment->newtio.c_lflag = 0;
+
+ cfmakeraw(&IspEnvironment->newtio);
+ IspEnvironment->newtio.c_cc[VTIME] = 1; /* inter-character timer used */
+ IspEnvironment->newtio.c_cc[VMIN] = 0; /* blocking read until 0 chars received */
+
+ tcflush(IspEnvironment->fdCom, TCIFLUSH);
+ tcsetattr(IspEnvironment->fdCom, TCSANOW, &IspEnvironment->newtio);
+
+#endif // defined COMPILE_FOR_LINUX
+}
+
+static void CloseSerialPort(ISP_ENVIRONMENT *IspEnvironment)
+{
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ CloseHandle(IspEnvironment->hCom);
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX
+
+ tcflush(IspEnvironment->fdCom, TCOFLUSH);
+ tcflush(IspEnvironment->fdCom, TCIFLUSH);
+ tcsetattr(IspEnvironment->fdCom, TCSANOW, &IspEnvironment->oldtio);
+
+ close(IspEnvironment->fdCom);
+
+#endif // defined COMPILE_FOR_LINUX
+}
+
+#endif // !defined COMPILE_FOR_LPC21
+
+/***************************** SendComPortBlock *************************/
+/** Sends a block of bytes out the opened com port.
+\param [in] s block to send.
+\param [in] n size of the block.
+*/
+static void SendComPortBlock(ISP_ENVIRONMENT *IspEnvironment, const void *s, size_t n)
+{
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ unsigned long realsize;
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ DumpString( 4, s, n, "Sending ");
+
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ WriteFile(IspEnvironment->hCom, s, n, &realsize, NULL);
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_LPC21
+
+ write(IspEnvironment->fdCom, s, n);
+
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_LPC21
+}
+
+/***************************** SendComPort ******************************/
+/** Sends a string out the opened com port.
+\param [in] s string to send.
+*/
+static void SendComPort(ISP_ENVIRONMENT *IspEnvironment, const char *s)
+{
+ SendComPortBlock( IspEnvironment, s, strlen(s));
+}
+
+
+/***************************** ReceiveComPortBlock **********************/
+/** Receives a buffer from the open com port. Returns all the characters
+ready (waits for up to 'n' milliseconds before accepting that no more
+characters are ready) or when the buffer is full. 'n' is system dependant,
+see SerialTimeout routines.
+\param [out] answer buffer to hold the bytes read from the serial port.
+\param [in] max_size the size of buffer pointed to by answer.
+\param [out] real_size pointer to a long that returns the amout of the
+buffer that is actually used.
+*/
+static void ReceiveComPortBlock( ISP_ENVIRONMENT *IspEnvironment,
+ void *answer, unsigned long max_size,
+ unsigned long *real_size)
+{
+
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ ReadFile(IspEnvironment->hCom, answer, max_size, real_size, NULL);
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_LPC21
+
+ *real_size = read(IspEnvironment->fdCom, answer, max_size);
+
+#endif // defined COMPILE_FOR_LINUX
+
+
+ DumpString( 5, answer, (*real_size), "Read(Length=%ld): ", (*real_size));
+
+ if( *real_size == 0)
+ {
+ SerialTimeoutTick( IspEnvironment );
+ }
+}
+
+
+/***************************** SerialTimeoutSet *************************/
+/** Sets (or resets) the timeout to the timout period requested. Starts
+counting to this period. This timeout support is a little odd in that the
+timeout specifies the accumulated deadtime waiting to read not the total
+time waiting to read. They should be close enought to the same for this
+use. Used by the serial input routines, the actual counting takes place in
+ReceiveComPortBlock.
+\param [in] timeout_milliseconds the time in milliseconds to use for
+timeout. Note that just because it is set in milliseconds doesn't mean
+that the granularity is that fine. In many cases (particularly Linux) it
+will be coarser.
+*/
+static void SerialTimeoutSet(ISP_ENVIRONMENT *IspEnvironment, unsigned timeout_milliseconds)
+{
+
+#if defined COMPILE_FOR_LINUX
+ IspEnvironment->serial_timeout_count = timeout_milliseconds/100;
+#elif defined COMPILE_FOR_LPC21
+ IspEnvironment->serial_timeout_count = timeout_milliseconds*200;
+#else
+ IspEnvironment->serial_timeout_count = timeout_milliseconds;
+#endif
+}
+
+/***************************** SerialTimeoutTick ************************/
+/** Performs a timer tick. In this simple case all we do is count down
+with protection against underflow and wrapping at the low end.
+*/
+static void SerialTimeoutTick(ISP_ENVIRONMENT *IspEnvironment)
+{
+ if( IspEnvironment->serial_timeout_count <= 1)
+ {
+ IspEnvironment->serial_timeout_count = 0;
+ }
+ else
+ {
+ IspEnvironment->serial_timeout_count--;
+ }
+}
+
+/***************************** SerialTimeoutCheck ***********************/
+/** Check to see if the serial timeout timer has run down.
+\retval 1 if timer has run out.
+\retval 0 if timer still has time left.
+*/
+static int SerialTimeoutCheck(ISP_ENVIRONMENT *IspEnvironment)
+{
+ if( IspEnvironment->serial_timeout_count == 0)
+ {
+ return 1;
+ }
+ return 0;
+}
+
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+/***************************** getch ************************************/
+/** Replacement for the common dos function of the same name. Reads a
+single unbuffered character from the 'keyboard'.
+\return The character read from the keyboard.
+*/
+static int getch(void)
+{
+ char ch;
+ struct termios origtty, tty;
+
+ /* store the current tty settings */
+ tcgetattr(0, &origtty);
+
+ /* start with the current settings */
+ tty = origtty;
+ /* make modifications to put it in raw mode, turn off echo */
+ tty.c_lflag &= ~ICANON;
+ tty.c_lflag &= ~ECHO;
+ tty.c_lflag &= ~ISIG;
+ tty.c_cc[VMIN] = 1;
+ tty.c_cc[VTIME] = 0;
+
+ /* put the settings into effect */
+ tcsetattr(0, TCSADRAIN, &tty);
+
+ /* Read in one character */
+ read(0,&ch,1);
+
+ /* reset the tty to its original settings */
+ tcsetattr(0, TCSADRAIN, &origtty);
+
+ return ch;
+}
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+
+#if defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+/***************************** kbhit ************************************/
+/** Replacement for the common dos function of the same name. Indicates if
+there are characters to be read from the console.
+\retval 0 No characters ready.
+\retval 1 Characters from the console ready to be read.
+*/
+static int kbhit(void)
+{
+ /* return 0 for no key pressed, 1 for key pressed */
+ int return_value = 0;
+
+ /* variables to store the current tty state, create a new one */
+ struct termios origtty, tty;
+ /* time struct for the select() function, to only wait a little while */
+ struct timeval select_time;
+ /* file descriptor variable for the select() call */
+ fd_set readset;
+
+ /* we're only interested in STDIN */
+ FD_ZERO(&readset);
+ FD_SET(STDIN_FILENO, &readset);
+
+ /* store the current tty settings */
+ tcgetattr(0, &origtty);
+
+ /* start with the current settings */
+ tty = origtty;
+ /* make modifications to put it in raw mode, turn off echo */
+ tty.c_lflag &= ~ICANON;
+ tty.c_lflag &= ~ECHO;
+ tty.c_lflag &= ~ISIG;
+ tty.c_cc[VMIN] = 1;
+ tty.c_cc[VTIME] = 0;
+
+ /* put the settings into effect */
+ tcsetattr(0, TCSADRAIN, &tty);
+
+ /* how long to block for - this must be > 0.0, but could be changed
+ to some other setting. 10-18msec seems to work well and only
+ minimally load the system (0% CPU loading) */
+ select_time.tv_sec = 0;
+ select_time.tv_usec = 10;
+
+ /* is there a keystroke there? */
+ if (select(1, &readset, NULL, NULL, &select_time))
+ {
+ /* yes, remember it */
+ return_value = 1;
+ }
+
+ /* reset the tty to its original settings */
+ tcsetattr(0, TCSADRAIN, &origtty);
+
+ /* return with what we found out */
+ return return_value;
+}
+#endif // defined COMPILE_FOR_LINUX || defined COMPILE_FOR_CYGWIN
+
+
+#if !defined COMPILE_FOR_LPC21
+/***************************** ControlModemLines ************************/
+/** Controls the modem lines to place the microcontroller into various
+states during the programming process.
+error rather abruptly terminates the program.
+\param [in] DTR the state to set the DTR line to.
+\param [in] RTS the state to set the RTS line to.
+*/
+static void ControlModemLines(ISP_ENVIRONMENT *IspEnvironment, unsigned char DTR, unsigned char RTS)
+{
+#if defined COMPILE_FOR_LINUX
+ int status;
+
+ if(ioctl(IspEnvironment->fdCom, TIOCMGET, &status) == 0)
+ {
+ DebugPrintf( 1, "ioctl get ok, status = %X\n",status);
+ }
+ else
+ {
+ DebugPrintf( 1, "ioctl get failed\n");
+ }
+
+ if(DTR) status |= TIOCM_DTR;
+ else status &= ~TIOCM_DTR;
+
+ if(RTS) status |= TIOCM_RTS;
+ else status &= ~TIOCM_RTS;
+
+ if(ioctl(IspEnvironment->fdCom, TIOCMSET, &status) == 0)
+ {
+ DebugPrintf( 1, "ioctl set ok, status = %X\n",status);
+ }
+ else
+ {
+ DebugPrintf( 1, "ioctl set failed\n");
+ }
+
+ if(ioctl(IspEnvironment->fdCom, TIOCMGET, &status) == 0)
+ {
+ DebugPrintf( 1, "ioctl get ok, status = %X\n",status);
+ }
+ else
+ {
+ DebugPrintf( 1, "ioctl get failed\n");
+ }
+
+#endif // defined COMPILE_FOR_LINUX
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ if(DTR) EscapeCommFunction(IspEnvironment->hCom, SETDTR);
+ else EscapeCommFunction(IspEnvironment->hCom, CLRDTR);
+
+ if(RTS) EscapeCommFunction(IspEnvironment->hCom, SETRTS);
+ else EscapeCommFunction(IspEnvironment->hCom, CLRRTS);
+
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+
+ DebugPrintf( 3, "DTR (%d), RTS (%d)\n", DTR, RTS);
+}
+
+
+/***************************** ClearSerialPortBuffers********************/
+/** Empty the serial port buffers. Cleans things to a known state.
+*/
+static void ClearSerialPortBuffers(ISP_ENVIRONMENT *IspEnvironment)
+{
+#if defined COMPILE_FOR_LINUX
+ /* variables to store the current tty state, create a new one */
+ struct termios origtty, tty;
+
+ /* store the current tty settings */
+ tcgetattr(IspEnvironment->fdCom, &origtty);
+
+ // Flush input and output buffers
+ tcsetattr(IspEnvironment->fdCom, TCSAFLUSH, &tty);
+
+ /* reset the tty to its original settings */
+ tcsetattr(IspEnvironment->fdCom, TCSADRAIN, &origtty);
+#endif // defined COMPILE_FOR_LINUX
+#if defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+ PurgeComm(IspEnvironment->hCom, PURGE_TXABORT | PURGE_RXABORT | PURGE_TXCLEAR | PURGE_RXCLEAR);
+#endif // defined COMPILE_FOR_WINDOWS || defined COMPILE_FOR_CYGWIN
+}
+#endif // !defined COMPILE_FOR_LPC21
+
+
+#if defined COMPILE_FOR_LINUX
+/***************************** Sleep ************************************/
+/** Provide linux replacement for windows function.
+\param [in] Milliseconds the time to wait for in milliseconds.
+*/
+static void Sleep(unsigned long MilliSeconds)
+{
+ usleep(MilliSeconds*1000); //convert to microseconds
+}
+#endif // defined COMPILE_FOR_LINUX
+
+
+/************* Applicationlayer. */
+
+/***************************** DebugPrintf ******************************/
+/** Prints a debug string depending the current debug level. The higher
+the debug level the more detail that will be printed. Each print
+has an associated level, the higher the level the more detailed the
+debugging information being sent.
+\param [in] level the debug level of the print statement, if the level
+ is less than or equal to the current debug level it will be printed.
+\param [in] fmt a standard printf style format string.
+\param [in] ... the usual printf parameters.
+*/
+static void DebugPrintf( int level, const char *fmt, ...)
+{
+ va_list ap;
+
+ if( level <= debug_level)
+ {
+ va_start( ap, fmt);
+ vprintf( fmt, ap);
+ va_end( ap);
+ fflush( stdout);
+ }
+}
+
+/***************************** ReceiveComPort ***************************/
+/** Receives a buffer from the open com port. Returns when the buffer is
+filled, the numer of requested linefeeds has been received or the timeout
+period has passed
+\param [in] ISPEnvironment.
+\param [out] Answer buffer to hold the bytes read from the serial port.
+\param [in] MaxSize the size of buffer pointed to by Answer.
+\param [out] RealSize pointer to a long that returns the amout of the
+buffer that is actually used.
+\param [in] WantedNr0x0A the maximum number of linefeeds to accept before
+returning.
+\param [in] timeOutMilliseconds the maximum amount of time to wait before
+reading with an incomplete buffer.
+*/
+static void ReceiveComPort( ISP_ENVIRONMENT *IspEnvironment,
+ void *Ans, unsigned long MaxSize,
+ unsigned long *RealSize, unsigned long WantedNr0x0A,
+ unsigned timeOutMilliseconds)
+{
+ unsigned long tmp_realsize;
+ unsigned long nr_of_0x0A = 0;
+ int eof = 0;
+ unsigned long p;
+ char *Answer;
+
+ Answer = Ans;
+
+ SerialTimeoutSet( IspEnvironment, timeOutMilliseconds);
+
+ (*RealSize) = 0;
+
+ do
+ {
+ ReceiveComPortBlock( IspEnvironment, Answer + (*RealSize), MaxSize - 1 - (*RealSize), &tmp_realsize);
+
+ if(tmp_realsize != 0)
+ {
+ for(p = (*RealSize); p < (*RealSize) + tmp_realsize; p++)
+ {
+ if(Answer[p] == 0x0a)
+ {
+ nr_of_0x0A++;
+ }
+ else if(Answer[p] < 0)
+ {
+ eof = 1;
+ }
+ }
+ }
+
+ (*RealSize) += tmp_realsize;
+
+ } while(((*RealSize) < MaxSize) && (SerialTimeoutCheck(IspEnvironment) == 0) && (nr_of_0x0A < WantedNr0x0A) && !eof);
+
+ Answer[(*RealSize)] = 0;
+
+ DumpString( 3, Answer, (*RealSize), "Answer(Length=%ld): ", (*RealSize));
+}
+
+
+#if !defined COMPILE_FOR_LPC21
+
+/***************************** ReceiveComPortBlockComplete **************/
+/** Receives a fixed block from the open com port. Returns when the
+block is completely filled or the timeout period has passed
+\param [out] block buffer to hold the bytes read from the serial port.
+\param [in] size the size of the buffer pointed to by block.
+\param [in] timeOut the maximum amount of time to wait before guvung up on
+completing the read.
+\return 0 if successful, non-zero otherwise.
+*/
+static int ReceiveComPortBlockComplete( ISP_ENVIRONMENT *IspEnvironment,
+ void *block, size_t size, unsigned timeout)
+{
+ unsigned long realsize = 0, read;
+ char *result;
+
+ result = block;
+
+ SerialTimeoutSet( IspEnvironment, timeout);
+
+ do
+ {
+ ReceiveComPortBlock( IspEnvironment, result + realsize, size - realsize, &read);
+
+ realsize += read;
+
+ } while((realsize < size) && (SerialTimeoutCheck(IspEnvironment) == 0));
+
+ DumpString( 3, result, realsize, "Answer(Length=%ld): ", realsize);
+
+ if( realsize != size)
+ {
+ return 1;
+ }
+ return 0;
+}
+
+/***************************** ReadArguments ****************************/
+/** Reads the command line arguments and parses it for the various
+options. Uses the same arguments as main. Used to separate the command
+line parsing from main and improve its readability. This should also make
+it easier to modify the command line parsing in the future.
+\param [in] argc the number of arguments.
+\param [in] argv an array of pointers to the arguments.
+*/
+static void ReadArguments(ISP_ENVIRONMENT *IspEnvironment, int argc, char *argv[])
+{
+ int i;
+
+ if(argc >= 5)
+ {
+ for(i = 1; i < argc - 4; i++)
+ {
+ if(stricmp(argv[i], "-bin") == 0)
+ {
+ IspEnvironment->FormatHex = 0;
+ DebugPrintf( 3, "Binary format file input.\n");
+ }
+ else if(stricmp(argv[i], "-hex") == 0)
+ {
+ IspEnvironment->FormatHex = 1;
+ DebugPrintf( 3, "Hex format file input.\n");
+ }
+ else if(stricmp(argv[i], "-term") == 0)
+ {
+ IspEnvironment->TerminalAfterUpload = 1;
+ DebugPrintf( 3, "Invoke terminal after upload.\n");
+ }
+ else if(stricmp(argv[i], "-termonly") == 0)
+ {
+ IspEnvironment->TerminalOnly = 1;
+ DebugPrintf( 3, "Only provide terminal.\n");
+ }
+ else if(stricmp(argv[i], "-detectonly") == 0)
+ {
+ IspEnvironment->DetectOnly = 1;
+ DebugPrintf( 3, "Only detect LPC chip part id.\n");
+ }
+ else if(stricmp(argv[i], "-debug") == 0)
+ {
+ debug_level = 4;
+ DebugPrintf( 3, "Turn on debug.\n");
+ }
+ else if(stricmp(argv[i], "-control") == 0)
+ {
+ IspEnvironment->ControlLines = 1;
+ DebugPrintf( 3, "Use RTS/DTS to control target state.\n");
+ }
+ else if(stricmp(argv[i], "-logfile") == 0)
+ {
+ IspEnvironment->LogFile = 1;
+ DebugPrintf( 3, "Log terminal output.\n");
+ }
+ else if( stricmp( argv[i], "-ADARM") == 0)
+ {
+ IspEnvironment->micro = ANALOG_DEVICES_ARM;
+ DebugPrintf( 2, "Target: Analog Devices.\n");
+ }
+ else if( stricmp( argv[i], "-PHILIPSARM") == 0)
+ {
+ IspEnvironment->micro = PHILIPS_ARM;
+ DebugPrintf( 2, "Target: Philips.\n");
+ }
+ else
+ {
+ DebugPrintf( 2, "Unknown command line option: \"%s\"\n", argv[i]);
+ }
+ }
+
+ IspEnvironment->input_file = argv[argc - 1];
+ IspEnvironment->StringOscillator = argv[argc - 2];
+ IspEnvironment->serial_port = argv[argc - 4];
+ IspEnvironment->baud_rate = argv[argc - 3];
+ }
+
+ if(argc < 5)
+ {
+ debug_level = (debug_level < 2) ? 2 : debug_level;
+ }
+
+ if(argc < 5)
+ {
+ DebugPrintf( 2, "\n");
+ DebugPrintf( 2, "Portable command line ISP for Philips LPC2000 family and \n");
+ DebugPrintf( 2, "Version " VERSION_STR " Analog Devices ADUC 70xx\n");
+ DebugPrintf( 2, "Compiled for %s: %s %s\n", COMPILED_FOR, __DATE__, __TIME__);
+ DebugPrintf( 2, "Copyright (c) by Martin Maurer, 2003-2005 Email: Martin.Maurer@clibb.de\n");
+ DebugPrintf( 2, "Portions Copyright (c) by Aeolus Development 2004\n");
+ DebugPrintf( 2, " http://www.aeolusdevelopment.com\n");
+ DebugPrintf( 2, "\n");
+
+ DebugPrintf( 1, "Syntax: lpc21isp [Options] comport baudrate Oscillator_in_kHz file\n\n");
+ DebugPrintf( 1, "Example: lpc21isp test.hex com1 115200 14746\n\n");
+ DebugPrintf( 1, "Options: -bin for uploading binary file\n");
+ DebugPrintf( 1, " -hex for uploading file in intel hex format (default)\n");
+ DebugPrintf( 1, " -term for starting terminal after upload\n");
+ DebugPrintf( 1, " -termonly for starting terminal without an upload\n");
+ DebugPrintf( 1, " -detectonly detect only used LPC chiptype (PHILIPSARM only)\n");
+ DebugPrintf( 1, " -debug for creating a lot of debug infos\n");
+ DebugPrintf( 1, " -control for controlling RS232 lines for easier booting\n");
+ DebugPrintf( 1, " (Reset = DTR, EnableBootLoader = RTS)\n");
+ DebugPrintf( 1, " -logfile for enabling logging of terminal output to lpc21isp.log\n");
+ DebugPrintf( 1, " -ADARM for downloading to an Analog Devices\n");
+ DebugPrintf( 1, " ARM microcontroller ADUC70xx\n");
+ DebugPrintf( 1, " -PHILIPSARM for downloading to a microcontroller from\n");
+ DebugPrintf( 1, " Philips LPC2000 family (default)\n");
+
+ exit(1);
+ }
+
+ if(IspEnvironment->micro == PHILIPS_ARM)
+ {
+ if (strlen(IspEnvironment->StringOscillator) > 5)
+ {
+ printf("Invalid crystal frequency %s",argv[argc - 1]);
+ exit(1);
+ }
+ }
+}
+
+typedef enum
+{
+ PROGRAM_MODE,
+ RUN_MODE
+} TARGET_MODE;
+
+/***************************** ResetTarget ******************************/
+/** Resets the target leaving it in either download (program) mode or
+run mode.
+\param [in] mode the mode to leave the target in.
+*/
+static void ResetTarget( ISP_ENVIRONMENT *IspEnvironment, TARGET_MODE mode)
+{
+
+ if(IspEnvironment->ControlLines)
+ {
+
+ switch( mode)
+ {
+ /* Reset and jump to boot loader. */
+ case PROGRAM_MODE:
+ ControlModemLines(IspEnvironment, 1, 1);
+ Sleep(100);
+ ClearSerialPortBuffers(IspEnvironment);
+ Sleep(100);
+ ControlModemLines(IspEnvironment, 0, 1);
+ Sleep(100);
+ // Clear the RTS line after having reset the micro
+ // Needed for the "GO <Address> <Mode>" ISP command to work */
+ ControlModemLines(IspEnvironment, 0, 0);
+ break;
+
+ /* Reset and start uploaded program */
+ case RUN_MODE:
+ ControlModemLines(IspEnvironment, 1, 0);
+ Sleep(100);
+ ClearSerialPortBuffers(IspEnvironment);
+ Sleep(100);
+ ControlModemLines(IspEnvironment, 0, 0);
+ Sleep(100);
+ break;
+ }
+ }
+}
+
+/***************************** LoadFile *********************************/
+/** Loads the requested file to download into memory.
+\param [in] IspEnvironment structure containing input filename
+*/
+static void LoadFile(ISP_ENVIRONMENT *IspEnvironment)
+{
+ int fd;
+ int i;
+ unsigned long Pos;
+ unsigned long FileLength;
+ BINARY *FileContent; /**< Used to store the content of a hex */
+ /* file before converting to binary. */
+ unsigned long BinaryMemSize;
+
+ fd = open(IspEnvironment->input_file, O_RDONLY | O_BINARY);
+ if(fd == -1)
+ {
+ DebugPrintf( 1, "Can't open file %s\n", IspEnvironment->input_file);
+ exit(1);
+ }
+
+ FileLength = lseek(fd, 0L, 2); // Get file size
+
+ if(FileLength == (size_t)-1)
+ {
+ DebugPrintf( 1, "\nFileLength = -1 !?!\n");
+ exit(1);
+ }
+
+ lseek(fd, 0L, 0);
+
+ FileContent = malloc(FileLength);
+
+ BinaryMemSize = FileLength * 2;
+
+ IspEnvironment->BinaryLength = 0; /* Increase length as needed. */
+
+ IspEnvironment->BinaryContent = malloc(BinaryMemSize);
+
+ read(fd, FileContent, FileLength);
+
+ close(fd);
+
+ DebugPrintf( 2, "File %s:\n\tloaded...\n", IspEnvironment->input_file);
+
+ // Intel-Hex -> Binary Conversion
+
+ if(IspEnvironment->FormatHex != 0)
+ {
+ unsigned char RecordLength;
+ unsigned short RecordAddress;
+ unsigned long RealAddress = 0;
+ unsigned char RecordType;
+ unsigned char Hexvalue;
+
+ DebugPrintf( 3, "Converting file %s to binary format...\n", IspEnvironment->input_file);
+
+ Pos = 0;
+ while(Pos < FileLength)
+ {
+ if(FileContent[Pos] == '\r')
+ {
+ Pos++;
+ continue;
+ }
+
+ if(FileContent[Pos] == '\n')
+ {
+ Pos++;
+ continue;
+ }
+
+ if(FileContent[Pos] != ':')
+ {
+ DebugPrintf( 1, "Missing start of record (':') wrong byte %c / %02X\n", FileContent[Pos], FileContent[Pos]);
+ exit(1);
+ }
+
+ Pos++;
+
+ RecordLength = Ascii2Hex(FileContent[Pos++]);
+ RecordLength <<= 4;
+ RecordLength |= Ascii2Hex(FileContent[Pos++]);
+
+ DebugPrintf( 4, "RecordLength = %02X\n", RecordLength);
+
+ RecordAddress = Ascii2Hex(FileContent[Pos++]);
+ RecordAddress <<= 4;
+ RecordAddress |= Ascii2Hex(FileContent[Pos++]);
+ RecordAddress <<= 4;
+ RecordAddress |= Ascii2Hex(FileContent[Pos++]);
+ RecordAddress <<= 4;
+ RecordAddress |= Ascii2Hex(FileContent[Pos++]);
+
+ DebugPrintf( 4, "RecordAddress = %04X\n", RecordAddress);
+
+ RealAddress = RealAddress - (RealAddress & 0xffff) + RecordAddress;
+
+ DebugPrintf( 4, "RealAddress = %08lX\n", RealAddress);
+
+ RecordType = Ascii2Hex(FileContent[Pos++]);
+ RecordType <<= 4;
+ RecordType |= Ascii2Hex(FileContent[Pos++]);
+
+ DebugPrintf( 4, "RecordType = %02X\n", RecordType);
+
+ if(RecordType == 0x00) // 00 - Data record
+ {
+ // Memory for binary file big enough ?
+ while(RealAddress + RecordLength > BinaryMemSize)
+ {
+ BinaryMemSize <<= 1;
+ IspEnvironment->BinaryContent = realloc(IspEnvironment->BinaryContent, BinaryMemSize);
+ }
+
+ // We need to know, what the highest address is,
+ // how many bytes / sectors we must flash
+ if(RealAddress + RecordLength > IspEnvironment->BinaryLength)
+ {
+ IspEnvironment->BinaryLength = RealAddress + RecordLength;
+ DebugPrintf( 3, "Image size now: %ld\n", IspEnvironment->BinaryLength);
+ }
+
+ for(i = 0; i < RecordLength; i++)
+ {
+ Hexvalue = Ascii2Hex(FileContent[Pos++]);
+ Hexvalue <<= 4;
+ Hexvalue |= Ascii2Hex(FileContent[Pos++]);
+ IspEnvironment->BinaryContent[RealAddress + i] = Hexvalue;
+ }
+ }
+ else if(RecordType == 0x01) // 01 - End of file record
+ {
+ break;
+ }
+ else if(RecordType == 0x02) // 02 - Extended segment address record
+ {
+ for(i = 0; i < RecordLength * 2; i++) // double amount of nibbles
+ {
+ RealAddress <<= 4;
+ if(i == 0)
+ {
+ RealAddress = Ascii2Hex(FileContent[Pos++]);
+ }
+ else
+ {
+ RealAddress |= Ascii2Hex(FileContent[Pos++]);
+ }
+ }
+ RealAddress <<= 4;
+ }
+ else if(RecordType == 0x03) // 03 - Start segment address record
+ {
+ for(i = 0; i < RecordLength * 2; i++) // double amount of nibbles
+ {
+ RealAddress <<= 4;
+ if(i == 0)
+ {
+ RealAddress = Ascii2Hex(FileContent[Pos++]);
+ }
+ else
+ {
+ RealAddress |= Ascii2Hex(FileContent[Pos++]);
+ }
+ }
+ RealAddress <<= 8;
+ }
+ else if(RecordType == 0x04) // 04 - Extended linear address record, used by IAR
+ {
+ DebugPrintf( 1, "RecordType %02X not yet implemented - ignore ?\n", RecordType);
+ // exit(1);
+ }
+ else if(RecordType == 0x05) // 05 - Start linear address record
+ {
+ DebugPrintf( 1, "RecordType %02X not yet implemented\n", RecordType);
+ exit(1);
+ }
+
+ while(FileContent[Pos++] != 0x0a) // Search till line end
+ {
+ }
+ }
+
+ DebugPrintf( 2, "\tconverted to binary format...\n");
+
+ // When debugging is switched on, output result of conversion to file debugout.bin
+ if(debug_level >= 4)
+ {
+ int fdout;
+ fdout = open("debugout.bin", O_RDWR | O_BINARY | O_CREAT | O_TRUNC, 0777);
+ write(fdout, IspEnvironment->BinaryContent, IspEnvironment->BinaryLength);
+ close(fdout);
+ }
+ }
+ else
+ {
+ memcpy(IspEnvironment->BinaryContent, FileContent, FileLength);
+
+ IspEnvironment->BinaryLength = FileLength;
+ }
+
+ DebugPrintf( 2, "\timage size : %ld\n", IspEnvironment->BinaryLength);
+
+ // check length to flash for correct alignment, can happen with broken ld-scripts
+ if (IspEnvironment->BinaryLength % 4 != 0)
+ {
+ unsigned long NewBinaryLength = ((IspEnvironment->BinaryLength + 3)/4) * 4;
+
+ DebugPrintf( 2, "Warning: data not aligned to 32 bits, padded (length was %lX, now %lX)\n", IspEnvironment->BinaryLength, NewBinaryLength);
+
+ IspEnvironment->BinaryLength = NewBinaryLength;
+ }
+
+}
+
+
+#define ANALOG_DEVICES_SYNC_CHAR ((BINARY)0x08)
+#define ANALOG_DEVICES_SYNC_RESPONSE ("ADuC")
+#define ANALOG_DEVICES_SYNC_SIZE (strlen( ANALOG_DEVICES_SYNC_RESPONSE))
+
+typedef struct {
+ BINARY product_id[15];
+ BINARY version[3];
+ BINARY reserved[4];
+ BINARY terminator[2];
+ } AD_SYNC_RESPONSE;
+
+/***************************** AnalogDevicesSync ************************/
+/** Attempt to synchronize with an Analog Device ARM micro. Sends a
+backspace and reads back the microcontrollers response. Performs
+multiple retries. Exits the program on error, returns to caller in the
+case of success.
+*/
+static void AnalogDevicesSync(ISP_ENVIRONMENT *IspEnvironment)
+{
+ BINARY sync; /* Holds sync command. */
+ AD_SYNC_RESPONSE response; /* Response from micro. */
+ int sync_attempts; /* Number of retries. */
+
+ /* Make sure we don't read garbage later instead of the */
+ /* response we expect from the micro. */
+ ClearSerialPortBuffers(IspEnvironment);
+
+ DebugPrintf( 2, "Synchronizing\n"); /* Progress report. */
+
+ sync = ANALOG_DEVICES_SYNC_CHAR; /* Build up sync command. */
+
+ /* Perform the actual sync attempt. First send the sync */
+ /* character, the attempt to read back the response. For the */
+ /* AD ARM micro this is a fixed length block. If response is */
+ /* received attempt to validate it by comparing the first */
+ /* characters to those expected. If the received block does */
+ /* not validate or is incomplete empty the serial buffer and */
+ /* retry. */
+ for(sync_attempts = 0; sync_attempts < 5; sync_attempts++)
+ {
+ SendComPortBlock( IspEnvironment, &sync, 1);
+
+ if( ReceiveComPortBlockComplete( IspEnvironment, &response, sizeof( response),
+ 500) == 0)
+ {
+
+ if( memcmp( response.product_id, ANALOG_DEVICES_SYNC_RESPONSE,
+ ANALOG_DEVICES_SYNC_SIZE) == 0)
+ {
+ return;
+ }
+ else
+ {
+ DumpString( 3, &response, sizeof(response),
+ "Unexpected response to sync attempt ");
+ }
+ }
+ else
+ {
+ DebugPrintf( 3, "No (or incomplete) answer on sync attempt\n");
+ }
+
+ ClearSerialPortBuffers(IspEnvironment);
+ }
+
+ DebugPrintf( 1, "No (or unacceptable) answer on sync attempt\n");
+ exit(4);
+}
+
+typedef struct {
+ char start1;
+ char start2;
+ BINARY bytes;
+ char cmd;
+ BINARY address_h;
+ BINARY address_u;
+ BINARY address_m;
+ BINARY address_l;
+ BINARY data[251];
+ } AD_PACKET;
+
+/***************************** AnalogDevicesFormPacket ******************/
+/** Create an Analog Devices communication packet from the constituent
+elements.
+\param [in] cmd The command being sent, one of 'E' for erase, 'W' for
+write, 'V' for verify or 'R' for run..
+\param [in] no_bytes the number of data bytes to send with the command in
+the packet.
+\param [in] address the address to apply the command to.
+\param [in] data the data to send with the packet, may be null if no_bytes
+is zero.
+\param[out] packet that will be filled.
+*/
+static void AnalogDevicesFormPacket( ISP_ENVIRONMENT *IspEnvironment,
+ char cmd, int no_bytes, unsigned int address,
+ const void *data, AD_PACKET *packet)
+{
+ BINARY checksum;
+ const BINARY *data_in;
+ int i;
+
+ (void)IspEnvironment; /* never used in this function */
+
+ /* Some sanity checking on the arguments. These should only */
+ /* fail if there is a bug in the caller. */
+ /* Check 1) that the number of data bytes is in an acceptable */
+ /* range, 2) that we have a non-null pointer if data is being */
+ /* put in the packet and 3) that we have a non-null pointer to */
+ /* the packet to be filled. We just exit with an error message */
+ /* if any of these tests fail. */
+ if( (no_bytes < 0) || (no_bytes > 250))
+ {
+ DebugPrintf( 1,
+ "The number of bytes (%d) passed to FormPacket is invalid.\n",
+ no_bytes);
+ exit( -1);
+ }
+ if( (data == 0) && (no_bytes != 0))
+ {
+ DebugPrintf( 1,
+ "A null pointer to data paased to FormPacket when data was expected.\n");
+ exit( -1);
+ }
+ if( packet == 0)
+ {
+ DebugPrintf( 1,
+ "A null packet pointer was passed to FormPacket.\n");
+ exit( -1);
+ }
+
+ checksum = 0; /* Checksum starts at zero. */
+
+ data_in = data; /* Pointer pun so we can walk through */
+ /* the data. */
+
+ packet->start1 = 0x7; /* The start of the packet is constant.*/
+ packet->start2 = 0xE;
+
+ /* Fill in the rest of the packet and calculate the checksum */
+ /* as we go. */
+
+ /* The number of bytes is the number of data bytes + the */
+ /* address bytes + the command byte. */
+ packet->bytes = (BINARY)(no_bytes + 5);
+
+ checksum += packet->bytes;
+
+ /* The command for the packet being sent. No error checking */
+ /* done on this. */
+ packet->cmd = cmd;
+
+ checksum += cmd;
+
+ /* Now break up the address and place in the proper packet */
+ /* locations. */
+ packet->address_l = (BINARY)(address & 0xFF);
+ packet->address_m = (BINARY)((address >> 8) & 0xFF);
+ packet->address_u = (BINARY)((address >> 16) & 0xFF);
+ packet->address_h = (BINARY)((address >> 24) & 0xFF);
+
+ checksum += packet->address_l;
+ checksum += packet->address_m;
+ checksum += packet->address_u;
+ checksum += packet->address_h;
+
+ /* Copy the data bytes into the packet. We could use memcpy */
+ /* but we have to calculate the checksum anyway. */
+ for( i = 0; i < no_bytes; i++)
+ {
+ packet->data[i] = data_in[i];
+ checksum += data_in[i];
+ }
+
+ /* Finally, add the checksum to the end of the packet. */
+ packet->data[i] = (BINARY)-checksum;
+}
+
+#define ANALOG_DEVICES_ACK 0x6
+#define ANALOG_DEVICES_NAK 0x7
+
+/***************************** AnalogDevicesSendPacket ******************/
+/** Send a previously form Analog Devices communication. Retry a
+couple of times if needed but fail by exiting the program if no ACK is
+forthcoming.
+\param [in] packet the packet to send.
+*/
+static void AnalogDevicesSendPacket( ISP_ENVIRONMENT *IspEnvironment,
+ const AD_PACKET * packet)
+{
+ BINARY response;
+ int retry = 0;
+
+ do {
+ retry++;
+
+ /* Make sure we don't read garbage later instead of */
+ /* the response we expect from the micro. */
+ ClearSerialPortBuffers(IspEnvironment);
+
+ /* Send the packet, the size is the number of data */
+ /* bytes in the packet plus 3 bytes worth of header */
+ /* plus checksum. */
+ SendComPortBlock( IspEnvironment, packet, packet->bytes + 4);
+
+ /* Receive the response and check, return to caller */
+ /* if successful. */
+ if( ReceiveComPortBlockComplete( IspEnvironment, &response, 1, 500) == 0)
+ {
+ if( response == ANALOG_DEVICES_ACK)
+ {
+ DebugPrintf( 3, "Packet Sent\n");
+ return;
+ }
+ if( response != ANALOG_DEVICES_NAK)
+ {
+ DebugPrintf( 3, "Unexpected response to packet (%x)\n", (int)response);
+ }
+ DebugPrintf( 2, "*");
+ }
+ } while( retry < 3);
+
+ DebugPrintf( 1, "Send packet failed\n");
+ exit( -1);
+}
+
+/***************************** AnalogDevicesErase ***********************/
+/** Erase the Analog Devices micro. We take the simple way out and
+just erase the whole thing.
+*/
+static void AnalogDevicesErase(ISP_ENVIRONMENT *IspEnvironment)
+{
+ BINARY pages;
+ AD_PACKET packet;
+
+ pages = 0;
+ DebugPrintf( 2, "Erasing .. ");
+ AnalogDevicesFormPacket( IspEnvironment, 'E', 1, 0, &pages, &packet);
+ AnalogDevicesSendPacket( IspEnvironment, &packet);
+ DebugPrintf( 2, "Erased\n");
+}
+
+#define AD_PACKET_SIZE (250)
+
+/***************************** AnalogDevicesWrite ***********************/
+/** Write the program.
+\param [in] data the program to download to the micro.
+\param [in] address where to start placing the program.
+\param [in] bytes the size of the progrm to download.
+*/
+static void AnalogDevicesWrite( ISP_ENVIRONMENT *IspEnvironment,
+ const void *data, long address, size_t bytes)
+{
+ AD_PACKET packet;
+ const BINARY *prog_data;
+
+ DebugPrintf( 2, "Writing %d bytes ", bytes);
+ prog_data = data;
+ while( bytes > AD_PACKET_SIZE)
+ {
+ AnalogDevicesFormPacket( IspEnvironment, 'W', AD_PACKET_SIZE, address, prog_data, &packet);
+ AnalogDevicesSendPacket( IspEnvironment, &packet);
+ address += AD_PACKET_SIZE;
+ prog_data += AD_PACKET_SIZE;
+ bytes -= AD_PACKET_SIZE;
+ DebugPrintf( 2, ".");
+ }
+ if( bytes > 0)
+ {
+ AnalogDevicesFormPacket( IspEnvironment, 'W', bytes, address, prog_data, &packet);
+ AnalogDevicesSendPacket( IspEnvironment, &packet);
+ DebugPrintf( 2, ".");
+ }
+}
+
+/***************************** AnalogDevicesDownload ********************/
+/** Perform the download into an Analog Devices micro. As a quick and
+ * dirty hack against flash relocations at 0x80000
+ * \return 0 if ok, error code else
+ * \ToDo: possible to implement the return value instead of calling
+ * exit() in sub-functions
+ */
+static int AnalogDevicesDownload(ISP_ENVIRONMENT *IspEnvironment)
+{
+ AnalogDevicesSync(IspEnvironment);
+ AnalogDevicesErase(IspEnvironment);
+ if( IspEnvironment->BinaryLength > 0x80000)
+ {
+ DebugPrintf( 2, "Note: Flash remapped 0x80000 to 0.\n");
+ AnalogDevicesWrite( IspEnvironment, IspEnvironment->BinaryContent + 0x80000, 0, IspEnvironment->BinaryLength-0x80000);
+ }
+ else
+ {
+ AnalogDevicesWrite( IspEnvironment, IspEnvironment->BinaryContent, 0, IspEnvironment->BinaryLength);
+ }
+ return(0);
+}
+
+/* note -- need to rationalize timeouts, use define?
+similarly for the number of sync attempts
+*/
+
+#endif // !defined COMPILE_FOR_LPC21
+
+
+static int SendAndVerify(ISP_ENVIRONMENT *IspEnvironment, const char *Command,
+ char *AnswerBuffer, int AnswerLength)
+{
+ unsigned long realsize;
+ int cmdlen;
+
+ SendComPort( IspEnvironment, Command);
+ ReceiveComPort( IspEnvironment, AnswerBuffer, AnswerLength-1, &realsize, 2, 5000);
+ cmdlen = strlen(Command);
+ return (strncmp(AnswerBuffer, Command, cmdlen) == 0
+ && strcmp(AnswerBuffer + cmdlen, "0\r\n") == 0);
+}
+
+/***************************** Download *********************************/
+/** Download the file from the internal memory image to the philips microcontroller.
+ * This function is visible from outside if COMPILE_FOR_LPC21
+ */
+#define LPC_RAMBASE 0x40000200L
+#if !defined COMPILE_FOR_LPC21
+static
+#endif
+int PhilipsDownload(ISP_ENVIRONMENT *IspEnvironment)
+{
+ unsigned long realsize;
+ char Answer[128];
+ char temp[128];
+ char *strippedAnswer, *endPtr;
+ int strippedsize;
+ int nQuestionMarks;
+ int found;
+ unsigned long Sector;
+ unsigned long SectorLength;
+ unsigned long SectorStart, SectorOffset, SectorChunk;
+ char tmpString[128];
+ char uuencode_table[64];
+ int Line;
+ unsigned long tmpStringPos;
+ unsigned long BlockOffset;
+ unsigned long Block;
+ unsigned long Pos;
+ unsigned long CopyLength;
+ int c,k=0,i;
+ unsigned long ivt_CRC; // CRC over interrupt vector table
+ unsigned long block_CRC;
+ time_t tStartUpload, tDoneUpload;
+ long WatchDogSeconds = 0;
+ int WaitForWatchDog = 0;
+
+ if(!IspEnvironment->DetectOnly)
+ {
+ // Build up uuencode table
+ uuencode_table[0] = 0x60; // 0x20 is translated to 0x60 !
+
+ for(i = 1; i <= 64; i++)
+ {
+ uuencode_table[i] = (char)(0x20 + i);
+ }
+
+ // Patch 0x14, otherwise it is not running and jumps to boot mode
+
+ ivt_CRC = 0;
+
+ /* Clear the vector at 0x14 so it doesn't affect the checksum: */
+ for(i = 0; i < 4; i++)
+ {
+ IspEnvironment->BinaryContent[i + 0x14] = 0;
+ }
+ /* Calculate a native checksum of the little endian vector table: */
+ for(i = 0; i < (4 * 8);) {
+ ivt_CRC += IspEnvironment->BinaryContent[i++];
+ ivt_CRC += IspEnvironment->BinaryContent[i++] << 8;
+ ivt_CRC += IspEnvironment->BinaryContent[i++] << 16;
+ ivt_CRC += IspEnvironment->BinaryContent[i++] << 24;
+ }
+
+ /* Negate the result and place in the vector at 0x14 as little endian
+ * again. The resulting vector table should checksum to 0. */
+ ivt_CRC = (unsigned long)-ivt_CRC;
+ for(i = 0; i < 4; i++)
+ {
+ IspEnvironment->BinaryContent[i + 0x14] = (unsigned char)(ivt_CRC >> (8 * i));
+ }
+
+ DebugPrintf( 3, "Position 0x14 patched: ivt_CRC = 0x%08lX\n", ivt_CRC);
+ }
+
+ DebugPrintf( 2, "Synchronizing");
+
+ for(nQuestionMarks = found = 0; !found && nQuestionMarks < 100; nQuestionMarks++)
+ {
+ DebugPrintf( 2, ".");
+ SendComPort( IspEnvironment, "?");
+
+ memset(Answer,0,sizeof(Answer));
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 1,100);
+
+ strippedAnswer = Answer;
+ strippedsize = realsize;
+ while((strippedsize > 0) && ((*strippedAnswer == '?') || (*strippedAnswer == 0)))
+ {
+ strippedAnswer++;
+ strippedsize--;
+ }
+
+ DumpString( 3, strippedAnswer, strippedsize, "StrippedAnswer(Length=%ld): '", strippedsize);
+
+ if(strcmp(strippedAnswer, "Bootloader\r\n") == 0 && IspEnvironment->TerminalOnly == 0)
+ {
+ long chars, xtal;
+ unsigned long ticks;
+ chars = (17 * IspEnvironment->BinaryLength + 1) / 10;
+ WatchDogSeconds = (10 * chars + 5) / atol(IspEnvironment->baud_rate) + 10;
+ xtal = atol(IspEnvironment->StringOscillator) * 1000;
+ ticks = (unsigned long)WatchDogSeconds * ((xtal + 15) / 16);
+ DebugPrintf( 2, "Entering ISP; re-synchronizing (watchdog = %ld seconds)\n", WatchDogSeconds);
+ sprintf(temp, "T %lu\r\n", ticks);
+ SendComPort( IspEnvironment, temp);
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 1,100);
+ if(strcmp(Answer, "OK\r\n") != 0)
+ {
+ printf("No answer on 'watchdog timer set'\n");
+ return(4);
+ }
+ SendComPort( IspEnvironment, "G 10356\r\n");
+ Sleep(200);
+ nQuestionMarks = 0;
+ WaitForWatchDog = 1;
+ continue;
+ }
+
+ tStartUpload = time(NULL);
+ if(strcmp(strippedAnswer, "Synchronized\r\n") == 0)
+ {
+ found = 1;
+ }
+#if !defined COMPILE_FOR_LPC21
+ else
+ {
+ ResetTarget(IspEnvironment, PROGRAM_MODE );
+ }
+#endif
+ }
+
+ if(!found)
+ {
+ DebugPrintf( 1, " no answer on '?'\n");
+ return(4);
+ }
+
+ DebugPrintf( 2, " OK\n");
+
+ SendComPort( IspEnvironment, "Synchronized\r\n");
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 2,1000);
+
+ if(strcmp(Answer, "Synchronized\r\nOK\r\n") != 0)
+ {
+ DebugPrintf( 1, "No answer on 'Synchronized'\n");
+ return(4);
+ }
+
+ DebugPrintf( 3, "Synchronized 1\n");
+
+ DebugPrintf( 3, "Setting oscillator\n");
+
+ sprintf( temp, "%s\r\n", IspEnvironment->StringOscillator);
+ SendComPort( IspEnvironment, temp);
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 2,1000);
+
+ sprintf( temp, "%s\r\nOK\r\n", IspEnvironment->StringOscillator);
+
+ if(strcmp(Answer, temp) != 0)
+ {
+ DebugPrintf( 1, "No answer on Oscillator-Command\n");
+ return(4);
+ }
+
+ DebugPrintf( 3, "Unlock\n");
+
+ if (!SendAndVerify(IspEnvironment, "U 23130\r\n", Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Unlock-Command:\n");
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ DebugPrintf( 2, "Read bootcode version: ");
+
+ SendComPort( IspEnvironment, "K\r\n");
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 4,5000);
+
+ if(strncmp(Answer, "K\r\n", 3) != 0)
+ {
+ DebugPrintf( 1, "no answer on Read Boot Code Version\n");
+ return(4);
+ }
+
+ if(strncmp(Answer, "K\r\n0\r\n", 6) == 0)
+ {
+ int maj, min, build;
+ strippedAnswer = Answer + 6;
+ if (sscanf(strippedAnswer, "%d %d %d", &build, &min, &maj) == 2) {
+ maj = min;
+ min = build;
+ build = 0;
+ } /* if */
+ DebugPrintf( 2, "%d.%d.%d\n", maj, min, build);
+ }
+ else
+ {
+ DebugPrintf( 2, "unknown\n");
+ }
+
+ DebugPrintf( 2, "Read part ID: ");
+ SendComPort( IspEnvironment, "J\r\n");
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 3,5000);
+
+ if(strncmp(Answer, "J\r\n", 3) != 0)
+ {
+ DebugPrintf( 1, "no answer on Read Part Id\n");
+ return(4);
+ }
+
+ strippedAnswer = (strncmp(Answer, "J\r\n0\r\n", 6) == 0) ? Answer + 6 : Answer;
+ Pos = strtoul(strippedAnswer, &endPtr, 10);
+ *endPtr = '\0'; /* delete \r\n */
+ for (i = sizeof LPCtypes / sizeof LPCtypes[0] - 1; i > 0 && LPCtypes[i].id != Pos; i--)
+ /* nothing */;
+ IspEnvironment->DetectedDevice = i;
+ if (IspEnvironment->DetectedDevice == 0)
+ DebugPrintf( 2, "unknown");
+ else
+ DebugPrintf( 2, "LPC%d, %d kiB ROM / %d kiB SRAM",
+ LPCtypes[IspEnvironment->DetectedDevice].Product,
+ LPCtypes[IspEnvironment->DetectedDevice].FlashSize,
+ LPCtypes[IspEnvironment->DetectedDevice].RAMSize);
+ DebugPrintf( 2, " (%s)\n", strippedAnswer);
+
+ if (IspEnvironment->DetectOnly)
+ return(0);
+
+ for(SectorStart = Sector = 0; ; SectorStart += LPCtypes[IspEnvironment->DetectedDevice].SectorTable[Sector++])
+ {
+ if (Sector >= LPCtypes[IspEnvironment->DetectedDevice].FlashSectors)
+ {
+ DebugPrintf( 1, "Programm too large; running out of Flash sectors.\n");
+ return(4);
+ }
+
+ DebugPrintf(2, "Sector %ld: ", Sector);
+ fflush(stdout);
+
+ sprintf(tmpString, "P %ld %ld\r\n", Sector, Sector);
+ if (!SendAndVerify(IspEnvironment, tmpString, Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Wrong answer on Prepare-Command (1) (Sector %ld)\n", Sector);
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ DebugPrintf( 2, ".");
+ fflush(stdout);
+
+ sprintf(tmpString, "E %ld %ld\r\n", Sector, Sector);
+ if (!SendAndVerify(IspEnvironment, tmpString, Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Wrong answer on Erase-Command (Sector %ld)\n", Sector);
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ DebugPrintf( 2, ".");
+ fflush(stdout);
+
+ SectorLength = LPCtypes[IspEnvironment->DetectedDevice].SectorTable[Sector];
+ if(SectorLength > IspEnvironment->BinaryLength - SectorStart)
+ {
+ SectorLength = IspEnvironment->BinaryLength - SectorStart;
+ }
+
+ for(SectorOffset = 0; SectorOffset < SectorLength; SectorOffset += SectorChunk)
+ {
+ if (SectorOffset > 0)
+ {
+ // Add a visible marker between segments in a sector
+ DebugPrintf(2, "|"); /* means: partial segment copied */
+ fflush(stdout);
+ }
+
+ // If the Flash ROM sector size is bigger than the number of bytes
+ // we can copy from RAM to Flash, we must "chop up" the sector and
+ // copy these individually.
+ // This is especially needed in the case where a Flash sector is
+ // bigger than the amount of SRAM.
+ SectorChunk = SectorLength - SectorOffset;
+ if(SectorChunk > (unsigned)LPCtypes[IspEnvironment->DetectedDevice].MaxCopySize)
+ {
+ SectorChunk = LPCtypes[IspEnvironment->DetectedDevice].MaxCopySize;
+ }
+
+ // Write multiple of 45 * 4 Byte blocks to RAM, but copy maximum of on sector to Flash
+ // In worst case we transfer up to 180 byte to much to RAM
+ // but then we can always use full 45 byte blocks and length is multiple of 4
+ CopyLength = SectorChunk;
+ if((CopyLength % (45 * 4)) != 0)
+ {
+ CopyLength += ((45 * 4) - (CopyLength % (45 * 4)));
+ }
+ sprintf(tmpString, "W %ld %ld\r\n", LPC_RAMBASE, CopyLength);
+ if (!SendAndVerify(IspEnvironment, tmpString, Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Wrong answer on Write-Command\n");
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ DebugPrintf( 2, ".");
+ fflush(stdout);
+
+ block_CRC = 0;
+ Line = 0;
+
+ // Transfer blocks of 45 * 4 bytes to RAM
+ for(Pos = SectorStart + SectorOffset; (Pos < SectorStart + SectorOffset + CopyLength) && (Pos < IspEnvironment->BinaryLength); Pos += (45 * 4))
+ {
+ for(Block = 0; Block < 4; Block++) // Each block 45 bytes
+ {
+ DebugPrintf( 2, ".");
+ fflush(stdout);
+
+ // Uuencode one 45 byte block
+ tmpStringPos = 0;
+
+ tmpString[tmpStringPos++] = (char)(' ' + 45); // Encode Length of block
+
+ for(BlockOffset = 0; BlockOffset < 45; BlockOffset++)
+ {
+ c = IspEnvironment->BinaryContent[Pos + Block * 45 + BlockOffset];
+
+ block_CRC += c;
+
+ k = (k << 8) + (c & 255);
+
+ if((BlockOffset % 3) == 2) // Collecting always 3 Bytes, then do processing in 4 Bytes
+ {
+ tmpString[tmpStringPos++] = uuencode_table[(k >> 18) & 63];
+ tmpString[tmpStringPos++] = uuencode_table[(k >> 12) & 63];
+ tmpString[tmpStringPos++] = uuencode_table[(k >> 6) & 63];
+ tmpString[tmpStringPos++] = uuencode_table[ k & 63];
+ }
+ }
+
+ tmpString[tmpStringPos++] = '\r';
+ tmpString[tmpStringPos++] = '\n';
+ tmpString[tmpStringPos++] = 0;
+
+ SendComPort( IspEnvironment, tmpString);
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 1,5000);
+
+ if(strncmp(Answer, tmpString, tmpStringPos) != 0)
+ {
+ DebugPrintf( 1, "Error on writing data (1)\n");
+ return(4);
+ }
+
+ Line++;
+
+ DebugPrintf( 3, "Line = %d\n", Line);
+
+ if(Line == 20)
+ {
+ // printf("block_CRC = %ld\n", block_CRC);
+
+ sprintf(tmpString, "%ld\r\n", block_CRC);
+ SendComPort( IspEnvironment, tmpString);
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 2,5000);
+
+ sprintf(tmpString, "%ld\r\nOK\r\n", block_CRC);
+ if(strcmp(Answer, tmpString) != 0)
+ {
+ DebugPrintf( 1, "Error on writing block_CRC (1)\n");
+ return(4);
+ }
+
+ Line = 0;
+ block_CRC = 0;
+ }
+ }
+ }
+
+ if(Line != 0)
+ {
+ sprintf(tmpString, "%ld\r\n", block_CRC);
+ SendComPort( IspEnvironment, tmpString);
+
+ ReceiveComPort( IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 2,5000);
+
+ sprintf(tmpString, "%ld\r\nOK\r\n", block_CRC);
+ if(strcmp(Answer, tmpString) != 0)
+ {
+ DebugPrintf( 1, "Error on writing block_CRC (2)\n");
+ return(4);
+ }
+ }
+
+ // Prepare command must be repeated before every write
+ sprintf(tmpString, "P %ld %ld\r\n", Sector, Sector);
+ if (!SendAndVerify(IspEnvironment, tmpString, Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Wrong answer on Prepare-Command (2) (Sector %ld)\n", Sector);
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ // Round CopyLength up to one of the following values: 512, 1024,
+ // 4096, 8192; but do not exceed the maximum copy size (usually
+ // 8192, but chip-dependent)
+ if(CopyLength < 512)
+ {
+ CopyLength = 512;
+ }
+ else if(SectorLength < 1024)
+ {
+ CopyLength = 1024;
+ }
+ else if(SectorLength < 4096)
+ {
+ CopyLength = 4096;
+ }
+ else
+ {
+ CopyLength = 8192;
+ }
+ if(CopyLength > (unsigned)LPCtypes[IspEnvironment->DetectedDevice].MaxCopySize)
+ {
+ CopyLength = LPCtypes[IspEnvironment->DetectedDevice].MaxCopySize;
+ }
+
+ sprintf(tmpString, "C %ld %ld %ld\r\n", SectorStart + SectorOffset, LPC_RAMBASE, CopyLength);
+ if (!SendAndVerify(IspEnvironment, tmpString, Answer, sizeof Answer))
+ {
+ DebugPrintf( 1, "Wrong answer on Write-Command\n");
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+
+ }
+
+ DebugPrintf(2, "\n");
+ fflush(stdout);
+
+ if((SectorStart + SectorLength) >= IspEnvironment->BinaryLength)
+ {
+ break;
+ }
+ }
+
+ tDoneUpload = time(NULL);
+ DebugPrintf( 2, "Download Finished... taking %d seconds\n", tDoneUpload - tStartUpload);
+
+ if (WaitForWatchDog)
+ {
+ DebugPrintf( 2, "Wait for restart, in %d seconds from now\n", WatchDogSeconds - (tDoneUpload - tStartUpload));
+ }
+ else
+ {
+ DebugPrintf( 2, "Now launching the brand new code\n" );
+ fflush(stdout);
+
+ SendComPort(IspEnvironment, "G 0 A\r\n"); //goto 0 : run this fresh new downloaded code code
+ ReceiveComPort(IspEnvironment, Answer, sizeof(Answer)-1, &realsize, 2, 5000);
+ /* the reply string is frequently terminated with a -1 (EOF) because the
+ * connection gets broken; zero-terminate the string ourselves
+ */
+ while (realsize > 0 && Answer[(int)realsize - 1] < 0)
+ realsize--;
+ Answer[(int)realsize] = '\0';
+ /* Better to check only the first 9 chars instead of complete receive buffer,
+ * because the answer can contain the output by the started programm
+ */
+ if(realsize == 0 || strncmp((const char *)Answer, "G 0 A\r\n0\r", 9) != 0)
+ {
+ DebugPrintf( 2, "Failed to run the new downloaded code: ");
+ PhilipsOutputErrorMessage(GetErrorNumber(Answer));
+ return(4);
+ }
+ fflush(stdout);
+ }
+ return(0);
+}
+
+
+#if !defined COMPILE_FOR_LPC21
+/***************************** Terminal *********************************/
+/** Acts as a simple dumb terminal. Press 'ESC' to exit.
+*/
+static void Terminal( ISP_ENVIRONMENT *IspEnvironment)
+{
+ int ch = 0;
+ char buffer[128];
+ int fdlogfile = -1;
+ unsigned long realsize;
+
+ // When logging is switched on, output terminal output to lpc21isp.log
+ if(IspEnvironment->LogFile)
+ {
+ fdlogfile = open("lpc21isp.log", O_RDWR | O_BINARY | O_CREAT | O_TRUNC, 0777);
+ }
+
+ printf("Terminal started (press Escape to abort)\n\n");
+ fflush(stdout);
+
+ do
+ {
+ // Check for received characters
+
+ ReceiveComPort( IspEnvironment, buffer, sizeof(buffer) - 1, &realsize, 0,200);
+
+ if( realsize )
+ {
+ write(1, buffer, realsize);
+ fflush(stdout);
+ if(IspEnvironment->LogFile) // When logging is turned on, then copy output to logfile
+ {
+ write(fdlogfile, buffer, realsize);
+ }
+ }
+
+ // check for keypress, and write any out the port.
+ if ( kbhit() )
+ {
+ ch = getch();
+ if(ch == 0x1b)
+ {
+ break;
+ }
+
+ buffer[0] = (unsigned char)ch;
+ buffer[1] = 0;
+
+ SendComPort( IspEnvironment, buffer);
+ }
+ } while(ch != 0x1b);
+
+ printf("\n\nTerminal stopped\n\n");
+ fflush(stdout);
+
+ if(IspEnvironment->LogFile)
+ {
+ close(fdlogfile);
+ }
+
+}
+
+#endif // !defined COMPILE_FOR_LPC21
+
+/***************************** main *************************************/
+/** main. Everything starts from here.
+\param [in] argc the number of arguments.
+\param [in] argv an array of pointers to the arguments.
+*/
+
+#if !defined COMPILE_FOR_LPC21
+
+int main(int argc, char *argv[])
+{
+ ISP_ENVIRONMENT IspEnvironment;
+ int downloadResult = -1;
+
+ // Initialize debug level
+ debug_level = 2;
+
+ // Initialize ISP Environment
+ IspEnvironment.micro = PHILIPS_ARM; /**< The type of micro that will be */
+ /* programmed. */
+ IspEnvironment.TerminalAfterUpload = 0;
+ IspEnvironment.TerminalOnly = 0;
+ IspEnvironment.DetectOnly = 0;
+ IspEnvironment.DetectedDevice = 0; /* index in LPCtypes[] */
+ IspEnvironment.FormatHex = 1;
+ IspEnvironment.ControlLines = 0;
+ IspEnvironment.LogFile = 0;
+
+ /* Read and parse the command line. */
+ ReadArguments( &IspEnvironment, argc, argv);
+ DebugPrintf( 2, "lpc21isp version " VERSION_STR "\n");
+
+ /* Download requested, read in the input file. */
+ if(!IspEnvironment.TerminalOnly && !IspEnvironment.DetectOnly)
+ {
+ LoadFile(&IspEnvironment);
+ }
+
+ OpenSerialPort(&IspEnvironment); /* Open the serial port to the microcontroller. */
+
+ ResetTarget(&IspEnvironment, PROGRAM_MODE);
+
+ ClearSerialPortBuffers(&IspEnvironment);
+
+
+ /* Perform the requested download. */
+ if(!IspEnvironment.TerminalOnly)
+ {
+ switch( IspEnvironment.micro)
+ {
+ case PHILIPS_ARM:
+ downloadResult = PhilipsDownload(&IspEnvironment);
+ break;
+
+ case ANALOG_DEVICES_ARM:
+ downloadResult = AnalogDevicesDownload(&IspEnvironment);
+ break;
+ }
+ if( downloadResult != 0 )
+ {
+ CloseSerialPort(&IspEnvironment);
+ exit(downloadResult);
+ }
+ }
+
+ ResetTarget(&IspEnvironment, RUN_MODE);
+
+ IspEnvironment.debug_level = 1; /* From now on there is no more debug output !! */
+ /* Therefore switch it off... */
+
+ /* User asked for terminal emulation, provide a really dumb */
+ /* terminal. */
+ if(IspEnvironment.TerminalAfterUpload || IspEnvironment.TerminalOnly)
+ {
+ Terminal(&IspEnvironment);
+ }
+
+ CloseSerialPort(&IspEnvironment); /* All done, close the serial port to the */
+ return(0); /* microcontroller and exit. */
+}
+
+#endif // !defined COMPILE_FOR_LPC21
+
+/***************************** DumpString ******************************/
+/** Prints an area of memory to stdout. Converts non-printables to hex.
+\param [in] level the debug level of the block to be dumped. If this is
+less than or equal to the current debug level than the dump will happen
+otherwise this just returns.
+\param [in] b pointer to an area of memory.
+\param [in] size the length of the memory block to print.
+\param [in] fmt a printf style format string used to produce a prefix to
+the block of dumped memory.
+\param [in] ... the arguments referenced by the fmt string.
+*/
+static void DumpString(int level, const void *b, size_t size, const char *fmt, ...)
+{
+ size_t i;
+ const char *s;
+ va_list ap;
+
+ if( level <= debug_level)
+ {
+ va_start( ap, fmt);
+ vprintf( fmt, ap);
+ va_end( ap);
+
+ s = b;
+
+ printf("'");
+ for( i = 0; i < size; i++)
+ {
+ if(s[i] >= 0x20 && s[i] <= 0x7e) /*isprint?*/
+ {
+ putchar(s[i]);
+ }
+ else
+ {
+ printf("(%02X)", s[i]);
+ }
+ }
+ printf("'\n");
+ }
+
+}
+
+
+#if !defined COMPILE_FOR_LPC21
+/***************************** Ascii2Hex ********************************/
+/** Converts a hex character to its equivalent number value. In case of an
+error rather abruptly terminates the program.
+\param [in] c the hex digit to convert.
+\return the value of the hex digit.
+*/
+static unsigned char Ascii2Hex(unsigned char c)
+{
+ if(c >= '0' && c <= '9')
+ {
+ return(unsigned char)(c - '0');
+ }
+ if(c >= 'A' && c <= 'F')
+ {
+ return(unsigned char)(c - 'A' + 10);
+ }
+ if(c >= 'a' && c <= 'f')
+ {
+ return(unsigned char)(c - 'a' + 10);
+ }
+ printf("Wrong Hex-Nibble %c (%02X)\n", c, c);
+ exit(1);
+ return(0); // this "return" will never be reached, but some compilers give a warning if it is not present
+}
+#endif // !defined COMPILE_FOR_LPC21
+
+
+/***************************** PhilipsOutputErrorMessage ***********************/
+/** Given an error number find and print the appropriate error message.
+\param [in] ErrorNumber The number of the error.
+*/
+static void PhilipsOutputErrorMessage(unsigned char ErrorNumber)
+{
+//#if !defined COMPILE_FOR_LPC21
+ switch(ErrorNumber)
+ {
+ case 0:
+ DebugPrintf( 1, "CMD_SUCCESS");
+ break;
+
+ case 1:
+ DebugPrintf( 1, "INVALID_COMMAND");
+ break;
+
+ case 2:
+ DebugPrintf( 1, "SRC_ADDR_ERROR: Source address is not on word boundary.");
+ break;
+ case 3:
+ DebugPrintf( 1, "DST_ADDR_ERROR: Destination address is not on a correct boundary.");
+ break;
+
+ case 4:
+ DebugPrintf( 1, "SRC_ADDR_NOT_MAPPED: Source address is not mapped in the memory map.\n");
+ DebugPrintf( 1, " Count value is taken into consideration where applicable.");
+ break;
+
+ case 5:
+ DebugPrintf( 1, "DST_ADDR_NOT_MAPPED: Destination address is not mapped in the memory map.\n");
+ DebugPrintf( 1, " Count value is taken into consideration where applicable.");
+ break;
+
+ case 6:
+ DebugPrintf( 1, "COUNT_ERROR: Byte count is not multiple of 4 or is not a permitted value.");
+ break;
+
+ case 7:
+ DebugPrintf( 1, "INVALID_SECTOR: Sector number is invalid or end sector number is\n");
+ DebugPrintf( 1, " greater than start sector number.");
+ break;
+
+ case 8:
+ DebugPrintf( 1, "SECTOR_NOT_BLANK");
+ break;
+
+ case 9:
+ DebugPrintf( 1, "SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION:\n");
+ DebugPrintf( 1, "Command to prepare sector for write operation was not executed.");
+ break;
+
+ case 10:
+ DebugPrintf( 1, "COMPARE_ERROR: Source and destination data not equal.");
+ break;
+
+ case 11:
+ DebugPrintf( 1, "BUSY: Flash programming hardware interface is busy.");
+ break;
+
+ case 12:
+ DebugPrintf( 1, "PARAM_ERROR: Insufficient number of parameters or invalid parameter.");
+ break;
+
+ case 13:
+ DebugPrintf( 1, "ADDR_ERROR: Address is not on word boundary.");
+ break;
+
+ case 14:
+ DebugPrintf( 1, "ADDR_NOT_MAPPED: Address is not mapped in the memory map.\n");
+ DebugPrintf( 1, " Count value is taken in to consideration where applicable.");
+ break;
+
+ case 15:
+ DebugPrintf( 1, "CMD_LOCKED");
+ break;
+
+ case 16:
+ DebugPrintf( 1, "INVALID_CODE: Unlock code is invalid.");
+ break;
+
+ case 17:
+ DebugPrintf( 1, "INVALID_BAUD_RATE: Invalid baud rate setting.");
+ break;
+
+ case 18:
+ DebugPrintf( 1, "INVALID_STOP_BIT: Invalid stop bit setting.");
+ break;
+
+ case 255: break;
+ default:
+ DebugPrintf( 1, "unknown error %u", ErrorNumber);
+ break;
+ }
+//#else // !defined COMPILE_FOR_LPC21
+// printf("error %u", ErrorNumber);
+//#endif // !defined COMPILE_FOR_LPC21
+}
+
+
+/***************************** GetErrorNumber ***************************/
+/** Find error number in string. This will normally be the string
+returned from the microcontroller.
+\param [in] Answer the buffer to search for the error number.
+\return the error number found, if no linefeed found before the end of the
+string an error value of 255 is returned. If a non-numeric value is found
+then it is printed to stdout and an error value of 255 is returned.
+*/
+static unsigned char GetErrorNumber(const char *Answer)
+{
+ unsigned int i = 0;
+
+ while(1)
+ {
+ if(Answer[i] == 0x00) return(255);
+ if(Answer[i] == 0x0a) break;
+ i++;
+ }
+
+ i++;
+
+ if(Answer[i] < '0' || Answer[i] > '9')
+ {
+ DebugPrintf( 1, "ErrorString: %s", &Answer[i]);
+ return(255);
+ }
+
+ return (unsigned char)(atoi(&Answer[i]));
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+utils_PROGRAMS = tolpc
+
+tolpc_SOURCES = tolpc.c tolpc_fn.c uuencode.c load_bfd.c
+tolpc_LIBS = bfd iberty
+
+# Override LOADLIBES from config.target (if specified)
+LOADLIBES=
--- /dev/null
+.PHONY: all
+
+ifeq ($(SOURCES_DIR),)
+all: tolpc #rs232_lt
+else
+# if called from OMK
+all:
+ $(MAKE) -C $(SOURCES_DIR) SOURCES_DIR='' all
+endif
+
+# if called from OMK
+binary-pass: all
+check-dir include-pass library-pass utils-pass default-config-pass:
+
+#all: tolpc lpcerm
+
+CFLAGS=-O0 -Wall -g
+LDFLAGS=-g -lbfd
+
+tolpc: tolpc.o tolpc_fn.o uuencode.o load_bfd.o
+
+hiterm: hiterm.o tolpc_fn.o
+
+rs232_lt: rs232_lt.o tolpc_fn.o
+ $(CC) $(LDFLAGS) $(CFLAGS) -lncurses -o $@ $^
+
+clean:
+ rm -f *.o
--- /dev/null
+
+TOLPC
+=====
+
+Program uploader for lpc21xx processor.
--- /dev/null
+/* Copyright (C) 1992, 1993, 1996, 1997, 1998 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Library General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Library General Public License for more details.
+
+ You should have received a copy of the GNU Library General Public
+ License along with the GNU C Library; see the file COPYING.LIB. If not,
+ write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include <termios.h>
+#include <errno.h>
+#include <stddef.h>
+
+struct speed_struct
+{
+ speed_t value;
+ speed_t internal;
+};
+
+static const struct speed_struct speeds[] =
+ {
+#ifdef B0
+ { 0, B0 },
+#endif
+#ifdef B50
+ { 50, B50 },
+#endif
+#ifdef B75
+ { 75, B75 },
+#endif
+#ifdef B110
+ { 110, B110 },
+#endif
+#ifdef B134
+ { 134, B134 },
+#endif
+#ifdef B150
+ { 150, B150 },
+#endif
+#ifdef B200
+ { 200, B200 },
+#endif
+#ifdef B300
+ { 300, B300 },
+#endif
+#ifdef B600
+ { 600, B600 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1200
+ { 1200, B1200 },
+#endif
+#ifdef B1800
+ { 1800, B1800 },
+#endif
+#ifdef B2400
+ { 2400, B2400 },
+#endif
+#ifdef B4800
+ { 4800, B4800 },
+#endif
+#ifdef B9600
+ { 9600, B9600 },
+#endif
+#ifdef B19200
+ { 19200, B19200 },
+#endif
+#ifdef B38400
+ { 38400, B38400 },
+#endif
+#ifdef B57600
+ { 57600, B57600 },
+#endif
+#ifdef B76800
+ { 76800, B76800 },
+#endif
+#ifdef B115200
+ { 115200, B115200 },
+#endif
+#ifdef B153600
+ { 153600, B153600 },
+#endif
+#ifdef B230400
+ { 230400, B230400 },
+#endif
+#ifdef B307200
+ { 307200, B307200 },
+#endif
+#ifdef B460800
+ { 460800, B460800 },
+#endif
+ };
+
+
+/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
+int
+cfsetspeed (struct termios *termios_p, speed_t speed)
+{
+ size_t cnt;
+
+ for (cnt = 0; cnt < sizeof (speeds) / sizeof (speeds[0]); ++cnt)
+ if (speed == speeds[cnt].internal)
+ {
+ cfsetispeed (termios_p, speed);
+ cfsetospeed (termios_p, speed);
+ return 0;
+ }
+ else if (speed == speeds[cnt].value)
+ {
+ cfsetispeed (termios_p, speeds[cnt].internal);
+ cfsetospeed (termios_p, speeds[cnt].internal);
+ return 0;
+ }
+
+ __set_errno (EINVAL);
+
+ return -1;
+}
--- /dev/null
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <stdlib.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <asm/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/stat.h>
+
+
+#define DEBUG 0
+
+int cnt;
+char * arg[10];
+
+unsigned char * bbuf=NULL;
+long Len=0;
+
+int tohit(int argc, char **argv);
+
+void SaveBB(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+ int fd1;
+
+ if (!bbuf){
+ printf("Error bufer empty\n");
+ return;
+ }
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+ i=0;
+ while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ if ((fd1 = open(str, O_CREAT | O_WRONLY, 0644)) == -1) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ i=write(fd1,bbuf,Len);
+ if(i<0){
+ printf("%s\n",strerror(errno));
+ }
+ else if(i!=Len){
+ printf("Error writing %s\n",str);
+ }
+ close(fd1);
+ printf("Write %d bytes\n",i);
+}
+
+void SaveBA(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ if (!bbuf){
+ printf("Error bufer empty\n");
+ return;
+ }
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+ i=0;
+ while(*buf && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ F=fopen(str,"w");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ fprintf(F,"%07d\n",*x);
+ x++;
+ }
+ fclose(F);
+ printf("Write %d num\n",i);
+}
+
+
+void Load(int fd,char *buf,int len,int fl)
+{
+ int i;
+ int j;
+ char str[100];
+ char a1[]="7";
+ char * a[3];
+
+ a[0]=NULL;
+ a[1]=a1;
+ a[2]=a1;
+
+ buf[len]=' ';
+ buf[len+1]=0;
+ buf+=5;
+ if(*buf!=' ') buf++;
+ i=1;
+ arg[0]=NULL;
+ j=0;
+ while(*buf){
+ if(j>0 && *buf==' '){
+ str[j]=0;
+ j++;
+ if(i<cnt) free(arg[i]);
+ arg[i]=(char *)malloc(j);
+ do {
+ j--;
+ arg[i][j]=str[j];
+ }while(j);
+ i++;
+ if(i==10) i--;
+ }
+ else{
+ if(*buf!=' ' && *buf!=10 && *buf!=13) str[j++]=*buf;
+ if (j==100) j--;
+ }
+ buf++;
+ }
+ if(i>1){
+ cnt=i;
+ }
+ for (i=0;i<cnt;i++){
+ printf(" A%d : %s\n",i,arg[i]);
+ }
+ if(cnt){
+ if(fl==0){
+ write(fd,"LOAD\n",5);
+ usleep(100000);
+ read(fd,str,100);
+ }
+ tohit(cnt,arg);
+ tohit(3,a);
+ usleep(200000);
+ read(fd,str,100);
+ }
+ else{
+ printf("Bad Parametr\n");
+ }
+}
+
+char GName[100];
+char GStart[20];
+char GLen[20];
+int GChan;
+int GSt=0;
+int Cb=0;
+
+void Get(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+ GChan=strtol(str,NULL,10);
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
+ GStart[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
+ GLen[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
+ GName[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ Cb=1;
+ GSt=0;
+ sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetM(int fd,char *buf,int len)
+{
+ char str[100];
+ int i;
+
+ while(*buf && *buf!=' ') buf++;
+ while(*buf && *buf==' ') buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) str[i++]=*buf++;
+ str[i]=0;
+ GChan=strtol(str,NULL,10);
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GStart[i++]=*buf++;
+ GStart[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GLen[i++]=*buf++;
+ GLen[i]=0;
+ while(*buf && (*buf==' ' || *buf==',')) buf++;
+
+ i=0;
+ while(*buf && *buf!=',' && *buf!=' ' && *buf!=10 && *buf!=13) GName[i++]=*buf++;
+ GName[i]=0;
+
+ if(i<1){
+ printf("Error bad parametr \n");
+ return;
+ }
+ Cb=2;
+ GSt=0;
+ sprintf(str,"GET 0,%s,%s\n",GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetCB(int fd)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ sprintf(str,"%s.%03d",GName,GSt);
+
+ F=fopen(str,"w");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ fprintf(F,"%07d\n",*x);
+ x++;
+ }
+ fclose(F);
+ printf("Write %d num\n",i);
+ GSt++;
+ if(GSt>GChan-1){
+ Cb=0;
+ GSt=0;
+ return;
+ }
+ sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void GetMCB(int fd)
+{
+ char str[100];
+ int i;
+ FILE * F;
+ __s16 * x;
+
+ sprintf(str,"%s.dat",GName);
+ if(GSt==0)F=fopen(str,"w");
+ else F=fopen(str,"a");
+ if (F==0) {
+ printf("Error openning %s\n",str);
+ printf("%s\n",strerror(errno));
+ return;
+ }
+ x=(__s16 *)bbuf;
+ for(i=0;i<(Len/2);i++){
+ if(i==(Len/2)-1) fprintf(F,"%07d\n",*x);
+ else fprintf(F,"%07d ",*x);
+ x++;
+ }
+ fclose(F);
+// printf("Write %d num\n",i);
+ GSt++;
+ if(GSt>GChan-1){
+ printf("Write %d chanels\n",GSt);
+ Cb=0;
+ GSt=0;
+ return;
+ }
+ sprintf(str,"GET %d,%s,%s\n",GSt,GStart,GLen);
+ printf("%s",str);
+ write(fd,str,strlen(str));
+}
+
+void LCmd(int fd,char* buf,int len)
+{
+ buf[len]=0;
+ if((strstr(buf,"!loadb")==buf) || (strstr(buf,"!LOADB")==buf))
+ Load(fd,buf,len,1);
+ else if((strstr(buf,"!load")==buf) || (strstr(buf,"!LOAD")==buf))
+ Load(fd,buf,len,0);
+ else if((strstr(buf,"!savebuf")==buf) || (strstr(buf,"!SAVEBUF")==buf))
+ SaveBB(fd,buf,len);
+ else if((strstr(buf,"!saveasc")==buf) || (strstr(buf,"!SAVEASC")==buf))
+ SaveBA(fd,buf,len);
+ else if((strstr(buf,"!getm")==buf) || (strstr(buf,"!GETM")==buf))
+ Get(fd,buf,len);
+ else if((strstr(buf,"!get")==buf) || (strstr(buf,"!GET")==buf))
+ GetM(fd,buf,len);
+ else printf ("Unknown comand : %s\n",buf);
+}
+
+void CB(int fd)
+{
+ if(Cb==1) GetCB(fd);
+ if(Cb==2) GetMCB(fd);
+}
+
+
+int main(int argc, char **argv)
+{
+ int ii;
+ int oi;
+ int i;
+ unsigned char ibuf[500];
+ unsigned char obuf[500];
+ unsigned char * sdev="/dev/ttyS1";
+ int fd=-1;
+ long len=0;
+ long dlen=0;
+ unsigned char *x;
+
+ unsigned char * bb;
+
+ cnt=0;
+
+ if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",sdev);
+ exit(-1);
+ }
+ rs232_setmode(fd,38800,0,0);
+
+
+ ii=0;
+ oi=0;
+ while(1){
+ if(rs232_test(fd,10000)==1){
+ oi+=read(fd, obuf+oi, 500-oi);
+ if(obuf[oi-1]==0xa || obuf[oi-1]==0xd || oi>400){
+ obuf[oi]=0;
+ if(dlen){
+ if(oi<=dlen){
+ memcpy(bb,obuf,oi);
+ bb+=oi;
+ dlen-=oi;
+ oi=0;
+ }
+ else{
+ memcpy(bb,obuf,dlen);
+ bb+=dlen;
+ x=obuf+dlen;
+ dlen=0;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ if(!dlen) CB(fd);
+ }
+ else {
+ x=strstr(obuf,"061:");
+ if(x){
+ x+=4;
+ sscanf(x,"%ld",&Len);
+ printf("len=%ld\n",Len);
+ len=Len;
+ if(bbuf) free(bbuf);
+ bbuf=(unsigned char *)malloc(len);
+ bb=bbuf;
+ while(*x!=0xa && *x!=0xd && *x) x++;
+ if(*x==0xd || *x==0xa) x++;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ x=strstr(obuf,"062:");
+ if(x){
+ dlen=len;
+ len=0;
+ x+=4;
+ if(oi-(x-obuf)>=dlen){
+ memcpy(bb,x,dlen);
+ bb+=dlen;
+ x+=dlen;
+ dlen=0;
+ i=0;
+ while(x-obuf<oi){
+ obuf[i++]=*x++;
+ }
+ oi=i;
+ obuf[oi]=0;
+ }
+ else{
+ memcpy(bb,x,oi-(x-obuf));
+ bb+=oi-(x-obuf);
+ dlen-=oi-(x-obuf);
+ oi=0;
+ }
+ if(!dlen) CB(fd);
+ }
+ }
+ write(0, obuf, oi);
+ oi=0;
+ }
+ }
+ if(rs232_test(1,10000)==1){
+ ii+=read(1, ibuf+ii, 500-ii);
+ if(ibuf[ii-1]==0xa || ibuf[ii-1]==0xd || ii>400){
+ if(ibuf[0]=='!'){
+ LCmd(fd,ibuf,ii);
+ }
+ else{
+ write(fd, ibuf, ii);
+ }
+ ii=0;
+ }
+ }
+ }
+}
+
--- /dev/null
+#include <stdlib.h>
+#include <bfd.h>
+#include <stdio.h>
+#include "tolpc_fn.h"
+#include "load_bfd.h"
+
+
+/**
+ * extract loadable sections from bfd file and load them
+ * @param fname bfd binary file name
+ * @param target NULL for default or string description (eg. "elf32-m68hc12")
+ * @param loader_cb section loader callback
+ * @param start_address code start address extracted from bfd
+ * @param verbose operation is silent if 0, sections are listed otherwise
+ * @return 0 if successful
+ */
+int load_bfd(char *fname, char *target, load_section loader_cb,
+ bfd_vma *start_address, int verbose) {
+ bfd *abfd;
+ asection *sec;
+ bfd_vma lma, vma, size;
+ bfd_boolean loadable;
+ void *contents;
+
+ bfd_init();
+ if ((abfd = bfd_openr(fname, target)) == NULL) {
+ bfd_perror("load_bfd: bfd_openr");
+ return(1);
+ }
+ if (!bfd_check_format(abfd, bfd_object)) {
+ bfd_perror("load_bfd: bfd_check_format");
+ return(1);
+ }
+
+ /* determine start address */
+ *start_address = bfd_get_start_address(abfd);
+
+ tolpc_verbose(1, "Loading %s\n"
+ "start address 0x%x\n"
+ "loading sections:\n", fname, (unsigned)*start_address);
+
+ /* load sections */
+ for (sec = abfd->sections; sec != NULL; sec = sec->next) {
+ /* get section load address and size */
+ lma = bfd_get_section_lma(abfd, sec);
+ vma = bfd_get_section_vma(abfd, sec);
+ size = bfd_section_size(abfd, sec);
+ loadable = bfd_get_section_flags(abfd, sec) & SEC_LOAD;
+ if (!loadable || (size == 0))
+ continue;
+
+ tolpc_verbose(1, "%s : ", bfd_get_section_name(abfd, sec));
+ tolpc_verbose(1, "lma=0x%x, vma=0x%x, len=%d",
+ (unsigned)lma, (unsigned)vma, (unsigned)size);
+
+ /* extract section contents */
+ if ((contents = malloc(size)) == NULL) {
+ perror("load_bfd: malloc");
+ return(1);
+ }
+ if (!bfd_get_section_contents(abfd, sec, contents, /*offs.?*/ 0, size)) {
+ bfd_perror("load_bfd: bfd_get_section_contents");
+ return(1);
+ }
+ /* call the loader */
+ if (loader_cb(lma, size, contents))
+ return(1);
+ free(contents);
+ }
+
+ tolpc_verbose(1, "Loading of %s finished.\n", fname);
+
+ bfd_close(abfd);
+ /* OK */
+ return(0);
+}
+
+#if TRAPARNA
+int null_loader(bfd_vma lma, bfd_size_type size, void *data) {
+ return(0);
+}
+
+main(int argc, char *argv[]) {
+ char *fname = argv[1];
+ bfd_vma start;
+
+ if (!load_bfd(fname, NULL, null_loader, &start, 1))
+ printf("Nahrano, staci skocit na adresu 0x%x.\n", start);
+ else
+ printf("@#%!@$# neco se posrabilo.\n");
+}
+#endif
--- /dev/null
+//
+// C++ Interface: load_bfd
+//
+// Description:
+//
+//
+// Author: Michal Sojka <sojkam1@fel.cvut.cz>, (C) 2005
+//
+// Copyright: See COPYING file that comes with this distribution
+//
+//
+
+/**
+ * load section callback function
+ * -- called in loop for each section with LOAD flag, found in bfd file
+ * @param lma load addres
+ * @param size section length
+ * @pram data data block to load
+ * @return 0 if load was successful, non-0 to terminate caller loop
+ */
+typedef int (*load_section)(bfd_vma lma, bfd_size_type size, void *data);
+
+
+int load_bfd(char *fname, char *target, load_section loader_cb,
+ bfd_vma *start_address, int verbose);
--- /dev/null
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <ncurses.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include "tolpc_fn.h"
+
+#define DEBUG 0
+#define HAS_GETOPT_LONG 1
+
+#define MEM_BUF_LEN 0x40000
+
+unsigned char mem_buf[MEM_BUF_LEN];
+
+int rs232_loop_test(char *sdev, int baud, int flowc);
+
+struct termios init_saved_termios;
+
+
+int flowc;
+
+static void
+usage(void)
+{
+ printf("usage: tohit <parameters> <send_file>\n");
+ printf(" -d, --sdev <name> name of RS232 device [%s]\n",tohit_sdev);
+ printf(" -B, --baud <num> RS232 baudrate [%d]\n",tohit_baud);
+ printf(" -f, --flowc-rts flow control\n");
+ printf(" -V, --version show version\n");
+ printf(" -h, --help this usage screen\n");
+}
+
+int main(int argc, char **argv)
+{
+ /* FILE *F; */
+
+ static struct option long_opts[] = {
+ { "sdev", 1, 0, 'd' },
+ { "baud", 1, 0, 'B' },
+ { "flowc-rts",0, 0, 'f' },
+ { "version",0,0, 'V' },
+ { "help", 0, 0, 'h' },
+ { 0, 0, 0, 0}
+ };
+ int opt;
+ int ret;
+
+ tohit_baud=9600;
+
+ #ifndef HAS_GETOPT_LONG
+ while ((opt = getopt(argc, argv, "d:B:fVh")) != EOF)
+ #else
+ while ((opt = getopt_long(argc, argv, "d:B:fVh",
+ &long_opts[0], NULL)) != EOF)
+ #endif
+ switch (opt) {
+ case 'd':
+ tohit_sdev=optarg;
+ break;
+ case 'B':
+ tohit_baud = strtol(optarg,NULL,0);
+ break;
+ case 'f':
+ flowc=1;
+ break;
+ case 'V':
+ fputs("tohit pre alpha\n", stdout);
+ exit(0);
+ case 'h':
+ default:
+ usage();
+ exit(opt == 'h' ? 0 : 1);
+ }
+
+ def_shell_mode();
+ savetty();
+ /*tcgetattr(0, &init_saved_termios);*/
+ initscr(); cbreak(); noecho();
+ nonl(); intrflush(stdscr, FALSE); keypad(stdscr, TRUE);
+ nodelay(stdscr, TRUE);
+
+ ret=rs232_loop_test(tohit_sdev,tohit_baud,flowc);
+
+ endwin();
+
+ return ret;
+}
+
+
+int rs232_loop_test(char *sdev, int baud, int flowc)
+{
+ int fd;
+ int c;
+ unsigned char *pout=NULL, *pin=NULL, uc;
+ int cntout=0,cntin=0, cnt;
+ int i, test_loop_fl=0;
+ int errorcnt=0;
+ int idle;
+ int stopin=0;
+ /* int stopout=0; */
+
+ /* Open RS232 device */
+ if ((fd = open(sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n",sdev);
+ return -1;
+ }
+
+ /* Set RS232 device mode and speed */
+ if(rs232_setmode(fd,baud,0,flowc)<0){
+ printf("Error in rs232_setmode\n");
+ return -1;
+ }
+
+/*
+ rs232_sendch(int fd,unsigned char c);
+ rs232_recch(int fd);
+ rs232_test(int fd,int time);
+*/
+
+ mvprintw(/*y*/2,/*x*/2,"Test of RS-232 transfers");
+
+ do{
+ c=getch();
+ idle=(c==ERR);
+
+ switch(c) {
+ case 't' :
+ cnt=20000;
+ if(cnt>MEM_BUF_LEN) cnt=MEM_BUF_LEN;
+ for(i=0;i<cnt;i++)
+ mem_buf[i]=i^(i>>7);
+ test_loop_fl=1;
+ cntout=cntin=cnt;
+ pout=pin=mem_buf;
+ errorcnt=0;
+ mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
+ "Running");
+ mvprintw(/*y*/9,/*x*/0," ");
+ mvprintw(/*y*/10,/*x*/0," ");
+ break;
+ case 's' :
+ stopin=!stopin;
+ break;
+ }
+
+ if(test_loop_fl) {
+ if(cntout)
+ if(write(fd, pout, 1) == 1) {
+ pout++;
+ cntout--;
+ idle=0;
+ }
+ if(cntin&&!stopin)
+ if(read(fd, &uc, 1) == 1) {
+ if(*pin!=uc) {
+ errorcnt++;
+ mvprintw(/*y*/9,/*x*/0,"Diff : %02X != %02X",uc,*pin);
+ mvprintw(/*y*/10,/*x*/0,"Errors : %4d",errorcnt);
+ }
+ pin++;
+ cntin--;
+ idle=0;
+ }
+ if(!cntin&&!cntout) {
+ mvprintw(/*y*/11,/*x*/0,"Loop test : %s",
+ errorcnt?"Failed ":"Passed ");
+ test_loop_fl=0;
+ }
+ }
+
+ if(idle) {
+ mvprintw(/*y*/8,/*x*/0,"Cnt Out: %6d In : %6d %s",
+ cntout,cntin,stopin?"Stop":" ");
+ }
+ } while(c!=KEY_F(10));
+
+ return 0;
+}
+
--- /dev/null
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <termios.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <stdarg.h>
+#include "tolpc_fn.h"
+#include "load_bfd.h"
+
+#define DEBUG 0
+#define HAS_GETOPT_LONG 1
+
+
+struct tolpc_env Tolpc =
+{
+ .sdev = "/dev/ttyS0", .crystal = 10000, .baud = 9600, .waitrep = 100000
+};
+
+struct tolpc_env *env = &Tolpc;
+
+void error(const char *fmt, ...)
+{
+ va_list ap;
+ char message[100];
+
+ va_start(ap, fmt);
+ vsnprintf(message, 100, fmt, ap);
+ va_end(ap);
+
+ fprintf(stderr, "tolpc error: %s\n", message);
+ exit(1);
+}
+
+static void usage(void)
+{
+ printf("usage:\n");
+ printf(" high level: tolpc [<global parameters>] -L [mode] -f <object file>\n");
+ printf(" low level: tolpc [<global parameters>] [command [,...]]\n");
+ printf("Command has the form: [command [, param1 [,param2, ...]]\n");
+ printf("\n");
+ printf("Global Parameters:\n");
+ printf(" -d, --sdev <name> name of RS232 device [%s]\n", env->sdev);
+ printf(" -q, --crystal <kHz> crystal frequency in kHz [%d]\n", env->crystal);
+ printf(" -b, --baud <num> RS232 baudrate [%d]\n", env->baud);
+ printf(" -w, --wait <num> timeout in miliseconds [%ld]\n", env->waitrep/1000);
+ printf(" -v, --verbose increase verbosity (can be used more times)\n");
+ printf("Commands:\n");
+ printf(" -L, --load [A|T] Load binary file and execute (loads all BFD sections,\n");
+ printf(" jumps to start address) [only RAM in this version].\n");
+ printf(" -U, --unlock\n");
+ printf(" -A, --echo <setting> Echo (use -A0 when uploading data using W)\n");
+ printf(" -G, --go [<mode>] Mode is A or T [A]\n");
+ printf(" -C, --copy <flash_addr> Copy RAM to Flash\n");
+ printf(" -c, --cmd <command> Execute other command (letters from LPC user manual)\n");
+ printf("Parameters:\n");
+ printf(" -s, --start <addr> start address of transfer\n");
+ printf(" -l, --length <num> length of upload block\n");
+ printf(" -f, --file <filename> file to read or write\n");
+ printf(" -o, --offset <num> offset in a file\n");
+ printf("Other:\n");
+ printf(" -k, --break send communication break character\n");
+ printf(" -V, --version show version\n");
+ printf(" -h, --help this usage screen\n");
+}
+
+struct cmd_params {
+ char cmd;
+ char *sarg;
+ int iarg;
+
+ long start;
+ int length;
+ int offset;
+ char *fname;
+
+ void *data;
+};
+
+int load_file(struct cmd_params *p)
+{
+ FILE *f;
+ struct stat st;
+ int ret;
+
+ if (!p->fname)
+ error("No file (-f) for %c command", p->cmd);
+
+ ret = stat(p->fname, &st);
+ if (ret) {
+ perror(p->fname);
+ exit(1);
+ }
+
+ if (p->length == 0) p->length = st.st_size - p->offset;
+
+ f = fopen(p->fname, "r");
+ if (f == NULL) {
+ perror(p->fname);
+ exit(1);
+ }
+
+ fseek(f, p->offset, SEEK_SET);
+
+ p->data = malloc(p->length);
+
+ fread(p->data, p->length, 1, f);
+ if (ferror(f)) {
+ perror(p->fname);
+ exit(1);
+ }
+
+ return p->length;
+}
+
+int ram_write_cb(bfd_vma lma, bfd_size_type size, void *data) {
+ return tolpc_write_ram(env, lma, size, data);
+}
+
+/**
+ * load bfd file to target (only RAM at this moment) and jump
+ * to its start address
+ * @return 0=OK
+ */
+int load_exec(struct cmd_params *p) {
+ int ret;
+ bfd_vma start;
+
+ if (!p->fname)
+ error("No file (-f) for %c command", p->cmd);
+
+ ret = tolpc_echo(env, '0');
+ if (ret) return ret;
+
+ ret = tolpc_unlock(env);
+ if (ret) return ret;
+
+ ret = load_bfd(p->fname, /*default target*/NULL, ram_write_cb, &start, tolpc_verbose_level);
+ if (ret) return ret;
+
+ tolpc_verbose(1, "Running the program\n");
+ ret = tolpc_go(env, start, p->iarg == 'A');
+
+ return(ret);
+}
+
+void not_implemented(char c)
+{
+ error("Not implemented: %c", c);
+}
+
+void clear_cmd(struct cmd_params *p)
+{
+ if (p->data) free(p->data);
+ memset(p, 0, sizeof(*p));
+ p->start = -1;
+}
+
+void run_cmd(struct cmd_params *p)
+{
+ int ret = 0;
+
+ switch (p->cmd) {
+ case 'U':
+ ret = tolpc_unlock(env);
+ break;
+ case 'A':
+ ret = tolpc_echo(env, p->iarg);
+ break;
+ case 'G':
+ if (p->iarg != 'A' && p->iarg != 'T')
+ error("Go mode can only be A or T.");
+ if (p->start < 0)
+ error("No start address is given for Go command");
+ ret = tolpc_go(env, p->start, p->iarg == 'A');
+ break;
+ case 'W':
+ load_file(p);
+ if (p->start < 0)
+ error("No start addres is given for Write command");
+ ret = tolpc_write_ram(env, p->start, p->length, p->data);
+ break;
+ case 'J':
+ {
+ char partid[100];
+ ret = tolpc_partid(env, partid, 99);
+ if (ret == 0) {
+ tolpc_verbose(1, "Part ID:");
+ puts(partid);
+ }
+ break;
+ }
+ case 'K':
+ {
+ char ver[100];
+ tolpc_bootver(env, ver, 99);
+ if (ret == 0) {
+ tolpc_verbose(1, "Boot code version:");
+ puts(ver);
+ }
+ break;
+ }
+ case 'L':
+ ret = load_exec(p);
+ break;
+ default:
+ not_implemented(p->cmd);
+
+ }
+ if (ret) error("Command %c", p->cmd);
+}
+
+void new_command(struct cmd_params *p, char cmd)
+{
+ if (p->cmd)
+ run_cmd(p);
+
+ clear_cmd(p);
+ p->cmd = cmd;
+}
+
+int main(int argc, char **argv)
+{
+ int i;
+ int opt;
+ char short_ops[100];
+ struct cmd_params p;
+
+ static struct option long_opts[] = {
+ { "sdev", 1, 0, 'd'},
+ { "crystal", 1, 0, 'q' },
+ { "baud", 1, 0, 'b' },
+ { "wait", 1, 0, 'w' },
+ { "verbose", 0, 0, 'v' },
+
+ { "unlock", 0, 0, 'U' },
+ { "echo", 1, 0, 'A' },
+ { "go", 2, 0, 'G' },
+ { "copy", 1, 0, 'C' },
+ { "cmd", 1, 0, 'c' },
+ { "load", 2, 0, 'L' }, // has optional argument
+
+ { "start", 1, 0, 's' },
+ { "length", 1, 0, 'l' },
+ { "file", 1, 0, 'f' },
+ { "offset", 1, 0, 'o' },
+
+ { "break", 0, 0, 'k' },
+ { "version", 0, 0, 'V' },
+ { "help", 0, 0, 'h' },
+ { 0, 0, 0, 0}
+ };
+
+ // Initial clear of of parameters structure (clear_cmd produces segfault here)
+ memset(&p, 0, sizeof(p));
+ p.start = -1;
+
+ memset(short_ops, 0, sizeof(short_ops));
+ i = 0;
+ for (opt = 0; long_opts[opt].name != NULL || i > 100 - 3; opt++) {
+ short_ops[i++] = long_opts[opt].val;
+ if (long_opts[opt].has_arg) short_ops[i++] = ':';
+ if (long_opts[opt].has_arg == 2) short_ops[i++] = ':';
+ }
+ short_ops[i] = '\0';
+
+#ifndef HAS_GETOPT_LONG
+ while ((opt = getopt(argc, argv, short_ops)) != EOF)
+#else
+ while ((opt = getopt_long(argc, argv, short_ops,
+ &long_opts[0], NULL)) != EOF)
+#endif
+ switch (opt) {
+ case 'd':
+ env->sdev = optarg;
+ break;
+ case 'b':
+ env->baud = strtol(optarg, NULL, 0);
+ break;
+ case 'q':
+ env->crystal = strtol(optarg, NULL, 0);
+ break;
+ case 'w':
+ env->waitrep = 1000*strtol(optarg, NULL, 0);
+ break;
+ case 'v':
+ tolpc_verbose_level++;
+ break;
+ case 'U':
+ new_command(&p, opt);
+ break;
+ case 'A':
+ new_command(&p, opt);
+ p.iarg = optarg[0];
+ break;
+ case 'G':
+ {
+ new_command(&p, opt);
+ p.iarg = 'A'; // ARM mode is default
+ if (optarg) p.iarg = optarg[0];
+ break;
+ }
+ case 'C':
+ new_command(&p, opt);
+ break;
+ case 'c':
+ {
+ char cmd = optarg[0];
+ switch (cmd) {
+ case 'W':
+ case 'J':
+ case 'K':
+ new_command(&p, cmd);
+ break;
+ default:
+ error("Unknown command %c", cmd);
+ break;
+ }
+ break;
+ }
+ case 'L':
+ new_command(&p, opt);
+ p.iarg = 'A'; // ARM mode is default
+ if (optarg) p.iarg = optarg[0];
+ break;
+ case 's':
+ p.start = strtol(optarg, NULL, 0);
+ break;
+ case 'l':
+ p.length = strtol(optarg, NULL, 0);
+ break;
+ case 'f':
+ p.fname = optarg;
+ break;
+ case 'o':
+ p.offset = strtol(optarg, NULL, 0);
+ break;
+ case 'V':
+ fputs("tolpc pre alpha\n", stdout);
+ exit(0);
+ case 'h':
+ default:
+ usage();
+ exit(opt == 'h' ? 0 : 1);
+ }
+ new_command(&p, 0); // run the last command
+ return 0;
+}
--- /dev/null
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <termios.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdarg.h>
+#include "tolpc_fn.h"
+#include "uuencode.h"
+
+#define DEBUG 0
+#define DEBUG_COUNT 0
+
+//#define WITHOUT_CFSETSPEED
+
+int tolpc_debug_level = 0;
+
+#ifdef WITHOUT_CFSETSPEED
+
+#include "baudrate.h"
+
+/* Set both the input and output baud rates stored in *TERMIOS_P to SPEED. */
+int rs232_cfsetspeed (struct termios *termios_p, speed_t speed) {
+ size_t cnt;
+
+ for (cnt = 0; cnt < sizeof(rs232_speeds) / sizeof(rs232_speeds[ 0 ]); ++cnt)
+ if (speed == rs232_speeds[ cnt ].internal) {
+ cfsetispeed (termios_p, speed);
+ cfsetospeed (termios_p, speed);
+ return 0;
+ } else if (speed == rs232_speeds[ cnt ].value) {
+ cfsetispeed (termios_p, rs232_speeds[ cnt ].internal);
+ cfsetospeed (termios_p, rs232_speeds[ cnt ].internal);
+ return 0;
+ }
+
+ return -1;
+}
+
+#endif /* WITHOUT_CFSETSPEED */
+
+#define FLOWC_XONXOFF 0x02
+#define FLOWC_RTSCTS 0x01
+
+int tolpc_verbose_level = 0;
+
+void tolpc_verbose(int level, const char *fmt, ...)
+{
+ va_list ap;
+
+ if (level <= tolpc_verbose_level) {
+ va_start(ap, fmt);
+ vfprintf(stderr, fmt, ap);
+ va_end(ap);
+ fflush(stdout);
+ }
+}
+#define verbose tolpc_verbose
+
+/**
+ * Set right mode and speed for RS232 interface
+ * baud can be either speed in character per second or special Bxxxx constant
+ */
+int setup_comm_dev(int dev, int baudrate, int flowc) {
+ struct termios term_attr;
+
+ if (tcgetattr(dev, &term_attr)) {
+ perror("setup_dev: tcgetattr");
+ return -1;
+ }
+ /* set immediate character input */
+ /*
+ ~ICANON -- do not wait for EOL at input,
+ ~ECHO -- do not echo characters locally
+ */
+ term_attr.c_lflag = 0;
+ term_attr.c_cc[VMIN] = 1;
+ term_attr.c_cc[VTIME] = 0;
+
+ /* input newlines: \r\n=>\n */
+ term_attr.c_iflag = IGNCR;
+ if (flowc & FLOWC_XONXOFF)
+ term_attr.c_iflag |= IXON | IXOFF;
+ if (flowc & FLOWC_RTSCTS)
+ term_attr.c_cflag |= CRTSCTS;
+
+ term_attr.c_oflag = 0;
+
+ /* set right ispeed and ospeed */
+ #ifdef WITHOUT_CFSETSPEED
+ if (rs232_cfsetspeed(&term_attr, baudrate) < 0) {
+ fprintf(stderr, "Error in rs232_cfsetspeed\n");
+ return -1;
+ }
+ #else /* WITHOUT_CFSETSPEED */
+ if (cfsetspeed(&term_attr, baudrate) < 0) {
+ fprintf(stderr, "Error in cfsetspeed\n");
+ return -1;
+ }
+ #endif /* WITHOUT_CFSETSPEED */
+
+ if (tcsetattr(dev, TCSAFLUSH, &term_attr)) {
+ perror("setup_dev: tcsetattr");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* * * * */
+
+static const char *isp_response_code[] = {
+ "CMD_SUCCESS",
+ "INVALID_COMMAND",
+ "SRC_ADDR_ERROR: Source address is not on word boundary",
+ "DST_ADDR_ERROR: Destination address is not on a correct boundary",
+ "SRC_ADDR_NOT_MAPPED: Source address is not mapped in the memory map",
+ "DST_ADDR_NOT_MAPPED: Destination address is not mapped in the memory map",
+ "COUNT_ERROR: Byte count is not multiple of 4 or is not a permitted value",
+ "INVALID_SECTOR: Sector number is invalid or end sector number is "
+ " greater than start sector number.",
+ "SECTOR_NOT_BLANK",
+ "SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION:"
+ " Command to prepare sector for write operation was not executed",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+};
+
+typedef enum _response_type_t {
+ NO_RESPONSE,
+ NUM_RESPONSE,
+ OK_RESPONSE
+} resp_type_t;
+
+int poll_input(FILE *stream, long tv_sec, long tv_usec) {
+ fd_set sel_set;
+ struct timeval timeout;
+ int sel, comm_dev = fileno(stream);
+
+ FD_ZERO(&sel_set);
+ FD_SET(comm_dev, &sel_set);
+ timeout.tv_sec = tv_sec;
+ timeout.tv_usec = tv_usec;
+ sel = select(comm_dev+1, &sel_set, NULL, NULL, &timeout);
+ if (sel == -1)
+ perror("poll_input: select");
+ return(sel);
+}
+
+int send_line(FILE *comm, resp_type_t response_type, char *line) {
+ char s[160], *p;
+ int sel, resp;
+ size_t size;
+
+ /* send command */
+ /*
+ according to documentation, \n should be sufficient
+ -- works well with commands, but uuencoded data transmission
+ seems to not work well with it; so using \r\n instead
+ */
+ if (fprintf(comm, "%s\r\n", line) < 0) {
+ perror("send_line: fprintf");
+ return -1;
+ }
+
+ /* check echo, 1s timeout */
+ if ((sel = poll_input(comm, 1, 0)) < 1) {
+ if (sel == 0)
+ fprintf(stderr, "send_line: command echo timeout\n");
+ else
+ perror("send_line: select");
+ return(1);
+ }
+ fgets(s, sizeof(s), comm);
+ /*DEBUG*/printf(":%s", s);
+ if (strncmp(line, s, strlen(line))) {
+ fprintf(stderr, "send_line: \"%s\" command echo mismatch (\"%s\" received)\n", line, s);
+ return(1);
+ }
+
+ if (response_type == NO_RESPONSE)
+ return 0;
+
+ p=s;
+ /* read with timout for every character (necessary for go command) */
+ do {
+ /* check response, 1s timeout */
+ if ((sel = poll_input(comm, 1, 0)) < 1) {
+ *p = '\0';
+ /*DEBUG*/printf(">%s", s);
+ fflush(stdout);
+ if (sel == 0) {
+ fprintf(stderr, "send_line: \"%s\" command response timeout\n", line);
+ }
+ else
+ perror("send_line: select");
+ return(1);
+ }
+ /* read one character */
+ size = fread(p, 1, 1, comm);
+ p++;
+ } while (*(p-1) != '\n');
+
+ *p = '\0';
+ /*DEBUG*/printf(">%s", s);
+
+ if (response_type == OK_RESPONSE) {
+ /* textual response -- expecting "OK" */
+ resp = (strncmp(s, "OK", 2) != 0);
+ if (resp)
+ fprintf(stderr, "Received something else than \"OK\"\n");
+ return(resp);
+ }
+ else {
+ /* numeric response */
+ if (sscanf(s, "%d", &resp) == 0) {
+ fprintf(stderr, "Invalid (non-numeric) command response received\n");
+ return(-1);
+ }
+ if (resp)
+ fprintf(stderr, "Error response code %d\n", resp);
+ return(resp);
+ }
+}
+
+int send_line_fmt(FILE *comm, resp_type_t resp, const char *fmt, ...) {
+ char s[160];
+ va_list ap;
+
+ va_start(ap, fmt);
+ vsprintf(s, fmt, ap);
+ va_end(ap);
+ return send_line(comm, resp, s);
+}
+
+#define MAX_SYNC_QM_TRIES 240
+int synchronize(FILE *comm, int crystal_freq) {
+ int n, sel;
+ char ch = '\0';
+ char sync_string[] = "Synchronized\n";
+ int sync_status = 0, sync_pos = 0, sync_len = strlen(sync_string);
+
+ printf("Synchronizing");
+ /* send '?'s and wait for response */
+ for (n = 0; n < MAX_SYNC_QM_TRIES; n++) {
+ /* if not receiving "Synchronized" response, send '?'s */
+ if (!sync_status) {
+ fputc('?', comm);
+ fflush(comm);
+ }
+
+ /* poll for input */
+ /* 0.1s is duration of 3 characters in 8N1 300b/s transfer */
+ sel = poll_input(comm, 0, 100000);
+ if (sel == -1) {
+ perror("synchronize: select");
+ return(1);
+ }
+
+ if (sel > 0) {
+ ch = fgetc(comm);
+ if (ch == sync_string[sync_pos]) {
+ if (sync_pos == 0)
+ sync_status = 1;
+ sync_pos++;
+ if (sync_pos == sync_len) {
+ printf("\n\"Synchronized\" received (recv. %d chars)\n", n);
+ break;
+ }
+ }
+ else {
+ sync_status = 0;
+ sync_pos = 0;
+ }
+ }
+ /* show progress */
+ if (!sync_status) {
+ putchar(sel ? ((ch == '?') ? '.' : 'x') : '_');
+ fflush(stdout);
+ }
+ }
+ if (n == MAX_SYNC_QM_TRIES) {
+ fprintf(stderr, "Didn't synchronize after %d tries.\n", n);
+ return(1);
+ }
+ /*
+ * here may be comm.dev mode switched back to ICANON...
+ */
+ /* respond to sync */
+ if (send_line(comm, OK_RESPONSE, "Synchronized"))
+ return(1);
+ printf("Synchronized, OK.\n");
+ /* send Xtal frequency */
+ printf("Sending crystal frequency: %d\n", crystal_freq);
+ //sprintf(s, "%d", crystal_freq);
+ if (send_line_fmt(comm, OK_RESPONSE, "%d", 7373)) //crystal_freq))
+ return 1;
+
+ return 0;
+}
+
+struct termios comm_attr_save;
+
+void close_comm(FILE *comm) {
+ /* restore serial line settings */
+ tcsetattr(fileno(comm), TCSANOW, &comm_attr_save);
+ fclose(comm);
+}
+
+FILE *open_comm(char *device, int baudrate, int flowc) {
+ FILE *comm;
+ int comm_dev, line;
+
+ /* TODO: Open the serial line the same way as lpc21isp. It seems
+ * that loading works even if there is terminal emulator attached to
+ * the same port. */
+ if ((comm = fopen(device, "r+")) == NULL) {
+ perror("open_comm: fopen");
+ return(NULL);
+ }
+ /* set stream as unbuffered */
+ setbuf(comm, NULL);
+
+ comm_dev = fileno(comm);
+ /* backup serial line settings */
+ if (tcgetattr(comm_dev, &comm_attr_save))
+ fprintf(stderr, "Warning: open_comm: can not get serial line settings by tcgetattr");
+ /* setup serial device parameters */
+ setup_comm_dev(comm_dev, baudrate, flowc);
+
+ /* initialize serial bootloader (on miniARM_DB board) */
+ ioctl (comm_dev, TIOCMGET, &line);
+ line |= TIOCM_DTR;
+ ioctl (comm_dev, TIOCMSET, &line);
+ usleep(1000*1000);
+ line &= ~TIOCM_DTR;
+ ioctl (comm_dev, TIOCMSET, &line);
+ usleep(100*1000);
+
+ return(comm);
+}
+
+/* * * * */
+
+int write_ram(FILE *comm, unsigned start, unsigned length, char *data) {
+ char s[100];
+ int i, line, line_len;
+ unsigned count = length;
+ unsigned checksum;
+
+ sprintf(s, "W %u %u", start, length);
+ if (send_line(comm, NUM_RESPONSE, s))
+ return(1);
+ while (count > 0) {
+ checksum = 0;
+ for (line = 0; (line < 20) && (count > 0); line++) {
+ line_len = (count < 45) ? count : 45;
+ for (i = 0; i < line_len; i++)
+ checksum += (unsigned char)data[i];
+ uuencode_line(s, data, line_len);
+ count -= line_len;
+ data += line_len;
+ if (send_line(comm, NO_RESPONSE, s))
+ return(1);
+ }
+ sprintf(s, "%u", checksum);
+ if (send_line(comm, OK_RESPONSE, s))
+ return(1);
+ }
+ return 0;
+}
+
+/* * * * */
+
+int tolpc_send_cmd(struct tolpc_env *env, char *fmt, ...) {
+ va_list ap;
+ char s[160];
+
+ if (env->comm_stream == NULL)
+ if (tolpc_open_target(env))
+ return -1;
+
+ va_start(ap, fmt);
+ vsprintf(s, fmt, ap);
+ va_end(ap);
+
+ return send_line(env->comm_stream, NUM_RESPONSE, s);
+}
+
+int tolpc_readline_to(struct tolpc_env *env, char *s, int size) {
+ fgets(s, size, env->comm_stream);
+ return 0;
+}
+
+int tolpc_open_target(struct tolpc_env *env) {
+ FILE *comm;
+
+ comm = open_comm(env->sdev, env->baud, FLOWC_XONXOFF);
+ if (comm == NULL)
+ return -1;
+ if (synchronize(comm, env->crystal))
+ return -1;
+
+ env->comm_stream = comm;
+ return 0;
+}
+
+int tolpc_write_ram(struct tolpc_env *env, unsigned int start, int length, unsigned char *data) {
+ return write_ram(env->comm_stream, start, length, data);
+}
+
+/* * */
+
+int tolpc_unlock(struct tolpc_env *env) {
+ int ret;
+ ret = tolpc_send_cmd(env, "U 23130");
+ return ret;
+}
+
+int tolpc_go(struct tolpc_env *env, unsigned int start, char arm_mode)
+{
+ int ret;
+
+ ret = tolpc_send_cmd(env, "G %u %c", start, arm_mode ? 'A' : 'T');
+ if (ret == 2)
+ {
+ verbose(1, "Timeout means the code is executed\n");
+ ret = 0;
+ }
+ return ret;
+}
+
+/**
+ * Reads part ID
+ * @param env
+ * @param part_id Where to store received part id.
+ * @param size Size of part_id.
+ * @return Zero on success, -1 on error.
+ */
+int tolpc_partid(struct tolpc_env *env, char* part_id, int size)
+{
+ int ret;
+
+ ret = tolpc_send_cmd(env, "J");
+ if (ret) return ret;
+
+ ret = tolpc_readline_to(env, part_id, size);
+ return ret == 0 ? 0 : -1;
+}
+
+/**
+ * Reads boot code version
+ * @param env
+ * @param ver Where to store received version.
+ * @param size Size of ver.
+ * @return Zero on success, -1 on error.
+ */
+int tolpc_bootver(struct tolpc_env *env, char* ver, int size)
+{
+ int ret;
+
+ ret = tolpc_send_cmd(env, "K");
+ if (ret) return ret;
+
+ ret = tolpc_readline_to(env, ver, size);
+ return ret == 0 ? 0 : -1;
+}
+
+/**
+ * Sets echo mode
+ * @param env
+ * @return Zero on success, 1 on bad response, -1 on communication error.
+ */
+int tolpc_echo(struct tolpc_env *env, char on)
+{
+#if 0
+ int ret;
+ ret = tolpc_send_cmd(env, "A %c", on);
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int tolpc_break(struct tolpc_env *env)
+{
+#if 0
+ int fd;
+ int i;
+ char c = 0;
+
+ /* Open RS232 device */
+ if ((fd = open(env->sdev, O_RDWR | O_NONBLOCK)) == -1) {
+ printf("Error openning %s\n", env->sdev);
+ return -1;
+ }
+
+ if (rs232_setmode(fd, env->baud / 2, 0) < 0) {
+ close(fd);
+ return -1;
+ }
+
+ #if DEBUG
+ printf("Sending break chars \n");
+ #endif
+
+ for (i = 100;i--;)
+ write(fd, &c, 1);
+
+ close(fd);
+#endif
+ return 1;
+}
--- /dev/null
+#ifndef _TOLPC_FN_H
+#define _TOLPC_FN_H
+
+#include <bfd.h>
+
+extern int tolpc_verbose_level;
+
+struct tolpc_env {
+ // File descriptor and stream of open serial line
+ int fd;
+ //FILE *f;
+
+ char *sdev; // Serial device to open
+ int baud; // Communication baudrate
+ int crystal; // Crtystal freq of LPC21xx
+ long waitrep; // How long to wait for reply.
+ FILE *comm_stream;
+};
+
+void tolpc_verbose(int level, const char *fmt, ...);
+//int tolpc_synchronize(struct tolpc_env *env);
+
+int tolpc_open_target(struct tolpc_env *env);
+int tolpc_go(struct tolpc_env *env, unsigned int start, char arm_mode);
+int tolpc_partid(struct tolpc_env *env, char* part_id, int size);
+int tolpc_break(struct tolpc_env *env);
+int tolpc_write_ram(struct tolpc_env *env, unsigned int start, int length, unsigned char *data);
+int tolpc_unlock(struct tolpc_env *env);
+int tolpc_bootver(struct tolpc_env *env, char* part_id, int size);
+int tolpc_echo(struct tolpc_env *env, char on);
+
+#endif /* _TOLPC_FN_H */
+
+
--- /dev/null
+/*
+* C Implementation: uuencode
+*
+* Description:
+*
+*
+* Author: Michal Sojka <sojkam1@fel.cvut.cz>, (C) 2005
+*
+* Copyright: See COPYING file that comes with this distribution
+*
+*/
+
+#include <inttypes.h>
+#include "uuencode.h"
+
+static char uuencode_table[64];
+static char initialized = 0;
+/**
+ * Initializes uuencode_table.
+ */
+void uuencode_init() {
+ int i;
+ uuencode_table[0] = 0x60;
+
+ for(i = 1; i < 64; i++) {
+ uuencode_table[i] = (char)(0x20 + i);
+ }
+ initialized = 1;
+}
+
+/**
+ * Uuencodes up to 45 bytes of data. The output string is not terminated by any newline character.
+ * @param dest Where to store output string. There should be space at least for 62 bytes.
+ * @param source
+ * @param length
+ * @return Zero on success, -1 on error.
+ */
+int uuencode_line(char *dest, unsigned char *source, int length) {
+ int i;
+ int data = 0;
+
+ if (!initialized)
+ uuencode_init();
+
+ if (length > 45 || length < 0)
+ return -1;
+
+ *dest++ = uuencode_table[length];
+ for (i = 0; i < length; i+=3) {
+ data = *source++;
+ data = (data << 8) | ((i+1 < length) ? *source++ : 0);
+ data = (data << 8) | ((i+2 < length) ? *source++ : 0);
+
+ *dest++ = uuencode_table[(data >> 18) & 0x3f];
+ *dest++ = uuencode_table[(data >> 12) & 0x3f];
+ *dest++ = uuencode_table[(data >> 6) & 0x3f];
+ *dest++ = uuencode_table[ data & 0x3f];
+ }
+ *dest = '\0';
+ return 0;
+}
--- /dev/null
+//
+// C++ Interface: uuencode
+//
+// Description:
+//
+//
+// Author: Michal Sojka <sojkam1@fel.cvut.cz>, (C) 2005
+//
+// Copyright: See COPYING file that comes with this distribution
+//
+//
+
+#ifndef _UUENCODE_H
+#define _UUENCODE_H
+
+int uuencode_line(char *dest, unsigned char *source, int length);
+
+#endif
--- /dev/null
+../common/arch/generic
\ No newline at end of file
--- /dev/null
+../common/board/Makefile
\ No newline at end of file
--- /dev/null
+../common/board/Makefile.omk
\ No newline at end of file
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# -*- makefile -*-
+
+ARCH=arm
+MACH=lpc21xx
+BOARD=lpceurobot
+
+CROSS_COMPILE = arm-elf-
+TARGET_ARCH = -mcpu=arm7tdmi
+LOADLIBES += -leurobothw
+
+# Set default C flags. If theese are set elsewhere (e.g. on a command
+# line), these default flags are not used.
+DEBUG ?= -g
+OPTIMIZE ?= -O2
+
+LPC_BAUD = 38400
+LPC_TTY ?= /dev/ttyUSB0
+LPC_XTAL = 14745
+TOLPC = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tolpc --baud $(LPC_BAUD) --sdev $(LPC_TTY) -q $(LPC_XTAL) -v -L -f
+LOAD_CMD-ram = $(TOLPC)
+LOAD_CMD-flash = load() { HEX=$(LOCAL_BUILD_DIR)/$$(basename $$1).hex; $(CROSS_COMPILE)objcopy -O ihex $$1 $$HEX; $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/lpc21isp -control $(LPC_TTY) $(LPC_BAUD) $(LPC_XTAL) $$HEX; }; load
+
+
+#LOAD_CMD-ramisp = $(TOLPC)
+LOAD_CMD-mpram = $(TOLPC)
+LOAD_CMD-mpflash = $(LOAD_CMD-flash)
+
+# $(CROSS_COMPILE)objcopy -O ihex in out
+# lpc21isp vstup.hex $(LPC_TTY) $(LPC_BAUD) $(LPC_XTAL)
+
+# This selects linker script
+LD_SCRIPT=lpc21xx
+DEFAULT_LD_SCRIPT_VARIANT=ram flash
+
+#OUTPUT_FORMATS = bin hex srec
+
+###
+CONFIG_USB_BASE=
+CONFIG_USB_PDIUSB=
+CONFIG_USB_MORE=
+CONFIG_CMDPROC_TEST=n
+
+LN_HEADERS=y
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def.h - common cover for definition of hardware adresses,
+ registers, timing and other hardware dependant
+ parts of embedded hardware
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_H_
+#define _SYSTEM_DEF_H_
+
+#include <types.h>
+
+#define WITH_SFI_SEL
+
+#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
+/* Software version */
+#define SW_VER_ID "LPCEUROBOT"
+#define SW_VER_MAJOR 0
+#define SW_VER_MINOR 1
+#define SW_VER_PATCH 0
+#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
+/* Hardware version */
+#define HW_VER_ID "LPCEUROBOT"
+#define HW_VER_MAJOR 1
+#define HW_VER_MINOR 0
+#define HW_VER_PATCH 0
+#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
+/* Version of mechanical */
+#define MECH_VER_ID "LPCEUROBOT"
+#define MECH_VER_MAJOR 0
+#define MECH_VER_MINOR 0
+#define MECH_VER_PATCH 0
+#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
+
+#define BOARD_LPCEUROBOT
+
+#define CPU_REF_HZ 14745000l /* reference clock */
+#define CPU_SYS_HZ (4*CPU_REF_HZ)/* system clock */
+#define CPU_APB_HZ (CPU_SYS_HZ/2)/* APB clock */
+#define CPU_VPB_HZ CPU_APB_HZ /* VPB clock = APB clock, multiple definition */
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+
+#define SCI_RS232_CHAN_DEFAULT 1
+
+/* #define DEB_LED_INIT() \ */
+/* do {\ */
+/* *DIO_PEDR=0x00;\ */
+/* SHADOW_REG_SET(DIO_PEDDR,0x0f); /\* set PJ.1, PJ.2, PJ.3 LED output *\/ \ */
+/* } while (0) */
+
+/* #define DEB_LED_OFF(num) \ */
+/* (*DIO_PEDR |= PEDR_PE0DRm << (num)) */
+/* #define DEB_LED_ON(num) \ */
+/* (*DIO_PEDR &=~(PEDR_PE0DRm << (num))) */
+
+
+#endif /* _SYSTEM_DEF_H_ */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+include_HEADERS = deb_led_board.h
+
+SUBDIRS = hwinit
--- /dev/null
+#ifndef DEB_LED_BOARD_H
+#define DEB_LED_BOARD_H
+
+#include <lpc21xx.h>
+
+#define __LED_SHIFT 21
+#define __LED_MASK 0x0f
+
+#define LEDR (1<<0) // LED R (1<<21)
+#define LEDG (1<<1) // LED G (1<<22)
+#define LEDB (1<<2) // LED B (1<<23)
+#define LEDY (1<<3) // LED Y (1<<24)
+
+#define DEB_LED_ERROR LEDR /* Error occured */
+#define DEB_LED_RUN LEDG /* Should blink when running */
+
+static inline unsigned
+__deb_led_get()
+{
+ return (IOPIN0 >> __LED_SHIFT) & __LED_MASK;
+}
+
+static inline void
+__deb_led_on(unsigned leds)
+{
+ IOSET0 = (leds & __LED_MASK) << __LED_SHIFT;
+}
+
+static inline void
+__deb_led_off(unsigned leds)
+{
+ IOCLR0 = (leds & __LED_MASK) << __LED_SHIFT;
+}
+
+static inline void
+__deb_led_set(unsigned leds)
+{
+ __deb_led_on(leds);
+ __deb_led_off(~leds);
+}
+
+static inline void
+__deb_led_change(unsigned leds)
+{
+ __deb_led_set(__deb_led_get() ^ leds);
+}
+
+static inline void
+__deb_led_init()
+{
+ IO0DIR |= (__LED_MASK << __LED_SHIFT);
+ __deb_led_set(0);
+}
+
+#endif
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+lib_LIBRARIES = eurobothw
+eurobothw_SOURCES = startcfg.c error.c
+
+include_HEADERS = error.h
+
+test_PROGRAMS = hwinit_test
+hwinit_test_SOURCES = test.c
+
+lib_obj_SOURCES = hwinit.c
+
+lib_LDSCRIPTS = board.ld
--- /dev/null
+/* Board specific objects linked with applications */
+INPUT(initarray.o hwinit.o)
--- /dev/null
+#include <deb_led.h>
+#include <error.h>
+
+static void
+waitblink(int len)
+{
+ while (len--) {
+ unsigned int i =2000000;
+ while(--i);
+ }
+}
+
+void error(enum error err)
+{
+ if (err == SUCCESS)
+ return;
+ /* For case of unintetional rewrite of IO port setting. */
+ deb_led_init();
+ while (1) {
+ int i;
+ for (i=7; i>=0; i--) {
+ deb_led_set(~0);
+ if (err & (1<<i))
+ waitblink(3); /* 1 */
+ else
+ waitblink(1); /* 0 */
+ deb_led_set(DEB_LED_ERROR);
+ waitblink(1);
+
+ }
+ waitblink(5);
+ }
+}
--- /dev/null
+#ifndef ERROR_H
+#define ERROR_H
+
+enum error {
+ SUCCESS = 0,
+ ERANGE = 11,
+};
+
+void error(enum error err);
+
+#endif
--- /dev/null
+#include <lpc21xx.h> /* LPC21xx definitions */\r
+#include <deb_led.h>\r
+#include "startcfg.h"\r
+#include <stdlib.h>\r
+#include <error.h>\r
+\r
+/* Called automatically from crt0.S before main() */\r
+/* void __hardware_init(void) __attribute__ ((used)); */\r
+void __hardware_init(void)\r
+{\r
+ int err = SUCCESS;\r
+\r
+ if ((void*)&__hardware_init > (void*)0x40000000) {\r
+ /* We are running from RAM */\r
+ MEMMAP = 0x2; /* Remap interrupt vectors */\r
+ }\r
+\r
+ deb_led_init();\r
+ \r
+ err = init_PLL(PLL_MUL_4 ,PLL_DIV_2 ,PLL_MODE_ENABLE); //58.98MHz\r
+ if (err) error(err);\r
+ \r
+ err = init_MAM(MAM_FULL); //58.98MHz\r
+ if (err) error(err);\r
+\r
+ set_APB(APB_DIV_2);\r
+
+\r
+}\r
+\r
+/* Put a pointer to this function in .init_array section */\r
+void (*fp) (void) __attribute__ ((section (".init_array"))) = __hardware_init;\r
--- /dev/null
+#include "startcfg.h"\r
+#include <errno.h> \r
+#include <lpc21xx.h> /* LPC21xx definitions */\r
+\r
+\r
+// ----------------- PLL part ------------------------\r
+#define PLL_OFF 0 // fully disable PLL\r
+#define PLL_ACTIVE 1 // activate PLL \r
+#define PLL_CONNECT 3 // connect PLL to Cclk\r
+\r
+#define PLL_FEED_1 0xAA // PLL feed sequence 1\r
+#define PLL_FEED_2 0x55 // PLL feed sequence 3 \r
+#define PLL_LOCK_MASK 0x400 // PLL lock mask\r
+\r
+\r
+\r
+#define PLL_DIV_MASK_2 (0<<5)\r
+#define PLL_DIV_MASK_4 (1<<5)\r
+#define PLL_DIV_MASK_8 (2<<5)\r
+#define PLL_DIV_MASK_16 (3<<5)\r
+\r
+// ----------------- MAM part ------------------------\r
+\r
+#define MAM_1ST_BOUND 20000\r
+#define MAM_2ND_BOUND 40000\r
+#define MAM_TIM_1 1\r
+#define MAM_TIM_2 2\r
+#define MAM_TIM_3 3\r
+\r
+\r
+//------------------ code ----------------------------\r
+\r
+void wait(void)\r
+{\r
+ unsigned int i =2000000;\r
+ while(--i);\r
+}\r
+\r
+\r
+void deb_led(char leds)\r
+{\r
+ IO0DIR |= ((1<<21) | (1<<22) | (1<<23) | (1<<24));\r
+\r
+ if (leds & 0x1) IOSET0 |= (1<<21);\r
+ else IOCLR0 |= (1<<21);\r
+\r
+ if (leds & 0x2) IOSET0 |= (1<<22);\r
+ else IOCLR0 |= (1<<22);\r
+\r
+ if (leds & 0x4) IOSET0 |= (1<<23);\r
+ else IOCLR0 |= (1<<23);\r
+\r
+ if (leds & 0x8) IOSET0 |= (1<<24);\r
+ else IOCLR0 |= (1<<24);\r
+}\r
+\r
+\r
+\r
+\r
+\r
+// setup procesor PLL\r
+unsigned char init_PLL(char mul,char div, char mode)\r
+{\r
+ \r
+ unsigned int fcco, cclk; \r
+\r
+\r
+ PLLCON = PLL_OFF; // disable PLL \r
+ PLLFEED = PLL_FEED_1; // PLL change sequence\r
+ PLLFEED = PLL_FEED_2;\r
+ \r
+ if (mode == PLL_MODE_DISABLE)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ fcco = FOSC * 2 * (mul + 1) * div ; // count Fcco\r
+ if (( FCCO_MIN > fcco)|(fcco > FCCO_MAX)) // check Fcco range\r
+ {\r
+ return ERANGE;\r
+ }\r
+\r
+ cclk = (mul + 1) * FOSC; // count cclk\r
+ if (( CCLK_MIN > cclk)|(cclk > CCLK_MAX)) // check cclk range\r
+ {\r
+ return ERANGE;\r
+ }\r
+\r
+ switch(div)\r
+ {\r
+ case(PLL_DIV_2): div = PLL_DIV_MASK_2;\r
+ break;\r
+\r
+ case(PLL_DIV_4): div = PLL_DIV_MASK_4;\r
+ break;\r
+\r
+ case(PLL_DIV_8): div = PLL_DIV_MASK_8;\r
+ break;\r
+\r
+ case(PLL_DIV_16): div = PLL_DIV_MASK_16;\r
+ break;\r
+\r
+ default: return ERANGE;\r
+ }\r
+\r
+\r
+ PLLCFG = mul | div; // write multiplicator and dividet to PLL config\r
+ PLLCON = PLL_ACTIVE; // enable PLL \r
+ PLLFEED = PLL_FEED_1; // PLL change sequence\r
+ PLLFEED = PLL_FEED_2;\r
+\r
+ while( (PLLSTAT & PLL_LOCK_MASK) == 0); // wait for PLL LOCK\r
+\r
+ PLLCON = PLL_CONNECT; // connect PLL to Cclk\r
+ PLLFEED = PLL_FEED_1; // PLL change sequence\r
+ PLLFEED = PLL_FEED_2;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+// get procesor speed\r
+unsigned int get_sys_speed(void)\r
+{\r
+ if( (PLLCON & PLL_CONNECT) == PLL_CONNECT) // if PLL is connected return PLL-Cclk speed\r
+ {\r
+ return( FOSC * ((PLLCFG & 0x1F) + 1));\r
+ }\r
+\r
+ return FOSC; // if PLL is disabled return native Fosc\r
+\r
+}\r
+\r
+\r
+// setup MAM module\r
+\r
+unsigned char init_MAM(char mode)\r
+{\r
+ unsigned int clk;\r
+\r
+ MAMCR = MAM_OFF;\r
+\r
+ #ifdef MEM_RAM // FIXME udelat pomoci linker scriptu\r
+ return 0;\r
+ #endif\r
+\r
+\r
+ if (mode == MAM_OFF) return 0;\r
+ \r
+\r
+ clk = get_sys_speed();\r
+\r
+ if(clk > MAM_2ND_BOUND)\r
+ {\r
+ MAMTIM = MAM_TIM_3; \r
+ } \r
+ else if (clk > MAM_1ST_BOUND) \r
+ {\r
+ MAMTIM = MAM_TIM_2;\r
+ }\r
+ else MAMTIM = MAM_TIM_1;\r
+\r
+ MAMCR = mode;\r
+\r
+ return 0;\r
+}\r
+\r
+// setup APB module\r
+unsigned char set_APB(char div)\r
+{\r
+ VPBDIV = div;\r
+ return 0;\r
+}\r
+\r
+\r
+unsigned int get_apb_speed(void)\r
+{\r
+ int sysClk,div;\r
+\r
+ switch( VPBDIV & 0x03)\r
+ {\r
+ case APB_DIV_1: div = 1;\r
+ break;\r
+\r
+ case APB_DIV_2: div = 2;\r
+ break;\r
+\r
+ case APB_DIV_4: div = 4;\r
+ break;\r
+\r
+ default: return ERANGE;\r
+ }\r
+\r
+\r
+ sysClk = get_sys_speed();\r
+\r
+ return (sysClk / div);\r
+\r
+\r
+}\r
+\r
+\r
--- /dev/null
+\r
+\r
+\r
+/** Fosc is crystal oscilator / resonator\r
+ * If is not defined, is used 14,745MHz nominal oscilator (CTU DRAGONS LPC BOARD )\r
+ */\r
+#ifndef FOSC // FIXME: rename to CPU_REF_HZ\r
+ #define FOSC 14745\r
+#endif\r
+\r
+\r
+/** If memory is in RAM, it must be defined! Otherwise is defined MEM_FLASH\r
+ * This is important for MAM module.\r
+ */\r
+#ifndef MEM_RAM\r
+ #define MEM_FLASH \r
+#endif\r
+\r
+\r
+/// Absolute minimum and maximum ratings\r
+#define FCCO_MIN 156000 // internal minimal clock\r
+#define FCCO_MAX 320000 // internal maximal clock\r
+#define CCLK_MIN 10000 // processor minimal clock\r
+#define CCLK_MAX 60000 // processor maximal clock\r
+\r
+\r
+/// PLL Available multiplicators \r
+#define PLL_MUL_1 0\r
+#define PLL_MUL_2 1\r
+#define PLL_MUL_3 2\r
+#define PLL_MUL_4 3\r
+#define PLL_MUL_5 4\r
+#define PLL_MUL_6 5\r
+#define PLL_MUL_7 6\r
+\r
+/// PLL Available divisors\r
+#define PLL_DIV_2 2\r
+#define PLL_DIV_4 4\r
+#define PLL_DIV_8 8\r
+#define PLL_DIV_16 16\r
+\r
+/// PLL mode\r
+#define PLL_MODE_DISABLE 1\r
+#define PLL_MODE_ENABLE 0\r
+\r
+/// MAM definitions\r
+#define MAM_OFF 0 // MAM functions disabled\r
+#define MAM_PARTIAL 1 // MAM functions partially enabled\r
+#define MAM_FULL 2 // MAM functions fully enabled\r
+\r
+\r
+/// APB divider\r
+///@{\r
+#define APB_DIV_1 1\r
+#define APB_DIV_2 2\r
+#define APB_DIV_4 0\r
+///@}\r
+\r
+\r
+\r
+\r
+\r
+void wait(void); // in future this should be deleted\r
+\r
+\r
+\r
+/** deb_led controls system debug leds\r
+ * @param leds LED value\r
+ */\r
+void deb_led(char leds);\r
+\r
+/** Enables PLL for higher Fosc values\r
+ * @return 0 or #ERANGE\r
+ * @param mul PLL multiplicator\r
+ * @param div PLL divider\r
+ * @param disable disables PLL\r
+ */\r
+unsigned char init_PLL(char mul,char div, char mode);\r
+\r
+/** get_sys_speed returns actual speed of Cclk (proc. frequency) in kHz\r
+ */\r
+unsigned int get_sys_speed(void);\r
+\r
+\r
+/** Setup MAM module\r
+ * @return 0 or ERANGE\r
+ * @param mode MAM mode\r
+ */\r
+unsigned char init_MAM(char mode);\r
+\r
+/** Sets APB divisor\r
+ * @return 0 \r
+ * @note VPB = APB - name conflict FIXME\r
+ * @param div divisor of APB\r
+ */\r
+unsigned char set_APB(char div);\r
+\r
+/** Returns actual speed of APB (peripheral frequency) in kHz\r
+ * @note VPB = APB - name conflict FIXME\r
+ */\r
+unsigned int get_apb_speed(void);\r
+\r
--- /dev/null
+#include <lpc21xx.h> /* LPC21xx definitions */
+#include <errno.h>
+#include "startcfg.h"
+#include <deb_led.h>
+
+extern unsigned int adc_val[4];
+
+#define LEDS 4
+
+int main (void)
+{
+ unsigned leds[] = {LEDR, LEDG, LEDB, LEDY};
+ int i=0;
+ while(1)
+ {
+ deb_led_set(leds[i]);
+ if (++i == LEDS) i=0;
+ wait();
+
+ }
+ return 0;
+}
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# -*- makefile -*-
+
+ARCH=arm
+MACH=lpc21xx
+BOARD=miniarm
+
+CROSS_COMPILE = arm-elf-
+TARGET_ARCH = -mcpu=arm7tdmi
+
+# Set default C flags. If theese are set elsewhere (e.g. on a command
+# line), these default flags are not used.
+DEBUG ?= -g
+OPTIMIZE ?= -O2
+
+LPC_BAUD = 38400
+TOLPC = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tolpc --baud $(LPC_BAUD) --sdev /dev/ttyS0
+LOAD_CMD-ramisp = $(TOLPC) -v -q 7372 -L -f
+LOAD_CMD-mpram = $(TOLPC) -v -q 7372 -L -f
+
+# This selects linker script
+LD_SCRIPT=lpc21xx
+DEFAULT_LD_SCRIPT_VARIANT=ramisp
+
+#OUTPUT_FORMATS = bin hex srec
+
+CONFIG_USB_BASE=n
+CONFIG_USB_PDIUSB=n
+CONFIG_USB_MORE=n
+
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*))
--- /dev/null
+/**************************** lpc210x.ld ********************************/\r
+/* Copyright 2003/12/30 Aeolus Development */\r
+/* */\r
+/* Freely modifiable and redistributable. Modify to suit your own needs*/\r
+/* Please remove Aeolus Development copyright for any significant */\r
+/* modifications or add explanatory notes to explain the mods and */\r
+/* list authour(s). */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE AEOULUS DEVELOPMENT "AS IS" AND ANY */\r
+/* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */\r
+/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AEOLUS DEVELOPMENT BE */\r
+/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */\r
+/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */\r
+/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */\r
+/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,*/\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */\r
+/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/************************************************************************/\r
+/*\r
+* TLIB revision history:\r
+* 1 lpc2119.ld 17-Jun-2004,16:08:28,`RADSETT' Original archive version\r
+* 2 lpc2119.ld 21-Jul-2004,11:31:02,`RADSETT' Increase interrupt stack sizes.\r
+* TLIB revision history ends.\r
+*/\r
+\r
+/* Search directories for libraries. Modify as needed. */\r
+\r
+/*\r
+SEARCH_DIR( /home/cabrit/arm/test)\r
+SEARCH_DIR( /usr/arm-elf/lib)\r
+SEARCH_DIR( /home/lib/gcc-lib/i486-linux/3.3.5)\r
+*/\r
+\r
+/* Memory layout for processor. Modify RAM size upwards for 2105 and */\r
+/* 2106 */\r
+\r
+MEMORY {\r
+ flash : ORIGIN = 0, LENGTH = 120K\r
+ ram : ORIGIN = 0x40000000, LENGTH = 16K\r
+ }\r
+\r
+__ram_size__ = 16K;\r
+\r
+__STACK_SIZE_FIQ__ = 0x100;\r
+__STACK_SIZE_IRQ__ = 0x100;\r
+__STACK_SIZE_SUPERVISOR__ = 0x4;\r
+__STACK_SIZE_ABORT__ = 0x4;\r
+__STACK_SIZE_UNDEFINED__ = 0x4;\r
+\r
+__stack_end__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
+ __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__ - __STACK_SIZE_ABORT__ -\r
+ __STACK_SIZE_UNDEFINED__;\r
+__stack_end_undefined__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
+ __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__ - __STACK_SIZE_ABORT__;\r
+__stack_end_abort__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
+ __STACK_SIZE_IRQ__ - __STACK_SIZE_SUPERVISOR__;\r
+__stack_end_supervisor__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__ - \r
+ __STACK_SIZE_IRQ__;\r
+__stack_end_irq__ = 0x40000000 + __ram_size__ - 4 - __STACK_SIZE_FIQ__;\r
+__stack_end_fiq__ = 0x40000000 + __ram_size__ - 4;\r
+\r
+\r
+SECTIONS {\r
+ . = 0; /* Start at address 0. */\r
+ startup : { *(.startup)} >flash /* Place startup first. */\r
+\r
+ prog : { /* Program (.text) sections */\r
+ *(.text) /* are next, then constant data.*/\r
+ *(.rodata)\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >flash\r
+ __end_of_text__ = .; /* Used by startup to find */\r
+ /* initialized vars. */\r
+\r
+ /* Initialized data, located in ram but a copy is placed */\r
+ /* in flash so it can be used to init the ram on startup. */\r
+ .data : { \r
+ __data_beg__ = .; /* Used by startup. */\r
+ __data_beg_src__ = __end_of_text__; /* Used by startup. */\r
+ *(.data)\r
+ __data_end__ = .; /* Used by startup. */\r
+ } >ram AT>flash\r
+\r
+ /* Unitialized data, located in ram, no copy in flash needed */\r
+ /* since startup will zero associated area in RAM. */\r
+ .bss : { \r
+ __bss_beg__ = .; /* Used by startup to find start of */\r
+ /* unitialized variables. */\r
+ *(.bss)\r
+ } >ram\r
+ /* Align here to ensure that the .bss section occupies space up to\r
+ _end. Align after .bss to ensure correct alignment even if the\r
+ .bss section disappears because there are no input sections. */\r
+ . = ALIGN(32 / 8);\r
+ }\r
+ . = ALIGN(32 / 8);\r
+\r
+ /* Used by startup to find end of unitialized variables. */\r
+ _end = .;\r
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; \r
+ PROVIDE (end = .);\r
+\r
+ /* Libraries to link against. */\r
+/* INPUT( -lc -lnewlib -lpc -lc -lgcc ) */\r
+\r
+ /* Provide a default vector for any unhandled interrupts. */\r
+PROVIDE( undefined_instruction_exception = endless_loop);\r
+PROVIDE( software_interrupt_exception = endless_loop);\r
+PROVIDE( prefetch_abort_exception = endless_loop);\r
+PROVIDE( data_abort_exception = endless_loop);\r
+PROVIDE( reserved_exception = endless_loop);\r
+PROVIDE( interrupt_exception = endless_loop);\r
+PROVIDE( fast_interrupt_exception = endless_loop);\r
+\r
+ /* Provide address definitions for any peripheral registers */\r
+ /* used. */\r
+\r
+/* WD */\r
+\r
+PROVIDE( WDMOD = 0xE0000000);\r
+PROVIDE( WDTC = 0xE0000004);\r
+PROVIDE( WDFEED = 0xE0000008);\r
+PROVIDE( WDTV = 0xE000000C);\r
+\r
+/* TIMER 0 */\r
+\r
+PROVIDE( T0IR = 0xE0004000);\r
+PROVIDE( T0TCR = 0xE0004004);\r
+PROVIDE( T0TC = 0xE0004008);\r
+PROVIDE( T0PR = 0xE000400C);\r
+PROVIDE( T0PC = 0xE0004010);\r
+PROVIDE( T0MCR = 0xE0004014);\r
+PROVIDE( T0MR0 = 0xE0004018);\r
+PROVIDE( T0MR1 = 0xE000401C);\r
+PROVIDE( T0MR2 = 0xE0004020);\r
+PROVIDE( T0MR3 = 0xE0004024);\r
+PROVIDE( T0CCR = 0xE0004028);\r
+PROVIDE( T0CR0 = 0xE000402C);\r
+PROVIDE( T0CR1 = 0xE0004030);\r
+PROVIDE( T0CR2 = 0xE0004034);\r
+PROVIDE( T0EMR = 0xE000403C);\r
+\r
+/* TIMER 1 */\r
+\r
+PROVIDE( T1IR = 0xE0008000);\r
+PROVIDE( T1TCR = 0xE0008004);\r
+PROVIDE( T1TC = 0xE0008008);\r
+PROVIDE( T1PR = 0xE000800C);\r
+PROVIDE( T1PC = 0xE0008010);\r
+PROVIDE( T1MCR = 0xE0008014);\r
+PROVIDE( T1MR0 = 0xE0008018);\r
+PROVIDE( T1MR1 = 0xE000801C);\r
+PROVIDE( T1MR2 = 0xE0008020);\r
+PROVIDE( T1MR3 = 0xE0008024);\r
+PROVIDE( T1CCR = 0xE0008028);\r
+PROVIDE( T1CR0 = 0xE000802C);\r
+PROVIDE( T1CR1 = 0xE0008030);\r
+PROVIDE( T1CR2 = 0xE0008034);\r
+PROVIDE( T1CR3 = 0xE0008038);\r
+PROVIDE( T1EMR = 0xE000803C);\r
+\r
+/* UART 0 */\r
+\r
+PROVIDE( U0RBR = 0xE000C000);\r
+PROVIDE( U0THR = 0xE000C000);\r
+PROVIDE( U0DLL = 0xE000C000);\r
+PROVIDE( U0IER = 0xE000C004);\r
+PROVIDE( U0DLM = 0xE000C004);\r
+PROVIDE( U0IIR = 0xE000C008);\r
+PROVIDE( U0FCR = 0xE000C008);\r
+PROVIDE( U0LCR = 0xE000C00C);\r
+PROVIDE( U0LSR = 0xE000C014);\r
+PROVIDE( U0SCR = 0xE000C01C);\r
+\r
+/* UART 1 */\r
+\r
+PROVIDE( U1RBR = 0xE0010000);\r
+PROVIDE( U1THR = 0xE0010000);\r
+PROVIDE( U1DLL = 0xE0010000);\r
+PROVIDE( U1IER = 0xE0010004);\r
+PROVIDE( U1DLM = 0xE0010004);\r
+PROVIDE( U1IIR = 0xE0010008);\r
+PROVIDE( U1FCR = 0xE0010008);\r
+PROVIDE( U1LCR = 0xE001000C);\r
+PROVIDE( U1MCR = 0xE0010010);\r
+PROVIDE( U1LSR = 0xE0010014);\r
+PROVIDE( U1MSR = 0xE0010018);\r
+PROVIDE( U1SCR = 0xE001001C);\r
+\r
+/* PWM */\r
+\r
+PROVIDE( PWMIR = 0xE0014000);\r
+PROVIDE( PWMTCR = 0xE0014004);\r
+PROVIDE( PWMTC = 0xE0014008);\r
+PROVIDE( PWMPR = 0xE001400C);\r
+PROVIDE( PWMPC = 0xE0014010);\r
+PROVIDE( PWMMCR = 0xE0014014);\r
+PROVIDE( PWMMR0 = 0xE0014018);\r
+PROVIDE( PWMMR1 = 0xE001401C);\r
+PROVIDE( PWMMR2 = 0xE0014020);\r
+PROVIDE( PWMMR3 = 0xE0014024);\r
+PROVIDE( PWMMR4 = 0xE0014040);\r
+PROVIDE( PWMMR5 = 0xE0014044);\r
+PROVIDE( PWMMR6 = 0xE0014048);\r
+PROVIDE( PWMPCR = 0xE001404C);\r
+PROVIDE( PWMLER = 0xE0014050);\r
+\r
+/* IIC */\r
+\r
+PROVIDE( I2CONSET = 0xE001C000);\r
+PROVIDE( I2STAT = 0xE001C004);\r
+PROVIDE( I2DAT = 0xE001C008);\r
+PROVIDE( I2ADR = 0xE001C00C);\r
+PROVIDE( I2SCLH = 0xE001C010);\r
+PROVIDE( I2SCLL = 0xE001C014);\r
+PROVIDE( I2CONCLR = 0xE001C018);\r
+\r
+/* SPI/SPI0 */\r
+\r
+PROVIDE( S0PCR = 0xE0020000);\r
+PROVIDE( S0PSR = 0xE0020004);\r
+PROVIDE( S0PPR = 0xE0020008);\r
+PROVIDE( S0PCCR = 0xE002000C);\r
+PROVIDE( S0PINT = 0xE002001C);\r
+\r
+ /* Synonyms for compatibility with the 210x series. */\r
+PROVIDE( SPCR = 0xE0020000);\r
+PROVIDE( SPSR = 0xE0020004);\r
+PROVIDE( SPPR = 0xE0020008);\r
+PROVIDE( SPCCR = 0xE002000C);\r
+PROVIDE( SPINT = 0xE002001C);\r
+\r
+/* RTC */\r
+\r
+PROVIDE( ILR = 0xE0024000);\r
+PROVIDE( CTC = 0xE0024004);\r
+PROVIDE( CCR = 0xE0024008);\r
+PROVIDE( CIIR = 0xE002400C);\r
+PROVIDE( AMR = 0xE0024010);\r
+PROVIDE( CTIME0 = 0xE0024014);\r
+PROVIDE( CTIME1 = 0xE0024018);\r
+PROVIDE( CTIME2 = 0xE002401C);\r
+PROVIDE( SEC = 0xE0024020);\r
+PROVIDE( MINUTE = 0xE0024024);\r
+PROVIDE( HOUR = 0xE0024028);\r
+PROVIDE( DOM = 0xE002402C);\r
+PROVIDE( DOW = 0xE0024030);\r
+PROVIDE( DOY = 0xE0024034);\r
+PROVIDE( MONTH = 0xE0024038);\r
+PROVIDE( YEAR = 0xE002403C);\r
+PROVIDE( ALSEC = 0xE0024060);\r
+PROVIDE( ALMIN = 0xE0024064);\r
+PROVIDE( ALHOUR = 0xE0024068);\r
+PROVIDE( ALDOM = 0xE002406C);\r
+PROVIDE( ALDOW = 0xE0024070);\r
+PROVIDE( ALDOY = 0xE0024074);\r
+PROVIDE( ALMON = 0xE0024078);\r
+PROVIDE( ALYEAR = 0xE002407C);\r
+PROVIDE( PREINT = 0xE0024080);\r
+PROVIDE( PREFRAC = 0xE0024084);\r
+\r
+/* GPIO PORT0 */\r
+\r
+PROVIDE( IO0PIN = 0xE0028000);\r
+PROVIDE( IO0SET = 0xE0028004);\r
+PROVIDE( IO0DIR = 0xE0028008);\r
+PROVIDE( IO0CLR = 0xE002800C);\r
+\r
+ /* Synonyms for compatibility with the 210x series. */\r
+PROVIDE( IOPIN = 0xE0028000);\r
+PROVIDE( IOSET = 0xE0028004);\r
+PROVIDE( IODIR = 0xE0028008);\r
+PROVIDE( IOCLR = 0xE002800C);\r
+\r
+/* GPIO PORT1 */\r
+\r
+PROVIDE( IO1PIN = 0xE0028010);\r
+PROVIDE( IO1SET = 0xE0028014);\r
+PROVIDE( IO1DIR = 0xE0028018);\r
+PROVIDE( IO1CLR = 0xE002800C);\r
+\r
+/* GPIO PORT2 */\r
+\r
+PROVIDE( IO2PIN = 0xE0028020);\r
+PROVIDE( IO2SET = 0xE0028024);\r
+PROVIDE( IO2DIR = 0xE0028028);\r
+PROVIDE( IO2CLR = 0xE002802C);\r
+\r
+/* GPIO PORT3 */\r
+\r
+PROVIDE( IO3PIN = 0xE0028030);\r
+PROVIDE( IO3SET = 0xE0028034);\r
+PROVIDE( IO3DIR = 0xE0028038);\r
+PROVIDE( IO3CLR = 0xE002803C);\r
+\r
+/* PIN CONNECT BLOCK */\r
+\r
+PROVIDE( PINSEL0 = 0xE002C000);\r
+PROVIDE( PINSEL1 = 0xE002C004);\r
+PROVIDE( PINSEL2 = 0xE002C014);\r
+\r
+/* SPI1 */\r
+\r
+PROVIDE( S1PCR = 0xE0030000);\r
+PROVIDE( S1PSR = 0xE0030004);\r
+PROVIDE( S1PPR = 0xE0030008);\r
+PROVIDE( S1PCCR = 0xE003000C);\r
+PROVIDE( S1PINT = 0xE003001C);\r
+\r
+/* ADC */\r
+\r
+ /* Renamed from AD... to prevent ld conflict. */\r
+PROVIDE( A2DCR = 0xE0034000);\r
+PROVIDE( A2DDR = 0xE0034004);\r
+\r
+/* CAN */\r
+\r
+PROVIDE( CAN_RECV = 0xE0038000);\r
+PROVIDE( AFMR = 0xE003C000);\r
+PROVIDE( SFF_sa = 0xE003C004);\r
+PROVIDE( SFF_GRP_sa = 0xE003C008);\r
+PROVIDE( EFF_sa = 0xE003C00C);\r
+PROVIDE( EFF_GRP_sa = 0xE003C010);\r
+PROVIDE( ENDofTable = 0xE003C014);\r
+PROVIDE( LUTerrAd = 0xE003C018);\r
+PROVIDE( LUTerr = 0xE003C01C);\r
+PROVIDE( CANTxSR = 0xE0040000);\r
+PROVIDE( CANRxSR = 0xE0040004);\r
+PROVIDE( CANMSR = 0xE0040008);\r
+\r
+/* CAN1 Interface */\r
+\r
+PROVIDE( C1MOD = 0xE0044000);\r
+PROVIDE( C1CMR = 0xE0044004);\r
+PROVIDE( C1GSR = 0xE0044008);\r
+PROVIDE( C1ICR = 0xE004400C);\r
+PROVIDE( C1IER = 0xE0044010);\r
+PROVIDE( C1BTR = 0xE0044014);\r
+PROVIDE( C1EWL = 0xE0044018);\r
+PROVIDE( C1SR = 0xE004401C);\r
+PROVIDE( C1RFS = 0xE0044020);\r
+PROVIDE( C1RID = 0xE0044024);\r
+PROVIDE( C1RDA = 0xE0044028);\r
+PROVIDE( C1RDB = 0xE004402C);\r
+PROVIDE( C1TFI1 = 0xE0044030);\r
+PROVIDE( C1TID1 = 0xE0044034);\r
+PROVIDE( C1TDA1 = 0xE0044038);\r
+PROVIDE( C1TDB1 = 0xE004403C);\r
+PROVIDE( C1TFI2 = 0xE0044040);\r
+PROVIDE( C1TID2 = 0xE0044044);\r
+PROVIDE( C1TDA2 = 0xE0044048);\r
+PROVIDE( C1TDB2 = 0xE004404C);\r
+PROVIDE( C1TFI3 = 0xE0044050);\r
+PROVIDE( C1TID3 = 0xE0044054);\r
+PROVIDE( C1TDA3 = 0xE0044058);\r
+PROVIDE( C1TDB3 = 0xE004405C);\r
+\r
+/* CAN2 Interface */\r
+\r
+PROVIDE( C2MOD = 0xE0048000);\r
+PROVIDE( C2CMR = 0xE0048004);\r
+PROVIDE( C2GSR = 0xE0048008);\r
+PROVIDE( C2ICR = 0xE004800C);\r
+PROVIDE( C2IER = 0xE0048010);\r
+PROVIDE( C2BTR = 0xE0048014);\r
+PROVIDE( C2EWL = 0xE0048018);\r
+PROVIDE( C2SR = 0xE004801C);\r
+PROVIDE( C2RFS = 0xE0048020);\r
+PROVIDE( C2RID = 0xE0048024);\r
+PROVIDE( C2RDA = 0xE0048028);\r
+PROVIDE( C2RDB = 0xE004802C);\r
+PROVIDE( C2TFI1 = 0xE0048030);\r
+PROVIDE( C2TID1 = 0xE0048034);\r
+PROVIDE( C2TDA1 = 0xE0048038);\r
+PROVIDE( C2TDB1 = 0xE004803C);\r
+PROVIDE( C2TFI2 = 0xE0048040);\r
+PROVIDE( C2TID2 = 0xE0048044);\r
+PROVIDE( C2TDA2 = 0xE0048048);\r
+PROVIDE( C2TDB2 = 0xE004804C);\r
+PROVIDE( C2TFI3 = 0xE0048050);\r
+PROVIDE( C2TID3 = 0xE0048054);\r
+PROVIDE( C2TDA3 = 0xE0048058);\r
+PROVIDE( C2TDB3 = 0xE004805C);\r
+\r
+/* CAN3 Interface */\r
+\r
+PROVIDE( C3MOD = 0xE004C000);\r
+PROVIDE( C3CMR = 0xE004C004);\r
+PROVIDE( C3GSR = 0xE004C008);\r
+PROVIDE( C3ICR = 0xE004C00C);\r
+PROVIDE( C3IER = 0xE004C010);\r
+PROVIDE( C3BTR = 0xE004C014);\r
+PROVIDE( C3EWL = 0xE004C018);\r
+PROVIDE( C3SR = 0xE004C01C);\r
+PROVIDE( C3RFS = 0xE004C020);\r
+PROVIDE( C3RID = 0xE004C024);\r
+PROVIDE( C3RDA = 0xE004C028);\r
+PROVIDE( C3RDB = 0xE004C02C);\r
+PROVIDE( C3TFI1 = 0xE004C030);\r
+PROVIDE( C3TID1 = 0xE004C034);\r
+PROVIDE( C3TDA1 = 0xE004C038);\r
+PROVIDE( C3TDB1 = 0xE004C03C);\r
+PROVIDE( C3TFI2 = 0xE004C040);\r
+PROVIDE( C3TID2 = 0xE004C044);\r
+PROVIDE( C3TDA2 = 0xE004C048);\r
+PROVIDE( C3TDB2 = 0xE004C04C);\r
+PROVIDE( C3TFI3 = 0xE004C050);\r
+PROVIDE( C3TID3 = 0xE004C054);\r
+PROVIDE( C3TDA3 = 0xE004C058);\r
+PROVIDE( C3TDB3 = 0xE004C05C);\r
+\r
+/* CAN4 Interface */\r
+\r
+PROVIDE( C4MOD = 0xE0050000);\r
+PROVIDE( C4CMR = 0xE0050004);\r
+PROVIDE( C4GSR = 0xE0050008);\r
+PROVIDE( C4ICR = 0xE005000C);\r
+PROVIDE( C4IER = 0xE0050010);\r
+PROVIDE( C4BTR = 0xE0050014);\r
+PROVIDE( C4EWL = 0xE0050018);\r
+PROVIDE( C4SR = 0xE005001C);\r
+PROVIDE( C4RFS = 0xE0050020);\r
+PROVIDE( C4RID = 0xE0050024);\r
+PROVIDE( C4RDA = 0xE0050028);\r
+PROVIDE( C4RDB = 0xE005002C);\r
+PROVIDE( C4TFI1 = 0xE0050030);\r
+PROVIDE( C4TID1 = 0xE0050034);\r
+PROVIDE( C4TDA1 = 0xE0050038);\r
+PROVIDE( C4TDB1 = 0xE005003C);\r
+PROVIDE( C4TFI2 = 0xE0050040);\r
+PROVIDE( C4TID2 = 0xE0050044);\r
+PROVIDE( C4TDA2 = 0xE0050048);\r
+PROVIDE( C4TDB2 = 0xE005004C);\r
+PROVIDE( C4TFI3 = 0xE0050050);\r
+PROVIDE( C4TID3 = 0xE0050054);\r
+PROVIDE( C4TDA3 = 0xE0050058);\r
+PROVIDE( C4TDB3 = 0xE005005C);\r
+\r
+/* SYSTEM CONTROL BLOCK */\r
+ /* MAM */\r
+\r
+PROVIDE( MAMCR = 0xE01FC000);\r
+PROVIDE( MAMTIM = 0xE01FC004);\r
+\r
+\r
+PROVIDE( MEMAP = 0xE01FC040);\r
+\r
+ /* PLL */\r
+\r
+PROVIDE( PLLCON = 0xE01FC080);\r
+PROVIDE( PLLCFG = 0xE01FC084);\r
+PROVIDE( PLLSTAT = 0xE01FC088);\r
+PROVIDE( PLLFEED = 0xE01FC08C);\r
+\r
+ /* POWER CONTROL */\r
+\r
+PROVIDE( PCON = 0xE01FC0C0);\r
+PROVIDE( PCONP = 0xE01FC0C4);\r
+\r
+ /* VPB */\r
+\r
+PROVIDE( VPBDIV = 0xE01FC100);\r
+\r
+ /* EXTERNAL INTERUPT/WAKE */\r
+\r
+PROVIDE( EXTINT = 0xE01FC140);\r
+PROVIDE( EXTWAKE = 0xE01FC144);\r
+PROVIDE( EXTMODE = 0xE01FC148);\r
+PROVIDE( EXTPOLAR = 0xE01FC14C);\r
+\r
+/* External Memory Controller- EMC */\r
+\r
+PROVIDE( BCFG0 = 0xFFE00000);\r
+PROVIDE( BCFG1 = 0xFFE00004);\r
+PROVIDE( BCFG2 = 0xFFE00008);\r
+PROVIDE( BCFG3 = 0xFFE0000C);\r
+\r
+/* Vector Interrupt Controller (VIC) */\r
+\r
+PROVIDE( VICIRQStatus = 0xFFFFF000);\r
+PROVIDE( VICFIQStatus = 0xFFFFF004);\r
+PROVIDE( VICRawIntr = 0xFFFFF008);\r
+PROVIDE( VICIntSelect = 0xFFFFF00C);\r
+PROVIDE( VICIntEnable = 0xFFFFF010);\r
+PROVIDE( VICIntEnClr = 0xFFFFF014);\r
+PROVIDE( VICSoftInt = 0xFFFFF018);\r
+PROVIDE( VICSoftIntClear = 0xFFFFF01C);\r
+PROVIDE( VICProtection = 0xFFFFF020);\r
+PROVIDE( VICVectAddrRead = 0xFFFFF030);\r
+PROVIDE( VICDefVectAddr = 0xFFFFF034);\r
+PROVIDE( VICVectAddr = 0xFFFFF100);\r
+PROVIDE( VICVectCntl = 0xFFFFF200);\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* RAMISP.ld: Linker Script File - for use with serial line boo loader*/\r
+/* */\r
+/***********************************************************************/\r
+ENTRY(_start)\r
+STACK_SIZE = 0x400;\r
+\r
+/* Memory Definitions */\r
+MEMORY\r
+{\r
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000\r
+ RAMBEG (rw) : ORIGIN = 0x40000000, LENGTH = 0x00000120\r
+ RAMISP (r) : ORIGIN = 0x40000120, LENGTH = 0x000000E0\r
+ RAMREST (rw) : ORIGIN = 0x40000200, LENGTH = 0x0000FE00\r
+}\r
+\r
+STARTUP(crt0.o)\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ /* first section is .text which is used for code */\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+/* LONG( ((ABSOLUTE( _start ) - . - 8) >> 2) + 0xea000000 ) /* B _start */\r
+ *(.text) /* remaining code */\r
+ *(.rodata) /* read-only data (constants) */\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ _etext = . ;\r
+ PROVIDE (etext = .);\r
+\r
+ .ivec :\r
+ {\r
+ *(.ivec) /* remaining code */\r
+ } > RAMBEG\r
+ \r
+ /* .data section which is used for initialized data */\r
+ .data :\r
+ {\r
+ _data = .;\r
+ *(.data)\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ _edata = . ;\r
+ PROVIDE (edata = .);\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ __bss_start = . ;\r
+ __bss_start__ = . ;\r
+ *(.bss)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ } > RAMREST\r
+\r
+ . = ALIGN(4);\r
+ __bss_end__ = . ;\r
+ PROVIDE (__bss_end = .);\r
+\r
+ .stack ALIGN(256) :\r
+ {\r
+ . += STACK_SIZE;\r
+ PROVIDE (_stack = .);\r
+ } > RAMREST\r
+\r
+ _end = . ;\r
+ PROVIDE (end = .);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS = defines libs
--- /dev/null
+# -*- makefile -*-
+
+ARCH=arm
+MACH=lpc21xx
+BOARD=spejblarm
+
+CROSS_COMPILE = arm-elf-
+TARGET_ARCH = -mcpu=arm7tdmi
+
+# Set default C flags. If theese are set elsewhere (e.g. on a command
+# line), these default flags are not used.
+DEBUG ?= -g
+OPTIMIZE ?= -O2
+
+LPC_BAUD = 38400
+TOLPC = $(MAKERULES_DIR)/$(COMPILED_DIR_NAME)/bin-utils/tolpc --baud $(LPC_BAUD) --sdev /dev/ttyS0
+LOAD_CMD-ramisp = $(TOLPC) -v -q 7372 -L -f
+LOAD_CMD-mpram = $(TOLPC) -v -q 7372 -L -f
+
+# This selects linker script
+LD_SCRIPT=lpc21xx
+DEFAULT_LD_SCRIPT_VARIANT=ramisp
+
+#OUTPUT_FORMATS = bin hex srec
+
+###
+CONFIG_USB_BASE=
+CONFIG_USB_PDIUSB=
+CONFIG_USB_MORE=
+CONFIG_CMDPROC_TEST=n
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h))
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ system_def.h - common cover for definition of hardware adresses,
+ registers, timing and other hardware dependant
+ parts of embedded hardware
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+
+ *******************************************************************/
+
+#ifndef _SYSTEM_DEF_H_
+#define _SYSTEM_DEF_H_
+
+#include <types.h>
+
+#define WITH_SFI_SEL
+
+#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
+/* Software version */
+#define SW_VER_ID "SPEJBLARM"
+#define SW_VER_MAJOR 0
+#define SW_VER_MINOR 1
+#define SW_VER_PATCH 0
+#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
+/* Hardware version */
+#define HW_VER_ID "SPEJBLARM"
+#define HW_VER_MAJOR 1
+#define HW_VER_MINOR 0
+#define HW_VER_PATCH 0
+#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
+/* Version of mechanical */
+#define MECH_VER_ID "SPEJBLARM"
+#define MECH_VER_MAJOR 0
+#define MECH_VER_MINOR 0
+#define MECH_VER_PATCH 0
+#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
+
+#define BOARD_SPEJBLARM
+
+#define CPU_REF_HZ 7372000l /* reference clock */
+#define CPU_SYS_HZ 60000000l /* default system */
+
+/* This two lines were added only to compile the new
+ * can_init_baudrate() function. I'm not sure whether these numbers or
+ * correct for this board. */
+#define CPU_APB_HZ (CPU_SYS_HZ/2)/* APB clock */
+#define CPU_VPB_HZ CPU_APB_HZ /* VPB clock = APB clock, multiple definition */
+
+unsigned long cpu_ref_hz; /* actual external XTAL reference */
+unsigned long cpu_sys_hz; /* actual system clock frequency */
+
+volatile unsigned long msec_time;
+
+#define SCI_RS232_CHAN_DEFAULT 1
+
+/* #define DEB_LED_INIT() \ */
+/* do {\ */
+/* *DIO_PEDR=0x00;\ */
+/* SHADOW_REG_SET(DIO_PEDDR,0x0f); /\* set PJ.1, PJ.2, PJ.3 LED output *\/ \ */
+/* } while (0) */
+
+/* #define DEB_LED_OFF(num) \ */
+/* (*DIO_PEDR |= PEDR_PE0DRm << (num)) */
+/* #define DEB_LED_ON(num) \ */
+/* (*DIO_PEDR &=~(PEDR_PE0DRm << (num))) */
+
+
+#endif /* _SYSTEM_DEF_H_ */
--- /dev/null
+# Generic directory or leaf node makefile for OCERA make framework
+
+ifndef MAKERULES_DIR
+MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" == `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) )
+endif
+
+ifeq ($(MAKERULES_DIR),)
+all : default
+.DEFAULT::
+ @echo -e "\nThe Makefile.rules has not been found in this or partent directory\n"
+else
+include $(MAKERULES_DIR)/Makefile.rules
+endif
+
--- /dev/null
+# -*- makefile -*-
+
+SUBDIRS =
+
+lib_LDSCRIPTS = board.ld
--- /dev/null
+/* Board specific objects linked with applications */
--- /dev/null
+common/doc
\ No newline at end of file
--- /dev/null
+common/libs4c
\ No newline at end of file
projects / sysless.git / commitdiff