1 /*******************************************************************
2 Components for embedded applications builded for
3 laboratory and medical instruments firmware
5 system_def_h8canusb.h - definition of hardware adresses and registers
7 Copyright (C) 2002 by Pavel Pisa pisa@cmp.felk.cvut.cz
8 (C) 2002 by PiKRON Ltd. http://www.pikron.com
10 *******************************************************************/
12 #ifndef _SYSTEM_DEF_HW01_H_
13 #define _SYSTEM_DEF_HW01_H_
15 //#define CPU_REF_HZ 20000000l /* reference clock for H8CANUSB */
16 //#define CPU_SYS_HZ 20000000l /* default system for H8CANUSB */
18 #define CPU_REF_HZ 4000000l /* reference clock for H8CANUSB */
19 #define CPU_SYS_HZ 16000000l /* default system for H8CANUSB */
22 unsigned long cpu_ref_hz; /* actual external XTAL reference */
23 unsigned long cpu_sys_hz; /* actual system clock frequency */
25 volatile unsigned long msec_time;
27 #define SCI_RS232_CHAN_DEFAULT 1
29 /* Buffer stransferred to second board power control register */
30 /* SRAM 32 kB (CS3) */
31 //#define SRAM_START (volatile uint8_t * const)(0x610000)
34 #define ISR_USB_INTV EXCPTVEC_IRQ2 /* pin IRQ2 on PF.0 */
35 #define PDIUSB_READ_DATA_ADDR (volatile uint8_t * const)(0x500000)
36 #define PDIUSB_WRITE_DATA_ADDR (volatile uint8_t * const)(0x500000)
37 #define PDIUSB_COMMAND_ADDR (volatile uint8_t * const)(0x500001)
39 /* P1.0 .. DACK_N/DMACK0, P7.0 .. DMREQ/DREQ0, P7.2 .. EOT_N/TEND0 */
40 #undef PDIUSB_WITH_ADD_IRQ_HANDLER
41 #define PDIUSB_WITH_EXCPTVECT_SET
42 #define PDIUSB_SUPPORT_ENABLED
47 /* IDE (CS4) (CS5) powered by PF2 */
48 #define SIDE_START1 (volatile uint8_t * const)(0x800000)
49 #define SIDE_START2 (volatile uint8_t * const)(0xA00000)
50 #define IDE0_DATA (volatile uint16_t * const)(SIDE_START1+0) /* DATA */
51 #define IDE0_ERROR (SIDE_START1+2) /* Error/Features RO/WO */
52 #define IDE0_NSECTOR (SIDE_START1+4) /* Sector Count R/W */
53 #define IDE0_SECTOR (SIDE_START1+6) /* SN, LBA 0-7 */
54 #define IDE0_LCYL (SIDE_START1+8) /* CL, LBA 8-15 */
55 #define IDE0_HCYL (SIDE_START1+10) /* CH, LBA 16-23 */
56 #define IDE0_CURRENT (SIDE_START1+12) /* 1L1DHHHH , LBA 24-27 */
57 #define IDE0_STATUS (SIDE_START1+14) /* Status */
58 #define IDE0_SELECT IDE0_CURRENT
59 #define IDE0_FEATURE IDE0_ERROR
60 #define IDE0_COMMAND IDE0_STATUS /* Command */
62 #define IDE0_DEVCTRL (SIDE_START2+12) /* used for resets */
63 #define IDE0_ALTSTATUS (SIDE_START2+14) /* IDE0_STATUS - no clear irq */
65 #define IDE0_SETPWR(pwr) do{ \
66 if(pwr) atomic_clear_mask_b1(4,DIO_PFDR); \
67 else atomic_set_mask_b1(4,DIO_PFDR); \
70 #define IDE0_PRESENT_M() ((*DIO_PORT9)&0x20)
72 #if (HW_VER_MAJOR == 0) && (HW_VER_MINOR == 2)
73 #define IDE_SWAP_BYTES
76 #define IDE0_SUPPORT_ENABLED
80 /* IRAM 16 kB of on-chip memory */
81 /* 0xffb000-0xffcfff .. 8 kB free */
82 /* 0xffd000-0xffdfff .. 4 kB for Flash emulation */
83 /* 0xffe000-0xffffc0 .. 4 kB - 64 B free*/
84 /* 0xffffc0-0xffffff .. 64 B free*/
85 #define IRAM_START (volatile uint8_t * const)(0xffb000)
86 #define IRAM_START1 (volatile uint8_t * const)(0xffe000)
87 #define FRAM_START (volatile uint8_t * const)(0xffffc0)
90 /* SCI1 - IIC0 (P34, P35) */
93 /* SCI4 - RS232/485 */
96 /* IRQ1 - Index mark */
99 /* Some registers are read only on H8S processors */
100 /* We use shadow registers for some of them */
101 #define SHADOW_REG_ALT(_reg,_mask,_xor) \
102 (*(_reg)=_reg##_shadow=(_reg##_shadow&~(_mask))^(_xor))
104 #define SHADOW_REG_SET(_reg,_mask) \
105 (*(_reg)=_reg##_shadow|=(_mask))
107 #define SHADOW_REG_CLR(_reg,_mask) \
108 (*(_reg)=_reg##_shadow&=~(_mask))
110 #define SHADOW_REG_RD(_reg) \
113 #define SHADOW_REG_WR(_reg,_val) \
114 (*(_reg)=_reg##_shadow=(_val))
116 uint8_t DIO_P1DDR_shadow;
117 uint8_t DIO_P3DDR_shadow;
118 uint8_t DIO_PADDR_shadow;
119 uint8_t DIO_PEDDR_shadow;
120 uint8_t DIO_PFDDR_shadow;
121 uint8_t DIO_PJDDR_shadow;
123 #define DEB_LED_INIT() \
126 SHADOW_REG_SET(DIO_PEDDR,0x0f); /* set PJ.1, PJ.2, PJ.3 LED output */ \
129 #define DEB_LED_OFF(num) \
130 (*DIO_PEDR |= PEDR_PE0DRm << (num))
131 #define DEB_LED_ON(num) \
132 (*DIO_PEDR &=~(PEDR_PE0DRm << (num)))
135 #endif /* _SYSTEM_DEF_HW01_H_ */