1 #include "local_config.h"
2 #include <system_def.h>
4 #include <lt_timer_types.h>
5 #include <hal_machperiph.h>
9 #include <lpciap_kvpb.h>
10 #endif /* CONFIG_KEYVAL */
11 #ifdef CONFIG_STDIO_COM_PORT
14 #ifdef CONFIG_OC_UL_DRV_SYSLESS
15 #include <ul_lib/ulan.h>
17 #include <ul_drv_init.h>
18 #include <ul_drv_iac.h>
19 #include <ul_lib/ul_drvdef.h>
20 extern long int uld_jiffies;
21 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
25 volatile lt_ticks_t sys_timer_ticks;
27 static void sysInit(void)
34 // setup the parallel port pin
35 GPIO0->FIOCLR = P0IO_ZERO_BITS; // clear the ZEROs output
36 GPIO0->FIOSET = P0IO_ONE_BITS; // set the ONEs output
37 GPIO0->FIODIR = P0IO_OUTPUT_BITS; // set the output bit direction
39 GPIO1->FIOCLR = P1IO_ZERO_BITS; // clear the ZEROs output
40 GPIO1->FIOSET = P1IO_ONE_BITS; // set the ONEs output
41 GPIO1->FIODIR = P1IO_OUTPUT_BITS; // set the output bit direction
43 GPIO2->FIOCLR = P2IO_ZERO_BITS; // clear the ZEROs output
44 GPIO2->FIOSET = P2IO_ONE_BITS; // set the ONEs output
45 GPIO2->FIODIR = P2IO_OUTPUT_BITS; // set the output bit direction
47 GPIO3->FIOCLR = P3IO_ZERO_BITS; // clear the ZEROs output
48 GPIO3->FIOSET = P3IO_ONE_BITS; // set the ONEs output
49 GPIO3->FIODIR = P3IO_OUTPUT_BITS; // set the output bit direction
51 GPIO4->FIOCLR = P4IO_ZERO_BITS; // clear the ZEROs output
52 GPIO4->FIOSET = P4IO_ONE_BITS; // set the ONEs output
53 GPIO4->FIODIR = P4IO_OUTPUT_BITS; // set the output bit direction
56 IRQ_HANDLER_FNC(timer0_isr)
63 TIM0->MR0 += PCLK / SYS_TIMER_HZ;
64 TIM0->IR=0x01; // Clear match0 interrupt
65 #ifdef CONFIG_OC_UL_DRV_SYSLESS
69 } while (((int32_t)(TIM0->MR0-TIM0->TC))<0);
78 request_irq(TIMER0_IRQn, timer0_isr, 0, NULL,NULL);
79 enable_irq(TIMER0_IRQn);
84 TIM0->MR0= PCLK / SYS_TIMER_HZ;
85 TIM0->MCR|=1; // TMCR_MR0_I;
87 TIM0->TCR = 1; //Run timer 0 */
90 #ifdef CONFIG_STDIO_COM_PORT
92 int uartcon_write(int file, const char * ptr, int len)
96 for(cnt=0;cnt<len;cnt++,ptr++){
105 void init_system_stub(void) {
106 system_stub_ops.write=uartcon_write;
109 #endif /* CONFIG_STDIO_COM_PORT */
111 #ifdef CONFIG_OC_UL_DRV_SYSLESS
113 extern unsigned uld_debug_flg; /* Left application set defaults */
115 #ifndef CONFIG_KEYVAL
116 unsigned long lpciap_buff[ISP_RAM2FLASH_BLOCK_SIZE/4];
117 #endif /* CONFIG_KEYVAL */
119 #define UL_MTYPE_START32BIT 0x100
121 static inline int ul_iac_mem_head_rd(uint8_t *buf, int len,
122 uint32_t* pmtype, uint32_t* pstart, uint32_t* plen)
125 if (len<6) return -1;
126 mtype=*(buf++); /* memory type */
128 val=*(buf++); /* start address */
130 if(mtype&UL_MTYPE_START32BIT){
131 if (len<8) return -1;
132 val+=(uint32_t)*(buf++)<<16;
133 val+=(uint32_t)*(buf++)<<24;
136 val=*(buf++); /* length */
138 if(mtype&UL_MTYPE_START32BIT){
140 val+=(uint32_t)*(buf++)<<16;
141 val+=(uint32_t)*(buf++)<<24;
145 mtype&=~UL_MTYPE_START32BIT; /* 32-bit start address */
150 int ul_iac_call_rdm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
152 uint32_t mtype,start,len;
156 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
157 return UL_IAC_RC_PROC;
161 data->buff=(char*)start;
162 return UL_IAC_RC_FREEMSG;
164 return UL_IAC_RC_PROC;
167 int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
169 uint32_t mtype,start,len;
173 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
174 return UL_IAC_RC_PROC;
178 lpcisp_erase((void*)start,len);
180 return UL_IAC_RC_FREEMSG;
182 #endif /* CONFIG_KEYVAL */
183 return UL_IAC_RC_PROC;
186 int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
188 uint32_t mtype,start,len;
192 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
193 return UL_IAC_RC_PROC;
196 memcpy((void*)start,data->buff,data->len);
197 return UL_IAC_RC_FREEMSG;
201 lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE);
202 return UL_IAC_RC_FREEMSG;
204 #endif /* CONFIG_KEYVAL */
205 return UL_IAC_RC_PROC;
209 int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
211 uint32_t debcmd,mtype,start;
212 uint8_t *p=(uint8_t*)ibuff;
214 if (msginfo->len<1) return UL_IAC_RC_PROC;
217 case 0x10: /* goto */
219 if (msginfo->len<5) return UL_IAC_RC_PROC;
224 if(mtype&UL_MTYPE_START32BIT){
225 mtype&=~UL_MTYPE_START32BIT;
226 if (msginfo->len<7) return UL_IAC_RC_PROC;
227 start+=(uint32_t)*(p++)<<16;
228 start+=(uint32_t)*(p++)<<24;
231 ((void (*)())start)();
234 return UL_IAC_RC_PROC;
237 int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
239 uint32_t rescmd,pass;
240 uint8_t *p=(uint8_t*)ibuff;
242 if (msginfo->len<1) return UL_IAC_RC_PROC;
245 case ULRES_CPU: /* CPU */
247 if (msginfo->len<3) return UL_IAC_RC_PROC;
251 // MEMMAP=MEMMAP_FLASH;
252 lpc_watchdog_init(1,10); /* 10ms */
258 return UL_IAC_RC_PROC;
265 /* set rs485 mode for UART1 */
266 PINCON->PINSEL4 = (PINCON->PINSEL4 & ~0x00000F0F) | 0x00000A0A; /* dsr(rxd), dtr(rs485_dir), rxd, txd */
268 udrv=ul_drv_new(UL_DRV_SYSLESS_PORT, /* port */
269 UL_DRV_SYSLESS_IRQ, /* irq */
270 UL_DRV_SYSLESS_BAUD, /* baud */
271 UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */
272 #ifdef CONFIG_OC_UL_DRV_U450_VARPINS
273 #if defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) && defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
274 "16450-dirneg-msrswap", /* chip name */
275 #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
276 "16450-msrswap", /* chip name */
277 #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG)
278 "16450-dirneg", /* chip name */
280 "16450", /* chip name */
282 #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/
283 "16450", /* chip name */
284 #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/
285 0); /* baud base - default */
290 ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL,0);
291 ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
292 ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
293 ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
294 ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
296 return ul_drv_add_dev(udrv);
298 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
302 // initialize the system
305 #ifdef WATCHDOG_ENABLED
306 lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS);
308 #endif /* WATCHDOG_ENABLED */
310 #ifdef CONFIG_STDIO_COM_PORT
311 uart0Init( B57600 , UART_8N1, UART_FIFO_8);
313 #endif /* CONFIG_STDIO_COM_PORT */
315 // initialize the system timer
318 #ifdef CONFIG_OC_UL_DRV_SYSLESS
319 // uld_debug_flg=0x3ff;
321 #endif /* CONFIG_OC_UL_DRV_SYSLESS */