board/arm/lpc17xx-common/defines/system_def-lmc1.h

   1 /*******************************************************************
   2   Components for embedded applications builded for
   3   laboratory and medical instruments firmware
   4
   5   system_def.h - common cover for definition of hardware adresses,
   6                  registers, timing and other hardware dependant
   7                  parts of embedded hardware
   8
   9   Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
  10             (C) 2002 by PiKRON Ltd. http://www.pikron.com
  11
  12  *******************************************************************/
  13
  14 #ifndef _SYSTEM_DEF_H_
  15 #define _SYSTEM_DEF_H_
  16
  17 #include <types.h>
  18 #include <system_stub.h>
  19 #include <LPC17xx.h>
  20 #include <bspbase.h>
  21
  22 #ifndef NULL
  23 #define NULL    0
  24 #endif
  25
  26 #define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
  27 /* Software version */
  28 #define SW_VER_ID       "LMC1"
  29 #define SW_VER_MAJOR    0
  30 #define SW_VER_MINOR    1
  31 #define SW_VER_PATCH    0
  32 #define SW_VER_CODE     VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
  33 /* Hardware version */
  34 #define HW_VER_ID       "LMC1"
  35 #define HW_VER_MAJOR    1
  36 #define HW_VER_MINOR    0
  37 #define HW_VER_PATCH    0
  38 #define HW_VER_CODE     VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
  39 /* Version of mechanical  */
  40 #define MECH_VER_ID     "LMC1"
  41 #define MECH_VER_MAJOR  0
  42 #define MECH_VER_MINOR  0
  43 #define MECH_VER_PATCH  0
  44 #define MECH_VER_CODE   VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
  45
  46
  47 /*--------------------- Clock Configuration ----------------------------------
  48 //
  49 // <e> Clock Configuration
  50 //   <h> System Controls and Status Register (SCS)
  51 //     <o1.4>    OSCRANGE: Main Oscillator Range Select
  52 //                     <0=>  1 MHz to 20 MHz
  53 //                     <1=> 15 MHz to 24 MHz
  54 //     <e1.5>       OSCEN: Main Oscillator Enable
  55 //     </e>
  56 //   </h>
  57 //
  58 //   <h> Clock Source Select Register (CLKSRCSEL)
  59 //     <o2.0..1>   CLKSRC: PLL Clock Source Selection
  60 //                     <0=> Internal RC oscillator
  61 //                     <1=> Main oscillator
  62 //                     <2=> RTC oscillator
  63 //   </h>
  64 //
  65 //   <e3> PLL0 Configuration (Main PLL)
  66 //     <h> PLL0 Configuration Register (PLL0CFG)
  67 //                     <i> F_cco0 = (2 * M * F_in) / N
  68 //                     <i> F_in must be in the range of 32 kHz to 50 MHz
  69 //                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
  70 //       <o4.0..14>  MSEL: PLL Multiplier Selection
  71 //                     <6-32768><#-1>
  72 //                     <i> M Value
  73 //       <o4.16..23> NSEL: PLL Divider Selection
  74 //                     <1-256><#-1>
  75 //                     <i> N Value
  76 //     </h>
  77 //   </e>
  78 //
  79 //   <e5> PLL1 Configuration (USB PLL)
  80 //     <h> PLL1 Configuration Register (PLL1CFG)
  81 //                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
  82 //                     <i> F_cco1 = F_osc * M * 2 * P
  83 //                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
  84 //       <o6.0..4>   MSEL: PLL Multiplier Selection
  85 //                     <1-32><#-1>
  86 //                     <i> M Value (for USB maximum value is 4)
  87 //       <o6.5..6>   PSEL: PLL Divider Selection
  88 //                     <0=> 1
  89 //                     <1=> 2
  90 //                     <2=> 4
  91 //                     <3=> 8
  92 //                     <i> P Value
  93 //     </h>
  94 //   </e>
  95 //
  96 //   <h> CPU Clock Configuration Register (CCLKCFG)
  97 //     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
  98 //                     <2-256:2><#-1>
  99 //   </h>
 100 //
 101 //   <h> USB Clock Configuration Register (USBCLKCFG)
 102 //     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL1
 103 //                     <0-15>
 104 //                     <i> Divide is USBSEL + 1
 105 //   </h>
 106 //
 107 //   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
 108 //     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
 109 //                     <0=> Pclk = Cclk / 4
 110 //                     <1=> Pclk = Cclk
 111 //                     <2=> Pclk = Cclk / 2
 112 //                     <3=> Pclk = Hclk / 8
 113 //     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
 114 //                     <0=> Pclk = Cclk / 4
 115 //                     <1=> Pclk = Cclk
 116 //                     <2=> Pclk = Cclk / 2
 117 //                     <3=> Pclk = Hclk / 8
 118 //     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
 119 //                     <0=> Pclk = Cclk / 4
 120 //                     <1=> Pclk = Cclk
 121 //                     <2=> Pclk = Cclk / 2
 122 //                     <3=> Pclk = Hclk / 8
 123 //     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
 124 //                     <0=> Pclk = Cclk / 4
 125 //                     <1=> Pclk = Cclk
 126 //                     <2=> Pclk = Cclk / 2
 127 //                     <3=> Pclk = Hclk / 8
 128 //     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
 129 //                     <0=> Pclk = Cclk / 4
 130 //                     <1=> Pclk = Cclk
 131 //                     <2=> Pclk = Cclk / 2
 132 //                     <3=> Pclk = Hclk / 8
 133 //     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
 134 //                     <0=> Pclk = Cclk / 4
 135 //                     <1=> Pclk = Cclk
 136 //                     <2=> Pclk = Cclk / 2
 137 //                     <3=> Pclk = Hclk / 8
 138 //     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
 139 //                     <0=> Pclk = Cclk / 4
 140 //                     <1=> Pclk = Cclk
 141 //                     <2=> Pclk = Cclk / 2
 142 //                     <3=> Pclk = Hclk / 8
 143 //     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
 144 //                     <0=> Pclk = Cclk / 4
 145 //                     <1=> Pclk = Cclk
 146 //                     <2=> Pclk = Cclk / 2
 147 //                     <3=> Pclk = Hclk / 8
 148 //     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
 149 //                     <0=> Pclk = Cclk / 4
 150 //                     <1=> Pclk = Cclk
 151 //                     <2=> Pclk = Cclk / 2
 152 //                     <3=> Pclk = Hclk / 8
 153 //     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
 154 //                     <0=> Pclk = Cclk / 4
 155 //                     <1=> Pclk = Cclk
 156 //                     <2=> Pclk = Cclk / 2
 157 //                     <3=> Pclk = Hclk / 8
 158 //     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
 159 //                     <0=> Pclk = Cclk / 4
 160 //                     <1=> Pclk = Cclk
 161 //                     <2=> Pclk = Cclk / 2
 162 //                     <3=> Pclk = Hclk / 8
 163 //     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
 164 //                     <0=> Pclk = Cclk / 4
 165 //                     <1=> Pclk = Cclk
 166 //                     <2=> Pclk = Cclk / 2
 167 //                     <3=> Pclk = Hclk / 6
 168 //     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
 169 //                     <0=> Pclk = Cclk / 4
 170 //                     <1=> Pclk = Cclk
 171 //                     <2=> Pclk = Cclk / 2
 172 //                     <3=> Pclk = Hclk / 6
 173 //     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
 174 //                     <0=> Pclk = Cclk / 4
 175 //                     <1=> Pclk = Cclk
 176 //                     <2=> Pclk = Cclk / 2
 177 //                     <3=> Pclk = Hclk / 6
 178 //   </h>
 179 //
 180 //   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
 181 //     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
 182 //                     <0=> Pclk = Cclk / 4
 183 //                     <1=> Pclk = Cclk
 184 //                     <2=> Pclk = Cclk / 2
 185 //                     <3=> Pclk = Hclk / 8
 186 //     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
 187 //                     <0=> Pclk = Cclk / 4
 188 //                     <1=> Pclk = Cclk
 189 //                     <2=> Pclk = Cclk / 2
 190 //                     <3=> Pclk = Hclk / 8
 191 //     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
 192 //                     <0=> Pclk = Cclk / 4
 193 //                     <1=> Pclk = Cclk
 194 //                     <2=> Pclk = Cclk / 2
 195 //                     <3=> Pclk = Hclk / 8
 196 //     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
 197 //                     <0=> Pclk = Cclk / 4
 198 //                     <1=> Pclk = Cclk
 199 //                     <2=> Pclk = Cclk / 2
 200 //                     <3=> Pclk = Hclk / 8
 201 //     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
 202 //                     <0=> Pclk = Cclk / 4
 203 //                     <1=> Pclk = Cclk
 204 //                     <2=> Pclk = Cclk / 2
 205 //                     <3=> Pclk = Hclk / 8
 206 //     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
 207 //                     <0=> Pclk = Cclk / 4
 208 //                     <1=> Pclk = Cclk
 209 //                     <2=> Pclk = Cclk / 2
 210 //                     <3=> Pclk = Hclk / 8
 211 //     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
 212 //                     <0=> Pclk = Cclk / 4
 213 //                     <1=> Pclk = Cclk
 214 //                     <2=> Pclk = Cclk / 2
 215 //                     <3=> Pclk = Hclk / 8
 216 //     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
 217 //                     <0=> Pclk = Cclk / 4
 218 //                     <1=> Pclk = Cclk
 219 //                     <2=> Pclk = Cclk / 2
 220 //                     <3=> Pclk = Hclk / 8
 221 //     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
 222 //                     <0=> Pclk = Cclk / 4
 223 //                     <1=> Pclk = Cclk
 224 //                     <2=> Pclk = Cclk / 2
 225 //                     <3=> Pclk = Hclk / 8
 226 //     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
 227 //                     <0=> Pclk = Cclk / 4
 228 //                     <1=> Pclk = Cclk
 229 //                     <2=> Pclk = Cclk / 2
 230 //                     <3=> Pclk = Hclk / 8
 231 //     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
 232 //                     <0=> Pclk = Cclk / 4
 233 //                     <1=> Pclk = Cclk
 234 //                     <2=> Pclk = Cclk / 2
 235 //                     <3=> Pclk = Hclk / 8
 236 //     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
 237 //                     <0=> Pclk = Cclk / 4
 238 //                     <1=> Pclk = Cclk
 239 //                     <2=> Pclk = Cclk / 2
 240 //                     <3=> Pclk = Hclk / 8
 241 //     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
 242 //                     <0=> Pclk = Cclk / 4
 243 //                     <1=> Pclk = Cclk
 244 //                     <2=> Pclk = Cclk / 2
 245 //                     <3=> Pclk = Hclk / 8
 246 //     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
 247 //                     <0=> Pclk = Cclk / 4
 248 //                     <1=> Pclk = Cclk
 249 //                     <2=> Pclk = Cclk / 2
 250 //                     <3=> Pclk = Hclk / 8
 251 //   </h>
 252 //
 253 //   <h> Power Control for Peripherals Register (PCONP)
 254 //     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
 255 //     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
 256 //     <o11.3>      PCUART0: UART 0 power/clock enable
 257 //     <o11.4>      PCUART1: UART 1 power/clock enable
 258 //     <o11.6>      PCPWM1: PWM 1 power/clock enable
 259 //     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
 260 //     <o11.8>      PCSPI: SPI interface power/clock enable
 261 //     <o11.9>      PCRTC: RTC power/clock enable
 262 //     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
 263 //     <o11.12>     PCAD: A/D converter power/clock enable
 264 //     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
 265 //     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
 266 //     <o11.15>     PCGPIO: GPIOs power/clock enable
 267 //     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
 268 //     <o11.17>     PCMC: Motor control PWM power/clock enable
 269 //     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
 270 //     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
 271 //     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
 272 //     <o11.22>     PCTIM2: Timer 2 power/clock enable
 273 //     <o11.23>     PCTIM3: Timer 3 power/clock enable
 274 //     <o11.24>     PCUART2: UART 2 power/clock enable
 275 //     <o11.25>     PCUART3: UART 3 power/clock enable
 276 //     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
 277 //     <o11.27>     PCI2S: I2S interface power/clock enable
 278 //     <o11.29>     PCGPDMA: GP DMA function power/clock enable
 279 //     <o11.30>     PCENET: Ethernet block power/clock enable
 280 //     <o11.31>     PCUSB: USB interface power/clock enable
 281 //   </h>
 282 // </e>
 283 */
 284
 285 #define CLOCK_SETUP           1
 286
 287 #define SCS_Val               0x00000020        /* OSCEN */
 288 #define CLKSRCSEL_Val         0x00000001        /* XTAL */
 289
 290 #define PLL0_SETUP            1
 291 #define PLL0CFG_Val           0x0000000B        /* 324403200Hz - must be in the range 275HMz-550MHz */
 292
 293 #define PLL1_SETUP            0
 294 #define PLL1CFG_Val           0x00000023
 295
 296 #define CCLKCFG_Val           0x00000003        /* pplclk/(CCLKCFG_Val+1)=81100800Hz */
 297 #define USBCLKCFG_Val         0x00000000
 298
 299 //#define PCLKSEL0_Val          0x00000000        /* all peripherial sysclk/4 */
 300 //#define PCLKSEL1_Val          0x00000000
 301 //#define PCONP_Val             0x042887DE
 302
 303 #define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8)))
 304
 305 /*--------------------- Flash Accelerator Configuration ----------------------
 306 //
 307 // <e> Flash Accelerator Configuration
 308 //   <o1.0..1>   FETCHCFG: Fetch Configuration
 309 //               <0=> Instruction fetches from flash are not buffered
 310 //               <1=> One buffer is used for all instruction fetch buffering
 311 //               <2=> All buffers may be used for instruction fetch buffering
 312 //               <3=> Reserved (do not use this setting)
 313 //   <o1.2..3>   DATACFG: Data Configuration
 314 //               <0=> Data accesses from flash are not buffered
 315 //               <1=> One buffer is used for all data access buffering
 316 //               <2=> All buffers may be used for data access buffering
 317 //               <3=> Reserved (do not use this setting)
 318 //   <o1.4>      ACCEL: Acceleration Enable
 319 //   <o1.5>      PREFEN: Prefetch Enable
 320 //   <o1.6>      PREFOVR: Prefetch Override
 321 //   <o1.12..15> FLASHTIM: Flash Access Time
 322 //               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
 323 //               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
 324 //               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
 325 //               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
 326 //               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
 327 //               <5=> 6 CPU clocks (for any CPU clock)
 328 // </e>
 329 */
 330 #define FLASH_SETUP           1
 331 #define FLASHCFG_Val          0x0000403A
 332
 333 /*----------------------------------------------------------------------------
 334   Define clocks
 335  *----------------------------------------------------------------------------*/
 336 #define XTAL        (12000000UL)        /* Oscillator frequency               */
 337 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
 338 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
 339 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
 340
 341
 342
 343
 344 #define SYS_TIMER_HZ        1000
 345
 346 #ifndef BIT
 347 #define BIT(n)              (1 << (n))
 348 #endif
 349
 350 // Port Bit Definitions & Macros:    Description - initial conditions
 351 #define CAN1_RX_BIT         BIT(0)      // CAN1 RX
 352 #define CAN1_TX_BIT         BIT(1)      // CAN1 TX
 353 #define TXD0_BIT            BIT(2)      // used by UART0
 354 #define RXD0_BIT            BIT(3)      // used by UART0
 355 #define CAN2_RX_BIT         BIT(4)      // CAN2 RX
 356 #define CAN2_TX_BIT         BIT(5)      // CAN2 TX
 357 #define LED2_BIT            BIT(6)      // active low/SSEL1
 358 #define SCK1_BIT            BIT(7)      // clock SSP1 to gradient valves
 359 #define MISO1_BIT           BIT(8)      // master input
 360 #define MOSI1_BIT           BIT(9)      // master output
 361 #define P0_10_UNUSED_BIT    BIT(10)     // P0.10 unused (SDA2/TXD2)
 362 #define P0_11_UNUSED_BIT    BIT(11)     // P0.11 unused (SCL2/RXD2)
 363 #define SCK0_BIT            BIT(15)     // clock SSP0 to display panel
 364 #define SSEL0_BIT           BIT(16)     // slave select SSP0
 365 #define MISO0_BIT           BIT(17)     // master input SSP0
 366 #define MOSI0_BIT           BIT(18)     // master output SSP0
 367 #define SDA1_BIT            BIT(19)     // I2C data - memory/connector
 368 #define SCL1_BIT            BIT(20)     // I2C clock
 369 #define SSP0_CS0_BIT        BIT(21)     // chip select SSP0 for display
 370 #define SSP0_CS1_BIT        BIT(22)     // chip select SSP0/ A/D for display
 371 #define ADC0_BIT            BIT(23)     // ADC motor current
 372 #define ADC1_BIT            BIT(24)     // ADC motor current
 373 #define ADC2_BIT            BIT(25)     // ADC motor current
 374 #define ADC3_BIT            BIT(26)     // ADC motor current
 375 #define P0_27_UNUSED_BIT    BIT(27)     // P0.27 unused
 376 #define P0_28_UNUSED_BIT    BIT(28)     // P0.28 unused
 377 #define USBDPLUS_BIT        BIT(29)     // P0.29 USBD+
 378 #define USBDMINUS_BIT       BIT(30)     // P0.30 USBD-
 379
 380
 381 // Port Bit Definitions & Macros:    Description - initial conditions
 382
 383 #define P1_ETH_BITS         (BIT(0)|BIT(1)|BIT(4)|BIT(8)|BIT(9)|\
 384                              BIT(10)|BIT(14)|BIT(15)|BIT(16)|BIT(17))
 385
 386 #define P1_0_UNUSED_BIT     BIT(0)      // P1.0 unused - low output
 387 #define P1_1_UNUSED_BIT     BIT(1)      // P1.1 unused - low output
 388 #define P1_4_UNUSED_BIT     BIT(4)      // P1.4 unused - low output
 389 #define P1_8_UNUSED_BIT     BIT(8)      // P1.8 unused - low output
 390 #define P1_9_UNUSED_BIT     BIT(9)      // P1.9 unused - low output
 391 #define P1_10_UNUSED_BIT    BIT(10)     // P1.10 unused - low output
 392 #define P1_14_UNUSED_BIT    BIT(14)     // P1.14 unused - low output
 393 #define P1_15_UNUSED_BIT    BIT(15)     // P1.15 unused - low output
 394 #define PWM1_BIT            BIT(18)     // motor pwm 0 / ADC0
 395 #define BLDC_HAL_A_BIT      BIT(19)     // motor HAL input A
 396 #define IRC_A_BIT           BIT(20)     // motor IRC channel A (MCI0)
 397 #define IRC_M_BIT           BIT(21)     // motor IRC channel mark (GPIO)
 398 #define BLDC_HAL_B_BIT      BIT(22)     // motor HAL input B
 399 #define IRC_B_BIT           BIT(23)     // motor IRC channel B (MCI1)
 400 #define IRC_I_BIT           BIT(24)     // motor IRC index (MCI2)
 401 #define BLDC_HAL_C_BIT      BIT(25)     // motor HAL input C
 402 #define PWM1_EN_BIT         BIT(26)     // motor pwm 0 enable
 403 #define PWM2_EN_BIT         BIT(27)     // motor pwm 1 enable
 404 #define PWM4_EN_BIT         BIT(28)     // motor pwm 2 enable
 405 #define PWM6_EN_BIT         BIT(29)     // motor pwm 3 enable
 406 #define ADC4_BIT            BIT(30)     // ADC4 tensometer
 407 #define ADC5_BIT            BIT(31)     // ADC5 external input
 408
 409 // Port Bit Definitions & Macros:    Description - initial conditions
 410 #define TXD1_BIT            BIT(0)      // P2.0 TXD
 411 #define RXD1_BIT            BIT(1)      // P2.1 RXD
 412 #define CTS1_BIT            BIT(2)      // P2.2 CTS connected to RXD1
 413 #define PWM4_BIT            BIT(3)      // P2.3 motor pwm 2 / ADC2
 414 #define DSR1_BIT            BIT(4)      // P2.4 DSR connected to TXD1
 415 #define PWM6_BIT            BIT(5)      // P2.5 motor pwm 3 / ADC3
 416 #define LED1_BIT            BIT(6)      // P2.6 LED1 - error
 417 #define RTS1_BIT            BIT(7)      // P2.7 RTS1 used as DIR1
 418 #define AUX_OUT2_BIT        BIT(8)      // P2.8 auxual TLL port
 419 #define USB_CONNECT_BIT     BIT(9)      // P2.9 USB output for soft connect
 420 #define BOOT_BIT            BIT(10)     // P2.10 Boot input
 421 #define AUX_IN2_BIT         BIT(11)     // P2.11 auxual TLL port
 422 #define AUX_OUT4_BIT        BIT(12)     // P2.12 auxual TLL port
 423 #define ETH_PD_IRQ_BIT      BIT(13)     // P2.13 power down/int
 424
 425 // Port Bit Definitions & Macros:    Description - initial conditions
 426 #define PWM2_BIT            BIT(25)     // P3.25 motor pwm 1 / ADC1
 427 #define AUX_OUT1_BIT        BIT(26)     // P3.26 auxual TLL port
 428
 429 // Port Bit Definitions & Macros:    Description - initial conditions
 430 #define AUX_OUT3_BIT        BIT(28)     // P4.28 auxual TLL port / TXD3
 431 #define AUX_IN1_BIT         BIT(29)     // P4.29 auxual TLL port / RXD3
 432
 433 #define P0IO_INPUT_BITS      (uint32_t) ( \
 434                                          CAN1_RX_BIT | \
 435                                          RXD0_BIT | \
 436                                          CAN2_RX_BIT | \
 437                                          MISO1_BIT | \
 438                                          P0_10_UNUSED_BIT | \
 439                                          P0_11_UNUSED_BIT | \
 440                                          MISO0_BIT | \
 441                                          SDA1_BIT | \
 442                                          SCL1_BIT | \
 443                                          ADC0_BIT | \
 444                                          ADC1_BIT | \
 445                                          ADC2_BIT | \
 446                                          ADC3_BIT | \
 447                                          USBDPLUS_BIT | \
 448                                          USBDMINUS_BIT | \
 449                                          0 )
 450
 451 #define P1IO_INPUT_BITS      (uint32_t) ( \
 452                                          P1_ETH_BITS | \
 453                                          BLDC_HAL_A_BIT | \
 454                                          IRC_A_BIT | \
 455                                          IRC_M_BIT | \
 456                                          BLDC_HAL_B_BIT | \
 457                                          IRC_B_BIT | \
 458                                          IRC_I_BIT | \
 459                                          BLDC_HAL_C_BIT | \
 460                                          ADC4_BIT | \
 461                                          ADC5_BIT | \
 462                                          0 )
 463
 464 #define P2IO_INPUT_BITS      (uint32_t) ( \
 465                                          RXD1_BIT | \
 466                                          CTS1_BIT | \
 467                                          DSR1_BIT | \
 468                                          BOOT_BIT | \
 469                                          AUX_IN2_BIT | \
 470                                          ETH_PD_IRQ_BIT | \
 471                                          0 )
 472
 473 #define P3IO_INPUT_BITS      (uint32_t) ( \
 474                                          0 )
 475
 476 #define P4IO_INPUT_BITS      (uint32_t) ( \
 477                                          AUX_IN1_BIT | \
 478                                          0 )
 479
 480 #define P0IO_ZERO_BITS       (uint32_t) ( \
 481                                          P0_27_UNUSED_BIT | \
 482                                          P0_28_UNUSED_BIT | \
 483                                          0 )
 484
 485 #define P1IO_ZERO_BITS       (uint32_t) ( \
 486                                          PWM1_BIT | \
 487                                          PWM1_EN_BIT | \
 488                                          PWM2_EN_BIT | \
 489                                          PWM4_EN_BIT | \
 490                                          PWM6_EN_BIT | \
 491                                          0 )
 492
 493 #define P2IO_ZERO_BITS       (uint32_t) ( \
 494                                          PWM4_BIT | \
 495                                          PWM6_BIT | \
 496                                          0 )
 497
 498 #define P3IO_ZERO_BITS       (uint32_t) ( \
 499                                          PWM2_BIT | \
 500                                          0 )
 501
 502 #define P4IO_ZERO_BITS       (uint32_t) ( \
 503                                          0 )
 504
 505 #define P0IO_ONE_BITS        (uint32_t) ( \
 506                                          CAN1_TX_BIT | \
 507                                          TXD0_BIT | \
 508                                          CAN2_TX_BIT | \
 509                                          LED2_BIT | \
 510                                          SCK1_BIT | \
 511                                          MOSI1_BIT | \
 512                                          SCK0_BIT | \
 513                                          SSEL0_BIT | \
 514                                          MOSI0_BIT | \
 515                                          SSP0_CS0_BIT | \
 516                                          SSP0_CS1_BIT | \
 517                                          0 )
 518
 519 #define P1IO_ONE_BITS        (uint32_t) ( \
 520                                          0 )
 521
 522 #define P2IO_ONE_BITS        (uint32_t) ( \
 523                                          TXD1_BIT | \
 524                                          LED1_BIT | \
 525                                          RTS1_BIT | \
 526                                          AUX_OUT2_BIT | \
 527                                          USB_CONNECT_BIT | \
 528                                          AUX_OUT4_BIT | \
 529                                          0 )
 530
 531 #define P3IO_ONE_BITS        (uint32_t) ( \
 532                                          AUX_OUT1_BIT | \
 533                                          0 )
 534
 535 #define P4IO_ONE_BITS        (uint32_t) ( \
 536                                          AUX_OUT3_BIT | \
 537                                          0 )
 538
 539 #define P0IO_OUTPUT_BITS     (uint32_t) ( \
 540                                          P0IO_ZERO_BITS | \
 541                                          P0IO_ONE_BITS )
 542
 543 #define P1IO_OUTPUT_BITS     (uint32_t) ( \
 544                                          P1IO_ZERO_BITS | \
 545                                          P1IO_ONE_BITS )
 546
 547 #define P2IO_OUTPUT_BITS     (uint32_t) ( \
 548                                          P2IO_ZERO_BITS | \
 549                                          P2IO_ONE_BITS )
 550
 551 #define P3IO_OUTPUT_BITS     (uint32_t) ( \
 552                                          P3IO_ZERO_BITS | \
 553                                          P3IO_ONE_BITS )
 554
 555 #define P4IO_OUTPUT_BITS     (uint32_t) ( \
 556                                          P4IO_ZERO_BITS | \
 557                                          P4IO_ONE_BITS )
 558
 559
 560
 561 /***************************************************************************/
 562 /* io functions */
 563 #define LED_GP                  LED2_BIT  /* GENREAL PURPOSE LED */
 564 #define LED_ERR                 LED1_BIT
 565
 566 /***************************************************************************/
 567 /* io functions */
 568 #define IN_PORT                 GPIO0->FIO
 569 #define OUT_PORT                GPIO1->FIO
 570 #define LED_PORT                GPIO2->FIO
 571
 572 #define CREATE_PORT_NAME_PIN(port) port##PIN
 573 #define CREATE_PORT_NAME_CLR(port) port##CLR
 574 #define CREATE_PORT_NAME_SET(port) port##SET
 575
 576 #define GET_IN_PIN(port,in)     ((CREATE_PORT_NAME_PIN(port) & in)?1:0)
 577 #define GET_IN_PORT(port)       (CREATE_PORT_NAME_PIN(port))
 578 #define SET_OUT_PIN(port,out)   (CREATE_PORT_NAME_SET(port)=out)
 579 #define CLR_OUT_PIN(port,out)   (CREATE_PORT_NAME_CLR(port)=out)
 580
 581 /***************************************************************************/
 582 /* watchdog */
 583 #define WATCHDOG_ENABLED
 584 #define WATCHDOG_TIMEOUT_MS     1000
 585
 586 /***************************************************************************/
 587 /* uLan configuration */
 588
 589 #ifdef UL_LOG_ENABLE
 590   #undef UL_LOG_ENABLE
 591 #endif
 592
 593 #ifdef ULD_DEFAULT_BUFFER_SIZE
 594   #undef ULD_DEFAULT_BUFFER_SIZE
 595   #define ULD_DEFAULT_BUFFER_SIZE 0x0800
 596 #endif
 597
 598 #define UL_DRV_SYSLESS_PORT UART1_BASE
 599 #define UL_DRV_SYSLESS_BAUD 19200
 600 #define UL_DRV_SYSLESS_IRQ UART1_IRQn
 601 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1
 602
 603 #define watchdog_feed lpc_watchdog_feed
 604 #define kvpb_erase lpcisp_kvpb_erase
 605 #define kvpb_copy lpcisp_kvpb_copy
 606 #define kvpb_flush lpcisp_kvpb_flush
 607 #define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO
 608
 609
 610
 611
 612
 613
 614
 615
 616 #endif /* _SYSTEM_DEF_H_ */