4 * Derived from the M2M implementation of Open Controller, by Ruud Vlaming
5 * and Peter W. Zuidema.
6 * Tran Duy Khanh <tran@pbmaster.org>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
19 #ifndef _SYSTEM_DEF_H_
20 #define _SYSTEM_DEF_H_
23 * OpenController OC8 (backplane)
24 * left to right: PB30 PB28 PB23 PB22 PB29 PB27 PB26 PB21
26 #define AT91B_LED1 (1<<27) /**< A2 - Rightmost LED */
27 #define AT91B_LED2 (1<<28) /**< B2 */
28 #define AT91B_LED3 (1<<29) /**< A1 */
29 #define AT91B_LED4 (1<<30) /**< B1 - Leftmost LED */
30 #define AT91B_LED5 (1<<21) /**< A4 */
31 #define AT91B_LED6 (1<<22) /**< B4 */
32 #define AT91B_LED7 (1<<26) /**< A3 */
33 #define AT91B_LED8 (1<<23) /**< B3 */
34 #define AT91B_NB_LED 4 /**< Number of LEDs */
35 #define AT91B_LED_MASK (AT91B_LED1|AT91B_LED2|AT91B_LED3|AT91B_LED4)
37 #define AT91B_POWERLED (1<<12) /** < PB12 */
39 /* All LEDs are on this PIO controller */
40 #define AT91D_BASE_PIO_LED (AT91C_BASE_PIOB)
45 #define M2M_ADC_CH1 AT91C_ADC_CH6 /**< Connector 4 Pin 2 'AD1' */
46 #define M2M_ADC_CH2 AT91C_ADC_CH7 /**< Connector 4 Pin 3 'AD2' */
47 #define M2M_ADC_CH3 AT91C_ADC_CH4 /**< Connector 7 Pin 2 'AD3' */
48 #define M2M_ADC_CH4 AT91C_ADC_CH5 /**< Connector 7 Pin 3 'AD4' */
49 #define M2M_ADC_CHANNEL_MASK (M2M_ADC_CH1 | M2M_ADC_CH2 | M2M_ADC_CH3 | M2M_ADC_CH4)
52 * Serial port definitions
53 * The linedriver between the microcontroller and the connector can switch
54 * between RS-232 and RS-485 mode. When in differential mode (RS-485) the RTS
55 * line is used to enable the TX outputs.
58 /* Serial port 0 : OC8 connector C5 (ethernet side) */
59 #define M2M_USART0_BASE AT91C_BASE_US0 /**< Serial port 0 base register */
60 #define M2M_USART0_ID AT91C_ID_US0 /**< Serial port 0 peripheral ID */
61 #define M2M_USART0_485 AT91C_PIO_PA2 /**< IO line to select mode RS-485 (1) or RS-232 (0) */
62 #define M2M_USART0_485_PIO AT91C_BASE_PIOA /**< IO line connected to PIO A or B */
63 #define M2M_USART0_RXD AT91C_PA0_RXD0 /**< RXD input pin : C5.2 and C5.5 (peripheral A) */
64 #define M2M_USART0_TXD AT91C_PA1_TXD0 /**< TXD output pin : C5.3 and C5.4 (peripheral A) */
65 #define M2M_USART0_RTS AT91C_PA3_RTS0 /**< RTS output pin : C5.7 (peripheral A) */
66 #define M2M_USART0_CTS AT91C_PA4_CTS0 /**< CTS input pin : C5.6 (peripheral A) */
68 /* Serial port 1 : OC8 connector C2 (next power connector) */
69 #define M2M_USART1_BASE AT91C_BASE_US1 /**< Serial port 1 base register */
70 #define M2M_USART1_ID AT91C_ID_US1 /**< Serial port 1 peripheral ID */
71 #define M2M_USART1_485 AT91C_PIO_PB18 /**< IO line to select mode RS-485 (1) or RS-232 (0) */
72 #define M2M_USART1_485_PIO AT91C_BASE_PIOB /**< IO line connected to PIO A or B */
73 #define M2M_USART1_RXD AT91C_PA5_RXD1 /**< RXD input pin : C2.2 and C2.5 (peripheral A) */
74 #define M2M_USART1_TXD AT91C_PA6_TXD1 /**< TXD output pin : C2.3 and C2.4 (peripheral A) */
75 #define M2M_USART1_RTS AT91C_PA8_RTS1 /**< RTS output pin : C2. (peripheral A) */
76 #define M2M_USART1_CTS AT91C_PA9_CTS1 /**< CTS input pin : C2. (peripheral A) */
77 #define M2M_USART1_DSR AT91C_PB24_DSR1 /**< DSR input pin : C2. (peripheral B) */
78 #define M2M_USART1_DTR AT91C_PB25_DTR1 /**< DTR output pin : C2. (peripheral B) */
80 /* Definitions for (old) comm/serial.c */
81 #define serCOM AT91C_BASE_US1 /**< Serial port base register */
82 #define serCOM_ID AT91C_ID_US1 /**< Serial port peripheral ID */
83 #define US_RXD_PIN AT91C_PA5_RXD1 /**< RXD input pin : C2.2 (peripheral A) */
84 #define US_TXD_PIN AT91C_PA6_TXD1 /**< TXD output pin : C2.3 (peripheral A) */
91 * Maximal SPI clock speed in Hz.
93 * Uses configCPU_CLOCK_HZ to calculate the settings. The resulting clock
94 * speed is MCK divided by an integer (1-255).
96 #define AT91C_SPI_CLK 16000000
99 * DAC - Digital to Analog Converter - SPI channel
101 #define M2M_DAC_SPI AT91C_BASE_SPI1
104 * DAC SPI ChipSelect address
105 * Select CS2 in the '4-to-16' mode: 1011b
107 #define M2M_DAC_CS 0xB
110 * DataFlash 4Mbit AT45DB321 / 16Mbit AT45161
112 #define M2M_DF_SPI AT91C_BASE_SPI1
115 * DataFlash ChipSelect address
116 * Select CS1 in the '4-to-16' mode: 1101b
118 #define M2M_DF_CS 0xD
121 * Front IO Expander MCP23S17 for joystick and OLED (OC8 only)
123 * Connected via demultiplexer 74AHC138 output Y0.
124 * SPI mode 3 (CPOL=1, NCPHA=0)
126 #define M2M_SPI_FRONT AT91C_BASE_SPI0
129 * Front IO expander SPI ChipSelect address
131 * Demux Y0 -> CBA = 000 -> CS0=0, CS1=0, CS3=0 => %0x00 = 0|4
132 * 4-to-16 mode (PCSDEC=1) use group 0-3 = CS0
134 #define M2M_SPI_FRONT_CS 0x0
139 * Connected via demultiplexer 74AHC138 output Y1.
140 * SPI mode 3 (CPOL=1, NCPHA=0)
142 #define M2M_SPI_SDCARD AT91C_BASE_SPI0
145 * SD-Card SPI ChipSelect address
147 * Demux Y1 -> CBA = 001 -> CS0=0, CS1=0, CS3=1 => %0x08 = 8|C
148 * 4-to-16 mode (PCSDEC=1) use group 8-11 = CS2
150 #define M2M_SPI_SDCARD_CS 0x8
153 * CARD A and CARD B are connected to this SPI bus.
155 * CARD A is located at the ethernet side. CARD B is located at the power side.
157 #define M2M_SPI_CARDS AT91C_BASE_SPI0
160 * CARD A CS1 ChipSelect address
162 * Demux Y5 -> CBA = 101 -> CS0=1, CS1=0, CS3=1 => %1x01 = 9|13
163 * 4-to-16 mode (PCSDEC=1) use group 8-11 = CS2
165 #define M2M_SPI_CARDA_CS1 0x9
168 * CARD A CS2 ChipSelect address
170 * Demux Y4 -> CBA = 100 -> CS0=1, CS1=0, CS3=0 => %0x01 = 1|5
171 * 4-to-16 mode (PCSDEC=1) use group 0-3 = CS0
173 #define M2M_SPI_CARDA_CS2 0x1
176 * CARD B CS1 ChipSelect address
178 * Demux Y3 -> CBA = 011 -> CS0=0, CS1=1, CS3=1 => %1x10 = 10|14
179 * 4-to-16 mode (PCSDEC=1) use group 8-11 = CS2
181 #define M2M_SPI_CARDB_CS1 0xA
184 * CARD B CS2 ChipSelect address
186 * Demux Y2 -> CBA = 010 -> CS0=0, CS1=1, CS3=0 => %0x10 = 2|6
187 * 4-to-16 mode (PCSDEC=1) use group 0-3 = CS0
189 #define M2M_SPI_CARDB_CS2 0x2
192 * IO Expander MCP23S17 to read the input on the backplane
194 * Connected via demultiplexer 74AHC138.
195 * SPI mode 3 (CPOL=1, NCPHA=0)
196 * \deprecated Obsolete (only rev 3 backplanes)
198 #define M2M_IOEXP_SPI AT91C_BASE_SPI0
201 * IO expander SPI ChipSelect address
202 * CS3 must be high : 1xxxb -> 4-to-16 mode 1110 = CS0
203 * Demux Y5 -> ABC = 101 -> CS0=1 CS1=0 CS3=1 = %1101 = 0xD
204 * \deprecated Obsolete (only rev 3 backplanes)
206 #define M2M_IOEXP_CS 0xD
209 * DataFlash definitions
213 * Page size in bytes of the applied DataFlash chip.
215 #define M2M_DF_PAGE_SIZE 528
218 * Total number of pages of the applied DataFlash chip.
220 * The 4Mbit DataFlash AT45DB041 has 2048 pages of 264 byte.\n
221 * The 16Mbit DataFlash AT45DB161 has 4096 pages of 528 byte.\n
222 * The 32Mbit DataFlash AT45DB321 has 8192 pages of 528 byte.\n
223 * The 64Mbit DataFlash AT45DB642 has 8192 pages of 1056 byte.\n
225 #define M2M_DF_PAGES 4096
228 * The page number where the settings start in the DataFlash.
230 #define M2M_DF_SETTINGS_FIRSTPAGE 0
233 * The number of pages reserved for the settings.
235 #define M2M_DF_SETTINGS_PAGES 1
238 * The page number where the logging starts in the DataFlash
240 #define M2M_DF_LOG_FIRSTPAGE 1
243 * The number of pages reserved for the logging.
245 #define M2M_DF_LOG_PAGES 3071
248 * The page number where the 1st firmware starts in the DataFlash.
250 #define M2M_DF_FW1_FIRSTPAGE 3072
253 * The number of pages reserved for the 1st firmware.
255 #define M2M_DF_FW1_PAGES 512
258 * The page number where the 2nd firmware starts in the DataFlash.
260 #define M2M_DF_FW2_FIRSTPAGE 3584
263 * The number of pages reserved for the 2nd firmware.
265 #define M2M_DF_FW2_PAGES 512
268 * I2C-bus definitions
272 * SE95 temperature sensor slave address.
274 * Sensor directly connected to the microcontroller TWI-bus.
276 #define M2M_I2C_SE95 0x1
279 * Oscillator definitions
283 * Main Oscillator frequency in Hertz - MAINCK.
285 * Never used yet, but should be in calculation below.
287 #define AT91B_MAIN_OSC 20000000
290 * configCPU_CLOCK_HZ = 47923200 (See FreeRTOSConfig.h)
292 * This macro is called from Cstartup_SAM7.c (ARM mode)
294 * TODO calculate it using AT91B_MAIN_OSC.
296 * PLLCK = MAINCK / DIV * (MUL + 1) =
298 * 14.318 MHz: DIV = 17; MUL = 113 -> PLLCK = 96014823 Hz \n
299 * 18.432 MHz: DIV = 5; MUL = 25 -> PLLCK = 95846400 Hz -> CPU CK = 47923200 Hz \n
300 * 20.000 MHz: DIV = 20; MUL = 95 -> PLLCK = 96000000 Hz -> CPU CK = 48000000 Hz \n
302 #define Set_pPMC_PMC_PLLR() \
303 pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 20) | \
304 (AT91C_CKGR_PLLCOUNT & (28<<8)) | \
305 (AT91C_CKGR_MUL & (95<<16)))
307 #endif /* _SYSTEM_DEF_H_ */