1 /* - ----------------------------------------------------------------------------
2 // - ATMEL Microcontroller Software Support - ROUSSET -
3 // - ----------------------------------------------------------------------------
4 // - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
5 // - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6 // - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
7 // - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
8 // - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
9 // - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
10 // - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
11 // - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
12 // - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
13 // - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14 // - ----------------------------------------------------------------------------
15 // - File Name : AT91SAM7XC256.h
16 // - Object : AT91SAM7XC256 definitions
17 // - Generated : AT91 SW Application Group 11/02/2005 (17:07:34)
19 // - CVS Reference : /AT91SAM7XC256.pl/1.1/Wed Nov 2 13:59:10 2005//
20 // - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
21 // - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
22 // - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
23 // - CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
24 // - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
25 // - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
26 // - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
27 // - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
28 // - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
29 // - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
30 // - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
31 // - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
32 // - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
33 // - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
34 // - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
35 // - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
36 // - CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
37 // - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
38 // - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
39 // - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
40 // - CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
41 // - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
42 // - CVS Reference : /AES_6149A.pl/1.12/Wed Nov 2 14:15:23 2005//
43 // - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
44 // - ----------------------------------------------------------------------------*/
46 #ifndef AT91SAM7XC256_H
47 #define AT91SAM7XC256_H
56 * @brief Microcontroller AT91SAM7XC256 definitions.
60 typedef volatile unsigned int AT91_REG; /* Hardware register definition */
62 /* *****************************************************************************
63 // SOFTWARE API DEFINITION FOR System Peripherals
64 // *****************************************************************************/
65 typedef struct _AT91S_SYS {
66 AT91_REG AIC_SMR[32]; // Source Mode Register
67 AT91_REG AIC_SVR[32]; // Source Vector Register
68 AT91_REG AIC_IVR; // IRQ Vector Register
69 AT91_REG AIC_FVR; // FIQ Vector Register
70 AT91_REG AIC_ISR; // Interrupt Status Register
71 AT91_REG AIC_IPR; // Interrupt Pending Register
72 AT91_REG AIC_IMR; // Interrupt Mask Register
73 AT91_REG AIC_CISR; // Core Interrupt Status Register
74 AT91_REG Reserved0[2]; //
75 AT91_REG AIC_IECR; // Interrupt Enable Command Register
76 AT91_REG AIC_IDCR; // Interrupt Disable Command Register
77 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
78 AT91_REG AIC_ISCR; // Interrupt Set Command Register
79 AT91_REG AIC_EOICR; // End of Interrupt Command Register
80 AT91_REG AIC_SPU; // Spurious Vector Register
81 AT91_REG AIC_DCR; // Debug Control Register (Protect)
82 AT91_REG Reserved1[1]; //
83 AT91_REG AIC_FFER; // Fast Forcing Enable Register
84 AT91_REG AIC_FFDR; // Fast Forcing Disable Register
85 AT91_REG AIC_FFSR; // Fast Forcing Status Register
86 AT91_REG Reserved2[45]; //
87 AT91_REG DBGU_CR; // Control Register
88 AT91_REG DBGU_MR; // Mode Register
89 AT91_REG DBGU_IER; // Interrupt Enable Register
90 AT91_REG DBGU_IDR; // Interrupt Disable Register
91 AT91_REG DBGU_IMR; // Interrupt Mask Register
92 AT91_REG DBGU_CSR; // Channel Status Register
93 AT91_REG DBGU_RHR; // Receiver Holding Register
94 AT91_REG DBGU_THR; // Transmitter Holding Register
95 AT91_REG DBGU_BRGR; // Baud Rate Generator Register
96 AT91_REG Reserved3[7]; //
97 AT91_REG DBGU_CIDR; // Chip ID Register
98 AT91_REG DBGU_EXID; // Chip ID Extension Register
99 AT91_REG DBGU_FNTR; // Force NTRST Register
100 AT91_REG Reserved4[45]; //
101 AT91_REG DBGU_RPR; // Receive Pointer Register
102 AT91_REG DBGU_RCR; // Receive Counter Register
103 AT91_REG DBGU_TPR; // Transmit Pointer Register
104 AT91_REG DBGU_TCR; // Transmit Counter Register
105 AT91_REG DBGU_RNPR; // Receive Next Pointer Register
106 AT91_REG DBGU_RNCR; // Receive Next Counter Register
107 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
108 AT91_REG DBGU_TNCR; // Transmit Next Counter Register
109 AT91_REG DBGU_PTCR; // PDC Transfer Control Register
110 AT91_REG DBGU_PTSR; // PDC Transfer Status Register
111 AT91_REG Reserved5[54]; //
112 AT91_REG PIOA_PER; // PIO Enable Register
113 AT91_REG PIOA_PDR; // PIO Disable Register
114 AT91_REG PIOA_PSR; // PIO Status Register
115 AT91_REG Reserved6[1]; //
116 AT91_REG PIOA_OER; // Output Enable Register
117 AT91_REG PIOA_ODR; // Output Disable Registerr
118 AT91_REG PIOA_OSR; // Output Status Register
119 AT91_REG Reserved7[1]; //
120 AT91_REG PIOA_IFER; // Input Filter Enable Register
121 AT91_REG PIOA_IFDR; // Input Filter Disable Register
122 AT91_REG PIOA_IFSR; // Input Filter Status Register
123 AT91_REG Reserved8[1]; //
124 AT91_REG PIOA_SODR; // Set Output Data Register
125 AT91_REG PIOA_CODR; // Clear Output Data Register
126 AT91_REG PIOA_ODSR; // Output Data Status Register
127 AT91_REG PIOA_PDSR; // Pin Data Status Register
128 AT91_REG PIOA_IER; // Interrupt Enable Register
129 AT91_REG PIOA_IDR; // Interrupt Disable Register
130 AT91_REG PIOA_IMR; // Interrupt Mask Register
131 AT91_REG PIOA_ISR; // Interrupt Status Register
132 AT91_REG PIOA_MDER; // Multi-driver Enable Register
133 AT91_REG PIOA_MDDR; // Multi-driver Disable Register
134 AT91_REG PIOA_MDSR; // Multi-driver Status Register
135 AT91_REG Reserved9[1]; //
136 AT91_REG PIOA_PPUDR; // Pull-up Disable Register
137 AT91_REG PIOA_PPUER; // Pull-up Enable Register
138 AT91_REG PIOA_PPUSR; // Pull-up Status Register
139 AT91_REG Reserved10[1]; //
140 AT91_REG PIOA_ASR; // Select A Register
141 AT91_REG PIOA_BSR; // Select B Register
142 AT91_REG PIOA_ABSR; // AB Select Status Register
143 AT91_REG Reserved11[9]; //
144 AT91_REG PIOA_OWER; // Output Write Enable Register
145 AT91_REG PIOA_OWDR; // Output Write Disable Register
146 AT91_REG PIOA_OWSR; // Output Write Status Register
147 AT91_REG Reserved12[85]; //
148 AT91_REG PIOB_PER; // PIO Enable Register
149 AT91_REG PIOB_PDR; // PIO Disable Register
150 AT91_REG PIOB_PSR; // PIO Status Register
151 AT91_REG Reserved13[1]; //
152 AT91_REG PIOB_OER; // Output Enable Register
153 AT91_REG PIOB_ODR; // Output Disable Registerr
154 AT91_REG PIOB_OSR; // Output Status Register
155 AT91_REG Reserved14[1]; //
156 AT91_REG PIOB_IFER; // Input Filter Enable Register
157 AT91_REG PIOB_IFDR; // Input Filter Disable Register
158 AT91_REG PIOB_IFSR; // Input Filter Status Register
159 AT91_REG Reserved15[1]; //
160 AT91_REG PIOB_SODR; // Set Output Data Register
161 AT91_REG PIOB_CODR; // Clear Output Data Register
162 AT91_REG PIOB_ODSR; // Output Data Status Register
163 AT91_REG PIOB_PDSR; // Pin Data Status Register
164 AT91_REG PIOB_IER; // Interrupt Enable Register
165 AT91_REG PIOB_IDR; // Interrupt Disable Register
166 AT91_REG PIOB_IMR; // Interrupt Mask Register
167 AT91_REG PIOB_ISR; // Interrupt Status Register
168 AT91_REG PIOB_MDER; // Multi-driver Enable Register
169 AT91_REG PIOB_MDDR; // Multi-driver Disable Register
170 AT91_REG PIOB_MDSR; // Multi-driver Status Register
171 AT91_REG Reserved16[1]; //
172 AT91_REG PIOB_PPUDR; // Pull-up Disable Register
173 AT91_REG PIOB_PPUER; // Pull-up Enable Register
174 AT91_REG PIOB_PPUSR; // Pull-up Status Register
175 AT91_REG Reserved17[1]; //
176 AT91_REG PIOB_ASR; // Select A Register
177 AT91_REG PIOB_BSR; // Select B Register
178 AT91_REG PIOB_ABSR; // AB Select Status Register
179 AT91_REG Reserved18[9]; //
180 AT91_REG PIOB_OWER; // Output Write Enable Register
181 AT91_REG PIOB_OWDR; // Output Write Disable Register
182 AT91_REG PIOB_OWSR; // Output Write Status Register
183 AT91_REG Reserved19[341]; //
184 AT91_REG PMC_SCER; // System Clock Enable Register
185 AT91_REG PMC_SCDR; // System Clock Disable Register
186 AT91_REG PMC_SCSR; // System Clock Status Register
187 AT91_REG Reserved20[1]; //
188 AT91_REG PMC_PCER; // Peripheral Clock Enable Register
189 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
190 AT91_REG PMC_PCSR; // Peripheral Clock Status Register
191 AT91_REG Reserved21[1]; //
192 AT91_REG PMC_MOR; // Main Oscillator Register
193 AT91_REG PMC_MCFR; // Main Clock Frequency Register
194 AT91_REG Reserved22[1]; //
195 AT91_REG PMC_PLLR; // PLL Register
196 AT91_REG PMC_MCKR; // Master Clock Register
197 AT91_REG Reserved23[3]; //
198 AT91_REG PMC_PCKR[4]; // Programmable Clock Register
199 AT91_REG Reserved24[4]; //
200 AT91_REG PMC_IER; // Interrupt Enable Register
201 AT91_REG PMC_IDR; // Interrupt Disable Register
202 AT91_REG PMC_SR; // Status Register
203 AT91_REG PMC_IMR; // Interrupt Mask Register
204 AT91_REG Reserved25[36]; //
205 AT91_REG RSTC_RCR; // Reset Control Register
206 AT91_REG RSTC_RSR; // Reset Status Register
207 AT91_REG RSTC_RMR; // Reset Mode Register
208 AT91_REG Reserved26[5]; //
209 AT91_REG RTTC_RTMR; // Real-time Mode Register
210 AT91_REG RTTC_RTAR; // Real-time Alarm Register
211 AT91_REG RTTC_RTVR; // Real-time Value Register
212 AT91_REG RTTC_RTSR; // Real-time Status Register
213 AT91_REG PITC_PIMR; // Period Interval Mode Register
214 AT91_REG PITC_PISR; // Period Interval Status Register
215 AT91_REG PITC_PIVR; // Period Interval Value Register
216 AT91_REG PITC_PIIR; // Period Interval Image Register
217 AT91_REG WDTC_WDCR; // Watchdog Control Register
218 AT91_REG WDTC_WDMR; // Watchdog Mode Register
219 AT91_REG WDTC_WDSR; // Watchdog Status Register
220 AT91_REG Reserved27[5]; //
221 AT91_REG VREG_MR; // Voltage Regulator Mode Register
222 } AT91S_SYS, *AT91PS_SYS;
225 // *****************************************************************************
226 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
227 // *****************************************************************************
228 typedef struct _AT91S_AIC {
229 AT91_REG AIC_SMR[32]; // Source Mode Register
230 AT91_REG AIC_SVR[32]; // Source Vector Register
231 AT91_REG AIC_IVR; // IRQ Vector Register
232 AT91_REG AIC_FVR; // FIQ Vector Register
233 AT91_REG AIC_ISR; // Interrupt Status Register
234 AT91_REG AIC_IPR; // Interrupt Pending Register
235 AT91_REG AIC_IMR; // Interrupt Mask Register
236 AT91_REG AIC_CISR; // Core Interrupt Status Register
237 AT91_REG Reserved0[2]; //
238 AT91_REG AIC_IECR; // Interrupt Enable Command Register
239 AT91_REG AIC_IDCR; // Interrupt Disable Command Register
240 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
241 AT91_REG AIC_ISCR; // Interrupt Set Command Register
242 AT91_REG AIC_EOICR; // End of Interrupt Command Register
243 AT91_REG AIC_SPU; // Spurious Vector Register
244 AT91_REG AIC_DCR; // Debug Control Register (Protect)
245 AT91_REG Reserved1[1]; //
246 AT91_REG AIC_FFER; // Fast Forcing Enable Register
247 AT91_REG AIC_FFDR; // Fast Forcing Disable Register
248 AT91_REG AIC_FFSR; // Fast Forcing Status Register
249 } AT91S_AIC, *AT91PS_AIC;
251 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
252 #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
253 #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
254 #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
255 #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
256 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
257 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
258 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
259 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
260 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
261 #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
262 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
263 #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
264 #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
265 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
266 #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
267 #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
269 // *****************************************************************************
270 // SOFTWARE API DEFINITION FOR Peripheral DMA Controller
271 // *****************************************************************************
272 typedef struct _AT91S_PDC {
273 AT91_REG PDC_RPR; // Receive Pointer Register
274 AT91_REG PDC_RCR; // Receive Counter Register
275 AT91_REG PDC_TPR; // Transmit Pointer Register
276 AT91_REG PDC_TCR; // Transmit Counter Register
277 AT91_REG PDC_RNPR; // Receive Next Pointer Register
278 AT91_REG PDC_RNCR; // Receive Next Counter Register
279 AT91_REG PDC_TNPR; // Transmit Next Pointer Register
280 AT91_REG PDC_TNCR; // Transmit Next Counter Register
281 AT91_REG PDC_PTCR; // PDC Transfer Control Register
282 AT91_REG PDC_PTSR; // PDC Transfer Status Register
283 } AT91S_PDC, *AT91PS_PDC;
285 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
286 #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
287 #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
288 #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
289 #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
290 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
292 // *****************************************************************************
293 // SOFTWARE API DEFINITION FOR Debug Unit
294 // *****************************************************************************
295 typedef struct _AT91S_DBGU {
296 AT91_REG DBGU_CR; // Control Register
297 AT91_REG DBGU_MR; // Mode Register
298 AT91_REG DBGU_IER; // Interrupt Enable Register
299 AT91_REG DBGU_IDR; // Interrupt Disable Register
300 AT91_REG DBGU_IMR; // Interrupt Mask Register
301 AT91_REG DBGU_CSR; // Channel Status Register
302 AT91_REG DBGU_RHR; // Receiver Holding Register
303 AT91_REG DBGU_THR; // Transmitter Holding Register
304 AT91_REG DBGU_BRGR; // Baud Rate Generator Register
305 AT91_REG Reserved0[7]; //
306 AT91_REG DBGU_CIDR; // Chip ID Register
307 AT91_REG DBGU_EXID; // Chip ID Extension Register
308 AT91_REG DBGU_FNTR; // Force NTRST Register
309 AT91_REG Reserved1[45]; //
310 AT91_REG DBGU_RPR; // Receive Pointer Register
311 AT91_REG DBGU_RCR; // Receive Counter Register
312 AT91_REG DBGU_TPR; // Transmit Pointer Register
313 AT91_REG DBGU_TCR; // Transmit Counter Register
314 AT91_REG DBGU_RNPR; // Receive Next Pointer Register
315 AT91_REG DBGU_RNCR; // Receive Next Counter Register
316 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
317 AT91_REG DBGU_TNCR; // Transmit Next Counter Register
318 AT91_REG DBGU_PTCR; // PDC Transfer Control Register
319 AT91_REG DBGU_PTSR; // PDC Transfer Status Register
320 } AT91S_DBGU, *AT91PS_DBGU;
322 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
323 #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
324 #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
325 #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
326 #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
327 #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
328 #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
329 #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
330 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
331 #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
332 #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
333 #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
334 #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
335 #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
336 #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
337 #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
338 #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
339 #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
340 #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
341 #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
342 #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
343 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
344 #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
345 #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
346 #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
347 #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
348 #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
349 #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
350 #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
351 #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
352 #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
353 #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
354 #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
355 #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
356 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
357 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
358 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
359 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
360 #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
362 // *****************************************************************************
363 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
364 // *****************************************************************************
365 typedef struct _AT91S_PIO {
366 AT91_REG PIO_PER; // PIO Enable Register
367 AT91_REG PIO_PDR; // PIO Disable Register
368 AT91_REG PIO_PSR; // PIO Status Register
369 AT91_REG Reserved0[1]; //
370 AT91_REG PIO_OER; // Output Enable Register
371 AT91_REG PIO_ODR; // Output Disable Registerr
372 AT91_REG PIO_OSR; // Output Status Register
373 AT91_REG Reserved1[1]; //
374 AT91_REG PIO_IFER; // Input Filter Enable Register
375 AT91_REG PIO_IFDR; // Input Filter Disable Register
376 AT91_REG PIO_IFSR; // Input Filter Status Register
377 AT91_REG Reserved2[1]; //
378 AT91_REG PIO_SODR; // Set Output Data Register
379 AT91_REG PIO_CODR; // Clear Output Data Register
380 AT91_REG PIO_ODSR; // Output Data Status Register
381 AT91_REG PIO_PDSR; // Pin Data Status Register
382 AT91_REG PIO_IER; // Interrupt Enable Register
383 AT91_REG PIO_IDR; // Interrupt Disable Register
384 AT91_REG PIO_IMR; // Interrupt Mask Register
385 AT91_REG PIO_ISR; // Interrupt Status Register
386 AT91_REG PIO_MDER; // Multi-driver Enable Register
387 AT91_REG PIO_MDDR; // Multi-driver Disable Register
388 AT91_REG PIO_MDSR; // Multi-driver Status Register
389 AT91_REG Reserved3[1]; //
390 AT91_REG PIO_PPUDR; // Pull-up Disable Register
391 AT91_REG PIO_PPUER; // Pull-up Enable Register
392 AT91_REG PIO_PPUSR; // Pull-up Status Register
393 AT91_REG Reserved4[1]; //
394 AT91_REG PIO_ASR; // Select A Register
395 AT91_REG PIO_BSR; // Select B Register
396 AT91_REG PIO_ABSR; // AB Select Status Register
397 AT91_REG Reserved5[9]; //
398 AT91_REG PIO_OWER; // Output Write Enable Register
399 AT91_REG PIO_OWDR; // Output Write Disable Register
400 AT91_REG PIO_OWSR; // Output Write Status Register
401 } AT91S_PIO, *AT91PS_PIO;
404 // *****************************************************************************
405 // SOFTWARE API DEFINITION FOR Clock Generator Controler
406 // *****************************************************************************
407 typedef struct _AT91S_CKGR {
408 AT91_REG CKGR_MOR; // Main Oscillator Register
409 AT91_REG CKGR_MCFR; // Main Clock Frequency Register
410 AT91_REG Reserved0[1]; //
411 AT91_REG CKGR_PLLR; // PLL Register
412 } AT91S_CKGR, *AT91PS_CKGR;
414 // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
415 #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
416 #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
417 #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
418 // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
419 #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
420 #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
421 // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
422 #define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
423 #define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
424 #define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
425 #define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
426 #define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
427 #define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
428 #define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
429 #define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
430 #define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
431 #define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
432 #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
433 #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
434 #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
435 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
437 // *****************************************************************************
438 // SOFTWARE API DEFINITION FOR Power Management Controler
439 // *****************************************************************************
440 typedef struct _AT91S_PMC {
441 AT91_REG PMC_SCER; // System Clock Enable Register
442 AT91_REG PMC_SCDR; // System Clock Disable Register
443 AT91_REG PMC_SCSR; // System Clock Status Register
444 AT91_REG Reserved0[1]; //
445 AT91_REG PMC_PCER; // Peripheral Clock Enable Register
446 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
447 AT91_REG PMC_PCSR; // Peripheral Clock Status Register
448 AT91_REG Reserved1[1]; //
449 AT91_REG PMC_MOR; // Main Oscillator Register
450 AT91_REG PMC_MCFR; // Main Clock Frequency Register
451 AT91_REG Reserved2[1]; //
452 AT91_REG PMC_PLLR; // PLL Register
453 AT91_REG PMC_MCKR; // Master Clock Register
454 AT91_REG Reserved3[3]; //
455 AT91_REG PMC_PCKR[4]; // Programmable Clock Register
456 AT91_REG Reserved4[4]; //
457 AT91_REG PMC_IER; // Interrupt Enable Register
458 AT91_REG PMC_IDR; // Interrupt Disable Register
459 AT91_REG PMC_SR; // Status Register
460 AT91_REG PMC_IMR; // Interrupt Mask Register
461 } AT91S_PMC, *AT91PS_PMC;
463 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
464 #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
465 #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
466 #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
467 #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
468 #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
469 #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
470 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
471 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
472 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
473 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
474 // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
475 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
476 #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
477 #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
478 #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
479 #define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
480 #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
481 #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
482 #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
483 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
484 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
485 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
486 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
487 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
488 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
489 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
490 #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
491 #define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
492 #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
493 #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
494 #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
495 #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
496 #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
497 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
498 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
499 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
501 // *****************************************************************************
502 // SOFTWARE API DEFINITION FOR Reset Controller Interface
503 // *****************************************************************************
504 typedef struct _AT91S_RSTC {
505 AT91_REG RSTC_RCR; // Reset Control Register
506 AT91_REG RSTC_RSR; // Reset Status Register
507 AT91_REG RSTC_RMR; // Reset Mode Register
508 } AT91S_RSTC, *AT91PS_RSTC;
510 // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
511 #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
512 #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
513 #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
514 #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
515 // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
516 #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
517 #define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
518 #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
519 #define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
520 #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
521 #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
522 #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
523 #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
524 #define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
525 #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
526 #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
527 // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
528 #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
529 #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
530 #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length
531 #define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
533 // *****************************************************************************
534 // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
535 // *****************************************************************************
536 typedef struct _AT91S_RTTC {
537 AT91_REG RTTC_RTMR; // Real-time Mode Register
538 AT91_REG RTTC_RTAR; // Real-time Alarm Register
539 AT91_REG RTTC_RTVR; // Real-time Value Register
540 AT91_REG RTTC_RTSR; // Real-time Status Register
541 } AT91S_RTTC, *AT91PS_RTTC;
543 // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
544 #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
545 #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
546 #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
547 #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
548 // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
549 #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
550 // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
551 #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
552 // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
553 #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
554 #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
556 // *****************************************************************************
557 // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
558 // *****************************************************************************
559 typedef struct _AT91S_PITC {
560 AT91_REG PITC_PIMR; // Period Interval Mode Register
561 AT91_REG PITC_PISR; // Period Interval Status Register
562 AT91_REG PITC_PIVR; // Period Interval Value Register
563 AT91_REG PITC_PIIR; // Period Interval Image Register
564 } AT91S_PITC, *AT91PS_PITC;
566 // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
567 #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
568 #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
569 #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
570 // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
571 #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
572 // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
573 #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
574 #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
575 // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
577 // *****************************************************************************
578 // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
579 // *****************************************************************************
580 typedef struct _AT91S_WDTC {
581 AT91_REG WDTC_WDCR; // Watchdog Control Register
582 AT91_REG WDTC_WDMR; // Watchdog Mode Register
583 AT91_REG WDTC_WDSR; // Watchdog Status Register
584 } AT91S_WDTC, *AT91PS_WDTC;
586 // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
587 #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
588 #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
589 // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
590 #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
591 #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
592 #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
593 #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
594 #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
595 #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
596 #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
597 #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
598 // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
599 #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
600 #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
602 // *****************************************************************************
603 // SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
604 // *****************************************************************************
605 typedef struct _AT91S_VREG {
606 AT91_REG VREG_MR; // Voltage Regulator Mode Register
607 } AT91S_VREG, *AT91PS_VREG;
609 // -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
610 #define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
612 // *****************************************************************************
613 // SOFTWARE API DEFINITION FOR Memory Controller Interface
614 // *****************************************************************************
615 typedef struct _AT91S_MC {
616 AT91_REG MC_RCR; // MC Remap Control Register
617 AT91_REG MC_ASR; // MC Abort Status Register
618 AT91_REG MC_AASR; // MC Abort Address Status Register
619 AT91_REG Reserved0[21]; //
620 AT91_REG MC_FMR; // MC Flash Mode Register
621 AT91_REG MC_FCR; // MC Flash Command Register
622 AT91_REG MC_FSR; // MC Flash Status Register
623 } AT91S_MC, *AT91PS_MC;
625 // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
626 #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
627 // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
628 #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
629 #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
630 #define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
631 #define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
632 #define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
633 #define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
634 #define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
635 #define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
636 #define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
637 #define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
638 #define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
639 #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
640 #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
641 #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
642 // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
643 #define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
644 #define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
645 #define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
646 #define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
647 #define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
648 #define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
649 #define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
650 #define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
651 #define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
652 #define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
653 // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
654 #define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
655 #define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
656 #define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
657 #define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
658 #define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
659 #define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
660 #define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
661 #define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
662 #define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
663 #define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
664 #define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
665 // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
666 #define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
667 #define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
668 #define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
669 #define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
670 #define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
671 #define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
672 #define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
673 #define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
674 #define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
675 #define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
676 #define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
677 #define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
678 #define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
679 #define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
680 #define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
681 #define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
682 #define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
683 #define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
684 #define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
685 #define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
686 #define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
687 #define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
688 #define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
689 #define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
690 #define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
692 // *****************************************************************************
693 // SOFTWARE API DEFINITION FOR Serial Parallel Interface
694 // *****************************************************************************
695 typedef struct _AT91S_SPI {
696 AT91_REG SPI_CR; // Control Register
697 AT91_REG SPI_MR; // Mode Register
698 AT91_REG SPI_RDR; // Receive Data Register
699 AT91_REG SPI_TDR; // Transmit Data Register
700 AT91_REG SPI_SR; // Status Register
701 AT91_REG SPI_IER; // Interrupt Enable Register
702 AT91_REG SPI_IDR; // Interrupt Disable Register
703 AT91_REG SPI_IMR; // Interrupt Mask Register
704 AT91_REG Reserved0[4]; //
705 AT91_REG SPI_CSR[4]; // Chip Select Register
706 AT91_REG Reserved1[48]; //
707 AT91_REG SPI_RPR; // Receive Pointer Register
708 AT91_REG SPI_RCR; // Receive Counter Register
709 AT91_REG SPI_TPR; // Transmit Pointer Register
710 AT91_REG SPI_TCR; // Transmit Counter Register
711 AT91_REG SPI_RNPR; // Receive Next Pointer Register
712 AT91_REG SPI_RNCR; // Receive Next Counter Register
713 AT91_REG SPI_TNPR; // Transmit Next Pointer Register
714 AT91_REG SPI_TNCR; // Transmit Next Counter Register
715 AT91_REG SPI_PTCR; // PDC Transfer Control Register
716 AT91_REG SPI_PTSR; // PDC Transfer Status Register
717 } AT91S_SPI, *AT91PS_SPI;
719 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
720 #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
721 #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
722 #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
723 #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
724 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
725 #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
726 #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
727 #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
728 #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
729 #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
730 #define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
731 #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
732 #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
733 #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
734 #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
735 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
736 #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
737 #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
738 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
739 #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
740 #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
741 // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
742 #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
743 #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
744 #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
745 #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
746 #define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
747 #define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
748 #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
749 #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
750 #define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
751 #define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
752 #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
753 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
754 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
755 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
756 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
757 #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
758 #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
759 #define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
760 #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
761 #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
762 #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
763 #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
764 #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
765 #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
766 #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
767 #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
768 #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
769 #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
770 #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
771 #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
772 #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
774 // *****************************************************************************
775 // SOFTWARE API DEFINITION FOR Usart
776 // *****************************************************************************
777 typedef struct _AT91S_USART {
778 AT91_REG US_CR; // Control Register
779 AT91_REG US_MR; // Mode Register
780 AT91_REG US_IER; // Interrupt Enable Register
781 AT91_REG US_IDR; // Interrupt Disable Register
782 AT91_REG US_IMR; // Interrupt Mask Register
783 AT91_REG US_CSR; // Channel Status Register
784 AT91_REG US_RHR; // Receiver Holding Register
785 AT91_REG US_THR; // Transmitter Holding Register
786 AT91_REG US_BRGR; // Baud Rate Generator Register
787 AT91_REG US_RTOR; // Receiver Time-out Register
788 AT91_REG US_TTGR; // Transmitter Time-guard Register
789 AT91_REG Reserved0[5]; //
790 AT91_REG US_FIDI; // FI_DI_Ratio Register
791 AT91_REG US_NER; // Nb Errors Register
792 AT91_REG Reserved1[1]; //
793 AT91_REG US_IF; // IRDA_FILTER Register
794 AT91_REG Reserved2[44]; //
795 AT91_REG US_RPR; // Receive Pointer Register
796 AT91_REG US_RCR; // Receive Counter Register
797 AT91_REG US_TPR; // Transmit Pointer Register
798 AT91_REG US_TCR; // Transmit Counter Register
799 AT91_REG US_RNPR; // Receive Next Pointer Register
800 AT91_REG US_RNCR; // Receive Next Counter Register
801 AT91_REG US_TNPR; // Transmit Next Pointer Register
802 AT91_REG US_TNCR; // Transmit Next Counter Register
803 AT91_REG US_PTCR; // PDC Transfer Control Register
804 AT91_REG US_PTSR; // PDC Transfer Status Register
805 } AT91S_USART, *AT91PS_USART;
807 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
808 #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
809 #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
810 #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
811 #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
812 #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
813 #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
814 #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
815 #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
816 #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
817 #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
818 #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
819 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
820 #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
821 #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
822 #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
823 #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
824 #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
825 #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
826 #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
827 #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
828 #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
829 #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
830 #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
831 #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
832 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
833 #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
834 #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
835 #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
836 #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
837 #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
838 #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
839 #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
840 #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
841 #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
842 #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
843 #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
844 #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
845 #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
846 #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
847 #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
848 #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
849 #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
850 #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
851 #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
852 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
853 #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
854 #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
855 #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
856 #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
857 #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
858 #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
859 #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
860 #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
861 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
862 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
863 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
864 #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
865 #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
866 #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
867 #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
869 // *****************************************************************************
870 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
871 // *****************************************************************************
872 typedef struct _AT91S_SSC {
873 AT91_REG SSC_CR; // Control Register
874 AT91_REG SSC_CMR; // Clock Mode Register
875 AT91_REG Reserved0[2]; //
876 AT91_REG SSC_RCMR; // Receive Clock ModeRegister
877 AT91_REG SSC_RFMR; // Receive Frame Mode Register
878 AT91_REG SSC_TCMR; // Transmit Clock Mode Register
879 AT91_REG SSC_TFMR; // Transmit Frame Mode Register
880 AT91_REG SSC_RHR; // Receive Holding Register
881 AT91_REG SSC_THR; // Transmit Holding Register
882 AT91_REG Reserved1[2]; //
883 AT91_REG SSC_RSHR; // Receive Sync Holding Register
884 AT91_REG SSC_TSHR; // Transmit Sync Holding Register
885 AT91_REG Reserved2[2]; //
886 AT91_REG SSC_SR; // Status Register
887 AT91_REG SSC_IER; // Interrupt Enable Register
888 AT91_REG SSC_IDR; // Interrupt Disable Register
889 AT91_REG SSC_IMR; // Interrupt Mask Register
890 AT91_REG Reserved3[44]; //
891 AT91_REG SSC_RPR; // Receive Pointer Register
892 AT91_REG SSC_RCR; // Receive Counter Register
893 AT91_REG SSC_TPR; // Transmit Pointer Register
894 AT91_REG SSC_TCR; // Transmit Counter Register
895 AT91_REG SSC_RNPR; // Receive Next Pointer Register
896 AT91_REG SSC_RNCR; // Receive Next Counter Register
897 AT91_REG SSC_TNPR; // Transmit Next Pointer Register
898 AT91_REG SSC_TNCR; // Transmit Next Counter Register
899 AT91_REG SSC_PTCR; // PDC Transfer Control Register
900 AT91_REG SSC_PTSR; // PDC Transfer Status Register
901 } AT91S_SSC, *AT91PS_SSC;
903 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
904 #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
905 #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
906 #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
907 #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
908 #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
909 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
910 #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
911 #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
912 #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
913 #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
914 #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
915 #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
916 #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
917 #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
918 #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
919 #define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
920 #define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
921 #define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
922 #define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
923 #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
924 #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
925 #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
926 #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
927 #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
928 #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
929 #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
930 #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
931 #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
932 #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
933 #define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
934 #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
935 #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
936 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
937 #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
938 #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
939 #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
940 #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
941 #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
942 #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
943 #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
944 #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
945 #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
946 #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
947 #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
948 #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
949 #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
950 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
951 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
952 #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
953 #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
954 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
955 #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
956 #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
957 #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
958 #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
959 #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
960 #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
961 #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
962 #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
963 #define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
964 #define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
965 #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
966 #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
967 #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
968 #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
969 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
970 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
971 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
973 // *****************************************************************************
974 // SOFTWARE API DEFINITION FOR Two-wire Interface
975 // *****************************************************************************
976 typedef struct _AT91S_TWI {
977 AT91_REG TWI_CR; // Control Register
978 AT91_REG TWI_MMR; // Master Mode Register
979 AT91_REG Reserved0[1]; //
980 AT91_REG TWI_IADR; // Internal Address Register
981 AT91_REG TWI_CWGR; // Clock Waveform Generator Register
982 AT91_REG Reserved1[3]; //
983 AT91_REG TWI_SR; // Status Register
984 AT91_REG TWI_IER; // Interrupt Enable Register
985 AT91_REG TWI_IDR; // Interrupt Disable Register
986 AT91_REG TWI_IMR; // Interrupt Mask Register
987 AT91_REG TWI_RHR; // Receive Holding Register
988 AT91_REG TWI_THR; // Transmit Holding Register
989 } AT91S_TWI, *AT91PS_TWI;
991 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
992 #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
993 #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
994 #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
995 #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
996 #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
997 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
998 #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
999 #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
1000 #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
1001 #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
1002 #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
1003 #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
1004 #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
1005 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
1006 #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
1007 #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
1008 #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
1009 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
1010 #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
1011 #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
1012 #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
1013 #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
1014 #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
1015 #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
1016 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
1017 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
1018 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
1020 // *****************************************************************************
1021 // SOFTWARE API DEFINITION FOR PWMC Channel Interface
1022 // *****************************************************************************
1023 typedef struct _AT91S_PWMC_CH {
1024 AT91_REG PWMC_CMR; // Channel Mode Register
1025 AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
1026 AT91_REG PWMC_CPRDR; // Channel Period Register
1027 AT91_REG PWMC_CCNTR; // Channel Counter Register
1028 AT91_REG PWMC_CUPDR; // Channel Update Register
1029 AT91_REG PWMC_Reserved[3]; // Reserved
1030 } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
1032 // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
1033 #define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
1034 #define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
1035 #define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
1036 #define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
1037 #define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
1038 #define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
1039 #define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
1040 // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
1041 #define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
1042 // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
1043 #define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
1044 // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
1045 #define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
1046 // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
1047 #define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
1049 // *****************************************************************************
1050 // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
1051 // *****************************************************************************
1052 typedef struct _AT91S_PWMC {
1053 AT91_REG PWMC_MR; // PWMC Mode Register
1054 AT91_REG PWMC_ENA; // PWMC Enable Register
1055 AT91_REG PWMC_DIS; // PWMC Disable Register
1056 AT91_REG PWMC_SR; // PWMC Status Register
1057 AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
1058 AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
1059 AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
1060 AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
1061 AT91_REG Reserved0[55]; //
1062 AT91_REG PWMC_VR; // PWMC Version Register
1063 AT91_REG Reserved1[64]; //
1064 AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
1065 } AT91S_PWMC, *AT91PS_PWMC;
1067 // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
1068 #define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
1069 #define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
1070 #define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
1071 #define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
1072 #define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
1073 #define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
1074 // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
1075 #define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
1076 #define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
1077 #define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
1078 #define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
1079 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
1080 // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
1081 // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
1082 // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
1083 // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
1084 // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
1086 // *****************************************************************************
1087 // SOFTWARE API DEFINITION FOR USB Device Interface
1088 // *****************************************************************************
1089 typedef struct _AT91S_UDP {
1090 AT91_REG UDP_NUM; // Frame Number Register
1091 AT91_REG UDP_GLBSTATE; // Global State Register
1092 AT91_REG UDP_FADDR; // Function Address Register
1093 AT91_REG Reserved0[1]; //
1094 AT91_REG UDP_IER; // Interrupt Enable Register
1095 AT91_REG UDP_IDR; // Interrupt Disable Register
1096 AT91_REG UDP_IMR; // Interrupt Mask Register
1097 AT91_REG UDP_ISR; // Interrupt Status Register
1098 AT91_REG UDP_ICR; // Interrupt Clear Register
1099 AT91_REG Reserved1[1]; //
1100 AT91_REG UDP_RSTEP; // Reset Endpoint Register
1101 AT91_REG Reserved2[1]; //
1102 AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
1103 AT91_REG Reserved3[2]; //
1104 AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
1105 AT91_REG Reserved4[3]; //
1106 AT91_REG UDP_TXVC; // Transceiver Control Register
1107 } AT91S_UDP, *AT91PS_UDP;
1109 // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
1110 #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
1111 #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
1112 #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
1113 // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
1114 #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
1115 #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
1116 #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
1117 #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
1118 #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
1119 // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
1120 #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
1121 #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
1122 // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
1123 #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
1124 #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
1125 #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
1126 #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
1127 #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
1128 #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
1129 #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
1130 #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
1131 #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
1132 #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
1133 #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
1134 // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
1135 // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
1136 // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
1137 #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
1138 // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
1139 // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
1140 #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
1141 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
1142 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
1143 #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
1144 #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
1145 #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
1146 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
1147 #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
1148 #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
1149 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
1150 #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
1151 #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
1152 #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
1153 #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
1154 #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
1155 #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
1156 #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
1157 #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
1158 #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
1159 #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
1160 #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
1161 #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
1162 #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
1163 #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
1164 #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
1165 #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
1166 // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
1167 #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
1168 #define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
1170 // *****************************************************************************
1171 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
1172 // *****************************************************************************
1173 typedef struct _AT91S_TC {
1174 AT91_REG TC_CCR; // Channel Control Register
1175 AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
1176 AT91_REG Reserved0[2]; //
1177 AT91_REG TC_CV; // Counter Value
1178 AT91_REG TC_RA; // Register A
1179 AT91_REG TC_RB; // Register B
1180 AT91_REG TC_RC; // Register C
1181 AT91_REG TC_SR; // Status Register
1182 AT91_REG TC_IER; // Interrupt Enable Register
1183 AT91_REG TC_IDR; // Interrupt Disable Register
1184 AT91_REG TC_IMR; // Interrupt Mask Register
1185 } AT91S_TC, *AT91PS_TC;
1187 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
1188 #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
1189 #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
1190 #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
1191 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
1192 #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
1193 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
1194 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
1195 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
1196 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
1197 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
1198 #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
1199 #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
1200 #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
1201 #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
1202 #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
1203 #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
1204 #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
1205 #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
1206 #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
1207 #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
1208 #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
1209 #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
1210 #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
1211 #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
1212 #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1213 #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1214 #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1215 #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1216 #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
1217 #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
1218 #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
1219 #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
1220 #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
1221 #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
1222 #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1223 #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1224 #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1225 #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1226 #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
1227 #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
1228 #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
1229 #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1230 #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1231 #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1232 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1233 #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
1234 #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
1235 #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
1236 #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
1237 #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
1238 #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
1239 #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
1240 #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
1241 #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
1242 #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
1243 #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
1244 #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
1245 #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
1246 #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
1247 #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
1248 #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
1249 #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
1250 #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
1251 #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
1252 #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
1253 #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
1254 #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
1255 #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
1256 #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
1257 #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
1258 #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
1259 #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
1260 #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
1261 #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
1262 #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
1263 #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
1264 #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
1265 #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
1266 #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
1267 #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
1268 #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
1269 #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
1270 #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
1271 #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
1272 #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
1273 #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
1274 #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
1275 #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
1276 #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
1277 #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
1278 #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
1279 #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
1280 #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
1281 #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
1282 #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
1283 #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
1284 #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
1285 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
1286 #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
1287 #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
1288 #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
1289 #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
1290 #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
1291 #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
1292 #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
1293 #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
1294 #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
1295 #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
1296 #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
1297 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
1298 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
1299 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
1301 // *****************************************************************************
1302 // SOFTWARE API DEFINITION FOR Timer Counter Interface
1303 // *****************************************************************************
1304 typedef struct _AT91S_TCB {
1305 AT91S_TC TCB_TC0; // TC Channel 0
1306 AT91_REG Reserved0[4]; //
1307 AT91S_TC TCB_TC1; // TC Channel 1
1308 AT91_REG Reserved1[4]; //
1309 AT91S_TC TCB_TC2; // TC Channel 2
1310 AT91_REG Reserved2[4]; //
1311 AT91_REG TCB_BCR; // TC Block Control Register
1312 AT91_REG TCB_BMR; // TC Block Mode Register
1313 } AT91S_TCB, *AT91PS_TCB;
1315 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
1316 #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
1317 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
1318 #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
1319 #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
1320 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
1321 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
1322 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
1323 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
1324 #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
1325 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
1326 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
1327 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
1328 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
1329 #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
1330 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
1331 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
1332 #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
1334 // *****************************************************************************
1335 // SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
1336 // *****************************************************************************
1337 typedef struct _AT91S_CAN_MB {
1338 AT91_REG CAN_MB_MMR; // MailBox Mode Register
1339 AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
1340 AT91_REG CAN_MB_MID; // MailBox ID Register
1341 AT91_REG CAN_MB_MFID; // MailBox Family ID Register
1342 AT91_REG CAN_MB_MSR; // MailBox Status Register
1343 AT91_REG CAN_MB_MDL; // MailBox Data Low Register
1344 AT91_REG CAN_MB_MDH; // MailBox Data High Register
1345 AT91_REG CAN_MB_MCR; // MailBox Control Register
1346 } AT91S_CAN_MB, *AT91PS_CAN_MB;
1348 // -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
1349 #define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
1350 #define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
1351 #define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
1352 #define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
1353 #define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
1354 #define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
1355 #define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
1356 #define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
1357 #define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
1358 // -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
1359 #define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
1360 #define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
1361 #define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
1362 // -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
1363 // -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
1364 // -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
1365 #define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
1366 #define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
1367 #define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
1368 #define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
1369 #define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
1370 #define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
1371 // -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
1372 // -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
1373 // -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
1374 #define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
1375 #define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
1377 // *****************************************************************************
1378 // SOFTWARE API DEFINITION FOR Control Area Network Interface
1379 // *****************************************************************************
1380 typedef struct _AT91S_CAN {
1381 AT91_REG CAN_MR; // Mode Register
1382 AT91_REG CAN_IER; // Interrupt Enable Register
1383 AT91_REG CAN_IDR; // Interrupt Disable Register
1384 AT91_REG CAN_IMR; // Interrupt Mask Register
1385 AT91_REG CAN_SR; // Status Register
1386 AT91_REG CAN_BR; // Baudrate Register
1387 AT91_REG CAN_TIM; // Timer Register
1388 AT91_REG CAN_TIMESTP; // Time Stamp Register
1389 AT91_REG CAN_ECR; // Error Counter Register
1390 AT91_REG CAN_TCR; // Transfer Command Register
1391 AT91_REG CAN_ACR; // Abort Command Register
1392 AT91_REG Reserved0[52]; //
1393 AT91_REG CAN_VR; // Version Register
1394 AT91_REG Reserved1[64]; //
1395 AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
1396 AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
1397 AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
1398 AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
1399 AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
1400 AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
1401 AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
1402 AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
1403 AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
1404 AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
1405 AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
1406 AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
1407 AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
1408 AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
1409 AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
1410 AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
1411 } AT91S_CAN, *AT91PS_CAN;
1413 // -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
1414 #define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
1415 #define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
1416 #define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
1417 #define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
1418 #define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
1419 #define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
1420 #define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
1421 #define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
1422 // -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
1423 #define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
1424 #define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
1425 #define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
1426 #define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
1427 #define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
1428 #define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
1429 #define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
1430 #define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
1431 #define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
1432 #define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
1433 #define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
1434 #define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
1435 #define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
1436 #define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
1437 #define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
1438 #define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
1439 #define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
1440 #define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
1441 #define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
1442 #define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
1443 #define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
1444 #define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
1445 #define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
1446 #define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
1447 #define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
1448 #define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
1449 #define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
1450 #define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
1451 #define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
1452 // -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
1453 // -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
1454 // -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
1455 #define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
1456 #define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
1457 #define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
1458 // -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
1459 #define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
1460 #define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
1461 #define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
1462 #define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
1463 #define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
1464 #define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
1465 // -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
1466 #define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
1467 // -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
1468 // -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
1469 #define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
1470 #define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
1471 // -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
1472 #define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
1473 // -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
1475 // *****************************************************************************
1476 // SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
1477 // *****************************************************************************
1478 typedef struct _AT91S_EMAC {
1479 AT91_REG EMAC_NCR; // Network Control Register
1480 AT91_REG EMAC_NCFGR; // Network Configuration Register
1481 AT91_REG EMAC_NSR; // Network Status Register
1482 AT91_REG Reserved0[2]; //
1483 AT91_REG EMAC_TSR; // Transmit Status Register
1484 AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
1485 AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
1486 AT91_REG EMAC_RSR; // Receive Status Register
1487 AT91_REG EMAC_ISR; // Interrupt Status Register
1488 AT91_REG EMAC_IER; // Interrupt Enable Register
1489 AT91_REG EMAC_IDR; // Interrupt Disable Register
1490 AT91_REG EMAC_IMR; // Interrupt Mask Register
1491 AT91_REG EMAC_MAN; // PHY Maintenance Register
1492 AT91_REG EMAC_PTR; // Pause Time Register
1493 AT91_REG EMAC_PFR; // Pause Frames received Register
1494 AT91_REG EMAC_FTO; // Frames Transmitted OK Register
1495 AT91_REG EMAC_SCF; // Single Collision Frame Register
1496 AT91_REG EMAC_MCF; // Multiple Collision Frame Register
1497 AT91_REG EMAC_FRO; // Frames Received OK Register
1498 AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
1499 AT91_REG EMAC_ALE; // Alignment Error Register
1500 AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
1501 AT91_REG EMAC_LCOL; // Late Collision Register
1502 AT91_REG EMAC_ECOL; // Excessive Collision Register
1503 AT91_REG EMAC_TUND; // Transmit Underrun Error Register
1504 AT91_REG EMAC_CSE; // Carrier Sense Error Register
1505 AT91_REG EMAC_RRE; // Receive Ressource Error Register
1506 AT91_REG EMAC_ROV; // Receive Overrun Errors Register
1507 AT91_REG EMAC_RSE; // Receive Symbol Errors Register
1508 AT91_REG EMAC_ELE; // Excessive Length Errors Register
1509 AT91_REG EMAC_RJA; // Receive Jabbers Register
1510 AT91_REG EMAC_USF; // Undersize Frames Register
1511 AT91_REG EMAC_STE; // SQE Test Error Register
1512 AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
1513 AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
1514 AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
1515 AT91_REG EMAC_HRT; // Hash Address Top[63:32]
1516 AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
1517 AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
1518 AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
1519 AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
1520 AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
1521 AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
1522 AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
1523 AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
1524 AT91_REG EMAC_TID; // Type ID Checking Register
1525 AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
1526 AT91_REG EMAC_USRIO; // USER Input/Output Register
1527 AT91_REG EMAC_WOL; // Wake On LAN Register
1528 AT91_REG Reserved1[13]; //
1529 AT91_REG EMAC_REV; // Revision Register
1530 } AT91S_EMAC, *AT91PS_EMAC;
1532 // -------- EMAC_NCR : (EMAC Offset: 0x0) --------
1533 #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1534 #define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
1535 #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
1536 #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
1537 #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
1538 #define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
1539 #define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
1540 #define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
1541 #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
1542 #define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
1543 #define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
1544 #define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
1545 #define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1546 // -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
1547 #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
1548 #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
1549 #define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
1550 #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
1551 #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
1552 #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
1553 #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
1554 #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
1555 #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
1556 #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
1557 #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
1558 #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
1559 #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
1560 #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
1561 #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
1562 #define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
1563 #define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
1564 #define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
1565 #define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1566 #define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1567 #define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1568 #define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
1569 #define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
1570 #define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
1571 #define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
1572 // -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
1573 #define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
1574 #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
1575 #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
1576 // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
1577 #define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
1578 #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
1579 #define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
1580 #define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
1581 #define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
1582 #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
1583 #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
1584 // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
1585 #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
1586 #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
1587 #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
1588 // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
1589 #define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
1590 #define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
1591 #define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
1592 #define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
1593 #define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
1594 #define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
1595 #define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
1596 #define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
1597 #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
1598 #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
1599 #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
1600 #define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
1601 #define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
1602 // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
1603 // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
1604 // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
1605 // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
1606 #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
1607 #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
1608 #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
1609 #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
1610 #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
1611 #define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
1612 // -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
1613 #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
1614 #define AT91C_EMAC_CLKEN ((unsigned int) 0x1 << 1) // (EMAC) Clock Enable
1615 // -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
1616 #define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
1617 #define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
1618 #define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
1619 #define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
1620 // -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
1621 #define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
1622 #define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
1624 // *****************************************************************************
1625 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
1626 // *****************************************************************************
1627 typedef struct _AT91S_ADC {
1628 AT91_REG ADC_CR; // ADC Control Register
1629 AT91_REG ADC_MR; // ADC Mode Register
1630 AT91_REG Reserved0[2]; //
1631 AT91_REG ADC_CHER; // ADC Channel Enable Register
1632 AT91_REG ADC_CHDR; // ADC Channel Disable Register
1633 AT91_REG ADC_CHSR; // ADC Channel Status Register
1634 AT91_REG ADC_SR; // ADC Status Register
1635 AT91_REG ADC_LCDR; // ADC Last Converted Data Register
1636 AT91_REG ADC_IER; // ADC Interrupt Enable Register
1637 AT91_REG ADC_IDR; // ADC Interrupt Disable Register
1638 AT91_REG ADC_IMR; // ADC Interrupt Mask Register
1639 AT91_REG ADC_CDR0; // ADC Channel Data Register 0
1640 AT91_REG ADC_CDR1; // ADC Channel Data Register 1
1641 AT91_REG ADC_CDR2; // ADC Channel Data Register 2
1642 AT91_REG ADC_CDR3; // ADC Channel Data Register 3
1643 AT91_REG ADC_CDR4; // ADC Channel Data Register 4
1644 AT91_REG ADC_CDR5; // ADC Channel Data Register 5
1645 AT91_REG ADC_CDR6; // ADC Channel Data Register 6
1646 AT91_REG ADC_CDR7; // ADC Channel Data Register 7
1647 AT91_REG Reserved1[44]; //
1648 AT91_REG ADC_RPR; // Receive Pointer Register
1649 AT91_REG ADC_RCR; // Receive Counter Register
1650 AT91_REG ADC_TPR; // Transmit Pointer Register
1651 AT91_REG ADC_TCR; // Transmit Counter Register
1652 AT91_REG ADC_RNPR; // Receive Next Pointer Register
1653 AT91_REG ADC_RNCR; // Receive Next Counter Register
1654 AT91_REG ADC_TNPR; // Transmit Next Pointer Register
1655 AT91_REG ADC_TNCR; // Transmit Next Counter Register
1656 AT91_REG ADC_PTCR; // PDC Transfer Control Register
1657 AT91_REG ADC_PTSR; // PDC Transfer Status Register
1658 } AT91S_ADC, *AT91PS_ADC;
1660 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
1661 #define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
1662 #define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
1663 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
1664 #define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
1665 #define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1666 #define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1667 #define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
1668 #define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
1669 #define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
1670 #define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
1671 #define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
1672 #define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
1673 #define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
1674 #define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
1675 #define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
1676 #define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
1677 #define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
1678 #define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1679 #define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
1680 #define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
1681 #define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
1682 #define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
1683 #define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
1684 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
1685 #define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
1686 #define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
1687 #define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
1688 #define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
1689 #define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
1690 #define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
1691 #define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
1692 #define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
1693 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
1694 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
1695 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
1696 #define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
1697 #define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
1698 #define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
1699 #define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
1700 #define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
1701 #define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
1702 #define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
1703 #define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
1704 #define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
1705 #define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
1706 #define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
1707 #define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
1708 #define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
1709 #define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
1710 #define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
1711 #define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
1712 #define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
1713 #define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
1714 #define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
1715 #define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
1716 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
1717 #define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
1718 // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
1719 // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
1720 // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
1721 // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
1722 #define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
1723 // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
1724 // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
1725 // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
1726 // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
1727 // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
1728 // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
1729 // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
1731 // *****************************************************************************
1732 // SOFTWARE API DEFINITION FOR Advanced Encryption Standard
1733 // *****************************************************************************
1734 typedef struct _AT91S_AES {
1735 AT91_REG AES_CR; // Control Register
1736 AT91_REG AES_MR; // Mode Register
1737 AT91_REG Reserved0[2]; //
1738 AT91_REG AES_IER; // Interrupt Enable Register
1739 AT91_REG AES_IDR; // Interrupt Disable Register
1740 AT91_REG AES_IMR; // Interrupt Mask Register
1741 AT91_REG AES_ISR; // Interrupt Status Register
1742 AT91_REG AES_KEYWxR[4]; // Key Word x Register
1743 AT91_REG Reserved1[4]; //
1744 AT91_REG AES_IDATAxR[4]; // Input Data x Register
1745 AT91_REG AES_ODATAxR[4]; // Output Data x Register
1746 AT91_REG AES_IVxR[4]; // Initialization Vector x Register
1747 AT91_REG Reserved2[35]; //
1748 AT91_REG AES_VR; // AES Version Register
1749 AT91_REG AES_RPR; // Receive Pointer Register
1750 AT91_REG AES_RCR; // Receive Counter Register
1751 AT91_REG AES_TPR; // Transmit Pointer Register
1752 AT91_REG AES_TCR; // Transmit Counter Register
1753 AT91_REG AES_RNPR; // Receive Next Pointer Register
1754 AT91_REG AES_RNCR; // Receive Next Counter Register
1755 AT91_REG AES_TNPR; // Transmit Next Pointer Register
1756 AT91_REG AES_TNCR; // Transmit Next Counter Register
1757 AT91_REG AES_PTCR; // PDC Transfer Control Register
1758 AT91_REG AES_PTSR; // PDC Transfer Status Register
1759 } AT91S_AES, *AT91PS_AES;
1761 // -------- AES_CR : (AES Offset: 0x0) Control Register --------
1762 #define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing
1763 #define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset
1764 #define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
1765 // -------- AES_MR : (AES Offset: 0x4) Mode Register --------
1766 #define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode
1767 #define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay
1768 #define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode
1769 #define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
1770 #define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
1771 #define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet).
1772 #define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode
1773 #define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
1774 #define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
1775 #define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
1776 #define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
1777 #define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
1778 #define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
1779 #define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
1780 #define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit.
1781 #define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit.
1782 #define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit.
1783 #define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit.
1784 #define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit.
1785 #define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
1786 #define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
1787 #define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
1788 #define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
1789 #define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
1790 #define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
1791 #define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
1792 // -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register --------
1793 #define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY
1794 #define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End
1795 #define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End
1796 #define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full
1797 #define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty
1798 #define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection
1799 // -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register --------
1800 // -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register --------
1801 // -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register --------
1802 #define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
1803 #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
1804 #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
1805 #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
1806 #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
1807 #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
1808 #define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
1810 // *****************************************************************************
1811 // SOFTWARE API DEFINITION FOR Triple Data Encryption Standard
1812 // *****************************************************************************
1813 typedef struct _AT91S_TDES {
1814 AT91_REG TDES_CR; // Control Register
1815 AT91_REG TDES_MR; // Mode Register
1816 AT91_REG Reserved0[2]; //
1817 AT91_REG TDES_IER; // Interrupt Enable Register
1818 AT91_REG TDES_IDR; // Interrupt Disable Register
1819 AT91_REG TDES_IMR; // Interrupt Mask Register
1820 AT91_REG TDES_ISR; // Interrupt Status Register
1821 AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
1822 AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
1823 AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
1824 AT91_REG Reserved1[2]; //
1825 AT91_REG TDES_IDATAxR[2]; // Input Data x Register
1826 AT91_REG Reserved2[2]; //
1827 AT91_REG TDES_ODATAxR[2]; // Output Data x Register
1828 AT91_REG Reserved3[2]; //
1829 AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
1830 AT91_REG Reserved4[37]; //
1831 AT91_REG TDES_VR; // TDES Version Register
1832 AT91_REG TDES_RPR; // Receive Pointer Register
1833 AT91_REG TDES_RCR; // Receive Counter Register
1834 AT91_REG TDES_TPR; // Transmit Pointer Register
1835 AT91_REG TDES_TCR; // Transmit Counter Register
1836 AT91_REG TDES_RNPR; // Receive Next Pointer Register
1837 AT91_REG TDES_RNCR; // Receive Next Counter Register
1838 AT91_REG TDES_TNPR; // Transmit Next Pointer Register
1839 AT91_REG TDES_TNCR; // Transmit Next Counter Register
1840 AT91_REG TDES_PTCR; // PDC Transfer Control Register
1841 AT91_REG TDES_PTSR; // PDC Transfer Status Register
1842 } AT91S_TDES, *AT91PS_TDES;
1844 // -------- TDES_CR : (TDES Offset: 0x0) Control Register --------
1845 #define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing
1846 #define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset
1847 // -------- TDES_MR : (TDES Offset: 0x4) Mode Register --------
1848 #define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode
1849 #define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode
1850 #define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode
1851 #define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode
1852 #define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
1853 #define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
1854 #define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet).
1855 #define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
1856 #define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
1857 #define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
1858 #define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
1859 #define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
1860 #define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
1861 #define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
1862 #define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
1863 #define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
1864 #define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
1865 #define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
1866 // -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register --------
1867 #define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY
1868 #define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End
1869 #define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End
1870 #define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full
1871 #define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty
1872 #define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection
1873 // -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register --------
1874 // -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register --------
1875 // -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register --------
1876 #define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
1877 #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
1878 #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
1879 #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
1880 #define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
1882 // *****************************************************************************
1883 // REGISTER ADDRESS DEFINITION FOR AT91SAM7XC256
1884 // *****************************************************************************
1885 // ========== Register definition for SYS peripheral ==========
1886 // ========== Register definition for AIC peripheral ==========
1887 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1888 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1889 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1890 #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1891 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1892 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1893 #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1894 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1895 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1896 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1897 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1898 #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1899 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1900 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1901 #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1902 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1903 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1904 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1905 // ========== Register definition for PDC_DBGU peripheral ==========
1906 #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1907 #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1908 #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1909 #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1910 #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1911 #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1912 #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1913 #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1914 #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1915 #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1916 // ========== Register definition for DBGU peripheral ==========
1917 #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
1918 #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1919 #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1920 #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1921 #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
1922 #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1923 #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1924 #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1925 #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1926 #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1927 #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1928 #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1929 // ========== Register definition for PIOA peripheral ==========
1930 #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1931 #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1932 #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1933 #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1934 #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1935 #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1936 #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1937 #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1938 #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1939 #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1940 #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1941 #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1942 #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1943 #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
1944 #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1945 #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1946 #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1947 #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1948 #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1949 #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1950 #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1951 #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1952 #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1953 #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1954 #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1955 #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1956 #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1957 #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1958 #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1959 // ========== Register definition for PIOB peripheral ==========
1960 #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
1961 #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
1962 #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
1963 #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
1964 #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
1965 #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
1966 #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
1967 #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
1968 #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
1969 #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
1970 #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
1971 #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
1972 #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
1973 #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
1974 #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
1975 #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
1976 #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
1977 #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
1978 #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
1979 #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
1980 #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
1981 #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
1982 #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
1983 #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
1984 #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
1985 #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
1986 #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
1987 #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
1988 #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
1989 // ========== Register definition for CKGR peripheral ==========
1990 #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1991 #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
1992 #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1993 // ========== Register definition for PMC peripheral ==========
1994 #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1995 #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
1996 #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
1997 #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1998 #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1999 #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
2000 #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
2001 #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
2002 #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
2003 #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
2004 #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
2005 #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
2006 #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
2007 #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
2008 #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
2009 // ========== Register definition for RSTC peripheral ==========
2010 #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
2011 #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
2012 #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
2013 // ========== Register definition for RTTC peripheral ==========
2014 #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
2015 #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
2016 #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
2017 #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
2018 // ========== Register definition for PITC peripheral ==========
2019 #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
2020 #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
2021 #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
2022 #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
2023 // ========== Register definition for WDTC peripheral ==========
2024 #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
2025 #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
2026 #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
2027 // ========== Register definition for VREG peripheral ==========
2028 #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
2029 // ========== Register definition for MC peripheral ==========
2030 #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
2031 #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
2032 #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
2033 #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
2034 #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
2035 #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
2036 // ========== Register definition for PDC_SPI1 peripheral ==========
2037 #define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
2038 #define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
2039 #define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
2040 #define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
2041 #define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
2042 #define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
2043 #define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
2044 #define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
2045 #define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
2046 #define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
2047 // ========== Register definition for SPI1 peripheral ==========
2048 #define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
2049 #define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
2050 #define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
2051 #define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
2052 #define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
2053 #define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
2054 #define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
2055 #define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
2056 #define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
2057 // ========== Register definition for PDC_SPI0 peripheral ==========
2058 #define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
2059 #define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
2060 #define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
2061 #define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
2062 #define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
2063 #define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
2064 #define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
2065 #define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
2066 #define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
2067 #define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
2068 // ========== Register definition for SPI0 peripheral ==========
2069 #define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
2070 #define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
2071 #define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
2072 #define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
2073 #define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
2074 #define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
2075 #define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
2076 #define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
2077 #define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
2078 // ========== Register definition for PDC_US1 peripheral ==========
2079 #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
2080 #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
2081 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
2082 #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
2083 #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
2084 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
2085 #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
2086 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
2087 #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
2088 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
2089 // ========== Register definition for US1 peripheral ==========
2090 #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
2091 #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
2092 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
2093 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
2094 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
2095 #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
2096 #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
2097 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
2098 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
2099 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
2100 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
2101 #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
2102 #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
2103 #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
2104 // ========== Register definition for PDC_US0 peripheral ==========
2105 #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
2106 #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
2107 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
2108 #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
2109 #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
2110 #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
2111 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
2112 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
2113 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
2114 #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
2115 // ========== Register definition for US0 peripheral ==========
2116 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
2117 #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
2118 #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
2119 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
2120 #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
2121 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
2122 #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
2123 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
2124 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
2125 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
2126 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
2127 #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
2128 #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
2129 #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
2130 // ========== Register definition for PDC_SSC peripheral ==========
2131 #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
2132 #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
2133 #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
2134 #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
2135 #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
2136 #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
2137 #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
2138 #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
2139 #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
2140 #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
2141 // ========== Register definition for SSC peripheral ==========
2142 #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
2143 #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
2144 #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
2145 #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
2146 #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
2147 #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
2148 #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
2149 #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
2150 #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
2151 #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
2152 #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
2153 #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
2154 #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
2155 #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
2156 // ========== Register definition for TWI peripheral ==========
2157 #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
2158 #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
2159 #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
2160 #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
2161 #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
2162 #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
2163 #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
2164 #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
2165 #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
2166 #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
2167 // ========== Register definition for PWMC_CH3 peripheral ==========
2168 #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
2169 #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
2170 #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
2171 #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
2172 #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
2173 #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
2174 // ========== Register definition for PWMC_CH2 peripheral ==========
2175 #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
2176 #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
2177 #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
2178 #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
2179 #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
2180 #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
2181 // ========== Register definition for PWMC_CH1 peripheral ==========
2182 #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
2183 #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
2184 #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
2185 #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
2186 #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
2187 #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
2188 // ========== Register definition for PWMC_CH0 peripheral ==========
2189 #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
2190 #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
2191 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
2192 #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
2193 #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
2194 #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
2195 // ========== Register definition for PWMC peripheral ==========
2196 #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
2197 #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
2198 #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
2199 #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
2200 #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
2201 #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
2202 #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
2203 #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
2204 #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
2205 // ========== Register definition for UDP peripheral ==========
2206 #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
2207 #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
2208 #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
2209 #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
2210 #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
2211 #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
2212 #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
2213 #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
2214 #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
2215 #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
2216 #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
2217 #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
2218 // ========== Register definition for TC0 peripheral ==========
2219 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
2220 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
2221 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
2222 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
2223 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
2224 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
2225 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
2226 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
2227 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
2228 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
2229 // ========== Register definition for TC1 peripheral ==========
2230 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
2231 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
2232 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
2233 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
2234 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
2235 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
2236 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
2237 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
2238 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
2239 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
2240 // ========== Register definition for TC2 peripheral ==========
2241 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
2242 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
2243 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
2244 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
2245 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
2246 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
2247 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
2248 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
2249 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
2250 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
2251 // ========== Register definition for TCB peripheral ==========
2252 #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
2253 #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
2254 // ========== Register definition for CAN_MB0 peripheral ==========
2255 #define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
2256 #define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
2257 #define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
2258 #define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
2259 #define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
2260 #define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
2261 #define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
2262 #define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
2263 // ========== Register definition for CAN_MB1 peripheral ==========
2264 #define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
2265 #define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
2266 #define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
2267 #define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
2268 #define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
2269 #define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
2270 #define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
2271 #define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
2272 // ========== Register definition for CAN_MB2 peripheral ==========
2273 #define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
2274 #define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
2275 #define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
2276 #define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
2277 #define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
2278 #define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
2279 #define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
2280 #define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
2281 // ========== Register definition for CAN_MB3 peripheral ==========
2282 #define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
2283 #define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
2284 #define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
2285 #define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
2286 #define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
2287 #define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
2288 #define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
2289 #define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
2290 // ========== Register definition for CAN_MB4 peripheral ==========
2291 #define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
2292 #define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
2293 #define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
2294 #define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
2295 #define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
2296 #define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
2297 #define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
2298 #define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
2299 // ========== Register definition for CAN_MB5 peripheral ==========
2300 #define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
2301 #define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
2302 #define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
2303 #define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
2304 #define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
2305 #define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
2306 #define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
2307 #define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
2308 // ========== Register definition for CAN_MB6 peripheral ==========
2309 #define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
2310 #define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
2311 #define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
2312 #define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
2313 #define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
2314 #define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
2315 #define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
2316 #define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
2317 // ========== Register definition for CAN_MB7 peripheral ==========
2318 #define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
2319 #define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
2320 #define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
2321 #define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
2322 #define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
2323 #define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
2324 #define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
2325 #define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
2326 // ========== Register definition for CAN peripheral ==========
2327 #define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
2328 #define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
2329 #define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
2330 #define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
2331 #define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
2332 #define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
2333 #define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
2334 #define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
2335 #define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
2336 #define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
2337 #define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
2338 #define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
2339 // ========== Register definition for EMAC peripheral ==========
2340 #define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
2341 #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
2342 #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
2343 #define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
2344 #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
2345 #define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
2346 #define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
2347 #define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
2348 #define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
2349 #define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
2350 #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
2351 #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
2352 #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
2353 #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
2354 #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
2355 #define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
2356 #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
2357 #define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
2358 #define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
2359 #define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
2360 #define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
2361 #define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
2362 #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
2363 #define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
2364 #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
2365 #define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
2366 #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
2367 #define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
2368 #define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
2369 #define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
2370 #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
2371 #define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
2372 #define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
2373 #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
2374 #define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
2375 #define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
2376 #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
2377 #define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
2378 #define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
2379 #define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
2380 #define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
2381 #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
2382 #define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
2383 #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
2384 #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
2385 #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
2386 #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
2387 #define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
2388 #define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
2389 // ========== Register definition for PDC_ADC peripheral ==========
2390 #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
2391 #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
2392 #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
2393 #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
2394 #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
2395 #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
2396 #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
2397 #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
2398 #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
2399 #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
2400 // ========== Register definition for ADC peripheral ==========
2401 #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
2402 #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
2403 #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
2404 #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
2405 #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
2406 #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
2407 #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
2408 #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
2409 #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
2410 #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
2411 #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
2412 #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
2413 #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
2414 #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
2415 #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
2416 #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
2417 #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
2418 #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
2419 // ========== Register definition for PDC_AES peripheral ==========
2420 #define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
2421 #define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
2422 #define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
2423 #define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
2424 #define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
2425 #define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
2426 #define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
2427 #define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
2428 #define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
2429 #define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
2430 // ========== Register definition for AES peripheral ==========
2431 #define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
2432 #define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
2433 #define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
2434 #define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
2435 #define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
2436 #define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
2437 #define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
2438 #define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
2439 #define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
2440 #define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
2441 #define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
2442 // ========== Register definition for PDC_TDES peripheral ==========
2443 #define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
2444 #define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
2445 #define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
2446 #define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
2447 #define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
2448 #define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
2449 #define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
2450 #define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
2451 #define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
2452 #define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
2453 // ========== Register definition for TDES peripheral ==========
2454 #define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
2455 #define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
2456 #define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
2457 #define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
2458 #define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
2459 #define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
2460 #define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
2461 #define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
2462 #define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
2463 #define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
2464 #define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
2465 #define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
2466 #define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register
2468 // *****************************************************************************
2469 // PIO DEFINITIONS FOR AT91SAM7XC256
2470 // *****************************************************************************
2471 #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
2472 #define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
2473 #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
2474 #define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
2475 #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
2476 #define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
2477 #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
2478 #define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
2479 #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
2480 #define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
2481 #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
2482 #define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
2483 #define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
2484 #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
2485 #define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
2486 #define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
2487 #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
2488 #define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
2489 #define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
2490 #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
2491 #define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
2492 #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
2493 #define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
2494 #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
2495 #define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
2496 #define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
2497 #define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
2498 #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
2499 #define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
2500 #define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
2501 #define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
2502 #define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
2503 #define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
2504 #define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
2505 #define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
2506 #define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
2507 #define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
2508 #define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
2509 #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
2510 #define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
2511 #define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
2512 #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
2513 #define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
2514 #define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
2515 #define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
2516 #define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
2517 #define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
2518 #define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
2519 #define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
2520 #define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
2521 #define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
2522 #define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
2523 #define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
2524 #define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
2525 #define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
2526 #define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
2527 #define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
2528 #define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
2529 #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
2530 #define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
2531 #define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
2532 #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
2533 #define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
2534 #define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
2535 #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
2536 #define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
2537 #define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
2538 #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
2539 #define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
2540 #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
2541 #define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
2542 #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
2543 #define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
2544 #define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
2545 #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
2546 #define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
2547 #define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
2548 #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
2549 #define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
2550 #define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
2551 #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
2552 #define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
2553 #define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
2554 #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
2555 #define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
2556 #define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
2557 #define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
2558 #define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
2559 #define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
2560 #define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
2561 #define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
2562 #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
2563 #define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
2564 #define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
2565 #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
2566 #define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
2567 #define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
2568 #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
2569 #define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
2570 #define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
2571 #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
2572 #define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
2573 #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
2574 #define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
2575 #define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
2576 #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
2577 #define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
2578 #define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
2579 #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
2580 #define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
2581 #define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
2582 #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
2583 #define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
2584 #define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
2585 #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
2586 #define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
2587 #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
2588 #define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
2589 #define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
2590 #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
2591 #define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
2592 #define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
2593 #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
2594 #define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
2595 #define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
2596 #define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
2597 #define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
2598 #define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
2599 #define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
2600 #define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
2601 #define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
2602 #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
2603 #define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
2604 #define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
2605 #define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
2606 #define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
2607 #define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
2608 #define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
2609 #define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
2610 #define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
2611 #define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
2612 #define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
2613 #define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
2614 #define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
2615 #define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
2616 #define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
2617 #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
2618 #define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
2619 #define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
2620 #define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
2621 #define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
2622 #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
2623 #define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2624 #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
2625 #define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
2626 #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
2627 #define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
2628 #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
2629 #define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
2630 #define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
2631 #define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
2632 #define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
2633 #define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
2635 // *****************************************************************************
2636 // PERIPHERAL ID DEFINITIONS FOR AT91SAM7XC256
2637 // *****************************************************************************
2638 #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
2639 #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
2640 #define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
2641 #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
2642 #define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
2643 #define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
2644 #define AT91C_ID_US0 ((unsigned int) 6) // USART 0
2645 #define AT91C_ID_US1 ((unsigned int) 7) // USART 1
2646 #define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
2647 #define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
2648 #define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
2649 #define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
2650 #define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
2651 #define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
2652 #define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
2653 #define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
2654 #define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
2655 #define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
2656 #define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit
2657 #define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard
2658 #define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
2659 #define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
2660 #define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
2661 #define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
2662 #define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
2663 #define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
2664 #define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
2665 #define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
2666 #define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
2667 #define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
2668 #define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
2669 #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
2670 #define AT91C_ALL_INT ((unsigned int) 0xC00FFFFF) // ALL VALID INTERRUPTS
2672 // *****************************************************************************
2673 // BASE ADDRESS DEFINITIONS FOR AT91SAM7XC256
2674 // *****************************************************************************
2675 #define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
2676 #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
2677 #define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
2678 #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
2679 #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
2680 #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
2681 #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
2682 #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
2683 #define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
2684 #define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
2685 #define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
2686 #define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
2687 #define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
2688 #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
2689 #define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
2690 #define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
2691 #define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
2692 #define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
2693 #define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
2694 #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
2695 #define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
2696 #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
2697 #define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
2698 #define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
2699 #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
2700 #define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
2701 #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
2702 #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
2703 #define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
2704 #define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
2705 #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
2706 #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
2707 #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
2708 #define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
2709 #define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
2710 #define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
2711 #define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
2712 #define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
2713 #define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
2714 #define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
2715 #define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
2716 #define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
2717 #define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
2718 #define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
2719 #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
2720 #define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
2721 #define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
2722 #define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address
2723 #define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address
2724 #define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address
2725 #define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address
2727 // *****************************************************************************
2728 // MEMORY MAPPING DEFINITIONS FOR AT91SAM7XC256
2729 // *****************************************************************************
2731 #define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
2732 #define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes)
2734 #define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address
2735 #define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes)
2736 #define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes
2737 #define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes
2738 #define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes
2739 #define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes
projects / sysless.git / blob