ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87

Set CPU rate to 2.2Ghz for sku 0x87 (CD575M) similar
to its DSC and POP counterparts

Bug 1342499

Change-Id: Ia4d3de1f572f8557f4eead4665c20fd80bea1c6f
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/419049
(cherry picked from commit 999af951da540a4db49d7294e4bec581ee2bd9ae)
Reviewed-on: http://git-master/r/422393
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra12: dvfs: Set CPU rate limit to 2.2GHz

Set CPU rate limit to 2.2GHz for Tegra12 sku 0x27.

Bug 1475295

Change-Id: Ia96011bf398dfb35721b201bd799ea66e9cdf78e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/381750
(cherry picked from commit f703fdc9373905a82437f673ab557c32ac63c59c)
Reviewed-on: http://git-master/r/422544
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: host: Don't use KEPLER_C syncpt incr

This is a partial revert of commit a571ce594: "video: tegra: host: Use
KEPLER_C syncpt incr".

That commit seems to be causing MMU faults from host under some
workloads.  The root cause isn't fully understood yet, but reverting
to the old behavior should be safe.

Bug 1497928

Change-Id: I5b464d40c57deb95ca4890240213685968bf94a1
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/422283
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: move firmware prints from info to debug

Firmware loading logs firmware names at the info loglevel; move this
to debug to prevent extraneous noise in syslog when these files are
opened.

Bug 1486252

Change-Id: Icea62ad19dd467dd01ca88125de88fbfafc1e716
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Reviewed-on: http://git-master/r/421353
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

mmc: tegra: use dev_info instead of dev_err

-use dev_info instead of dev_err
-best tap value is an information and not an err
hence changing to dev_info

Bug 1492481

Change-Id: Icf8cc4168d9cab8e121355814c66ece2b2230531
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/391306
(cherry picked from commit 12bb4f269cac4b2a14c8effb116bd029ce108318)
Reviewed-on: http://git-master/r/414968
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

mmc: tegra: use pr_info instead of pr_err

-use pr_info instead of pr_err
-best tap value is an information and not an err
hence changing to pr_info

Bug 1492481

Change-Id: I34d8634ae1e358d3c227a1101f8ae9f7f87627a0
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/395639
(cherry picked from commit 73687a8eb4734170f7451f08dcf865bd5b494a8a)
Reviewed-on: http://git-master/r/414967
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: reserve PSTORE memory

Configure to reserve memory for PSTORE ftrace and console
as 1MB each.

Bug 1449479

Change-Id: I5392d3f1aee81aa02c09108a562085278d5ad39b
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/362430
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
(cherry picked from commit bcb186075677a767c07a89b3bde1f34cc0d788ee)
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408433
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: reserve memory for ramoops by default

Reserving memory of 1MB for ramoops by default in tegra_reserve when
PSTORE configs are enabled. This way we can enable ramoops on all
platforms by just enabling the configs.

Bug 1258617

Change-Id: I2074c553cc9c32bca133bc8eb36eb03dc12fbbe1
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/361425
(cherry picked from commit f90bd3fe3ecee42c1f2db4b5325e31fe33ff39f3)
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408432
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: Tegra: add support for ramoops

Ramoops is an oops/panic logger that writes its logs to RAM before
the system crashes.
This replaces the old methods which uses last_kmsg.

the last kernel logs can now be found at
/sys/fs/pstore/console-ramoops.

If not found it can be manually mounted using the command from shell
prompt:

mount -t pstore pstore /sys/fs/pstore

Bug 1258617

Change-Id: I7507bfe66a36ae882ad1d2a8f4b111bce9a1d8bc
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/309549
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit 5e18da24e97561f8590f3ef0256906d967351a2b)
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408431
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: Check VPR before enabling GPU

Check that VPR is locked down before enabling GPU.

Change-Id: I455b3cb0fee489e19daf7217f925d7d8348458f1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/390184
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
(cherry picked from commit 9857267dba8b4081a94e90cf39d76f4d4fb2e71e)
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408430
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

mmc: tegra: Fix parent clk configuration

Do not ignore parent clk setting and parent clock source flag
update for any case. For eMMC, in resume, without pll_c as clk
source, 200MHz cannot be set in HS200 mode set.

Bug 1480583

Reviewed-on: http://git-master/r/389704
(cherry picked from commit b9b0cb1541d66ba2450a680666c3fe962b4f71df)

Change-Id: I7898a57871cd16de49142a6534a998bef0c43529
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/395205
(cherry picked from commit 720c60aef1859b9c0d913c131203e02e6af4c3e6)
Reviewed-on: http://git-master/r/412607
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

mmc: tegra: add tap hole coeff for 200MHz for SDMMC3

This patch adds tap hole coeff for 200MHz for SDMMC3,
for tegra12x

Bug 1505798

Change-Id: I54de2a7529952367e361d8bd55a669335142193f
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412543
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: sdhci: set max clk to 200MHz for SDMMC3

This patch sets max clk limit to 200MHz for SDMMC3 for PM375.
Requesting 208MHz results in getting 204MHz from PLL_P and CRC
errors are seen.

Bug 1505798

Change-Id: I14825335fa5895ef2dde905f1e3cd568d2dafa62
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412542
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

fury: check inode's i_private before assignation

Bug 200000044

Change-Id: I4a09caf016193801c5841b82e024f8ef41a3763f
Signed-off-by: Chun Xu <chunx@nvidia.com>
Reviewed-on: http://git-master/r/411287
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar S <nkumars@nvidia.com>
Tested-by: Naveen Kumar S <nkumars@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: hdmi: remove HDMI hotoplug emulation

Remove unnecessary hotplug emulation for HDTV.
(Only DVI monitors require hotplug emulation).

bug 1495496

Change-Id: Ie7c30f9307864099fd6ad14f2d863a809f570104
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/411747
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Pankaj Dabade <pdabade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: dc: fix bandwidth calc for 4K

Fix 32bit arithmatic overflow in bandwidth calculation by
switching division and multiplying.

bug 1499542

Change-Id: Ia37ce2f0a6c4e0f08398f2eaa3be557461fdfbb7
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/411746
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

arm: tegra: update emc dvfs table for jetson-tk1

Update the emc dvfs table

Bug 200004533

Change-Id: Iae708a77150ac04c88708c5e3f495301bb029c22
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/409191
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

arm: tegra12: dtb: jetson-tk1: remove initrd update

initrd_start and size should be decided by bootloader.
No need to hardcode in dts file.

Bug 200004406

Change-Id: Ic204b8d1a8a45a46729fd3560ad3622640f5d01d
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/410672
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bryan Wu <pengw@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra12: config: Disable modem configs

Bug 200004850

Change-Id: I4b3131addcf09cc044d2305f733272ab23f37392
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/410159
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

video: tegra: dc: support 4096 sized windows

Program the full 13-bit and 15-bit range of fields related to window size.

Bug 200003004

Change-Id: I388795e002a50f735303461d69841085d9fcfde9
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/376774
(cherry picked from commit 16dc3c06abcbe56e21d1d0951316bfd9e3f24ce7)
Reviewed-on: http://git-master/r/408617
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit

mmc: tegra: Set correct tuning constraints

-If we insert SDR50 card after removing SDR104 card,
tuning constraints of SDR104 are being set for SDR50.
This patch sets correct tuning constraints for SDR50 mode
card

Bug 1423425

Reviewed-on: http://git-master/r/367708
(cherry picked from commit 9a9b70233c0669c6c3e26ec525a56b350b971657)

Change-Id: I14150ff7bdbb2387d185a6d800d5160dc0fa54bc
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/369823
(cherry picked from commit edc48c9254e9d3aea84ca652a1966ea587f191cc)
Reviewed-on: http://git-master/r/410198
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Modify UI calculations in tuning

Discrediting all the UI's from either end that are less than 30%
of the estimated UI.
Not using a discredited UI for any comparisons. If one of the UIs
in a comparison is already discredited, discrediting the other UI
as well.
Checking for multiple holes in the same window.
For margin calculations for window ends identified as tap holes, use
n'th Vmin hole for n'th Vmax hole position.

Bug 1423429

Change-Id: Ic71a8a18b0c41a7c88715b18e1caa04e0d992bef
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/378626
(cherry picked from commit ad6fc488978e21f5d1f41136a9f7a9c0a9c376e5)
Reviewed-on: http://git-master/r/410197
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Correct tuning voltage value

Correct sdhci-tegra.2 tuning voltage value

Bug 1423429

Change-Id: I9ba17c9a7a7d975c0d3fb1713829539d7c9868b3
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/373419
(cherry picked from commit f48c112fe4ec64dfafd383c60ad160f07f27050f)
Reviewed-on: http://git-master/r/410196
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Use first valid full win for negative margins

For negative margin calculations, use the first valid full window
in the first valid UI if Avg UI is found.
If Avg UI is not found, use first and second full windows to determine
the negative margin.
During negative margin calculation, marking each step as boundary.

Bug 1423429

Change-Id: I85cc57b1038bbce314d5bd89ef8aace117bdd8fe
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
(cherry picked from commit f3173ecf17d34644e482846d756e73fc67d9e7fa)
Reviewed-on: http://git-master/r/410195
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Add SDR50 tuning support

Added tuning tap hole equations to support SDR50 mode
for SD and SDIO device.

Bug 1447641

Change-Id: I09425098c0991553df87231ea9fdccf5bae683d3
Reviewed-on: http://git-master/r/361310
(cherry picked from commit 622918573fa3e3914ed9e633d467a0433a4a8ff2)

Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Change-Id: I3a0d1178b3c085057a16a981294085b667a5e3dc
Reviewed-on: http://git-master/r/365738
(cherry picked from commit 6cb8308deb102d300241136a001cc8b6f3ce1f81)
Reviewed-on: http://git-master/r/410194
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Add T114 tuning & platform data

Added T114 supported tuning and platform data

Bug 1423429
Bug 1423423

Change-Id: Ie00ed4b39021f9596297d707664c0ca44b67c1c2
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363816
(cherry picked from commit aa912a07c4aac36c5f6bb7b0f7a913ab04bc9845)
Reviewed-on: http://git-master/r/410193
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Modify partial window negative margins

Modifying the negative margin additions to partial window start
as per the new corner case identified by characterization team.
In case where the avg ui is found, negative margins are found
using first full window start and avg ui. If the avg ui is not
found, est ui is taken as avg ui and negative margins are obtained
using avg ui and all boundary starts.

Bug 1423423
Bug 1423429

Reviewed-on: http://git-master/r/#/c/361974/
(cherry picked from commit de54e591bfcd9f9f2e0989b4284d04cb30a729c0)

Change-Id: I762cbe7e36f72f9744ca8cd8dee3114758aa7597
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363815
(cherry picked from commit 1fb7531f70eb7cdd4bf6e766e8bc78890b0dafaa)
Reviewed-on: http://git-master/r/410192
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Use SDR104 UHS mode for SDR50 mode

Program SDR104 mode in the UHS_MODE_SEL register for SDR50 mode as well.
This is required for better timing and reliable transfers in SDR50 mode.

Bug 1423423

Reviewed-on: http://git-master/r/360182
(cherry picked from commit 52b973fb21acc16a5b6a05d321c6e425a2f63f9a)

Change-Id: I7e7b24fa2849daf83840aef4641e051b927e34a1
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363813
(cherry picked from commit b9e63eb49cb2dcb6fa92c5382d3760b5182c033c)
Reviewed-on: http://git-master/r/410191
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: sdhci: Pass speedo id in platform data

-Passing speedo id from sdhci platform data. Speedo id is required
for some calculation in auto tuning.

-Set trim value to 3 for SDMMC4

Bug 1423429

Reviewed-on: http://git-master/r/359376
(cherry picked from commit 533c3b6bf9f6ca622a35ace6f9865e76ca7a0fc6)

Change-Id: If130f95175397c2943967edcba5466d01cd4ada8
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363811
(cherry picked from commit c17402b37013f13b7c0f0c0dc56187eff47576fe)
Reviewed-on: http://git-master/r/410190
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Implementation of new tuning algorithm

Implemented the new tuning algorithm that
- Removes the tap holes from auto tuning windows
- Adjust window ends with margins for Vmin for the corresponding freq
- Dynamically updates dvfs table entry if a new Vmin is found from
auto tuning calculations
- Calculates the best tap value from the windows after removing tap
holes and margin additions.

Disabling external loopback clock for SDMMC3 as per characterization
results.

Bug 1423429

Reviewed-on: http://git-master/r/359375
(cherry picked from commit 8f33c039e2a8551b04d9023702a94c49dd2fffac)

Change-Id: I49b8dca227ae9f40cbbcbc81a36130a693588056
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363810
(cherry picked from commit e12f878c391eb732369313b53a1a94b5a673a8bc)
Reviewed-on: http://git-master/r/410189
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: dvfs: Predict required voltage for a given freq

Export the tegra_dvfs_predict_millivolts interface to drivers to be
used during tuning and getting the minimum core voltage for a given
frequency.

Bug 1423429

Reviewed-on: http://git-master/r/359374
(cherry picked from commit 363ba00eab262307efc02880db06b1c5fb67fa92)

Change-Id: I9dbadd831fa2f5b940ffb305a25ab56de63eec6e
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363809
(cherry picked from commit 1c92be1a06a6ccb944dbcc755dd3434e74ccaca1)
Reviewed-on: http://git-master/r/410188
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

linux: ARM: tegra: Add tegra_dvfs_predict_millivolts

Add tegra_dvfs_predict_millivolts function prototype

Bug 1423429

Reviewed-on: http://git-master/r/359373
(cherry picked from commit dab86eab4481e9801d4361a155a4d09ae5d44340)

Change-Id: I93e97f25919846bf37af9cefad2029151b5f1715
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/363808
(cherry picked from commit f299a1bcc3c6844c0d696233f1d80fddd01701c1)
Reviewed-on: http://git-master/r/410187
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

mmc: tegra: Enable external loopback for SDMMC3

Enabled external loopback for SDMMC3 for non-tunable modes.

Bug 1426947

Change-Id: I2c14bfc7d9cb21a44208cda88188836a3de61e77
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/360197
(cherry picked from commit 383d882f4e5e4799fc0ba65f9e2a428d9cc77bfd)
Reviewed-on: http://git-master/r/410186
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: dvfs: Add interface to set fmax at vmin

Added interface to specify clock fmax/vmin limits at run-time. Calling
this interface updates frequencies in the respective DVFS table to be
consistent with the new limits (voltage ladder is preserved):

- for voltages below new vmin, the respective frequencies are shifted
below new fmax to the levels already present in the table; if the 1st
table entry has frequency above new fmax, all entries below vmin
are filled in with 1kHz (min rate used in DVFS tables).

- for voltages above new vmin, the respective frequencies are set at
or above new fmax (not necessarily present in DVFS table before)

- if new vmin is already in the table the respective frequency is set
to new fmax (not necessarily present in DVFS table before)

Since, such update may result in changing voltage requirement up at
the same clock frequency, the interface can be called only for clocks
that are allowed to override core voltage (SDMMC on tegra platforms),
and only if core voltage is already overridden to the level higher
than new vmin.

Bug 1423423
Bug 1423429

Change-Id: I4f61ea6e3f8b6792ed058509339e16bff1947104
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/350016
(cherry picked from commit e6d6c5612f9dd22519297912365e0e54e31785ba)
Reviewed-on: http://git-master/r/410185
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra12: dvfs: Use one SDMMC dvfs table

New SDMMC tunning algorithm will not require core voltage override
range: tuning is performed at one nominal voltage point. Respectively
removed support for 2 SDMMC tables selected based on override range
size.

Bug 1423429

Change-Id: Ibeea397351afad8fe23950a16e03e920f2d3f37f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/350015
(cherry picked from commit 71eb3c0ad951c6c3c4a5dec55ab7dc1dc6cee7fe)
Reviewed-on: http://git-master/r/410184
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: fuse: added chip revision for T124

Chip revision for T124 was not present in struct chip_revision,
hence T124 chip revision added.

Bug 1486361

Change-Id: Icad37ed895b84bf94e6e868a38e4af1f5c115ee8
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/409312
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Shardar Mohammed <smohammed@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

usb: phy: tegra: increase the timeout for phy clk

Increase the timeout for phy clk to stabilize

Bug 1485579

Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: Ic73436dd5b74f327707b0c36ef0323d6decd9c67
Reviewed-on: http://git-master/r/408597
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ARM: dtb: tegra12: jetson-tk1: update pmc values

Update PMC values to realistic values proven working
for Jetson-tk1.

Bug 1501662

Change-Id: I1d38da5665ec0e75e72bc89c7517fd3f139d2098
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/408037
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

arm: tegra: pm: move err print to debug print

Unwanted print, that too with err level is moved
to debug level

Bug 1501662

Change-Id: I0fbfa966ab69ec40dd4a218e4e03226ab197a8da
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/408038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

cpufreq: remove race while accessing cur_policy

While accessing cur_policy during executing events
CPUFREQ_GOV_START, CPUFREQ_GOV_STOP, CPUFREQ_GOV_LIMITS
same mutex lock is not taken, dbs_data->mutex, which leads
to race and data corruption while running continious suspend
resume test.

Bug 1455519

Change-Id: I6b385578c791648681746b749d33f671d00154f3
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/407589
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

sound: tegra: ahub: add clock settings for T124

Several additional audio clocks need to be initialized before
accessing any audio register, otherwise system will just hard hang.

Probably fastboot bootloader initialize these clocks, which actually
should be handled in driver. We found this issue for U-Boot bringup.

Bug 1482099

Change-Id: Ia7a7c0115bc92a4e98e6f337cf8efc7b2f7a72a0
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408429
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra12: config: enable clock preinit code

Enable clock preinit code by default for U-Boot.

Bug 1482099

Change-Id: I643cc04e20b1f9b6b71576fc7e8c1828901e2e6c
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408428
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra12: add clock preinit code for U-Boot

U-Boot doesn't setup clock as NVTBoot or fastboot, so clocks need to
be preinit before our normal clock init.

Bug 1482099

Change-Id: I69734a47b7eb7af21c703aebcebc0c6735c6430c
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/408427
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

soc: codecs: max98090: fix interrupt registration

This patch clears previous interrupt and installs interrupt
handler at the end of device probe. Also it enables jack
detection only after handler is installed. This prevents,
false/stale interrupt generation and hence device access
by interrupt handler even before device probe has completed.

Bug 1464724

Change-Id: Id3c37ef4800e35cfec540bb1584c9b1cc7f7172f
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/405899
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: host: fix memory leaks with firmware

Pointer variables to store fecs and gpccs firmwares are local
variables.
Once firmwares are copied to local buffer, we can release
them with release_firmware() call before returning from function.

Release fecs and gpccs firmwares after copying to
fix memroy leak

Bug 1484645

Change-Id: I118874d65e30b6966f83d35347132d8f764bab8d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/387139
(cherry picked from commit d7cac8dd9a5d3f6cb44348a9698d0a6aefa80737)
Reviewed-on: http://git-master/r/407188
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Tested-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

tty: serial8250: add break handler quirk for tegra

On tegra,after a break is issued, uart status register
generates FIFOE error rather than the next character
ready status. For that quirk is already present. Hook is added
for the quirk so that sysrq key combination works. This helps
in debugging soft hangs

Bug 1401397

Change-Id: I0131cfc986aba694ddc21d859685748843534611
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/401535
(cherry picked from commit c72b366e010b5cfbac6541eb339a0324b863ff17)
Reviewed-on: http://git-master/r/406398
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit

PCIE: tegra: resume timing correction

The time from +1.05V_RUN to PEX_L1_RST_L signal
(PEX_L1_RST_N on T124) should be 100ms minimum

Bug 1500840

Change-Id: I170ed3225f80b5ef0ccaf4b38565d3adf94a674a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/402841
(cherry picked from commit d380528e5e865437681c21befc40de430b39f9a9)
Reviewed-on: http://git-master/r/406394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: host: fix invalid pointer

Props to Mayank for spotting the bug

bug 1484677

Change-Id: I263f81b891a3321b074ba334747144bf6d1b4934
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/384381
(cherry picked from commit 440b03565fa18447a909fb42ca248954a4ac12f5)
Reviewed-on: http://git-master/r/406942
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: dtb: remove laguna string for jetson

This commit removes laguna comptability strings for
jetson-tk1 boards.

bug 1509239

Change-Id: Ifef547aa19f479c3adc03cc7c3557aa9372e1cb2
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/406015
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: pm375: add jetson-tk1 references

This commit adds jetson-tk1 compatible reference checks
to the architecture code.

bug 1509239

Change-Id: I859452a0c8705b6fda8e1739906eb78f2b0527b2
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/406016
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Sundeep Borra <sborra@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

gpu: nvgpu: Do not enable HCE priv mode

Do not enable HCE priv mode.

Bug 1501689

Change-Id: I3da0ed7c7c1d59ef3e2a8bc727ca531eb22bab11
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/398110
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: pm375: disable usb device mode

Disable usb device mode for pm375 rev A-D

Bug 1495952

Change-Id: I553d3c05f9a8421ff4900999d9d6e5c21dc5e596
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/396368
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: powergate: suppress unwanted info

is_powered is a check and it should not throw
wrong information that powergating is not supported
for this SOC

Bug 1499524

Change-Id: Id2f0ff0d295d49b952fba571b17639723bbdec65
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/395835
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: laguna: correct vbus regulators

vbus regulators were configured wrongly for pm375.
This patch corrects the vbus regulators.

Change-Id: Ib49f95b3ea9d46cb97978d1433f4d05681d10f0a
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/396247
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra12: enable CONFIG_TMPFS_POSIX_ACL

Enable POSIX ACL support for DEVTMPFS; this is
"optional but strongly recommended" by systemd and
required for proper operation of some Linux distributions.

Bug 1499849

Change-Id: I414316e6b231da34c97971cf0eecf699da3075b6
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Reviewed-on: http://git-master/r/396806
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

usb: otg: tegra: sysfs-setting for gadget mode

Add ability to set the OTG port to device mode through sysfs.

Bug 1463801
Bug 1380254
Bug 1435985

Change-Id: I7bf5a3d8576e88ffb399a0bab2d43b446d6753c8
Signed-off-by: Haribabu Narayanan <hnarayanan@nvidia.com>
Reviewed-on: http://git-master/r/377073
(cherry picked from commit 8921a2c370014e997df95818802ceb487084fadb)
Reviewed-on: http://git-master/r/396367
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Tested-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

regulator: as3722: sd1 external control only during suspend

If SD1 external control is enabled from boot, it has adverse
effect on power down cycle. Which can lead to long term product
stability. So enable SD1 external control only while going to
to suspend and disable while resuming

Bug 1495458

Change-Id: Ia65bf6f358d15604cea3914914188ce1725b4120
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/395039
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ASoc: Tegra: max98090: secondary mic only for t14x

Secondary MIC available in tegra14x platforms only. Hence adding
appropriate conditions.
Also, DMIC3 and DMIC4 are declared for max98091 and not max98090.

bug 1457218

Change-Id: Ieeaff6890a195a4620f80b17ea9a9e0a1ff975c9
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/394119
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

iommu/tegra: smmu: fix unaliged sg mapping

map_sg() miscaluculated the number of pages to map where 'offset' and
PAGE_ALIGN was ignored. This patch fixes the ext4 memory corruption
problem when USB is used. This patch was based on Nilesh More's hard
working journey to narrow down the root cause of this problem. This bug
was introduced by the commit:

  f46788a6f7d9 - iommu/tegra: smmu: Optimize smmu_iommu_map_sg()

Bug 1418514

Change-Id: I3492ca3aad48f63bc81e50886eefc32cb6a17a8b
Reported-by: Nilesh More <nmore@nvidia.com>
Tested-by: Nilesh More <nmore@nvidia.com>
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/394554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nilesh More <nmore@nvidia.com>
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
(cherry picked from commit 7b4dac1d522cf48e4e6bd227ff235bffa82cb755)
Signed-off-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-on: http://git-master/r/394993

video: tegra: host: g20a: Add AELPG feature

Add basic functionality and helper routines for AELPG. Also,
enable AELPG during init.

Enabling adaptive elpg is needed for the data corruption
issues seen as per the bug reported below.
Bug 1458353

Change-Id: Ie6effc354dc1ade2a4baa2585984ff39d7c0660d
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/338873
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit 2b235e3708857f12ee765a85ce7a61cc464ac98e)
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/394410
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: host: gk20a: add AELPG headers

Enabling adaptive elpg is needed for the data corruption
issues seen as per the bug reported below.
Bug 1458353

Change-Id: Ie285e7e7e3849e0b8cb263a67a5dfe7056150d51
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/338872
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
(cherry picked from commit b0b937165d49e3f57fa25815239e2a0f6f155527)
Reviewed-on: http://git-master/r/394409
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

pcie: host: tegra: re-enable MSI after resume

Initialize core MSI data once and re-enable MSI
registers on resume, if MSI were enabled.

Bug 1478052

Change-Id: I3d3d7e21be121e38d5159302ec47aaff9dcf7525
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/354470
(cherry picked from commit 7908f31c3e7a5cfa9c053f89acc5691c6502e3a3)
Reviewed-on: http://git-master/r/394682
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

arm: tegra12: enable dram temperature only for LPDDR2

This patch disables creating debugfs entry for non
LP DRAM variants. As currently two DRAM variants are
supported i.e. LPDDR2 and DDR3, so it enables dram
temperature entry only for LPDDR2.

Bug 1473611

Change-Id: I3b9ef616e5110a09f06522d761549f6db4bd578d
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/385488
(cherry picked from commit 4d0fa6f0c069d796de4b037f12b532c856742256)
Reviewed-on: http://git-master/r/393193
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

video: tegra: hdmi: WAR: emulate hdmi hotoplug

Emulate hotplug to make DVI monitors work through HDMI-to-DVI
dongle. In the last hdmi state, enabled_state, force trigger
hotplug for the HDMi go through clean power off, read EDID,
power on, and configure sequence.

bug 1495496

Change-Id: I0d9c3d7e5d1244d677a0d547c68c6cb9f961a956
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/392977
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: dc: get default mode from EDID

Override hard-coded default HDMI mode with the preferred mode
obtained from EDID read. Since the preferred mode is obtained
dynamically from EDID, the default hard-coded HDMI mode is set
to 640x480 @60Hz, which is universally supported.

bug 1495496

Change-Id: I19bc910758015927938fe5dde3e5359a78d905d4
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/393564
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: config: disable firmware loading

disable firmware loading by Realtek 8169 driver.

Bug 1481697

Change-Id: Ie0413caf9029d5515d862429956c386f16082553
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/394645
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

ASoC: codecs: max98090: correct DMIC names

DMIC1 and DIMC2 were renamed to DMICL and DMICR respectively.
Hence correcting the names accordingly.

bug 1457229

Change-Id: Iecff0cabb18743a8d399965fab320ac3683f622a
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/394109
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: Add SW thermal throttling for Jetson

Enable cpu & gpu balanced cooling devices so that SW thermal throttling
gets enabled.

Bug 1496341

Change-Id: I28f7f9cda4aaa4fbe7d5eb6b7ebcee54a7f492a4
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/393645
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra12: Use runnable governor as default

Switch cpuquiet to use the runnable_threads governor instead of the
balanced governor as the default governor.

Bug 1493183

Change-Id: Ie7519e1744bb620e54be7a9c9010290a72b941f9
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/393174
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra12: disable sata idle powergating

SATA idle powergating is broken. Thus disabling it.

Bug 1483608

Change-Id: I31d50e443986be332d5916dff1d7413581e179a6
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/390900
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

tegra: T124: HDMI: fix pixel clock setting

- Enhance the HDMI pixel clock setting by determining a better parent
  clock rate.  Half resolutions for HDMI pclk are not used due to
  uneven duty cycle.
- Fix the divider value out of sync problem between two registers,
  DISP_DISP_CLOCK_CONTROL and CLK_RST_CONTROLLER_CLK_SOURCE_HDMI, due
  to the rounding difference.  The clk_set_rate() routine uses round-up,
  while the tegra_dc_program_mode() routine uses round-closest.  Due to
  the DVFS, the frequency determination can not exceed the requested
  rate and this means that round-up must be used for divider handling
  instead of round-closest.

bug 1420652

Change-Id: Ib32e79f96dcd272a392de7f852c3c0285f9c453a
Signed-off-by: Sungwook Kim <sungwookk@nvidia.com>
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/366390
(cherry picked from commit 6eb5d7e7b5dcd9a118649e5a8d02e35cf45a4fc6)
Reviewed-on: http://git-master/r/392419
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: Check DC connected status

1. Prevent any operations from user-space and tty when no HDMI
device is connected. DC will stay powergated till hotplugged.
2. Virtual Terminal requests blank after blank timeout. If HDMI
isn't connected we shouldn't allow this operation.

bug 1487112
bug 1481748

Change-Id: I0bd97e62ca059513044bc49b8d8c045610268016
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/391152
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

misc: nct : configure nct local hi/lo temp also

configure nct local hi/lo temp also so
that action is taken if there is an increase
in local temp

Bug 1490524

Change-Id: I3186ff3ade97e7655c5c7494efa7c51b6946de5d
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/391649
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: enable nct interrupt for pm375 & laguna

Enable nct alert interrupt for pm375

Bug 1490524

Change-Id: I473365b4d7c9ab26626dac73b9b15f2e708f2719
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/391648
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

PCIE: tegra: enable ASPM and disable L0s

Enable ASPM feature for Tegra12 but keep L0s
disabled as its broken.

Bug 1483608

Change-Id: Ie1f8c10dc1d95c4b5164f9030aa5560542c81f1b
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/391647
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

misc: nct1008: avoid reading bogus temperature

Added a check for temperature above max value and return error when
that happens to avoid showing insane temperature values to user. Bogus
temperature readout happens rarely due to the NCT device still being
initialized and unprepared while interrupts happen.

Based on commit 707c55d46a9c9f3780caa64426efa8220be11a1e which was
reviewed-on: http://git-master/r/376832

Bug 1454792

Change-Id: I7f31f80f47abc197e6dda3d661dfb82e946ea039
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/392045
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

misc: nct1008: use signed long for temp

Avoid setting signed temperature value into unsigned long pointer

Bug 1454792

Change-Id: I583f2296c294b6d499fcdf8e1b9338cce5b8344d
Reviewed-on: http://git-master/r/384655
(cherry picked from commit 72ccbb69fcf0375ce7a26db7c32dd3dd925a6f26)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/392044
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

misc: nct1008: change overheat enable message

Avoid using the word 'warning' in the log message that reports
successful setup of the overheat warning message. This confuses
tests that scan for errors and warnings on console.

Also changed the level of the message to pr_debug.

Bug 1436329

Change-Id: Idbc6cc5eed42265a1487a9809969bce7edc7a620
Reviewed-on: http://git-master/r/378669
(cherry picked from commit 999acb87fffe01365485333ac28b160a34502efb)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/392043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: host: gk20a: Check for free va fail

Return error if freeing virtual address space fails. Do not try to
free graphics context that has not been allocated.

Change-Id: I1c22650aae25038d56582e00b8906532ace482f1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/382474
(cherry picked from commit 20a8917aaa7c6bbad3c74f5279fb8b142f858e77)
Reviewed-on: http://git-master/r/391823
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: fb: Keep old mode list

Keeping the old mode list and framebuffer console is storing a
video mode pointer pointing to one of the modes in modelist.
Adding enable function to enable DC when hotplug succeeds.

bug 1481759

Change-Id: I8164c0d318edc3cbc6f61481eda8c90daabe14a5
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/382507
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

PCIE: tegra: run PCIE at GEN1 speed

To preserve power, run PCIE @ GEN1 speed.
This will introduce cap on pciex clock to 250Mhz

Bug 1483563

Change-Id: Iedc05870647368523070a8033e7cbba1e0bc2b43
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/384368
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: update hdmi tdms parameter for PM375

update hdmi tdms parameter for PM375

Bug 1481888

Change-Id: Icd04f0d8a80ee84b8ba9a2441a841d7bd5954c3a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/384776
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: laguna: configure ams gpio1 and gpio2

Configure ams gpio1 and 2 as bial pull-down from pdata

Bug 1485412

Change-Id: I8df5c6e79933e1c9c01f35ae7938bfd360fce88f
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/384705
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: update PM375 pinmux setting

Update PM375 pinmux by tristating the unusued
pins based on pinmux excel
T124_customer_pinmux_PM375_29Oct2013.xlsm

Bug 1483835

Change-Id: I1eaea4f5d40096d9a1d560f59561db2dce2dfda6
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/383907
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

PCIE: tegra: limit mselect clk to 102Mhz

This will put cap on power consumption in idle
If someone one to bup the clock, it can be done from
debugfs

Bug 1483563

Change-Id: I668193864fa26b108bec1c1f953f275847ee293c
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/384367
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra12: enable SATA idle powergating

Enable SATA idle powergating

Bug 1483608

Change-Id: I23d8675620c6ff844bda558a48c608aaebcf6e5a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/383755
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: dont register unavailable sensors

PM375 does not have mpu, bmp, akm, wifi sensors.
So dont register those i2c devices

Bug 1483432

Change-Id: Ic91049b35ad65e558f5a4a292f36550eca51fd1c
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/383692
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

ARM: tegra: config: Enable GK20A devfreq for L4T

Also disable gk20a perfmon, which was earlier enabled.

Bug 1484540

Change-Id: I539a60d45db1990df3db7dcc98da1d78a788c600
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/384149
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: gk20a: remove pmu dump stats

This commit removes the dumping of pmu stats only
if the pmu exterr intr occurs.

bug 1458353

Change-Id: I0836da647abca64879991af9c280572477d1ce97
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: http://git-master/r/383442
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

arm: tegra: HDMI: fix 720p low output swing for PM375

Fix 720p HDMI low output swing for PM375.

bug 1481888

Change-Id: Ide0e8a9d02213b3a2e59e3f5ad614f9c2e423139
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/383441
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: gk20a: do not set error notifier during debugging

Do not set error notifier on exceptions handled by attached
SM debugger.

bug 1468586
bug 1470992

Change-Id: I9c35b098ade022df7c2745a4f974ef0d1a7fad58
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/377866
(cherry picked from commit e30f88aa7fbb56a703a50a445ae6761bcb0d5e99)
Reviewed-on: http://git-master/r/383228
GVS: Gerrit_Virtual_Submit

video: tegra: host: gk20a: add missing returns

Bug 1375360

Change-Id: I20562349a45185e97ee2a3a1c9e3262ed302d76a
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/376657
(cherry picked from commit af817f4a70c04203622a8d56068ed72f28dfe66b)
Reviewed-on: http://git-master/r/383227
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

ARM: tegra: dtb: Add new file to support gpio-keys

Many GPIOs registered as interrupt are not applicable for PM375,
new file added for PM375 to support GPIOs which are applicable for
PM375.

Added file: tegra124-pm375-gpio-keys.dtsi

Bug 1475519

Change-Id: Ic7cdae2afa43751b3ba045f08c62dbb2c36b6562
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/382467
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra: config: disable BLUEDROID_PM

Disable BLUEDROID_PM in L4T defconfig.

Bug 1457135

Change-Id: I027e83cde9a37e244c473b35179cf1fe529ed9af
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/368728
Cherry-picked from 1217dac9195728b160e01749a222882d7519386c
Reviewed-on: http://git-master/r/376564
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

ARM: tegra124: pm375: add pcie_usb_vbus consumer

Bug 1466561

Change-Id: I4522495ed4d8d0ef39c4e3747f1e4413999b6633
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/382433
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: pm375 : Enable utmi1

Enable usb port included in the mPCIe

Bug 1466561

Change-Id: I0aaa655652bb7c6f27a082b0cd3909cbb4334057
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/381487
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

video: tegra: gpu debugger

Add a control to manage SMPC context switch mode.
This is needed in reaction to the recent security
change which disabled set_falcon[5] etc.

Bug 1375360

Change-Id: Ia9d1a97a1b89b48538010d74207ff4d1b8852083
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/375772
(cherry picked from commit c3c7d8b60f62bc276d0e773994ea6e0a4d9422cb)
Reviewed-on: http://git-master/r/382743
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: host: gk20a implement priv access map

This change enables a whitelist for priv register accesses on gk20a
through the set_falcon[4] path (used by usermode drivers).

Bug 1375360

Change-Id: I18274097fddaab0a15a8ad59f1d23f9e974a50e7
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/375651
(cherry picked from commit afd7fec44674af2569ac6443cf245e25786cc335)
Reviewed-on: http://git-master/r/376912
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

video: tegra: host: gk20a: Fix deferred mmu fault

Deferred MMU fault did not clear stored mmu_fault_engines variable
and this caused the MMU fault handler to handle subsequent MMU fault
as a fake fault.

This patch modifies the code so that we clear the mmu_fault_engines
variable if we need to continue fault handling on channel tear down.

Bug 1472328

Change-Id: Iabec72575072b207aef1b05ef2f661d7dc8f3c40
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/378792
(cherry picked from commit 25d1566063ae030124c28780fb825e982a5a24e2)
Reviewed-on: http://git-master/r/381534
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

arm: tegra: add emc dvfs table for PM375

Add EMC DVFS table for PM375

Bug 1454434

Change-Id: I83ef7cfcf65f5d1a4b7e7a711e6373e249439e34
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/382438
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>