soc: codecs: max98090: fix interrupt registration

This patch clears previous interrupt and installs interrupt
handler at the end of device probe. Also it enables jack
detection only after handler is installed. This prevents,
false/stale interrupt generation and hence device access
by interrupt handler even before device probe has completed.

Bug 1464724

Change-Id: Id3c37ef4800e35cfec540bb1584c9b1cc7f7172f
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/405899
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index 611fed829ff66aea6ca2fb06a98916cc541a2876..2b79879684c8fbde61699c71ed1c664ff451bf78 100644 (file)
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -3715,17 +3715,6 @@ static int max98090_probe(struct snd_soc_codec *codec)
 
        INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
 
-       /* Enable jack detection */
-       snd_soc_write(codec, M98090_REG_3D_CFG_JACK,
-               M98090_JDETEN_MASK | M98090_JDEB_25MS);
-
-       /* Register for interrupts */
-       if ((request_threaded_irq(pdata->irq, NULL,
-               max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
-               "max98090_interrupt", codec)) < 0) {
-               dev_info(codec->dev, "request_irq failed\n");
-       }
-
 #ifdef MAX98090_HIGH_PERFORMANCE
        /* High Performance */
        snd_soc_update_bits(codec, M98090_REG_43_DAC_CFG,
@@ -3758,6 +3747,20 @@ static int max98090_probe(struct snd_soc_codec *codec)
 
        max98090_add_widgets(codec);
 
+       /* Clear existing interrupts */
+       snd_soc_read(codec, M98090_REG_01_IRQ_STATUS);
+
+       /* Register for interrupts */
+       if ((request_threaded_irq(pdata->irq, NULL,
+               max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+               "max98090_interrupt", codec)) < 0) {
+               dev_info(codec->dev, "request_irq failed\n");
+       }
+
+       /* Enable jack detection */
+       snd_soc_write(codec, M98090_REG_3D_CFG_JACK,
+               M98090_JDETEN_MASK | M98090_JDEB_25MS);
+
 err_access:
        return ret;
 }