platform: tegra: clocks: Fix SC7 entry for LP4

Fis the SC7 entry rate for LP4 based platforms. This avoids doing MRWs
and the complexities of tracking FSPs on LPDDR4 during DRAM waking.

Change-Id: Id651997adc3b87ca786759e6d99ae5b0474b945c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/660322
(cherry picked from commit 9dd12a170882586f64237ee4d553ce90a5ec07f4)
Reviewed-on: http://git-master/r/663399
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

diff --git a/drivers/platform/tegra/tegra21_clocks.c b/drivers/platform/tegra/tegra21_clocks.c
index a5931fe7a4ef3e1069b2780bc0ef5b7acfde5711..c4b5d5e2543efa55d090d4914f1c7dd35f745fba 100644 (file)
--- a/drivers/platform/tegra/tegra21_clocks.c
+++ b/drivers/platform/tegra/tegra21_clocks.c
@@ -5363,6 +5363,15 @@ static void tegra21_emc_sync_plls(struct clk *emc,
 }
 
 #ifdef CONFIG_PM_SLEEP
+
+/*
+ * WAR: fixing SC7 entry rate is to ensure stable boot up after SC7 resume on
+ * LP4 platforms. This ensures that there are no MRWs necesary by the bootrom
+ * when waking the DRAM (since the MRs will already have valid settings for 204
+ * MHz). Problem is that the BR is not aware of what FSP is in use.
+ */
+#define FIXED_SC7_ENTRY_RATE   204000000
+
 static void tegra21_emc_clk_suspend(struct clk *c, unsigned long rate)
 {
        /* No change if other than LPDDR4 */
@@ -5377,8 +5386,8 @@ static void tegra21_emc_clk_suspend(struct clk *c, unsigned long rate)
         * Scale EMC rate at boot rate - required for entering SC7(LP0)
         * on LPDDR4.
         */
-       if (rate != c->boot_rate)
-               tegra21_emc_clk_set_rate(c, c->boot_rate);
+       if (rate != FIXED_SC7_ENTRY_RATE)
+               tegra21_emc_clk_set_rate(c, FIXED_SC7_ENTRY_RATE);
 }
 #endif