]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commitdiff
arm64: tegra21: emc: Reduce number of access to EMC
authorAlex Waterman <alexw@nvidia.com>
Sat, 6 Dec 2014 00:56:51 +0000 (16:56 -0800)
committerMitch Luban <mluban@nvidia.com>
Thu, 18 Dec 2014 00:07:08 +0000 (16:07 -0800)
Reduce the number of EMC reads generated by the periodic training code.
Instead of reading the starting EMC_CFG and etc values from the EMC
before determining if training is necessary, do it afterwords, iff
training actually needs to happen.

Change-Id: I41c6961f7aaa383013746e0631aed21eb9c44323
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/660454
(cherry picked from commit 5f2fc45e9423cc496a599a5f145eeec7a2939ee9)
Reviewed-on: http://git-master/r/663398
Reviewed-by: Mitch Luban <mluban@nvidia.com>
drivers/platform/tegra/mc/tegra21_emc_cc_r21015.c

index 1a064b2073e658a9b292324b812bc5ca46a35562..352cf154594c981f2216d3c15cb07f704d0e1f05 100644 (file)
@@ -547,17 +547,18 @@ u32 __do_periodic_emc_compensation_r21015(
        };
        u32 items = ARRAY_SIZE(list);
 
-       emc_dbg_o = emc_readl(EMC_DBG);
-       emc_cfg_o = emc_readl(EMC_CFG);
-       emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD |
-                               EMC_CFG_DRAM_CLKSTOP_PD |
-                               EMC_CFG_DRAM_CLKSTOP_PD);
+       if (current_timing->periodic_training) {
 
-       channel_mode = !!(current_timing->burst_regs[EMC_FBIO_CFG7_INDEX] &
-                         (1 << 2));
-       dram_dev_num = 1 + (mc_readl(MC_EMEM_ADR_CFG) & 0x1);
+               emc_dbg_o = emc_readl(EMC_DBG);
+               emc_cfg_o = emc_readl(EMC_CFG);
+               emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD |
+                                       EMC_CFG_DRAM_CLKSTOP_PD |
+                                       EMC_CFG_DRAM_CLKSTOP_PD);
+
+               channel_mode = !!(current_timing->burst_regs[EMC_FBIO_CFG7_INDEX] &
+                                 (1 << 2));
+               dram_dev_num = 1 + (mc_readl(MC_EMEM_ADR_CFG) & 0x1);
 
-       if (current_timing->periodic_training) {
                /*
                 * 1. Power optimizations should be off.
                 */