2 * Based on arch/arm/include/asm/mmu_context.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_MMU_CONTEXT_H
20 #define __ASM_MMU_CONTEXT_H
22 #include <linux/compiler.h>
23 #include <linux/sched.h>
25 #include <asm/cacheflush.h>
26 #include <asm/proc-fns.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm/cputype.h>
29 #include <asm/pgtable.h>
31 extern unsigned int max_asid_bits;
33 extern unsigned int cpu_last_asid;
35 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
36 void __new_context(struct mm_struct *mm);
38 #ifdef CONFIG_PID_IN_CONTEXTIDR
39 static inline void contextidr_thread_switch(struct task_struct *next)
42 " msr contextidr_el1, %0\n"
45 : "r" (task_pid_nr(next)));
48 static inline void contextidr_thread_switch(struct task_struct *next)
54 * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
56 static inline void cpu_set_reserved_ttbr0(void)
58 unsigned long ttbr = page_to_phys(virt_to_page(empty_zero_page));
61 " msr ttbr0_el1, %0 // set TTBR0\n"
67 static inline void switch_new_context(struct mm_struct *mm)
73 local_irq_save(flags);
74 cpu_switch_mm(mm->pgd, mm);
75 local_irq_restore(flags);
78 static inline void check_and_switch_context(struct mm_struct *mm,
79 struct task_struct *tsk)
81 /* unneeded switch to ASID0 */
82 /* cpu_set_reserved_ttbr0(); */
84 if (!((mm->context.id ^ cpu_last_asid) >> max_asid_bits))
86 * The ASID is from the current generation, just switch to the
87 * new pgd. This condition is only true for calls from
88 * context_switch() and interrupts are already disabled.
90 cpu_switch_mm(mm->pgd, mm);
91 else if (irqs_disabled())
93 * Defer the new ASID allocation until after the context
94 * switch critical region since __new_context() cannot be
95 * called with interrupts disabled.
97 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
100 * That is a direct call to switch_mm() or activate_mm() with
101 * interrupts enabled and a new context.
103 switch_new_context(mm);
106 #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
107 #define destroy_context(mm) do { } while(0)
109 #define finish_arch_post_lock_switch \
110 finish_arch_post_lock_switch
111 static inline void finish_arch_post_lock_switch(void)
113 if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
114 struct mm_struct *mm = current->mm;
119 local_irq_save(flags);
120 cpu_switch_mm(mm->pgd, mm);
121 local_irq_restore(flags);
126 * This is called when "tsk" is about to enter lazy TLB mode.
128 * mm: describes the currently active mm context
129 * tsk: task which is entering lazy tlb
130 * cpu: cpu number which is entering lazy tlb
132 * tsk->mm will be NULL
135 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
140 * This is the actual mm switch as far as the scheduler
141 * is concerned. No registers are touched. We avoid
142 * calling the CPU specific function when the mm hasn't
146 switch_mm(struct mm_struct *prev, struct mm_struct *next,
147 struct task_struct *tsk)
149 unsigned int cpu = smp_processor_id();
152 /* check for possible thread migration */
153 if (!cpumask_empty(mm_cpumask(next)) &&
154 !cpumask_test_cpu(cpu, mm_cpumask(next)))
155 __flush_icache_all();
157 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
158 check_and_switch_context(next, tsk);
161 #define deactivate_mm(tsk,mm) do { } while (0)
162 #define activate_mm(prev,next) switch_mm(prev, next, NULL)