2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
4 * Derived from the ems_pci.c driver:
5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/netdevice.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <socketcan/can.h>
30 #include <socketcan/can/dev.h>
31 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
39 #define DRV_NAME "sja1000_plx_pci"
41 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
42 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
44 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
45 "Adlink PCI-7841/cPCI-7841 SE, "
46 "Marathon CAN-bus-PCI, "
47 "TEWS TECHNOLOGIES TPMC810");
48 MODULE_LICENSE("GPL v2");
50 #define PLX_PCI_MAX_CHAN 2
53 int channels; /* detected channels count */
54 struct net_device *net_dev[PLX_PCI_MAX_CHAN];
55 void __iomem *conf_addr;
58 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
60 /* PLX90xx registers */
61 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */
62 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
63 * Serial EEPROM, and Initialization
67 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
68 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
69 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
70 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
73 * The board configuration is probably following:
74 * RX1 is connected to ground.
75 * TX1 is not connected.
76 * CLKO is not connected.
77 * Setting the OCR register to 0xDA is a good idea.
78 * This means normal output mode, push-pull and the correct polarity.
80 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
83 * In the CDR register, you should set CBP to 1.
84 * You will probably also want to set the clock divider value to 7
85 * (meaning direct oscillator output) because the second SJA1000 chip
86 * is driven by the first one CLKOUT output.
88 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
90 /* SJA1000 Control Register in the BasicCAN Mode */
93 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
94 #define REG_CR_BASICCAN_INITIAL 0x21
95 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1
96 #define REG_SR_BASICCAN_INITIAL 0x0c
97 #define REG_IR_BASICCAN_INITIAL 0xe0
99 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
100 #define REG_MOD_PELICAN_INITIAL 0x01
101 #define REG_SR_PELICAN_INITIAL 0x3c
102 #define REG_IR_PELICAN_INITIAL 0x00
104 #define ADLINK_PCI_VENDOR_ID 0x144A
105 #define ADLINK_PCI_DEVICE_ID 0x7841
107 #define MARATHON_PCI_DEVICE_ID 0x2715
109 #define TEWS_PCI_VENDOR_ID 0x1498
110 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
112 static void plx_pci_reset_common(struct pci_dev *pdev);
113 static void plx_pci_reset_marathon(struct pci_dev *pdev);
115 struct plx_pci_channel_map {
118 u32 size; /* 0x00 - auto, e.g. length of entire bar */
121 struct plx_pci_card_info {
125 u8 ocr; /* output control register */
126 u8 cdr; /* clock divider register */
128 /* Parameters for mapping local configuration space */
129 struct plx_pci_channel_map conf_map;
131 /* Parameters for mapping the SJA1000 chips */
132 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
134 /* Pointer to device-dependent reset function */
135 void (*reset_func)(struct pci_dev *pdev);
138 static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
139 "Adlink PCI-7841/cPCI-7841", 2,
140 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
141 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
142 &plx_pci_reset_common
143 /* based on PLX9052 */
146 static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
147 "Adlink PCI-7841/cPCI-7841 SE", 2,
148 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
149 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
150 &plx_pci_reset_common
151 /* based on PLX9052 */
154 static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
155 "Marathon CAN-bus-PCI", 2,
156 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
157 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
158 &plx_pci_reset_marathon
159 /* based on PLX9052 */
162 static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
163 "TEWS TECHNOLOGIES TPMC810", 2,
164 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
165 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
166 &plx_pci_reset_common
167 /* based on PLX9030 */
170 static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
172 /* Adlink PCI-7841/cPCI-7841 */
173 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
174 PCI_ANY_ID, PCI_ANY_ID,
175 PCI_CLASS_NETWORK_OTHER << 8, ~0,
176 (kernel_ulong_t)&plx_pci_card_info_adlink
179 /* Adlink PCI-7841/cPCI-7841 SE */
180 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
181 PCI_ANY_ID, PCI_ANY_ID,
182 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
183 (kernel_ulong_t)&plx_pci_card_info_adlink_se
186 /* Marathon CAN-bus-PCI card */
187 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
188 PCI_ANY_ID, PCI_ANY_ID,
190 (kernel_ulong_t)&plx_pci_card_info_marathon
193 /* TEWS TECHNOLOGIES TPMC810 card */
194 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
195 PCI_ANY_ID, PCI_ANY_ID,
197 (kernel_ulong_t)&plx_pci_card_info_tews
201 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
203 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
205 return ioread8(priv->reg_base + port);
208 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
210 iowrite8(val, priv->reg_base + port);
214 * Check if a CAN controller is present at the specified location
215 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
216 * Also check states of some registers in reset mode.
218 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
223 * Check registers after hardware reset (the Basic mode)
224 * See states on p. 10 of the Datasheet.
226 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
227 REG_CR_BASICCAN_INITIAL &&
228 (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
229 (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
232 /* Bring the SJA1000 into the PeliCAN mode*/
233 priv->write_reg(priv, REG_CDR, CDR_PELICAN);
236 * Check registers after reset in the PeliCAN mode.
237 * See states on p. 23 of the Datasheet.
239 if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
240 priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
241 priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
248 * PLX90xx software reset
249 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
250 * For most cards it's enough for reset the SJA1000 chips.
252 static void plx_pci_reset_common(struct pci_dev *pdev)
254 struct plx_pci_card *card = pci_get_drvdata(pdev);
257 cntrl = ioread32(card->conf_addr + PLX_CNTRL);
258 cntrl |= PLX_PCI_RESET;
259 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
261 cntrl ^= PLX_PCI_RESET;
262 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
265 /* Special reset function for Marathon card */
266 static void plx_pci_reset_marathon(struct pci_dev *pdev)
268 void __iomem *reset_addr;
270 int reset_bar[2] = {3, 5};
272 plx_pci_reset_common(pdev);
274 for (i = 0; i < 2; i++) {
275 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
277 dev_err(&pdev->dev, "Failed to remap reset "
278 "space %d (BAR%d)\n", i, reset_bar[i]);
280 /* reset the SJA1000 chip */
281 iowrite8(0x1, reset_addr);
283 pci_iounmap(pdev, reset_addr);
288 static void plx_pci_del_card(struct pci_dev *pdev)
290 struct plx_pci_card *card = pci_get_drvdata(pdev);
291 struct net_device *dev;
292 struct sja1000_priv *priv;
295 for (i = 0; i < card->channels; i++) {
296 dev = card->net_dev[i];
300 dev_info(&pdev->dev, "Removing %s\n", dev->name);
301 unregister_sja1000dev(dev);
302 priv = netdev_priv(dev);
304 pci_iounmap(pdev, priv->reg_base);
305 free_sja1000dev(dev);
308 plx_pci_reset_common(pdev);
311 * Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
314 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
317 pci_iounmap(pdev, card->conf_addr);
321 pci_disable_device(pdev);
322 pci_set_drvdata(pdev, NULL);
326 * Probe PLX90xx based device for the SJA1000 chips and register each
327 * available CAN channel to SJA1000 Socket-CAN subsystem.
329 static int __devinit plx_pci_add_card(struct pci_dev *pdev,
330 const struct pci_device_id *ent)
332 struct sja1000_priv *priv;
333 struct net_device *dev;
334 struct plx_pci_card *card;
335 struct plx_pci_card_info *ci;
340 ci = (struct plx_pci_card_info *)ent->driver_data;
342 if (pci_enable_device(pdev) < 0) {
343 dev_err(&pdev->dev, "Failed to enable PCI device\n");
347 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
348 ci->name, PCI_SLOT(pdev->devfn));
350 /* Allocate card structures to hold addresses, ... */
351 card = kzalloc(sizeof(*card), GFP_KERNEL);
353 dev_err(&pdev->dev, "Unable to allocate memory\n");
354 pci_disable_device(pdev);
358 pci_set_drvdata(pdev, card);
362 /* Remap PLX90xx configuration space */
363 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
366 dev_err(&pdev->dev, "Failed to remap configuration space "
367 "(BAR%d)\n", ci->conf_map.bar);
368 goto failure_cleanup;
370 card->conf_addr = addr + ci->conf_map.offset;
372 ci->reset_func(pdev);
374 /* Detect available channels */
375 for (i = 0; i < ci->channel_count; i++) {
376 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
378 dev = alloc_sja1000dev(0);
381 goto failure_cleanup;
384 card->net_dev[i] = dev;
385 priv = netdev_priv(dev);
387 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
388 priv->irq_flags = SA_SHIRQ;
390 priv->irq_flags = IRQF_SHARED;
393 dev->irq = pdev->irq;
396 * Remap IO space of the SJA1000 chips
397 * This is device-dependent mapping
399 addr = pci_iomap(pdev, cm->bar, cm->size);
402 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
403 goto failure_cleanup;
406 priv->reg_base = addr + cm->offset;
407 priv->read_reg = plx_pci_read_reg;
408 priv->write_reg = plx_pci_write_reg;
410 /* Check if channel is present */
411 if (plx_pci_check_sja1000(priv)) {
412 priv->can.clock.freq = ci->can_clock;
416 SET_NETDEV_DEV(dev, &pdev->dev);
418 /* Register SJA1000 device */
419 err = register_sja1000dev(dev);
421 dev_err(&pdev->dev, "Registering device failed "
423 free_sja1000dev(dev);
424 goto failure_cleanup;
429 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
430 "registered as %s\n", i + 1, priv->reg_base,
431 dev->irq, dev->name);
433 dev_err(&pdev->dev, "Channel #%d not detected\n",
435 free_sja1000dev(dev);
439 if (!card->channels) {
441 goto failure_cleanup;
445 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
446 * Local_2 interrupts from the SJA1000 chips
448 val = ioread32(card->conf_addr + PLX_INTCSR);
449 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
450 iowrite32(val, card->conf_addr + PLX_INTCSR);
455 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
457 plx_pci_del_card(pdev);
462 static struct pci_driver plx_pci_driver = {
464 .id_table = plx_pci_tbl,
465 .probe = plx_pci_add_card,
466 .remove = plx_pci_del_card,
469 static int __init plx_pci_init(void)
471 return pci_register_driver(&plx_pci_driver);
474 static void __exit plx_pci_exit(void)
476 pci_unregister_driver(&plx_pci_driver);
479 module_init(plx_pci_init);
480 module_exit(plx_pci_exit);