3 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
5 * MCP2510 support and bug fixes by Christian Pellegrin
6 * <chripell@evolware.org>
8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
9 * Written under contract by:
10 * Chris Elston, Katalix Systems, Ltd.
12 * Based on Microchip MCP251x CAN controller driver written by
13 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 * Based on CAN bus driver for the CCAN controller written by
16 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
17 * - Simon Kallweit, intefo AG
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the version 2 of the GNU General Public License
22 * as published by the Free Software Foundation
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35 * Your platform definition file should specify something like:
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * .board_specific_setup = &mcp251x_setup,
40 * .model = CAN_MCP251X_MCP2510,
41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
45 * static struct spi_board_info spi_board_info[] = {
47 * .modalias = "mcp251x",
48 * .platform_data = &mcp251x_info,
50 * .max_speed_hz = 2*1000*1000,
55 * Please see mcp251x.h for a description of the fields in
56 * struct mcp251x_platform_data.
60 #include <linux/device.h>
61 #include <linux/kernel.h>
62 #include <linux/module.h>
63 #include <linux/interrupt.h>
64 #include <linux/platform_device.h>
65 #include <linux/netdevice.h>
66 #include <linux/can.h>
67 #include <linux/spi/spi.h>
68 #include <linux/can/dev.h>
69 #include <linux/can/core.h>
70 #include <linux/if_arp.h>
71 #include <linux/dma-mapping.h>
72 #include <linux/delay.h>
73 #include <linux/completion.h>
74 #include <linux/freezer.h>
75 #include <linux/uaccess.h>
77 #include <linux/can/mcp251x.h>
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
87 /* MPC251x registers */
90 # define CANCTRL_REQOP_MASK 0xe0
91 # define CANCTRL_REQOP_CONF 0x80
92 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
93 # define CANCTRL_REQOP_LOOPBACK 0x40
94 # define CANCTRL_REQOP_SLEEP 0x20
95 # define CANCTRL_REQOP_NORMAL 0x00
96 # define CANCTRL_OSM 0x08
97 # define CANCTRL_ABAT 0x10
102 # define CNF2_BTLMODE 0x80
104 # define CNF3_SOF 0x08
105 # define CNF3_WAKFIL 0x04
106 # define CNF3_PHSEG2_MASK 0x07
108 # define CANINTE_MERRE 0x80
109 # define CANINTE_WAKIE 0x40
110 # define CANINTE_ERRIE 0x20
111 # define CANINTE_TX2IE 0x10
112 # define CANINTE_TX1IE 0x08
113 # define CANINTE_TX0IE 0x04
114 # define CANINTE_RX1IE 0x02
115 # define CANINTE_RX0IE 0x01
117 # define CANINTF_MERRF 0x80
118 # define CANINTF_WAKIF 0x40
119 # define CANINTF_ERRIF 0x20
120 # define CANINTF_TX2IF 0x10
121 # define CANINTF_TX1IF 0x08
122 # define CANINTF_TX0IF 0x04
123 # define CANINTF_RX1IF 0x02
124 # define CANINTF_RX0IF 0x01
126 # define EFLG_EWARN 0x01
127 # define EFLG_RXWAR 0x02
128 # define EFLG_TXWAR 0x04
129 # define EFLG_RXEP 0x08
130 # define EFLG_TXEP 0x10
131 # define EFLG_TXBO 0x20
132 # define EFLG_RX0OVR 0x40
133 # define EFLG_RX1OVR 0x80
134 #define TXBCTRL(n) ((n * 0x10) + 0x30)
135 # define TXBCTRL_ABTF 0x40
136 # define TXBCTRL_MLOA 0x20
137 # define TXBCTRL_TXERR 0x10
138 # define TXBCTRL_TXREQ 0x08
139 #define RXBCTRL(n) ((n * 0x10) + 0x60)
140 # define RXBCTRL_BUKT 0x04
141 # define RXBCTRL_RXM0 0x20
142 # define RXBCTRL_RXM1 0x40
144 /* Buffer size required for the largest SPI transfer (i.e., reading a
146 #define CAN_FRAME_MAX_DATA_LEN 8
147 #define SPI_TRANSFER_BUF_LEN (2*(6 + CAN_FRAME_MAX_DATA_LEN))
148 #define CAN_FRAME_MAX_BITS 128
150 #define DEVICE_NAME "mcp251x"
152 static int enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
153 module_param(enable_dma, int, S_IRUGO);
154 MODULE_PARM_DESC(enable_dma, "Enable SPI DMA. Default: 0 (Off)");
156 static struct can_bittiming_const mcp251x_bittiming_const = {
167 struct mcp251x_priv {
169 struct net_device *net;
170 struct spi_device *spi;
172 struct mutex spi_lock; /* SPI buffer lock */
175 dma_addr_t spi_tx_dma;
176 dma_addr_t spi_rx_dma;
178 struct sk_buff *tx_skb;
179 struct workqueue_struct *wq;
180 struct work_struct tx_work;
181 struct work_struct irq_work;
182 struct completion awake;
186 #define AFTER_SUSPEND_UP 1
187 #define AFTER_SUSPEND_DOWN 2
188 #define AFTER_SUSPEND_POWER 4
192 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
194 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
195 struct spi_transfer t = {
196 .tx_buf = priv->spi_tx_buf,
197 .rx_buf = priv->spi_rx_buf,
201 struct spi_message m;
205 mutex_lock(&priv->spi_lock);
207 priv->spi_tx_buf[0] = INSTRUCTION_READ;
208 priv->spi_tx_buf[1] = reg;
210 spi_message_init(&m);
213 t.tx_dma = priv->spi_tx_dma;
214 t.rx_dma = priv->spi_rx_dma;
218 spi_message_add_tail(&t, &m);
220 ret = spi_sync(spi, &m);
222 dev_dbg(&spi->dev, "%s: failed: ret = %d\n", __func__, ret);
224 val = priv->spi_rx_buf[2];
226 mutex_unlock(&priv->spi_lock);
228 dev_dbg(&spi->dev, "%s: read %02x = %02x\n", __func__, reg, val);
232 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
234 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
235 struct spi_transfer t = {
236 .tx_buf = priv->spi_tx_buf,
237 .rx_buf = priv->spi_rx_buf,
241 struct spi_message m;
244 mutex_lock(&priv->spi_lock);
246 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
247 priv->spi_tx_buf[1] = reg;
248 priv->spi_tx_buf[2] = val;
250 spi_message_init(&m);
253 t.tx_dma = priv->spi_tx_dma;
254 t.rx_dma = priv->spi_rx_dma;
258 spi_message_add_tail(&t, &m);
260 ret = spi_sync(spi, &m);
262 mutex_unlock(&priv->spi_lock);
265 dev_dbg(&spi->dev, "%s: failed\n", __func__);
268 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
269 u8 mask, uint8_t val)
271 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
272 struct spi_transfer t = {
273 .tx_buf = priv->spi_tx_buf,
274 .rx_buf = priv->spi_rx_buf,
278 struct spi_message m;
281 mutex_lock(&priv->spi_lock);
283 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
284 priv->spi_tx_buf[1] = reg;
285 priv->spi_tx_buf[2] = mask;
286 priv->spi_tx_buf[3] = val;
288 spi_message_init(&m);
291 t.tx_dma = priv->spi_tx_dma;
292 t.rx_dma = priv->spi_rx_dma;
296 spi_message_add_tail(&t, &m);
298 ret = spi_sync(spi, &m);
300 mutex_unlock(&priv->spi_lock);
303 dev_dbg(&spi->dev, "%s: failed\n", __func__);
306 static int mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
309 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
310 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
311 u32 sid, eid, exide, rtr;
313 dev_dbg(&spi->dev, "%s\n", __func__);
315 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
317 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
319 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
320 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
321 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
323 if (pdata->model == CAN_MCP251X_MCP2510) {
326 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 1, sid >> 3);
327 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 2,
328 ((sid & 7) << 5) | (exide << 3) |
330 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 3,
332 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 4, eid & 0xff);
333 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 5,
334 (rtr << 6) | frame->can_dlc);
336 for (i = 0; i < frame->can_dlc ; i++) {
337 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + 6 + i,
341 struct spi_transfer t = {
342 .tx_buf = priv->spi_tx_buf,
343 .rx_buf = priv->spi_rx_buf,
345 .len = 6 + CAN_FRAME_MAX_DATA_LEN,
347 struct spi_message m;
349 u8 *tx_buf = priv->spi_tx_buf;
351 mutex_lock(&priv->spi_lock);
353 tx_buf[0] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
354 tx_buf[1] = sid >> 3;
355 tx_buf[2] = ((sid & 7) << 5) | (exide << 3) |
357 tx_buf[3] = (eid >> 8) & 0xff;
358 tx_buf[4] = eid & 0xff;
359 tx_buf[5] = (rtr << 6) | frame->can_dlc;
361 memcpy(tx_buf + 6, frame->data, frame->can_dlc);
363 spi_message_init(&m);
366 t.tx_dma = priv->spi_tx_dma;
367 t.rx_dma = priv->spi_rx_dma;
371 spi_message_add_tail(&t, &m);
373 ret = spi_sync(spi, &m);
375 mutex_unlock(&priv->spi_lock);
378 dev_dbg(&spi->dev, "%s: failed: ret = %d\n", __func__,
383 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
387 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
389 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
390 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
392 struct can_frame *frame;
394 dev_dbg(&spi->dev, "%s\n", __func__);
396 skb = dev_alloc_skb(sizeof(struct can_frame));
398 dev_dbg(&spi->dev, "%s: out of memory for Rx'd frame\n",
400 priv->net->stats.rx_dropped++;
403 skb->dev = priv->net;
404 frame = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
406 if (pdata->model == CAN_MCP251X_MCP2510) {
410 rx_buf[1] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + 1);
411 rx_buf[2] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + 2);
412 rx_buf[3] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + 3);
413 rx_buf[4] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + 4);
414 rx_buf[5] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + 5);
416 if ((rx_buf[2] >> 3) & 0x1) {
417 /* Extended ID format */
418 frame->can_id = CAN_EFF_FLAG;
419 frame->can_id |= ((rx_buf[2] & 3) << 16) |
420 (rx_buf[3] << 8) | rx_buf[4] |
421 (((rx_buf[1] << 3) | (rx_buf[2] >> 5)) << 18);
423 /* Standard ID format */
424 frame->can_id = (rx_buf[1] << 3) | (rx_buf[2] >> 5);
427 if ((rx_buf[5] >> 6) & 0x1) {
428 /* Remote transmission request */
429 frame->can_id |= CAN_RTR_FLAG;
433 frame->can_dlc = rx_buf[5] & 0x0f;
434 if (frame->can_dlc > 8) {
435 dev_warn(&spi->dev, "invalid frame recevied\n");
436 priv->net->stats.rx_errors++;
441 for (i = 0; i < frame->can_dlc; i++) {
442 frame->data[i] = mcp251x_read_reg(spi,
447 struct spi_transfer t = {
448 .tx_buf = priv->spi_tx_buf,
449 .rx_buf = priv->spi_rx_buf,
451 .len = 14, /* RX buffer: RXBnCTRL to RXBnD7 */
453 struct spi_message m;
455 u8 *tx_buf = priv->spi_tx_buf;
456 u8 *rx_buf = priv->spi_rx_buf;
458 mutex_lock(&priv->spi_lock);
460 tx_buf[0] = INSTRUCTION_READ_RXB(buf_idx);
462 spi_message_init(&m);
465 t.tx_dma = priv->spi_tx_dma;
466 t.rx_dma = priv->spi_rx_dma;
470 spi_message_add_tail(&t, &m);
472 ret = spi_sync(spi, &m);
475 dev_dbg(&spi->dev, "%s: failed: ret = %d\n",
477 priv->net->stats.rx_errors++;
478 mutex_unlock(&priv->spi_lock);
482 if ((rx_buf[2] >> 3) & 0x1) {
483 /* Extended ID format */
484 frame->can_id = CAN_EFF_FLAG;
485 frame->can_id |= ((rx_buf[2] & 3) << 16) |
486 (rx_buf[3] << 8) | rx_buf[4] |
487 (((rx_buf[1] << 3) | (rx_buf[2] >> 5)) << 18);
489 /* Standard ID format */
490 frame->can_id = (rx_buf[1] << 3) | (rx_buf[2] >> 5);
493 if ((rx_buf[5] >> 6) & 0x1) {
494 /* Remote transmission request */
495 frame->can_id |= CAN_RTR_FLAG;
499 frame->can_dlc = rx_buf[5] & 0x0f;
500 if (frame->can_dlc > 8) {
501 dev_warn(&spi->dev, "invalid frame recevied\n");
502 priv->net->stats.rx_errors++;
504 mutex_unlock(&priv->spi_lock);
508 memcpy(frame->data, rx_buf + 6, CAN_FRAME_MAX_DATA_LEN);
510 mutex_unlock(&priv->spi_lock);
513 priv->net->stats.rx_packets++;
514 priv->net->stats.rx_bytes += frame->can_dlc;
516 skb->protocol = __constant_htons(ETH_P_CAN);
517 skb->pkt_type = PACKET_BROADCAST;
518 skb->ip_summed = CHECKSUM_UNNECESSARY;
522 static void mcp251x_hw_sleep(struct spi_device *spi)
524 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
527 static void mcp251x_hw_wakeup(struct spi_device *spi)
529 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
533 /* Can only wake up by generating a wake-up interrupt. */
534 mcp251x_write_bits(spi, CANINTE, CANINTE_WAKIE, CANINTE_WAKIE);
535 mcp251x_write_bits(spi, CANINTF, CANINTF_WAKIF, CANINTF_WAKIF);
537 /* Wait until the device is awake */
538 wait_for_completion(&priv->awake);
541 static int mcp251x_hard_start_xmit(struct sk_buff *skb, struct net_device *net)
543 struct mcp251x_priv *priv = netdev_priv(net);
544 struct spi_device *spi = priv->spi;
546 dev_dbg(&spi->dev, "%s\n", __func__);
549 dev_warn(&spi->dev, "hard_xmit called with not null tx_skb\n");
550 return NETDEV_TX_BUSY;
553 if (skb->len != sizeof(struct can_frame)) {
554 dev_dbg(&spi->dev, "dropping packet - bad length\n");
556 net->stats.tx_dropped++;
560 netif_stop_queue(net);
562 net->trans_start = jiffies;
563 queue_work(priv->wq, &priv->tx_work);
568 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
570 struct mcp251x_priv *priv = netdev_priv(net);
571 struct spi_device *spi = priv->spi;
573 dev_dbg(&spi->dev, "%s (unimplemented)\n", __func__);
583 static void mcp251x_set_normal_mode(struct spi_device *spi)
585 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
587 /* Enable interrupts */
588 mcp251x_write_reg(spi, CANINTE,
589 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
590 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
592 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
593 /* Put device into loopback mode */
594 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
596 /* Put device into normal mode */
597 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
599 /* Wait for the device to enter normal mode */
600 while (mcp251x_read_reg(spi, CANSTAT) & 0xE0)
605 static void mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
606 struct spi_device *spi)
610 /* Set initial baudrate */
611 ret = can_set_bittiming(net);
613 dev_err(&spi->dev, "unable to set initial baudrate!\n");
615 /* Enable RX0->RX1 buffer roll over and disable filters */
616 mcp251x_write_bits(spi, RXBCTRL(0),
617 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1,
618 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
619 mcp251x_write_bits(spi, RXBCTRL(1),
620 RXBCTRL_RXM0 | RXBCTRL_RXM1,
621 RXBCTRL_RXM0 | RXBCTRL_RXM1);
623 dev_dbg(&spi->dev, "%s RXBCTL 0 and 1: %02x %02x\n", __func__,
624 mcp251x_read_reg(spi, RXBCTRL(0)),
625 mcp251x_read_reg(spi, RXBCTRL(1)));
628 static void mcp251x_hw_reset(struct spi_device *spi)
630 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
633 mutex_lock(&priv->spi_lock);
635 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
637 ret = spi_write(spi, priv->spi_tx_buf, 1);
639 mutex_unlock(&priv->spi_lock);
642 dev_dbg(&spi->dev, "%s: failed: ret = %d\n", __func__, ret);
645 static int mcp251x_open(struct net_device *net)
647 struct mcp251x_priv *priv = netdev_priv(net);
648 struct spi_device *spi = priv->spi;
649 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
651 dev_dbg(&spi->dev, "%s\n", __func__);
653 if (pdata->transceiver_enable)
654 pdata->transceiver_enable(1);
656 priv->force_quit = 0;
658 enable_irq(spi->irq);
659 mcp251x_hw_wakeup(spi);
660 mcp251x_hw_reset(spi);
661 mcp251x_setup(net, priv, spi);
662 mcp251x_set_normal_mode(spi);
663 netif_wake_queue(net);
668 static int mcp251x_stop(struct net_device *net)
670 struct mcp251x_priv *priv = netdev_priv(net);
671 struct spi_device *spi = priv->spi;
672 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
674 dev_dbg(&spi->dev, "%s\n", __func__);
676 /* Disable and clear pending interrupts */
677 mcp251x_write_reg(spi, CANINTE, 0x00);
678 mcp251x_write_reg(spi, CANINTF, 0x00);
680 priv->force_quit = 1;
681 disable_irq(spi->irq);
682 flush_workqueue(priv->wq);
684 mcp251x_write_reg(spi, TXBCTRL(0), 0);
686 net->stats.tx_errors++;
687 dev_kfree_skb(priv->tx_skb);
691 mcp251x_hw_sleep(spi);
693 if (pdata->transceiver_enable)
694 pdata->transceiver_enable(0);
699 static int mcp251x_do_set_bittiming(struct net_device *net)
701 struct mcp251x_priv *priv = netdev_priv(net);
702 struct can_bittiming *bt = &priv->can.bittiming;
703 struct spi_device *spi = priv->spi;
706 dev_dbg(&spi->dev, "%s: BRP = %d, PropSeg = %d, PS1 = %d,"
707 " PS2 = %d, SJW = %d\n", __func__, bt->brp,
708 bt->prop_seg, bt->phase_seg1, bt->phase_seg2,
711 /* Store original mode and set mode to config */
712 state = mcp251x_read_reg(spi, CANCTRL);
713 state = mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
714 mcp251x_write_bits(spi, CANCTRL, CANCTRL_REQOP_MASK,
717 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << 6) | (bt->brp - 1));
718 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
719 ((bt->phase_seg1 - 1) << 3) |
721 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
722 (bt->phase_seg2 - 1));
724 /* Restore original state */
725 mcp251x_write_bits(spi, CANCTRL, CANCTRL_REQOP_MASK, state);
730 static int mcp251x_do_get_state(struct net_device *net, enum can_state *state)
732 struct mcp251x_priv *priv = netdev_priv(net);
733 struct spi_device *spi = priv->spi;
736 eflag = mcp251x_read_reg(spi, EFLG);
738 if (eflag & EFLG_TXBO)
739 *state = CAN_STATE_BUS_OFF;
740 else if (eflag & (EFLG_RXEP | EFLG_TXEP))
741 *state = CAN_STATE_BUS_PASSIVE;
742 else if (eflag & EFLG_EWARN)
743 *state = CAN_STATE_BUS_WARNING;
745 *state = CAN_STATE_ACTIVE;
750 static void mcp251x_tx_work_handler(struct work_struct *ws)
752 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
754 struct spi_device *spi = priv->spi;
755 struct can_frame *frame = (struct can_frame *)priv->tx_skb->data;
757 dev_dbg(&spi->dev, "%s\n", __func__);
759 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
760 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
762 mcp251x_hw_tx(spi, frame, 0);
765 static void mcp251x_irq_work_handler(struct work_struct *ws)
767 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
769 struct spi_device *spi = priv->spi;
770 struct net_device *net = priv->net;
771 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
774 /* the next limitation is needed so we give some time to the
779 if (priv->after_suspend) {
780 /* Wait whilst the device wakes up */
781 udelay(200 * (128 * USEC_PER_SEC /
782 pdata->oscillator_frequency));
783 mcp251x_hw_reset(spi);
784 mcp251x_setup(net, priv, spi);
785 if (priv->after_suspend & AFTER_SUSPEND_UP) {
786 /* clear since we lost tx buffer */
787 netif_device_attach(net);
789 net->stats.tx_errors++;
790 dev_kfree_skb(priv->tx_skb);
792 netif_wake_queue(net);
794 mcp251x_set_normal_mode(spi);
796 mcp251x_hw_sleep(spi);
797 priv->after_suspend = 0;
802 while (!priv->force_quit && !freezing(current) && loops < MAX_LOOPS) {
803 if (priv->restart_tx) {
804 priv->restart_tx = 0;
806 "timeout in txing a packet, restarting\n");
807 mcp251x_write_reg(spi, TXBCTRL(0), 0);
809 net->stats.tx_errors++;
810 dev_kfree_skb(priv->tx_skb);
813 netif_wake_queue(net);
817 /* Wait whilst the device wakes up */
818 udelay(200 * (128 * USEC_PER_SEC /
819 pdata->oscillator_frequency));
823 intf = mcp251x_read_reg(spi, CANINTF);
826 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
828 dev_dbg(&spi->dev, "interrupt:%s%s%s%s%s%s%s%s\n",
829 (intf & CANINTF_MERRF) ? " MERR" : "",
830 (intf & CANINTF_WAKIF) ? " WAK" : "",
831 (intf & CANINTF_ERRIF) ? " ERR" : "",
832 (intf & CANINTF_TX2IF) ? " TX2" : "",
833 (intf & CANINTF_TX1IF) ? " TX1" : "",
834 (intf & CANINTF_TX0IF) ? " TX0" : "",
835 (intf & CANINTF_RX1IF) ? " RX1" : "",
836 (intf & CANINTF_RX0IF) ? " RX0" : "");
838 if (intf & CANINTF_WAKIF)
839 complete(&priv->awake);
841 if (intf & CANINTF_MERRF) {
842 /* if there are no pending Tx buffers, restart queue */
843 txbnctrl = mcp251x_read_reg(spi, TXBCTRL(0));
844 if (!(txbnctrl & TXBCTRL_TXREQ)) {
846 net->stats.tx_errors++;
847 dev_kfree_skb(priv->tx_skb);
850 netif_wake_queue(net);
854 if (intf & CANINTF_ERRIF) {
856 struct can_frame *frame = NULL;
857 u8 eflag = mcp251x_read_reg(spi, EFLG);
859 dev_dbg(&spi->dev, "EFLG = 0x%02x\n", eflag);
861 /* Create error frame */
862 skb = dev_alloc_skb(sizeof(struct can_frame));
864 frame = (struct can_frame *)
865 skb_put(skb, sizeof(struct can_frame));
866 frame->can_id = CAN_ERR_FLAG;
867 frame->can_dlc = CAN_ERR_DLC;
870 skb->protocol = __constant_htons(ETH_P_CAN);
871 skb->pkt_type = PACKET_BROADCAST;
872 skb->ip_summed = CHECKSUM_UNNECESSARY;
874 /* Set error frame flags based on bus state */
875 if (eflag & EFLG_TXBO) {
876 frame->can_id |= CAN_ERR_BUSOFF;
877 } else if (eflag & EFLG_TXEP) {
878 frame->can_id |= CAN_ERR_CRTL;
880 CAN_ERR_CRTL_TX_PASSIVE;
881 } else if (eflag & EFLG_RXEP) {
882 frame->can_id |= CAN_ERR_CRTL;
884 CAN_ERR_CRTL_RX_PASSIVE;
885 } else if (eflag & EFLG_TXWAR) {
886 frame->can_id |= CAN_ERR_CRTL;
888 CAN_ERR_CRTL_TX_WARNING;
889 } else if (eflag & EFLG_RXWAR) {
890 frame->can_id |= CAN_ERR_CRTL;
892 CAN_ERR_CRTL_RX_WARNING;
896 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
897 if (eflag & EFLG_RX0OVR)
898 net->stats.rx_over_errors++;
899 if (eflag & EFLG_RX1OVR)
900 net->stats.rx_over_errors++;
902 frame->can_id |= CAN_ERR_CRTL;
904 CAN_ERR_CRTL_RX_OVERFLOW;
907 mcp251x_write_reg(spi, EFLG, 0x00);
913 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
915 net->stats.tx_packets++;
916 net->stats.tx_bytes +=
917 ((struct can_frame *)
918 (priv->tx_skb->data))->can_dlc;
919 dev_kfree_skb(priv->tx_skb);
922 netif_wake_queue(net);
925 if (intf & CANINTF_RX0IF)
926 mcp251x_hw_rx(spi, 0);
928 if (intf & CANINTF_RX1IF)
929 mcp251x_hw_rx(spi, 1);
934 mcp251x_read_reg(spi, CANSTAT);
936 dev_dbg(&spi->dev, "interrupt ended\n");
939 static irqreturn_t mcp251x_can_isr(int irq, void *dev_id)
941 struct net_device *net = (struct net_device *)dev_id;
942 struct mcp251x_priv *priv = netdev_priv(net);
944 dev_dbg(&priv->spi->dev, "%s: irq\n", __func__);
945 /* Schedule bottom half */
946 if (!work_pending(&priv->irq_work))
947 queue_work(priv->wq, &priv->irq_work);
952 static void mcp251x_tx_timeout(struct net_device *net)
954 struct mcp251x_priv *priv = netdev_priv(net);
956 priv->restart_tx = 1;
957 queue_work(priv->wq, &priv->irq_work);
960 static struct net_device *alloc_mcp251x_netdev(int sizeof_priv)
962 struct net_device *net;
963 struct mcp251x_priv *priv;
965 net = alloc_candev(sizeof_priv);
969 priv = netdev_priv(net);
971 net->open = mcp251x_open;
972 net->stop = mcp251x_stop;
973 net->hard_start_xmit = mcp251x_hard_start_xmit;
974 net->tx_timeout = mcp251x_tx_timeout;
975 net->watchdog_timeo = HZ;
977 priv->can.bittiming_const = &mcp251x_bittiming_const;
978 priv->can.do_set_bittiming = mcp251x_do_set_bittiming;
979 priv->can.do_get_state = mcp251x_do_get_state;
980 priv->can.do_set_mode = mcp251x_do_set_mode;
987 static int __devinit mcp251x_can_probe(struct spi_device *spi)
989 struct net_device *net;
990 struct mcp251x_priv *priv;
991 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
995 /* Platform data is required for osc freq */
999 /* Allocate can/net device */
1000 net = alloc_mcp251x_netdev(sizeof(struct mcp251x_priv));
1006 priv = netdev_priv(net);
1007 dev_set_drvdata(&spi->dev, priv);
1010 mutex_init(&priv->spi_lock);
1012 priv->can.bittiming.clock = pdata->oscillator_frequency / 2;
1014 /* If requested, allocate DMA buffers */
1016 spi->dev.coherent_dma_mask = DMA_32BIT_MASK;
1018 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1019 that much and share it between Tx and Rx DMA buffers. */
1020 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1021 PAGE_SIZE, &priv->spi_tx_dma, GFP_DMA);
1023 if (priv->spi_tx_buf) {
1024 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
1026 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1029 /* Fall back to non-DMA */
1034 /* Allocate non-DMA buffers */
1036 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1037 if (!priv->spi_tx_buf) {
1041 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1042 if (!priv->spi_tx_buf) {
1048 if (pdata->power_enable)
1049 pdata->power_enable(1);
1051 /* Call out to platform specific setup */
1052 if (pdata->board_specific_setup)
1053 pdata->board_specific_setup(spi);
1055 SET_NETDEV_DEV(net, &spi->dev);
1057 priv->wq = create_freezeable_workqueue("mcp251x_wq");
1059 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1060 INIT_WORK(&priv->irq_work, mcp251x_irq_work_handler);
1062 init_completion(&priv->awake);
1064 /* Configure the SPI bus */
1065 spi->mode = SPI_MODE_0;
1066 spi->bits_per_word = 8;
1070 if (request_irq(spi->irq, mcp251x_can_isr,
1071 IRQF_TRIGGER_FALLING, DEVICE_NAME, net) < 0) {
1072 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1075 disable_irq(spi->irq);
1077 mcp251x_hw_reset(spi);
1078 mcp251x_hw_sleep(spi);
1080 ret = register_netdev(net);
1082 dev_info(&spi->dev, "probed\n");
1086 free_irq(spi->irq, net);
1089 kfree(priv->spi_rx_buf);
1092 kfree(priv->spi_tx_buf);
1096 dma_free_coherent(&spi->dev, PAGE_SIZE,
1097 priv->spi_tx_buf, priv->spi_tx_dma);
1100 dev_err(&spi->dev, "probe failed\n");
1105 static int __devexit mcp251x_can_remove(struct spi_device *spi)
1107 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1108 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1109 struct net_device *net = priv->net;
1111 free_irq(spi->irq, net);
1112 priv->force_quit = 1;
1113 flush_workqueue(priv->wq);
1114 destroy_workqueue(priv->wq);
1117 dma_free_coherent(&spi->dev, PAGE_SIZE,
1118 priv->spi_tx_buf, priv->spi_tx_dma);
1120 kfree(priv->spi_tx_buf);
1121 kfree(priv->spi_rx_buf);
1124 unregister_netdev(net);
1127 if (pdata->power_enable)
1128 pdata->power_enable(0);
1134 static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1136 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1137 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1138 struct net_device *net = priv->net;
1140 if (netif_running(net)) {
1141 netif_device_detach(net);
1143 mcp251x_hw_sleep(spi);
1144 if (pdata->transceiver_enable)
1145 pdata->transceiver_enable(0);
1146 priv->after_suspend = AFTER_SUSPEND_UP;
1148 priv->after_suspend = AFTER_SUSPEND_DOWN;
1150 if (pdata->power_enable) {
1151 pdata->power_enable(0);
1152 priv->after_suspend |= AFTER_SUSPEND_POWER;
1158 static int mcp251x_can_resume(struct spi_device *spi)
1160 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1161 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1162 struct net_device *net = priv->net;
1164 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1165 pdata->power_enable(1);
1166 queue_work(priv->wq, &priv->irq_work);
1168 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1169 if (pdata->transceiver_enable)
1170 pdata->transceiver_enable(1);
1171 mcp251x_hw_wakeup(spi);
1173 netif_device_attach(net);
1179 #define mcp251x_can_suspend NULL
1180 #define mcp251x_can_resume NULL
1183 static struct spi_driver mcp251x_can_driver = {
1185 .name = DEVICE_NAME,
1186 .bus = &spi_bus_type,
1187 .owner = THIS_MODULE,
1190 .probe = mcp251x_can_probe,
1191 .remove = __devexit_p(mcp251x_can_remove),
1192 .suspend = mcp251x_can_suspend,
1193 .resume = mcp251x_can_resume,
1196 static int __init mcp251x_can_init(void)
1198 return spi_register_driver(&mcp251x_can_driver);
1201 static void __exit mcp251x_can_exit(void)
1203 spi_unregister_driver(&mcp251x_can_driver);
1206 module_init(mcp251x_can_init);
1207 module_exit(mcp251x_can_exit);
1209 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1210 "Christian Pellegrin <chripell@evolware.org>");
1211 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1212 MODULE_LICENSE("GPL v2");