2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
4 * Derived from the ems_pci.c driver:
5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the version 2 of the GNU General Public License
12 * as published by the Free Software Foundation
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/netdevice.h>
28 #include <linux/delay.h>
29 #include <linux/pci.h>
30 #include <socketcan/can.h>
31 #include <socketcan/can/dev.h>
32 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 16)
40 #define DRV_NAME "sja1000_plx_pci"
42 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
43 MODULE_DESCRIPTION("Socket-CAN driver for the PLX90xx PCI-bridge cards with "
45 MODULE_SUPPORTED_DEVICE("Marathon CAN-bus-PCI, "
46 "Adlink PCI-7841/cPCI-7841, "
47 "Adlink PCI-7841/cPCI-7841 SE, "
48 "TEWS TECHNOLOGIES TPMC810");
49 MODULE_LICENSE("GPL v2");
51 #define PLX_PCI_MAX_CHAN 2
54 int channels; /* detected channels count */
55 struct net_device *net_dev[PLX_PCI_MAX_CHAN];
56 void __iomem *conf_addr;
59 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
62 * the PLX90xx registers
64 #define PLX_INTCSR 0x4c /* Interrup Control/Status */
65 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
66 * Serial EEPROM, and Initialization
70 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
71 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
72 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
73 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
76 * The board configuration is probably following:
77 * RX1 is connected to ground.
78 * TX1 is not connected.
79 * CLKO is not connected.
80 * Setting the OCR register to 0xDA is a good idea.
81 * This means normal output mode, push-pull and the correct polarity.
83 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
86 * In the CDR register, you should set CBP to 1.
87 * You will probably also want to set the clock divider value to 7
88 * (meaning direct oscillator output) because the second SJA1000 chip
89 * is driven by the first one CLKOUT output.
91 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
93 #define ADLINK_PCI_VENDOR_ID 0x144A
94 #define ADLINK_PCI_DEVICE_ID 0x7841
96 #define MARATHON_PCI_DEVICE_ID 0x2715
98 #define TEWS_PCI_VENDOR_ID 0x1498
99 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
101 static void plx_pci_reset_common(struct pci_dev *pdev);
102 static void plx_pci_reset_marathon(struct pci_dev *pdev);
104 struct plx_pci_channel_map {
107 u32 size; /* 0x00 - auto, e.g. length of entire bar */
110 struct plx_pci_card_info {
114 u8 ocr; /* output control register */
115 u8 cdr; /* clock divider register */
117 /* Parameters for mapping local configuration space */
118 struct plx_pci_channel_map conf_map;
120 /* Parameters for mapping the SJA1000 chips */
121 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
123 /* Pointer to device-dependent reset function */
124 void (*reset_func)(struct pci_dev *pdev);
127 static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
128 "Marathon CAN-bus-PCI", 2,
129 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
130 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
131 &plx_pci_reset_marathon
132 /* based on PLX9052 */
135 static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
136 "Adlink PCI-7841/cPCI-7841", 2,
137 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
138 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
139 &plx_pci_reset_common
140 /* based on PLX9052 */
143 static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
144 "Adlink PCI-7841/cPCI-7841 SE", 2,
145 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
146 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
147 &plx_pci_reset_common
148 /* based on PLX9052 */
151 static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
152 "TEWS TECHNOLOGIES TPMC810", 2,
153 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
154 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
155 &plx_pci_reset_common
156 /* based on PLX9030 */
159 static struct pci_device_id plx_pci_tbl[] = {
161 /* Marathon CAN-bus-PCI card */
162 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
163 PCI_ANY_ID, PCI_ANY_ID,
165 (kernel_ulong_t)&plx_pci_card_info_marathon
168 /* Adlink PCI-7841/cPCI-7841 */
169 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
170 PCI_ANY_ID, PCI_ANY_ID,
171 PCI_CLASS_NETWORK_OTHER << 8, ~0,
172 (kernel_ulong_t)&plx_pci_card_info_adlink
175 /* Adlink PCI-7841/cPCI-7841 SE */
176 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
177 PCI_ANY_ID, PCI_ANY_ID,
178 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
179 (kernel_ulong_t)&plx_pci_card_info_adlink_se
182 /* TEWS TECHNOLOGIES TPMC810 card */
183 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
184 PCI_ANY_ID, PCI_ANY_ID,
186 (kernel_ulong_t)&plx_pci_card_info_tews
190 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
192 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
194 return ioread8(priv->reg_base + port);
197 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
199 iowrite8(val, priv->reg_base + port);
203 * Check if a CAN controller is present at the specified location
204 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
205 * Also check states of some registers in reset mode.
207 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
212 * Check registers after hardware reset (the Basic mode)
213 * See states on p. 10 of the Datasheet.
215 if ((priv->read_reg(priv, REG_MOD) & 0xa1) == 0x21 &&
216 (priv->read_reg(priv, REG_SR) == 0x0c) &&
217 (priv->read_reg(priv, REG_IR) == 0xe0))
220 /* Bring the SJA1000 into the PeliCAN mode*/
221 priv->write_reg(priv, REG_CDR, CDR_PELICAN);
224 * Check registers after reset in the PeliCAN mode.
225 * See states on p. 23 of the Datasheet.
227 if ((priv->read_reg(priv, REG_MOD) & 0xf1) == 0x01 &&
228 (priv->read_reg(priv, REG_SR) & 0x37) == 0x34 &&
229 (priv->read_reg(priv, REG_IR) & 0xfb) == 0x00)
236 * The PLX90xx software reset
237 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
238 * For most cards it's enough for reset the SJA1000 chips.
240 static void plx_pci_reset_common(struct pci_dev *pdev)
242 struct plx_pci_card *card = pci_get_drvdata(pdev);
245 cntrl = ioread32(card->conf_addr + PLX_CNTRL);
246 cntrl |= PLX_PCI_RESET;
247 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
249 cntrl ^= PLX_PCI_RESET;
250 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
253 /* Special reset function for Marathon card */
254 static void plx_pci_reset_marathon(struct pci_dev *pdev)
256 void __iomem *reset_addr;
258 int reset_bar[2] = {3, 5};
260 plx_pci_reset_common(pdev);
262 for (i = 0; i < 2; i++) {
263 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
265 dev_err(&pdev->dev, "Failed to remap reset "
266 "space %d (BAR%d)\n", i, reset_bar[i]);
268 /* reset the SJA1000 chip */
269 iowrite8(0x1, reset_addr);
271 pci_iounmap(pdev, reset_addr);
276 static void plx_pci_del_card(struct pci_dev *pdev)
278 struct plx_pci_card *card = pci_get_drvdata(pdev);
279 struct net_device *dev;
280 struct sja1000_priv *priv;
283 for (i = 0; i < card->channels; i++) {
284 dev = card->net_dev[i];
288 dev_info(&pdev->dev, "Removing %s\n", dev->name);
289 unregister_sja1000dev(dev);
290 priv = netdev_priv(dev);
292 pci_iounmap(pdev, priv->reg_base);
293 free_sja1000dev(dev);
296 plx_pci_reset_common(pdev);
299 * Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
302 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
305 pci_iounmap(pdev, card->conf_addr);
309 pci_disable_device(pdev);
310 pci_set_drvdata(pdev, NULL);
314 * Probe the PLX90xx based device for the SJA1000 chips and register each
315 * available CAN channel to SJA1000 Socket-CAN subsystem.
317 static int __devinit plx_pci_add_card(struct pci_dev *pdev,
318 const struct pci_device_id *ent)
320 struct sja1000_priv *priv;
321 struct net_device *dev;
322 struct plx_pci_card *card;
323 struct plx_pci_card_info *ci;
328 ci = (struct plx_pci_card_info *)ent->driver_data;
330 if (pci_enable_device(pdev) < 0) {
331 dev_err(&pdev->dev, "Failed to enable PCI device\n");
335 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
336 ci->name, PCI_SLOT(pdev->devfn));
338 /* Allocate card structures to hold addresses, ... */
339 card = kzalloc(sizeof(*card), GFP_KERNEL);
341 dev_err(&pdev->dev, "Unable to allocate memory\n");
342 pci_disable_device(pdev);
346 pci_set_drvdata(pdev, card);
350 /* Remap the PLX90xx configuration space */
351 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
354 dev_err(&pdev->dev, "Failed to remap configuration space "
355 "(BAR%d)\n", ci->conf_map.bar);
356 goto failure_cleanup;
358 card->conf_addr = addr + ci->conf_map.offset;
360 ci->reset_func(pdev);
362 /* Detect available channels */
363 for (i = 0; i < ci->channel_count; i++) {
364 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
366 dev = alloc_sja1000dev(0);
369 goto failure_cleanup;
372 card->net_dev[i] = dev;
373 priv = netdev_priv(dev);
375 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
376 priv->irq_flags = SA_SHIRQ;
378 priv->irq_flags = IRQF_SHARED;
381 dev->irq = pdev->irq;
384 * Remap IO space of the SJA1000 chips
385 * This is device-dependent mapping
387 addr = pci_iomap(pdev, cm->bar, cm->size);
390 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
391 goto failure_cleanup;
394 priv->reg_base = addr + cm->offset;
395 priv->read_reg = plx_pci_read_reg;
396 priv->write_reg = plx_pci_write_reg;
398 /* Check if channel is present */
399 if (plx_pci_check_sja1000(priv)) {
400 priv->can.clock.freq = ci->can_clock;
404 SET_NETDEV_DEV(dev, &pdev->dev);
406 /* Register SJA1000 device */
407 err = register_sja1000dev(dev);
409 dev_err(&pdev->dev, "Registering device failed "
411 free_sja1000dev(dev);
412 goto failure_cleanup;
417 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
418 "registered as %s\n", i + 1, priv->reg_base,
419 dev->irq, dev->name);
421 dev_err(&pdev->dev, "Channel #%d not detected\n",
423 free_sja1000dev(dev);
427 if (!card->channels) {
429 goto failure_cleanup;
433 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
434 * Local_2 interrupts from the SJA1000 chips
436 val = ioread32(card->conf_addr + PLX_INTCSR);
437 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
438 iowrite32(val, card->conf_addr + PLX_INTCSR);
443 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
445 plx_pci_del_card(pdev);
450 static struct pci_driver plx_pci_driver = {
452 .id_table = plx_pci_tbl,
453 .probe = plx_pci_add_card,
454 .remove = plx_pci_del_card,
457 static int __init plx_pci_init(void)
459 return pci_register_driver(&plx_pci_driver);
462 static void __exit plx_pci_exit(void)
464 pci_unregister_driver(&plx_pci_driver);
467 module_init(plx_pci_init);
468 module_exit(plx_pci_exit);