2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
5 * (C) 2008 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/netdevice.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/string.h>
22 #include <linux/if_arp.h>
23 #include <linux/skbuff.h>
24 #include <linux/types.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/clk.h>
29 #include <linux/can.h>
30 #include <linux/can/error.h>
31 #include <linux/can/dev.h>
33 #include <mach/board.h>
35 #define DRV_NAME "at91_can"
36 #define MAX_INTERRUPT_WORK 4
42 #define AT91_MB_RX_NUM 12
43 #define AT91_MB_TX_SHIFT 2
45 #define AT91_MB_RX_FIRST 0
46 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
47 #define AT91_MB_RX_BANKS 3
48 #define AT91_MB_RX_BANK_WIDTH (AT91_MB_RX_NUM / AT91_MB_RX_BANKS)
49 #define AT91_MB_RX_BANK_MASK(i) (((1 << AT91_MB_RX_BANK_WIDTH) - 1) << \
50 (AT91_MB_RX_BANK_WIDTH * (i)))
52 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
53 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
54 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
56 /* Common registers */
71 /* Mailbox registers (0 <= i <= 15) */
72 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
73 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
74 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
75 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
76 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
77 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
78 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
79 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
82 #define AT91_MR_AT91EN (1 << 0)
83 #define AT91_MR_LPM (1 << 1)
84 #define AT91_MR_ABM (1 << 2)
85 #define AT91_MR_OVL (1 << 3)
86 #define AT91_MR_TEOF (1 << 4)
87 #define AT91_MR_TTM (1 << 5)
88 #define AT91_MR_TIMFRZ (1 << 6)
89 #define AT91_MR_DRPT (1 << 7)
91 #define AT91_SR_RBSY (1 << 29)
93 #define AT91_MMR_PRIO_SHIFT 16
95 #define AT91_MID_MIDE (1 << 29)
97 #define AT91_MSR_MRTR (1 << 20)
98 #define AT91_MSR_MABT (1 << 22)
99 #define AT91_MSR_MRDY (1 << 23)
100 #define AT91_MSR_MMI (1 << 24)
102 #define AT91_MCR_MRTR (1 << 20)
103 #define AT91_MCR_MTCR (1 << 23)
107 AT91_MB_MODE_DISABLED = 0,
109 AT91_MB_MODE_RX_OVRWR = 2,
111 AT91_MB_MODE_CONSUMER = 4,
112 AT91_MB_MODE_PRODUCER = 5,
115 /* Interrupt mask bits */
116 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
117 - (1 << AT91_MB_RX_FIRST))
118 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
119 - (1 << AT91_MB_TX_FIRST))
120 #define AT91_IRQ_MB_AL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
122 #define AT91_IRQ_ERRA (1 << 16)
123 #define AT91_IRQ_WARN (1 << 17)
124 #define AT91_IRQ_ERRP (1 << 18)
125 #define AT91_IRQ_BOFF (1 << 19)
126 #define AT91_IRQ_SLEEP (1 << 20)
127 #define AT91_IRQ_WAKEUP (1 << 21)
128 #define AT91_IRQ_TOVF (1 << 22)
129 #define AT91_IRQ_TSTP (1 << 23)
130 #define AT91_IRQ_CERR (1 << 24)
131 #define AT91_IRQ_SERR (1 << 25)
132 #define AT91_IRQ_AERR (1 << 26)
133 #define AT91_IRQ_FERR (1 << 27)
134 #define AT91_IRQ_BERR (1 << 28)
136 #define AT91_IRQ_ERR_ALL 0x1fff0000
137 #define AT91_IRQ_ERR_CANFRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
138 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
139 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
140 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
143 struct can_priv can; /* must be the first member! */
146 struct at91_can_data *pdata;
148 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
149 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
150 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
151 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
152 unsigned int tx_next;
153 unsigned int tx_echo;
155 unsigned int rx_bank;
159 static inline int get_tx_next_mb(struct at91_priv *priv)
161 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
164 static inline int get_tx_next_prio(struct at91_priv *priv)
166 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
169 static inline int get_tx_echo_mb(struct at91_priv *priv)
171 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
175 static inline u32 at91_read(struct net_device *dev, enum at91_reg reg)
177 return readl((void __iomem *)dev->base_addr + reg);
181 at91_write(struct net_device *dev, enum at91_reg reg, u32 value)
183 writel(value, (void __iomem *)dev->base_addr + reg);
188 set_mb_mode_prio(struct net_device *dev, int mb, enum at91_mb_mode mode,
191 at91_write(dev, AT91_MMR(mb),
197 set_mb_mode(struct net_device *dev, int mb, enum at91_mb_mode mode)
199 set_mb_mode_prio(dev, mb, mode, 0);
204 * Enable or disable transceiver
206 static void enable_can_transceiver(struct at91_priv *priv, int enable)
208 if (priv->pdata && priv->pdata->transceiver_enable)
209 priv->pdata->transceiver_enable(enable);
214 * theory of operation:
216 * Accoring to the datasheet priority 0 is the highest priority, 15 is
217 * the lowest. If two mailboxes have the same priority level the
218 * message of the mailbox with the lowest number is sent first.
220 * We use the first TX mailbox mailbox (AT91_MB_TX_FIRST) with prio 0,
221 * then the next mailbox with prio 0, and so on, until all mailboxes
222 * are used. Then we start from the beginning with mailbox
223 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
224 * prio 1. When we reach the last mailbox with prio 15, we have to
225 * stop sending, waiting for all messages to be delivered, than start
226 * again with mailbox AT91_MB_TX_FIRST prio 0.
228 * We use the priv->tx_next as counter for the next transmission
229 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
230 * encode the mailbox number, the upper 4 bits the mailbox priority:
232 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
233 * (mb - AT91_MB_TX_FIRST);
236 static int at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
238 struct at91_priv *priv = netdev_priv(dev);
239 struct net_device_stats *stats = &dev->stats;
240 struct can_frame *cf = (struct can_frame *)skb->data;
241 u32 reg_mid, reg_mcr;
244 mb = get_tx_next_mb(priv);
245 prio = get_tx_next_prio(priv);
247 if (!(at91_read(dev, AT91_MSR(mb)) & AT91_MSR_MRDY)) {
249 /* FIXME: kfree? stats? */
253 if (cf->can_id & CAN_EFF_FLAG)
254 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
256 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
258 reg_mcr = (cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0 |
259 (cf->can_dlc << 16) |
262 /* disable MB while writing ID (see datasheet) */
263 set_mb_mode(dev, mb, AT91_MB_MODE_DISABLED);
264 at91_write(dev, AT91_MID(mb), reg_mid);
265 set_mb_mode_prio(dev, mb, AT91_MB_MODE_TX, prio);
267 at91_write(dev, AT91_MDL(mb), *(u32 *)(cf->data + 0));
268 at91_write(dev, AT91_MDH(mb), *(u32 *)(cf->data + 4));
270 /* This triggers transmission */
272 at91_write(dev, AT91_MCR(mb), reg_mcr);
274 stats->tx_bytes += cf->can_dlc;
275 dev->trans_start = jiffies;
277 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
278 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
281 * we have to stop the queue and deliver all messages in case
282 * of a prio+mb counter wrap around. This is the case if
283 * tx_next buffer prio and mailbox equals 0.
285 * also stop the queue if next buffer is still in use
289 if (!(at91_read(dev, AT91_MSR(get_tx_next_mb(priv))) &
291 (priv->tx_next & AT91_NEXT_MASK) == 0) {
292 netif_stop_queue(dev);
294 "stopping netif_queue, priv->tx_next=%d, "
297 get_tx_next_prio(priv),
298 get_tx_next_mb(priv));
301 /* Enable interrupt for this mailbox */
302 at91_write(dev, AT91_IER, 1 << mb);
309 * at91_clear_bank - clear and reactive bank
311 * @bank: bank to clear
313 * Clears and reenables IRQs on given bank in order to enable
314 * reception of new CAN messages
316 static void at91_clear_bank(struct net_device *dev, int bank)
321 last = AT91_MB_RX_BANK_WIDTH * (bank + 1);
322 for (i = AT91_MB_RX_BANK_WIDTH * bank; i < last; i++)
323 at91_write(dev, AT91_MCR(i), AT91_MCR_MTCR);
325 mask = AT91_MB_RX_BANK_MASK(bank);
326 at91_write(dev, AT91_IER, mask);
331 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
333 * @mb: mailbox number to read from
334 * @cf: can frame where to store message
336 * Reads a CAN message from the given mailbox and stores data into
337 * given can frame. "mb" and "cf" must be valid.
339 static void at91_read_mb(struct net_device *dev, int mb, struct can_frame *cf)
341 u32 reg_msr, reg_mid, reg_mdl, reg_mdh;
343 reg_mid = at91_read(dev, AT91_MID(mb));
344 if (reg_mid & AT91_MID_MIDE)
345 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
347 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
349 reg_msr = at91_read(dev, AT91_MSR(mb));
350 if (reg_msr & AT91_MSR_MRTR)
351 cf->can_id |= CAN_RTR_FLAG;
352 cf->can_dlc = (reg_msr >> 16) & 0xf;
354 reg_mdl = at91_read(dev, AT91_MDL(mb));
355 reg_mdh = at91_read(dev, AT91_MDH(mb));
357 *(u32 *)(cf->data + 0) = reg_mdl;
358 *(u32 *)(cf->data + 4) = reg_mdh;
360 /* FIXME: take care about AT91_MB_MODE_RX_OVRWR mb */
365 * at91_read_msg - read CAN message from mailbox
367 * @mb: mail box to read from
369 * Reads a CAN message from given mailbox, and put into linux network
370 * RX queue, does all housekeeping chores (stats, ...)
372 static void at91_read_msg(struct net_device *dev, int mb)
374 struct net_device_stats *stats = &dev->stats;
375 struct can_frame *cf;
378 skb = netdev_alloc_skb(dev, sizeof(struct can_frame));
379 if (unlikely(!skb)) {
382 "Memory squeeze, dropping packet.\n");
386 skb->protocol = htons(ETH_P_CAN);
387 cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
389 at91_read_mb(dev, mb, cf);
393 dev->last_rx = jiffies;
395 stats->rx_bytes += cf->can_dlc;
400 * theory of operation
402 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
403 * them into 3 groups (3 x 4 mbs) a.k.a banks.
405 * like it or not, but the chip always saves a received CAN message
406 * into the first free mailbox it finds. This makes it very difficult
407 * to read the messages in the right order from the chip. This is how
408 * we work around that problem:
410 * The first message goes into mb nr. 0 and issues an interrupt. We
411 * read it, do _not_ reenable the mb (to receive another message), but
412 * disable the interrupt though. This is done for the first bank
413 * (i.e. mailbox 0-3).
418 * +-+-+-+-++-+-+-+-++-+-+-+-+
419 * |x|x|x|x|| | | | || | | | |
420 * +-+-+-+-++-+-+-+-++-+-+-+-+
421 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
422 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
424 * Then we switch to bank 1. If this bank is full, too, we reenable
425 * bank number 0, and switch to bank 2. Imagine bank 2 like an overflow
426 * bank, which takes CAN messages if bank 1 is full, but bank 0 not
427 * cleared yet. In other words: from the reception of a message into
428 * mb 7, we have the "four mailboxes" (of bank 2) time to enter the
429 * interrupt service routine and reenable bank 0.
431 * Nevertheless, after reenabling bank 0, we look at bank 2 first, to
432 * see if there are some messages. Then we reactivate bank 1 and 2,
433 * and switch to bank 0.
436 static void at91_irq_rx(struct net_device *dev, u32 reg_sr)
438 struct at91_priv *priv = netdev_priv(dev);
439 unsigned long *addr = (unsigned long *)®_sr;
442 /* masking of reg_sr not needed, already done by at91_irq */
444 mb = find_next_bit(addr, AT91_MB_RX_NUM,
445 AT91_MB_RX_BANK_WIDTH * priv->rx_bank);
446 while (mb < AT91_MB_RX_NUM) {
448 "%s: SR=0x%08x, mb=%d, mb_bit=0x%04x, rx_bank=%d\n",
449 __func__, reg_sr, mb, 1 << mb, priv->rx_bank);
451 at91_read_msg(dev, mb);
453 /* disable interrupt */
454 at91_write(dev, AT91_IDR, 1 << mb);
456 /* find next pending mailbox */
457 mb = find_next_bit(addr, AT91_MB_RX_NUM, mb + 1);
460 switch (priv->rx_bank) {
462 if (!(at91_read(dev, AT91_IMR) & AT91_MB_RX_BANK_MASK(0)))
466 if (!(at91_read(dev, AT91_IMR) & AT91_MB_RX_BANK_MASK(1))) {
467 at91_clear_bank(dev, 0);
472 at91_clear_bank(dev, 1);
473 at91_clear_bank(dev, 2);
480 static void at91_tx_timeout(struct net_device *dev)
482 dev->stats.tx_errors++;
483 dev_dbg(ND2D(dev), "TX timeout!\n");
488 * theory of operation:
490 * priv->tx_echo holds the number of the oldest can_frame put for
491 * transmission into the hardware, but not yet ACKed by the CAN tx
494 * We iterate from priv->tx_echo to priv->tx_next and check if the
495 * packet has been transmitted, echo it back to the CAN framework. If
496 * we discover a not yet transmitted package, stop looking for more.
499 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
501 struct at91_priv *priv = netdev_priv(dev);
505 /* masking of reg_sr not needed, already done by at91_irq */
507 for (/* nix */; priv->tx_echo < priv->tx_next; priv->tx_echo++) {
508 mb = get_tx_echo_mb(priv);
510 /* no event in mailbox? */
511 if (!(reg_sr & (1 << mb)))
514 reg_msr = at91_read(dev, AT91_MSR(mb));
516 /* FIXME: BUGON no ready | abort */
519 "%s: SR=0x%08x, mb=%d, mb_bit=0x%04x, mb status: %s, "
520 "tx_next=%d, tx_echo=%d\n",
521 __func__, reg_sr, mb, 1 << mb,
522 reg_msr & AT91_MSR_MRDY ? "MRDY" : "MABT",
523 priv->tx_next, priv->tx_echo);
525 /* Disable irq for this TX mailbox */
526 at91_write(dev, AT91_IDR, 1 << mb);
529 * only echo if mailbox signals us an transfer
530 * complete (MSR_MRDY). Otherwise it's an tansfer
531 * abort. "can_bus_off()" takes care about the skbs
532 * parked in the echo queue.
534 if (likely(reg_msr & AT91_MSR_MRDY)) {
535 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
536 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
537 dev->stats.tx_packets++;
542 * restart queue if we don't have a wrap around but restart if
543 * we get an TX int for the last can frame directly before a
546 if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
547 (priv->tx_echo & AT91_NEXT_MASK) == 0)
548 netif_wake_queue(dev);
552 static void at91_irq_err_canframe(struct net_device *dev, u32 reg_sr)
555 if (reg_sr & AT91_IRQ_CERR)
556 dev_dbg(ND2D(dev), "CERR irq\n");
559 if (reg_sr & AT91_IRQ_SERR)
560 dev_dbg(ND2D(dev), "SERR irq\n");
562 /* Acknowledgement error */
563 if (reg_sr & AT91_IRQ_AERR)
564 dev_dbg(ND2D(dev), "AERR irq\n");
567 if (reg_sr & AT91_IRQ_FERR)
568 dev_dbg(ND2D(dev), "FERR irq\n");
571 if (reg_sr & AT91_IRQ_BERR)
572 dev_dbg(ND2D(dev), "BERR irq\n");
576 static void at91_irq_err(struct net_device *dev, u32 reg_sr_masked)
578 struct at91_priv *priv = netdev_priv(dev);
579 enum can_state new_state;
580 u32 reg_sr, reg_ecr, reg_idr, reg_ier;
583 reg_sr = at91_read(dev, AT91_SR);
584 reg_ecr = at91_read(dev, AT91_ECR);
586 rec = reg_ecr & 0xff;
588 dev_dbg(ND2D(dev), "%s: TEC=%3d%s, REC=%3d, bits set: %s%s%s%s\n",
591 reg_sr & AT91_IRQ_BOFF ? " (bus-off!)" : "",
593 reg_sr & AT91_IRQ_ERRA ? "ERRA " : "",
594 reg_sr & AT91_IRQ_WARN ? "WARN " : "",
595 reg_sr & AT91_IRQ_ERRP ? "ERRP " : "",
596 reg_sr & AT91_IRQ_BOFF ? "BOFF " : "");
598 /* we need to look at the unmasked reg_sr */
599 if (unlikely(reg_sr & AT91_IRQ_BOFF))
600 new_state = CAN_STATE_BUS_OFF;
601 else if (unlikely(reg_sr & AT91_IRQ_ERRP))
602 new_state = CAN_STATE_BUS_PASSIVE;
603 else if (unlikely(reg_sr & AT91_IRQ_WARN))
604 new_state = CAN_STATE_BUS_WARNING;
605 else if (likely(reg_sr & AT91_IRQ_ERRA))
606 new_state = CAN_STATE_ACTIVE;
612 /* state hasn't changed, no error in canframe */
613 if (new_state == priv->can.state &&
614 !(reg_sr_masked & AT91_IRQ_ERR_CANFRAME))
618 switch (priv->can.state) {
619 case CAN_STATE_ACTIVE:
622 * to : BUS_WARNING, BUS_PASSIVE, BUS_OFF
623 * => : there was a warning int
625 if (new_state >= CAN_STATE_BUS_WARNING &&
626 new_state <= CAN_STATE_BUS_OFF)
627 priv->can.can_stats.error_warning++;
628 case CAN_STATE_BUS_WARNING: /* fallthrough */
630 * from: ACTIVE, BUS_WARNING
631 * to : BUS_PASSIVE, BUS_OFF
632 * => : error passive int
634 if (new_state >= CAN_STATE_BUS_PASSIVE &&
635 new_state <= CAN_STATE_BUS_OFF)
636 priv->can.can_stats.error_passive++;
638 case CAN_STATE_BUS_OFF:
640 * this is a crude chip, happens very often that it is
641 * in BUS_OFF but still tries to send a package. on
642 * success it leaves bus off. so we have to reenable
645 if (new_state <= CAN_STATE_BUS_PASSIVE)
646 netif_carrier_on(dev);
653 /* process state changes depending on the new state */
655 case CAN_STATE_ACTIVE:
657 * actually we want to enable AT91_IRQ_WARN here, but
658 * it screws up the system under certain
659 * circumstances. so just enable AT91_IRQ_ERRP, thus
662 case CAN_STATE_BUS_WARNING: /* fallthrough */
663 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
664 reg_ier = AT91_IRQ_ERRP;
666 case CAN_STATE_BUS_PASSIVE:
667 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
668 reg_ier = AT91_IRQ_BOFF;
670 case CAN_STATE_BUS_OFF:
671 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
672 AT91_IRQ_WARN | AT91_IRQ_BOFF;
676 * FIXME: really abort?
678 * a somewhat "special" chip, even in BUS_OFF mode, it
679 * accesses the bus. this is a no-no. we try to abort
680 * transfers on all mailboxes. but the chip doesn't
681 * seem to handle this correctly. a stuck-in-transfer
682 * message isn't aborted. after bringing the CAN bus
683 * back xin shape again, the stuck-in-transfer message
684 * is tranferred and its MRDY bit is set. all other
685 * queued messages are aborted (not send) their MABT
686 * bit in MSR is _not_ set but the MRDY bit, too.
688 dev_dbg(ND2D(dev), "%s: aborting transfers, due to BUS OFF\n",
691 at91_write(dev, AT91_ACR, AT91_IRQ_MB_TX);
699 dev_dbg(ND2D(dev), "%s: writing IDR=0x%08x, IER=0x%08x\n",
700 __func__, reg_idr, reg_ier);
701 at91_write(dev, AT91_IDR, reg_idr);
702 at91_write(dev, AT91_IER, reg_ier);
707 struct can_frame *cf;
709 skb = netdev_alloc_skb(dev, sizeof(struct can_frame));
713 skb->protocol = htons(ETH_P_CAN);
714 cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
715 memset(cf, 0, sizeof(struct can_frame));
717 cf->can_id = CAN_ERR_FLAG;
718 cf->can_dlc = CAN_ERR_DLC;
721 case CAN_STATE_BUS_WARNING:
722 case CAN_STATE_BUS_PASSIVE:
723 cf->can_id |= CAN_ERR_CRTL;
725 if (new_state == CAN_STATE_BUS_WARNING)
726 cf->data[1] = (tec > rec) ?
727 CAN_ERR_CRTL_TX_WARNING :
728 CAN_ERR_CRTL_RX_WARNING;
730 cf->data[1] = (tec > rec) ?
731 CAN_ERR_CRTL_TX_PASSIVE :
732 CAN_ERR_CRTL_RX_PASSIVE;
735 case CAN_STATE_BUS_OFF:
736 cf->can_id |= CAN_ERR_BUSOFF;
745 dev->last_rx = jiffies;
746 dev->stats.rx_packets++;
747 dev->stats.rx_bytes += cf->can_dlc;
751 priv->can.state = new_state;
758 static irqreturn_t at91_irq(int irq, void *ndev_id)
760 struct net_device *dev = ndev_id;
761 irqreturn_t handled = IRQ_NONE;
763 int boguscnt = MAX_INTERRUPT_WORK;
766 reg_sr = at91_read(dev, AT91_SR);
767 reg_imr = at91_read(dev, AT91_IMR);
768 dev_dbg(ND2D(dev), "%s: SR=0x%08x, IMR=0x%08x, [0x%08x]\n",
770 reg_sr, reg_imr, reg_sr & reg_imr);
772 /* Ignore masked interrupts */
777 handled = IRQ_HANDLED;
779 if (reg_sr & AT91_IRQ_MB_RX) {
780 /* receive interrupt */
781 at91_irq_rx(dev, reg_sr);
784 if (reg_sr & AT91_IRQ_MB_TX) {
785 /* transmission complete interrupt */
786 at91_irq_tx(dev, reg_sr);
789 at91_irq_err(dev, reg_sr);
791 } while (--boguscnt > 0);
793 if (unlikely(boguscnt <= 0)) {
794 dev_warn(ND2D(dev), "Too much work at interrupt, "
795 "status (at enter): 0x%08x, now: 0x%08x\n",
797 at91_read(dev, AT91_SR) & at91_read(dev, AT91_IMR));
799 /* Clear all interrupt sources. */
808 static void at91_setup_mailboxes(struct net_device *dev)
810 struct at91_priv *priv = netdev_priv(dev);
814 * The first 12 mailboxes are used as a reception FIFO. The
815 * last mailbox is configured with overwrite option. The
816 * overwrite flag indicates a FIFO overflow.
818 /* FIXME: clear accept regs (MID/MAM) */
819 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
820 set_mb_mode(dev, i, AT91_MB_MODE_RX);
821 set_mb_mode(dev, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
823 /* The last 4 mailboxes are used for transmitting. */
824 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
825 set_mb_mode_prio(dev, i, AT91_MB_MODE_TX, 0);
828 /* reset both tx and rx helper pointers */
829 priv->tx_next = priv->tx_echo = priv->rx_bank = 0;
833 static struct net_device_stats *at91_get_stats(struct net_device *dev)
835 struct at91_priv *priv = netdev_priv(dev);
836 u32 reg_ecr = at91_read(dev, AT91_ECR);
838 dev->stats.rx_errors = reg_ecr & 0xff;
839 dev->stats.tx_errors = reg_ecr >> 16;
842 * here comes another one:
844 * the transmit error counter (TEC) has only a width of 8
845 * bits, so when the devices goes into BUS OFF (which is
846 * defined by a TEC > 255), the TEC in the chip shows "0". Not
847 * only that, it keeps accumulating errors, so they can vary
848 * between 0 and 255. We set TEC to 256 (hard) in BUS_OFF.
851 if (unlikely(priv->can.state == CAN_STATE_BUS_OFF))
852 dev->stats.tx_errors = 256;
858 static int at91_set_bittiming(struct net_device *dev)
860 struct at91_priv *priv = netdev_priv(dev);
861 struct can_bittiming *bt = &priv->can.bittiming;
864 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) << 24) |
865 ((bt->brp - 1) << 16) |
866 ((bt->sjw - 1) << 12) |
867 ((bt->prop_seg - 1) << 8) |
868 ((bt->phase_seg1 - 1) << 4) |
869 ((bt->phase_seg2 - 1) << 0);
871 dev_dbg(ND2D(dev), "writing AT91_BR: 0x%08x, can_sys_clock: %d\n",
872 reg_br, priv->can.bittiming.clock);
873 at91_write(dev, AT91_BR, reg_br);
879 static void at91_chip_start(struct net_device *dev)
881 struct at91_priv *priv = netdev_priv(dev);
884 /* disable interrupts */
885 at91_write(dev, AT91_IDR, 0x1fffffff);
888 reg_mr = at91_read(dev, AT91_MR);
889 at91_write(dev, AT91_MR, reg_mr & ~AT91_MR_AT91EN);
892 at91_setup_mailboxes(dev);
894 enable_can_transceiver(priv, 1);
897 reg_mr = at91_read(dev, AT91_MR);
898 at91_write(dev, AT91_MR, reg_mr | AT91_MR_AT91EN);
900 priv->can.state = CAN_STATE_ACTIVE;
902 /* Enable interrupts */
905 AT91_IRQ_ERRP; /* AT91_IRQ_WARN screws up system */
906 /* AT91_IRQ_CERR | AT91_IRQ_SERR | AT91_IRQ_AERR | */
907 /* AT91_IRQ_FERR | AT91_IRQ_BERR; */
908 at91_write(dev, AT91_IDR, 0x1fffffff);
909 at91_write(dev, AT91_IER, reg_ier);
913 static void at91_chip_stop(struct net_device *dev)
915 struct at91_priv *priv = netdev_priv(dev);
918 /* disable interrupts */
919 at91_write(dev, AT91_IDR, 0x1fffffff);
921 reg_mr = at91_read(dev, AT91_MR);
922 at91_write(dev, AT91_MR, reg_mr & ~AT91_MR_AT91EN);
924 priv->can.state = CAN_STATE_STOPPED;
925 enable_can_transceiver(priv, 0);
929 static int at91_open(struct net_device *dev)
931 struct at91_priv *priv = netdev_priv(dev);
934 clk_enable(priv->clk);
936 /* determine and set bittime */
937 err = can_set_bittiming(dev);
941 /* register interrupt handler */
942 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
948 /* start chip and queuing */
949 at91_chip_start(dev);
950 netif_start_queue(dev);
955 clk_disable(priv->clk);
962 * stop CAN bus activity
964 static int at91_close(struct net_device *dev)
966 struct at91_priv *priv = netdev_priv(dev);
968 netif_stop_queue(dev);
971 free_irq(dev->irq, dev);
972 clk_disable(priv->clk);
974 can_close_cleanup(dev);
980 static int at91_get_state(struct net_device *dev, u32 *state)
982 struct at91_priv *priv = netdev_priv(dev);
983 *state = priv->can.state;
988 static int at91_set_mode(struct net_device *dev, u32 _mode)
990 enum can_mode mode = _mode;
994 dev_dbg(ND2D(dev), "%s: CAN_MODE_START requested\n", __func__);
996 at91_chip_start(dev);
997 netif_wake_queue(dev);
1008 static struct can_bittiming_const at91_bittiming_const = {
1020 static int __init at91_can_probe(struct platform_device *pdev)
1022 struct net_device *dev;
1023 struct at91_priv *priv;
1024 struct resource *res;
1029 clk = clk_get(&pdev->dev, "can_clk");
1031 dev_err(&pdev->dev, "no clock defined\n");
1036 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1037 irq = platform_get_irq(pdev, 0);
1043 if (!request_mem_region(res->start,
1044 res->end - res->start + 1,
1050 addr = ioremap_nocache(res->start, res->end - res->start + 1);
1056 dev = alloc_candev(sizeof(struct at91_priv));
1062 dev->open = at91_open;
1063 dev->stop = at91_close;
1064 dev->hard_start_xmit = at91_start_xmit;
1065 dev->tx_timeout = at91_tx_timeout;
1066 dev->get_stats = at91_get_stats;
1068 dev->base_addr = (unsigned long)addr;
1069 dev->flags |= IFF_ECHO;
1071 priv = netdev_priv(dev);
1072 priv->can.bittiming.clock = clk_get_rate(clk);
1073 priv->can.bittiming_const = &at91_bittiming_const;
1074 priv->can.do_set_bittiming = at91_set_bittiming;
1075 priv->can.do_get_state = at91_get_state;
1076 priv->can.do_set_mode = at91_set_mode;
1079 priv->pdata = pdev->dev.platform_data;
1081 dev_set_drvdata(&pdev->dev, dev);
1082 SET_NETDEV_DEV(dev, &pdev->dev);
1084 err = register_candev(dev);
1086 dev_err(&pdev->dev, "registering netdev failed\n");
1091 dev_info(&pdev->dev, "device registered (base_addr=%#lx, irq=%d)\n",
1092 dev->base_addr, dev->irq);
1101 release_mem_region(res->start, res->end - res->start + 1);
1109 static int __devexit at91_can_remove(struct platform_device *pdev)
1111 struct net_device *dev = platform_get_drvdata(pdev);
1112 struct at91_priv *priv = netdev_priv(dev);
1113 struct resource *res;
1115 unregister_netdev(dev);
1117 platform_set_drvdata(pdev, NULL);
1121 iounmap((void __iomem *)dev->base_addr);
1123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124 release_mem_region(res->start, res->end - res->start + 1);
1132 static int at91_can_suspend(struct platform_device *pdev,
1135 struct net_device *net_dev = platform_get_drvdata(pdev);
1136 struct at91_priv *priv = netdev_priv(net_dev);
1138 if (netif_running(net_dev)) {
1139 /* TODO Disable IRQ? */
1140 netif_stop_queue(net_dev);
1141 netif_device_detach(net_dev);
1142 enable_can_transceiver(priv, 0);
1143 clk_disable(priv->clk);
1149 static int at91_can_resume(struct platform_device *pdev)
1151 struct net_device *net_dev = platform_get_drvdata(pdev);
1152 struct at91_priv *priv = netdev_priv(net_dev);
1154 if (netif_running(net_dev)) {
1155 clk_enable(priv->clk);
1156 enable_can_transceiver(priv, 1);
1157 netif_device_attach(net_dev);
1158 netif_start_queue(net_dev);
1159 /* TODO Enable IRQ? */
1164 #define at91_can_suspend NULL
1165 #define at91_can_resume NULL
1168 static struct platform_driver at91_can_driver = {
1169 .probe = at91_can_probe,
1170 .remove = __devexit_p(at91_can_remove),
1171 .suspend = at91_can_suspend,
1172 .resume = at91_can_resume,
1175 .owner = THIS_MODULE,
1179 static int __init at91_can_module_init(void)
1181 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME);
1182 return platform_driver_register(&at91_can_driver);
1185 static void __exit at91_can_module_exit(void)
1187 platform_driver_unregister(&at91_can_driver);
1188 printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
1191 module_init(at91_can_module_init);
1192 module_exit(at91_can_module_exit);
1194 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1195 MODULE_LICENSE("GPL v2");
1196 MODULE_DESCRIPTION("LLCF/socketcan '" DRV_NAME "' network device driver");