2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
46 * static struct spi_board_info spi_board_info[] = {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/completion.h>
62 #include <linux/delay.h>
63 #include <linux/device.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/freezer.h>
66 #include <linux/interrupt.h>
68 #include <linux/kernel.h>
69 #include <linux/module.h>
70 #include <linux/netdevice.h>
71 #include <linux/platform_device.h>
72 #include <linux/spi/spi.h>
73 #include <linux/uaccess.h>
74 #include <socketcan/can.h>
75 #include <socketcan/can/core.h>
76 #include <socketcan/can/dev.h>
77 #include <socketcan/can/platform/mcp251x.h>
79 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
80 #error This driver does not support Kernel versions < 2.6.22
83 /* SPI interface instruction set */
84 #define INSTRUCTION_WRITE 0x02
85 #define INSTRUCTION_READ 0x03
86 #define INSTRUCTION_BIT_MODIFY 0x05
87 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
88 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
89 #define INSTRUCTION_RESET 0xC0
91 /* MPC251x registers */
94 # define CANCTRL_REQOP_MASK 0xe0
95 # define CANCTRL_REQOP_CONF 0x80
96 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
97 # define CANCTRL_REQOP_LOOPBACK 0x40
98 # define CANCTRL_REQOP_SLEEP 0x20
99 # define CANCTRL_REQOP_NORMAL 0x00
100 # define CANCTRL_OSM 0x08
101 # define CANCTRL_ABAT 0x10
105 # define CNF1_SJW_SHIFT 6
107 # define CNF2_BTLMODE 0x80
108 # define CNF2_SAM 0x40
109 # define CNF2_PS1_SHIFT 3
111 # define CNF3_SOF 0x08
112 # define CNF3_WAKFIL 0x04
113 # define CNF3_PHSEG2_MASK 0x07
115 # define CANINTE_MERRE 0x80
116 # define CANINTE_WAKIE 0x40
117 # define CANINTE_ERRIE 0x20
118 # define CANINTE_TX2IE 0x10
119 # define CANINTE_TX1IE 0x08
120 # define CANINTE_TX0IE 0x04
121 # define CANINTE_RX1IE 0x02
122 # define CANINTE_RX0IE 0x01
124 # define CANINTF_MERRF 0x80
125 # define CANINTF_WAKIF 0x40
126 # define CANINTF_ERRIF 0x20
127 # define CANINTF_TX2IF 0x10
128 # define CANINTF_TX1IF 0x08
129 # define CANINTF_TX0IF 0x04
130 # define CANINTF_RX1IF 0x02
131 # define CANINTF_RX0IF 0x01
133 # define EFLG_EWARN 0x01
134 # define EFLG_RXWAR 0x02
135 # define EFLG_TXWAR 0x04
136 # define EFLG_RXEP 0x08
137 # define EFLG_TXEP 0x10
138 # define EFLG_TXBO 0x20
139 # define EFLG_RX0OVR 0x40
140 # define EFLG_RX1OVR 0x80
141 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
142 # define TXBCTRL_ABTF 0x40
143 # define TXBCTRL_MLOA 0x20
144 # define TXBCTRL_TXERR 0x10
145 # define TXBCTRL_TXREQ 0x08
146 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
147 # define SIDH_SHIFT 3
148 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
149 # define SIDL_SID_MASK 7
150 # define SIDL_SID_SHIFT 5
151 # define SIDL_EXIDE_SHIFT 3
152 # define SIDL_EID_SHIFT 16
153 # define SIDL_EID_MASK 3
154 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
155 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
156 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
157 # define DLC_RTR_SHIFT 6
158 #define TXBCTRL_OFF 0
159 #define TXBSIDH_OFF 1
160 #define TXBSIDL_OFF 2
161 #define TXBEID8_OFF 3
162 #define TXBEID0_OFF 4
165 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
166 # define RXBCTRL_BUKT 0x04
167 # define RXBCTRL_RXM0 0x20
168 # define RXBCTRL_RXM1 0x40
169 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
170 # define RXBSIDH_SHIFT 3
171 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
172 # define RXBSIDL_IDE 0x08
173 # define RXBSIDL_EID 3
174 # define RXBSIDL_SHIFT 5
175 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
176 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
177 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
178 # define RXBDLC_LEN_MASK 0x0f
179 # define RXBDLC_RTR 0x40
180 #define RXBCTRL_OFF 0
181 #define RXBSIDH_OFF 1
182 #define RXBSIDL_OFF 2
183 #define RXBEID8_OFF 3
184 #define RXBEID0_OFF 4
188 #define GET_BYTE(val, byte) \
189 (((val) >> ((byte) * 8)) & 0xff)
190 #define SET_BYTE(val, byte) \
191 (((val) & 0xff) << ((byte) * 8))
194 * Buffer size required for the largest SPI transfer (i.e., reading a
197 #define CAN_FRAME_MAX_DATA_LEN 8
198 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
199 #define CAN_FRAME_MAX_BITS 128
201 #define TX_ECHO_SKB_MAX 1
203 #define DEVICE_NAME "mcp251x"
205 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
206 module_param(mcp251x_enable_dma, int, S_IRUGO);
207 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
209 static struct can_bittiming_const mcp251x_bittiming_const = {
221 struct mcp251x_priv {
223 struct net_device *net;
224 struct spi_device *spi;
226 struct mutex spi_lock; /* SPI buffer lock */
229 dma_addr_t spi_tx_dma;
230 dma_addr_t spi_rx_dma;
232 struct sk_buff *tx_skb;
234 struct workqueue_struct *wq;
235 struct work_struct tx_work;
236 struct work_struct irq_work;
240 #define AFTER_SUSPEND_UP 1
241 #define AFTER_SUSPEND_DOWN 2
242 #define AFTER_SUSPEND_POWER 4
243 #define AFTER_SUSPEND_RESTART 8
247 static void mcp251x_clean(struct net_device *net)
249 struct mcp251x_priv *priv = netdev_priv(net);
251 net->stats.tx_errors++;
253 dev_kfree_skb(priv->tx_skb);
255 can_free_echo_skb(priv->net, 0);
261 * Note about handling of error return of mcp251x_spi_trans: accessing
262 * registers via SPI is not really different conceptually than using
263 * normal I/O assembler instructions, although it's much more
264 * complicated from a practical POV. So it's not advisable to always
265 * check the return value of this function. Imagine that every
266 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
267 * error();", it would be a great mess (well there are some situation
268 * when exception handling C++ like could be useful after all). So we
269 * just check that transfers are OK at the beginning of our
270 * conversation with the chip and to avoid doing really nasty things
271 * (like injecting bogus packets in the network stack).
273 static int mcp251x_spi_trans(struct spi_device *spi, int len)
275 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
276 struct spi_transfer t = {
277 .tx_buf = priv->spi_tx_buf,
278 .rx_buf = priv->spi_rx_buf,
282 struct spi_message m;
285 spi_message_init(&m);
287 if (mcp251x_enable_dma) {
288 t.tx_dma = priv->spi_tx_dma;
289 t.rx_dma = priv->spi_rx_dma;
293 spi_message_add_tail(&t, &m);
295 ret = spi_sync(spi, &m);
297 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
301 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
303 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
306 mutex_lock(&priv->spi_lock);
308 priv->spi_tx_buf[0] = INSTRUCTION_READ;
309 priv->spi_tx_buf[1] = reg;
311 mcp251x_spi_trans(spi, 3);
312 val = priv->spi_rx_buf[2];
314 mutex_unlock(&priv->spi_lock);
319 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
321 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
323 mutex_lock(&priv->spi_lock);
325 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
326 priv->spi_tx_buf[1] = reg;
327 priv->spi_tx_buf[2] = val;
329 mcp251x_spi_trans(spi, 3);
331 mutex_unlock(&priv->spi_lock);
334 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
335 u8 mask, uint8_t val)
337 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
339 mutex_lock(&priv->spi_lock);
341 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
342 priv->spi_tx_buf[1] = reg;
343 priv->spi_tx_buf[2] = mask;
344 priv->spi_tx_buf[3] = val;
346 mcp251x_spi_trans(spi, 4);
348 mutex_unlock(&priv->spi_lock);
351 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
352 int len, int tx_buf_idx)
354 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
355 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
357 if (pdata->model == CAN_MCP251X_MCP2510) {
360 for (i = 1; i < TXBDAT_OFF + len; i++)
361 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
364 mutex_lock(&priv->spi_lock);
366 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
367 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
369 mutex_unlock(&priv->spi_lock);
373 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
376 u32 sid, eid, exide, rtr;
377 u8 buf[SPI_TRANSFER_BUF_LEN];
379 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
381 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
383 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
384 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
385 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
387 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
388 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
389 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
390 (exide << SIDL_EXIDE_SHIFT) |
391 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
392 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
393 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
394 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
395 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
396 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
397 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
400 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
403 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
404 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
406 if (pdata->model == CAN_MCP251X_MCP2510) {
409 for (i = 1; i < RXBDAT_OFF; i++)
410 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
412 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
413 for (; i < (RXBDAT_OFF + len); i++)
414 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
416 mutex_lock(&priv->spi_lock);
418 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
419 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
420 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
422 mutex_unlock(&priv->spi_lock);
426 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
428 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
430 struct can_frame *frame;
431 u8 buf[SPI_TRANSFER_BUF_LEN];
433 skb = alloc_can_skb(priv->net, &frame);
435 dev_err(&spi->dev, "cannot allocate RX skb\n");
436 priv->net->stats.rx_dropped++;
440 mcp251x_hw_rx_frame(spi, buf, buf_idx);
441 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
442 /* Extended ID format */
443 frame->can_id = CAN_EFF_FLAG;
445 /* Extended ID part */
446 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
447 SET_BYTE(buf[RXBEID8_OFF], 1) |
448 SET_BYTE(buf[RXBEID0_OFF], 0) |
449 /* Standard ID part */
450 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
451 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
452 /* Remote transmission request */
453 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
454 frame->can_id |= CAN_RTR_FLAG;
456 /* Standard ID format */
458 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
459 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
462 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
463 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
465 priv->net->stats.rx_packets++;
466 priv->net->stats.rx_bytes += frame->can_dlc;
470 static void mcp251x_hw_sleep(struct spi_device *spi)
472 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
475 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32)
476 static int mcp251x_hard_start_xmit(struct sk_buff *skb, struct net_device *net)
478 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
479 struct net_device *net)
482 struct mcp251x_priv *priv = netdev_priv(net);
483 struct spi_device *spi = priv->spi;
485 if (priv->tx_skb || priv->tx_len) {
486 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
487 netif_stop_queue(net);
488 return NETDEV_TX_BUSY;
491 if (can_dropped_invalid_skb(net, skb))
494 netif_stop_queue(net);
496 net->trans_start = jiffies;
497 queue_work(priv->wq, &priv->tx_work);
502 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
504 struct mcp251x_priv *priv = netdev_priv(net);
508 /* We have to delay work since SPI I/O may sleep */
509 priv->can.state = CAN_STATE_ERROR_ACTIVE;
510 priv->restart_tx = 1;
511 if (priv->can.restart_ms == 0)
512 priv->after_suspend = AFTER_SUSPEND_RESTART;
513 queue_work(priv->wq, &priv->irq_work);
522 static void mcp251x_set_normal_mode(struct spi_device *spi)
524 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
525 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
526 unsigned long timeout;
528 /* Enable interrupts */
529 mcp251x_write_reg(spi, CANINTE,
530 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
531 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
533 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
534 /* Put device into loopback mode */
535 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
537 /* Put device into normal mode */
538 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL |
539 ((pdata->model == CAN_MCP251X_MCP2515 &&
540 priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) ?
543 /* Wait for the device to enter normal mode */
544 timeout = jiffies + HZ;
545 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
547 if (time_after(jiffies, timeout)) {
548 dev_err(&spi->dev, "MCP251x didn't"
549 " enter in normal mode\n");
554 priv->can.state = CAN_STATE_ERROR_ACTIVE;
557 static int mcp251x_do_set_bittiming(struct net_device *net)
559 struct mcp251x_priv *priv = netdev_priv(net);
560 struct can_bittiming *bt = &priv->can.bittiming;
561 struct spi_device *spi = priv->spi;
563 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
565 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
566 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
568 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
570 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
571 (bt->phase_seg2 - 1));
572 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
573 mcp251x_read_reg(spi, CNF1),
574 mcp251x_read_reg(spi, CNF2),
575 mcp251x_read_reg(spi, CNF3));
580 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
581 struct spi_device *spi)
583 mcp251x_do_set_bittiming(net);
585 /* Enable RX0->RX1 buffer roll over and disable filters */
586 mcp251x_write_reg(spi, RXBCTRL(0),
587 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
588 mcp251x_write_reg(spi, RXBCTRL(1),
589 RXBCTRL_RXM0 | RXBCTRL_RXM1);
593 static void mcp251x_hw_reset(struct spi_device *spi)
595 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
597 unsigned long timeout;
599 mutex_lock(&priv->spi_lock);
601 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
603 ret = spi_write(spi, priv->spi_tx_buf, 1);
605 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
607 mutex_unlock(&priv->spi_lock);
609 /* Wait for reset to finish */
610 timeout = jiffies + HZ;
612 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
613 != CANCTRL_REQOP_CONF) {
615 if (time_after(jiffies, timeout)) {
616 dev_err(&spi->dev, "MCP251x didn't"
617 " enter in conf mode after reset\n");
623 static int mcp251x_hw_probe(struct spi_device *spi)
627 mcp251x_hw_reset(spi);
630 * Please note that these are "magic values" based on after
631 * reset defaults taken from data sheet which allows us to see
632 * if we really have a chip on the bus (we avoid common all
633 * zeroes or all ones situations)
635 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
636 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
638 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
640 /* Check for power up default values */
641 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
644 static irqreturn_t mcp251x_can_isr(int irq, void *dev_id)
646 struct net_device *net = (struct net_device *)dev_id;
647 struct mcp251x_priv *priv = netdev_priv(net);
649 /* Schedule bottom half */
650 if (!work_pending(&priv->irq_work))
651 queue_work(priv->wq, &priv->irq_work);
656 static int mcp251x_open(struct net_device *net)
658 struct mcp251x_priv *priv = netdev_priv(net);
659 struct spi_device *spi = priv->spi;
660 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
663 ret = open_candev(net);
665 dev_err(&spi->dev, "unable to set initial baudrate!\n");
669 if (pdata->transceiver_enable)
670 pdata->transceiver_enable(1);
672 priv->force_quit = 0;
676 ret = request_irq(spi->irq, mcp251x_can_isr,
677 IRQF_TRIGGER_FALLING, DEVICE_NAME, net);
679 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
680 if (pdata->transceiver_enable)
681 pdata->transceiver_enable(0);
686 mcp251x_hw_reset(spi);
687 ret = mcp251x_setup(net, priv, spi);
689 free_irq(spi->irq, net);
690 mcp251x_hw_sleep(spi);
691 if (pdata->transceiver_enable)
692 pdata->transceiver_enable(0);
696 mcp251x_set_normal_mode(spi);
697 netif_wake_queue(net);
702 static int mcp251x_stop(struct net_device *net)
704 struct mcp251x_priv *priv = netdev_priv(net);
705 struct spi_device *spi = priv->spi;
706 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
710 /* Disable and clear pending interrupts */
711 mcp251x_write_reg(spi, CANINTE, 0x00);
712 mcp251x_write_reg(spi, CANINTF, 0x00);
714 priv->force_quit = 1;
715 free_irq(spi->irq, net);
716 flush_workqueue(priv->wq);
718 mcp251x_write_reg(spi, TXBCTRL(0), 0);
719 if (priv->tx_skb || priv->tx_len)
722 mcp251x_hw_sleep(spi);
724 if (pdata->transceiver_enable)
725 pdata->transceiver_enable(0);
727 priv->can.state = CAN_STATE_STOPPED;
732 static void mcp251x_tx_work_handler(struct work_struct *ws)
734 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
736 struct spi_device *spi = priv->spi;
737 struct net_device *net = priv->net;
738 struct can_frame *frame;
741 frame = (struct can_frame *)priv->tx_skb->data;
743 if (priv->can.state == CAN_STATE_BUS_OFF) {
745 netif_wake_queue(net);
748 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
749 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
750 mcp251x_hw_tx(spi, frame, 0);
751 priv->tx_len = 1 + frame->can_dlc;
752 can_put_echo_skb(priv->tx_skb, net, 0);
757 static void mcp251x_irq_work_handler(struct work_struct *ws)
759 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
761 struct spi_device *spi = priv->spi;
762 struct net_device *net = priv->net;
764 enum can_state new_state;
766 if (priv->after_suspend) {
768 mcp251x_hw_reset(spi);
769 mcp251x_setup(net, priv, spi);
770 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
771 mcp251x_set_normal_mode(spi);
772 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
773 netif_device_attach(net);
774 /* Clean since we lost tx buffer */
775 if (priv->tx_skb || priv->tx_len) {
777 netif_wake_queue(net);
779 mcp251x_set_normal_mode(spi);
781 mcp251x_hw_sleep(spi);
783 priv->after_suspend = 0;
786 if (priv->can.restart_ms == 0 && priv->can.state == CAN_STATE_BUS_OFF)
789 while (!priv->force_quit && !freezing(current)) {
791 int can_id = 0, data1 = 0;
793 if (priv->restart_tx) {
794 priv->restart_tx = 0;
795 mcp251x_write_reg(spi, TXBCTRL(0), 0);
796 if (priv->tx_skb || priv->tx_len)
798 netif_wake_queue(net);
799 can_id |= CAN_ERR_RESTARTED;
802 intf = mcp251x_read_reg(spi, CANINTF);
804 if (intf & CANINTF_RX0IF) {
805 mcp251x_hw_rx(spi, 0);
806 /* Free one buffer ASAP */
807 mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF, 0x00);
810 if (intf & CANINTF_RX1IF)
811 mcp251x_hw_rx(spi, 1);
813 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
815 eflag = mcp251x_read_reg(spi, EFLG);
816 mcp251x_write_reg(spi, EFLG, 0x00);
818 /* Update can state */
819 if (eflag & EFLG_TXBO) {
820 new_state = CAN_STATE_BUS_OFF;
821 can_id |= CAN_ERR_BUSOFF;
822 } else if (eflag & EFLG_TXEP) {
823 new_state = CAN_STATE_ERROR_PASSIVE;
824 can_id |= CAN_ERR_CRTL;
825 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
826 } else if (eflag & EFLG_RXEP) {
827 new_state = CAN_STATE_ERROR_PASSIVE;
828 can_id |= CAN_ERR_CRTL;
829 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
830 } else if (eflag & EFLG_TXWAR) {
831 new_state = CAN_STATE_ERROR_WARNING;
832 can_id |= CAN_ERR_CRTL;
833 data1 |= CAN_ERR_CRTL_TX_WARNING;
834 } else if (eflag & EFLG_RXWAR) {
835 new_state = CAN_STATE_ERROR_WARNING;
836 can_id |= CAN_ERR_CRTL;
837 data1 |= CAN_ERR_CRTL_RX_WARNING;
839 new_state = CAN_STATE_ERROR_ACTIVE;
842 /* Update can state statistics */
843 switch (priv->can.state) {
844 case CAN_STATE_ERROR_ACTIVE:
845 if (new_state >= CAN_STATE_ERROR_WARNING &&
846 new_state <= CAN_STATE_BUS_OFF)
847 priv->can.can_stats.error_warning++;
848 case CAN_STATE_ERROR_WARNING: /* fallthrough */
849 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
850 new_state <= CAN_STATE_BUS_OFF)
851 priv->can.can_stats.error_passive++;
856 priv->can.state = new_state;
858 if ((intf & CANINTF_ERRIF) || (can_id & CAN_ERR_RESTARTED)) {
860 struct can_frame *frame;
862 /* Create error frame */
863 skb = alloc_can_err_skb(net, &frame);
865 /* Set error frame flags based on bus state */
866 frame->can_id = can_id;
867 frame->data[1] = data1;
869 /* Update net stats for overflows */
870 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
871 if (eflag & EFLG_RX0OVR)
872 net->stats.rx_over_errors++;
873 if (eflag & EFLG_RX1OVR)
874 net->stats.rx_over_errors++;
875 frame->can_id |= CAN_ERR_CRTL;
877 CAN_ERR_CRTL_RX_OVERFLOW;
883 "cannot allocate error skb\n");
887 if (priv->can.state == CAN_STATE_BUS_OFF) {
888 if (priv->can.restart_ms == 0) {
890 mcp251x_hw_sleep(spi);
898 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
899 net->stats.tx_packets++;
900 net->stats.tx_bytes += priv->tx_len - 1;
902 can_get_echo_skb(net, 0);
905 netif_wake_queue(net);
910 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
911 static const struct net_device_ops mcp251x_netdev_ops = {
912 .ndo_open = mcp251x_open,
913 .ndo_stop = mcp251x_stop,
914 .ndo_start_xmit = mcp251x_hard_start_xmit,
918 static int __devinit mcp251x_can_probe(struct spi_device *spi)
920 struct net_device *net;
921 struct mcp251x_priv *priv;
922 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
926 /* Platform data is required for osc freq */
929 /* Allocate can/net device */
930 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
936 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)
937 net->netdev_ops = &mcp251x_netdev_ops;
939 net->open = mcp251x_open;
940 net->stop = mcp251x_stop;
941 net->hard_start_xmit = mcp251x_hard_start_xmit;
943 net->flags |= IFF_ECHO;
945 priv = netdev_priv(net);
946 priv->can.bittiming_const = &mcp251x_bittiming_const;
947 priv->can.do_set_mode = mcp251x_do_set_mode;
948 priv->can.clock.freq = pdata->oscillator_frequency / 2;
950 dev_set_drvdata(&spi->dev, priv);
953 mutex_init(&priv->spi_lock);
955 /* If requested, allocate DMA buffers */
956 if (mcp251x_enable_dma) {
957 spi->dev.coherent_dma_mask = ~0;
960 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
961 * that much and share it between Tx and Rx DMA buffers.
963 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
968 if (priv->spi_tx_buf) {
969 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
971 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
974 /* Fall back to non-DMA */
975 mcp251x_enable_dma = 0;
979 /* Allocate non-DMA buffers */
980 if (!mcp251x_enable_dma) {
981 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
982 if (!priv->spi_tx_buf) {
986 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
987 if (!priv->spi_rx_buf) {
993 if (pdata->power_enable)
994 pdata->power_enable(1);
996 /* Call out to platform specific setup */
997 if (pdata->board_specific_setup)
998 pdata->board_specific_setup(spi);
1000 SET_NETDEV_DEV(net, &spi->dev);
1002 priv->wq = create_freezeable_workqueue("mcp251x_wq");
1004 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1005 INIT_WORK(&priv->irq_work, mcp251x_irq_work_handler);
1007 /* Configure the SPI bus */
1008 spi->mode = SPI_MODE_0;
1009 spi->bits_per_word = 8;
1012 if (!mcp251x_hw_probe(spi)) {
1013 dev_info(&spi->dev, "Probe failed\n");
1016 mcp251x_hw_sleep(spi);
1018 if (pdata->transceiver_enable)
1019 pdata->transceiver_enable(0);
1021 ret = register_candev(net);
1023 dev_info(&spi->dev, "probed\n");
1027 if (!mcp251x_enable_dma)
1028 kfree(priv->spi_rx_buf);
1030 if (!mcp251x_enable_dma)
1031 kfree(priv->spi_tx_buf);
1034 if (mcp251x_enable_dma)
1035 dma_free_coherent(&spi->dev, PAGE_SIZE,
1036 priv->spi_tx_buf, priv->spi_tx_dma);
1038 if (pdata->power_enable)
1039 pdata->power_enable(0);
1040 dev_err(&spi->dev, "probe failed\n");
1045 static int __devexit mcp251x_can_remove(struct spi_device *spi)
1047 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1048 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1049 struct net_device *net = priv->net;
1051 unregister_candev(net);
1054 priv->force_quit = 1;
1055 flush_workqueue(priv->wq);
1056 destroy_workqueue(priv->wq);
1058 if (mcp251x_enable_dma) {
1059 dma_free_coherent(&spi->dev, PAGE_SIZE,
1060 priv->spi_tx_buf, priv->spi_tx_dma);
1062 kfree(priv->spi_tx_buf);
1063 kfree(priv->spi_rx_buf);
1066 if (pdata->power_enable)
1067 pdata->power_enable(0);
1073 static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1075 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1076 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1077 struct net_device *net = priv->net;
1079 if (netif_running(net)) {
1080 netif_device_detach(net);
1082 mcp251x_hw_sleep(spi);
1083 if (pdata->transceiver_enable)
1084 pdata->transceiver_enable(0);
1085 priv->after_suspend = AFTER_SUSPEND_UP;
1087 priv->after_suspend = AFTER_SUSPEND_DOWN;
1090 if (pdata->power_enable) {
1091 pdata->power_enable(0);
1092 priv->after_suspend |= AFTER_SUSPEND_POWER;
1098 static int mcp251x_can_resume(struct spi_device *spi)
1100 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1101 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1103 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1104 pdata->power_enable(1);
1105 queue_work(priv->wq, &priv->irq_work);
1107 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1108 if (pdata->transceiver_enable)
1109 pdata->transceiver_enable(1);
1110 queue_work(priv->wq, &priv->irq_work);
1112 priv->after_suspend = 0;
1118 #define mcp251x_can_suspend NULL
1119 #define mcp251x_can_resume NULL
1122 static struct spi_driver mcp251x_can_driver = {
1124 .name = DEVICE_NAME,
1125 .bus = &spi_bus_type,
1126 .owner = THIS_MODULE,
1129 .probe = mcp251x_can_probe,
1130 .remove = __devexit_p(mcp251x_can_remove),
1131 .suspend = mcp251x_can_suspend,
1132 .resume = mcp251x_can_resume,
1135 static int __init mcp251x_can_init(void)
1137 return spi_register_driver(&mcp251x_can_driver);
1140 static void __exit mcp251x_can_exit(void)
1142 spi_unregister_driver(&mcp251x_can_driver);
1145 module_init(mcp251x_can_init);
1146 module_exit(mcp251x_can_exit);
1148 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1149 "Christian Pellegrin <chripell@evolware.org>");
1150 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1151 MODULE_LICENSE("GPL v2");