2 * @brief PINMUX Driver Implementation File
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8 /* (c) Texas Instruments 2009-2012, All rights reserved. */
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14 #define PINMUX_SET(REG, BALLID, MUX) \
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15 pinMuxReg->PINMUX##REG## = (pinMuxReg->PINMUX##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX##)
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17 #define PINMUX_GATE_EMIF_CLK_ENABLE \
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18 pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK
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20 #define PINMUX_GIOB_DISABLE_HET2_ENABLE \
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21 pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2
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23 #define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
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24 pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num##)
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26 #define PINMUX_ETHERNET_SELECT(interface) \
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27 pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface##)
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29 /* USER CODE BEGIN (0) */
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34 /* USER CODE BEGIN (1) */
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37 /* Enable Pin Muxing */
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38 kickerReg->KICKER0 = 0x83E70B13;
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39 kickerReg->KICKER1 = 0x95A4F1E0;
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41 /* USER CODE BEGIN (2) */
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44 pinMuxReg->PINMUX0 = PINMUX_BALL_C3_HET1_29 | PINMUX_BALL_B2_HET1_27;
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46 pinMuxReg->PINMUX1 = PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
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48 pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
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50 pinMuxReg->PINMUX3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
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52 pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
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54 pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
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56 pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
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58 pinMuxReg->PINMUX7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_HET1_25 | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_ETMDATA_30;
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60 pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_HET1_19 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
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62 pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_HET1_31 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_HET1_21;
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64 pinMuxReg->PINMUX10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
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66 pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
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68 pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_HET1_23 | PINMUX_BALL_H18_MIBSPI5NENA;
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70 pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
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72 pinMuxReg->PINMUX14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
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74 pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
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76 pinMuxReg->PINMUX16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
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78 pinMuxReg->PINMUX17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
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80 pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
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82 pinMuxReg->PINMUX19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
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84 pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_HET1_17 | PINMUX_BALL_C9_EMIF_ADDR_11;
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86 pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
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88 pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
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90 pinMuxReg->PINMUX23 = 0x01010100|
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91 PINMUX_BALL_C6_EMIF_ADDR_8;
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93 pinMuxReg->PINMUX24 = 0x01010101;
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95 pinMuxReg->PINMUX25 = 0x01010101;
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97 pinMuxReg->PINMUX26 = PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
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99 pinMuxReg->PINMUX27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
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101 pinMuxReg->PINMUX28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
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103 pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA;
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108 PINMUX_ALT_ADC_TRIGGER_SELECT(1);
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109 PINMUX_ETHERNET_SELECT(RMII);
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111 PINMUX_SET(0,A5,GIOA_0);
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112 PINMUX_SET(18,A11,HET1_14);
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113 PINMUX_SET(3,B3,HET1_22);
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114 PINMUX_SET(1,C2,GIOA_1);
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115 PINMUX_SET(21,K2,GIOB_1);
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116 PINMUX_SET(0,W10,GIOB_3);
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118 /* USER CODE BEGIN (3) */
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119 /* USER CODE END */
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121 /* Disable Pin Muxing */
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122 kickerReg->KICKER0 = 0x00000000;
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123 kickerReg->KICKER1 = 0x00000000;
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125 /* USER CODE BEGIN (4) */
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126 /* USER CODE END */
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129 /* USER CODE BEGIN (5) */
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130 /* USER CODE END */
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