// Options:
// Bit 13: Output Gain Selection bit set = 1x (VOUT = VREF * D/4096)
// Bit 15: DACA (0) or DACB (1) Selection bit.
-#define DAC1_INIT_VAL _BV(13)
-#define DAC2_INIT_VAL _BV(13) | _BV(15)
-#define DAC3_INIT_VAL _BV(13)
-#define DAC4_INIT_VAL _BV(13) | _BV(15)
+#define DAC1_INIT_VAL (_BV(13) )
+#define DAC2_INIT_VAL (_BV(13) | _BV(15))
+#define DAC3_INIT_VAL (_BV(13) )
+#define DAC4_INIT_VAL (_BV(13) | _BV(15))
/**
* Pin status for each DAC pin, the structure of each field is defined
// Options:
// Bit 13: Output Gain Selection bit set = 1x (VOUT = VREF * D/4096)
// Bit 15: DACA (0) or DACB (1) Selection bit.
-#define DACA_INIT_VAL _BV(13)
-#define DACB_INIT_VAL _BV(13) | _BV(15)
+#define DACA_INIT_VAL (_BV(13) | _BV(12) )
+#define DACB_INIT_VAL (_BV(13) | _BV(12) | _BV(15))
int8_t drv_din_ref(uint16_t ref_a, uint16_t ref_b)
{