From: Carlos Jenkins Date: Wed, 19 Jun 2013 18:05:59 +0000 (+0200) Subject: Fixed variable threshold digital inputs. X-Git-Tag: version_0.1~27^2~1 X-Git-Url: http://rtime.felk.cvut.cz/gitweb/pes-rpp/rpp-simulink.git/commitdiff_plain/c0d851e422011deb4e348f591e736ec74cc7a974 Fixed variable threshold digital inputs. --- diff --git a/rpp/lib/apps/rpp-test-suite/src/din.c b/rpp/lib/apps/rpp-test-suite/src/din.c index c70250a..e222537 100644 --- a/rpp/lib/apps/rpp-test-suite/src/din.c +++ b/rpp/lib/apps/rpp-test-suite/src/din.c @@ -99,7 +99,7 @@ void test_din() { /// Configure module // Configure voltage reference - rpp_din_ref(2048, 2048); + rpp_din_ref(900, 900); // Configure pins int pin; for(pin = 1; pin <= 16; pin++) { diff --git a/rpp/lib/rpp/src/drv/dac.c b/rpp/lib/rpp/src/drv/dac.c index dd2b296..8228550 100644 --- a/rpp/lib/rpp/src/drv/dac.c +++ b/rpp/lib/rpp/src/drv/dac.c @@ -34,10 +34,10 @@ // Options: // Bit 13: Output Gain Selection bit set = 1x (VOUT = VREF * D/4096) // Bit 15: DACA (0) or DACB (1) Selection bit. -#define DAC1_INIT_VAL _BV(13) -#define DAC2_INIT_VAL _BV(13) | _BV(15) -#define DAC3_INIT_VAL _BV(13) -#define DAC4_INIT_VAL _BV(13) | _BV(15) +#define DAC1_INIT_VAL (_BV(13) ) +#define DAC2_INIT_VAL (_BV(13) | _BV(15)) +#define DAC3_INIT_VAL (_BV(13) ) +#define DAC4_INIT_VAL (_BV(13) | _BV(15)) /** * Pin status for each DAC pin, the structure of each field is defined diff --git a/rpp/lib/rpp/src/drv/din.c b/rpp/lib/rpp/src/drv/din.c index 135bf68..1cb26f8 100644 --- a/rpp/lib/rpp/src/drv/din.c +++ b/rpp/lib/rpp/src/drv/din.c @@ -54,8 +54,8 @@ const static uint32_t dsc_pin_map[8U] = { // Options: // Bit 13: Output Gain Selection bit set = 1x (VOUT = VREF * D/4096) // Bit 15: DACA (0) or DACB (1) Selection bit. -#define DACA_INIT_VAL _BV(13) -#define DACB_INIT_VAL _BV(13) | _BV(15) +#define DACA_INIT_VAL (_BV(13) | _BV(12) ) +#define DACB_INIT_VAL (_BV(13) | _BV(12) | _BV(15)) int8_t drv_din_ref(uint16_t ref_a, uint16_t ref_b) {