Old functions from fray.c file used in fr_tms570.c file were moved into fr_tms570.c and renamed
Old unused functions from fray.c file were deleted.
Macros from fray.h file moved into fr_tms570.h file.
Unused macros from ti_drv_fr.h deleted
Comments tuned
Some variables and functions redefined as static.
#include "drv/Std_Types.h"
#include "drv/Fr_GeneralTypes.h"
-/* Development error detection
- * Comment to disable error detection and make function processing faster.
- */
-
-#define DET_ACTIVATED
-
-
/* Protocol constants */
#define cCASActionPointOffset 1 /**< Initialization value of the CAS action point offset timer. Units MT */
#define cChannelIdleDelimiter 11 /**< Duration of the channel idle delimiter. Units gdBit */
/* Flags for indicating error during parameters check */
#define ERR_PARAM_NO_ERROR 0
+
/* Global parameters errors */
#define ERR_PARAM_gColdStartAttempts (1 << 1)
#define ERR_PARAM_gdActionPointOffset (1 << 2)
#define ERR_PARAM_gdNIT (1 << 23)
#define ERR_PARAM_gdSampleClockPeriod (1 << 24)
#define ERR_PARAM_gNetworkManagementVectorLength (1 << 25)
+
/* Local parameters errors */
#define ERR_PARAM_pAllowHaltDueToClock (1 << 1)
#define ERR_PARAM_pAllowPassiveToActive (1 << 2)
#define ERR_PARAM_pSamplesPerMicrotick (1 << 24)
#define ERR_PARAM_pDecodingCorrection (1 << 25)
#define ERR_PARAM_pOffsetCorrectionOut (1 << 26)
+
/* Message RAM parameters errors */
#define ERR_PARAM_statSegmentBufferCount (1 << 0)
#define ERR_PARAM_dynSegmentBufferCount (1 << 1)
#define ERR_PARAM_fifoBufferCount (1 << 2)
#define ERR_PARAM_maxBuffLimit (1 << 3)
-/* Buffer congiguratin parameters errors */
+
+/* Buffer configuration parameters errors */
#define ERR_PARAM_BUFFIFO_PAYLOAD_HIGH (1 << 0)
#define ERR_PARAM_BUFFIFO_NOT_RX (1 << 1)
#define ERR_PARAM_BUFFIFO_PAYLOAD_DIFFERS (1 << 2)
#define ERR_PARAM_BUFSTAT_PAYLOAD_HIGH (1 << 8)
#define ERR_PARAM_BUF_TOTAL_PAYLOAD_HIGH (1 << 9)
#define ERR_PARAM_BUFDYN_CHANNELS (1 << 10)
-/* Error codes */
+
+/* Error codes for controller initialization */
#define FR_INIT_ERR_BAD_PARAM (1 << 26)
#define FR_INIT_ERR_CLUSTER_CONFIG (1 << 27)
#define FR_INIT_ERR_NODE_CONFIG (1 << 28)
#define FR_INIT_ERR_BUFFPARAM_CONFIG (1 << 30)
#define FR_INIT_ERR_BUFF_CONFIG (1 << 31)
+/* Error flags for startup failures */
#define FR_STARTUP_ERR_SW_STUP_FOLLOW (1 << 26)
#define FR_STARTUP_ERR_CSINH_DIS (1 << 27)
#define FR_STARTUP_ERR_SW_STUP_READY (1 << 28)
/* TMS570 FlexRay related constants */
#define FR_MAX_BUFFERS_CNT 128
#define FR_FCS_LISTEN_TIMEOUT 10000000U
+
+/* Macros with constants for FlexRay POC status, read from CCEV register */
#define FR_POCS_DEFAULT_CONFIG 0x0
#define FR_POCS_READY 0x1
#define FR_POCS_NORMAL_ACTIVE 0x2
#define FR_POCS_INTEGRATION_CONSISTENCY_CHECK 0x28
#define FR_POCS_INITIALIZE_SCHEDULE 0x29
#define FR_POCS_ABORT_STARTUP 0x2A
+
+/* Macros with constants for Wakeup status read from CCEV register */
#define FR_WSV_UNDEFINED 0x0
#define FR_WSV_RECEIVED_HEADER 0x1
#define FR_WSV_RECEIVED_WUP 0x2
#define FR_WSV_COLLISION_UNKNOWN 0x5
#define FR_WSV_TRANSMITTED 0x6
-
-
-
-
-
+/* Macros with constants for SPI communication with the bus controller */
+#define FRAY_SPICMD_INIT_VAL 0xFFFF
+#define FRAY_NUM_PORTS 2
+
+/* Macros with flags for buffers configuration */
+#define FRAY_BUF_MBI_EN 0x01
+#define FRAY_BUF_MBI_DIS 0x00
+#define FRAY_BUF_TX_MODE_CONTINUOUS 0x02
+#define FRAY_BUF_TX_MODE_SINGLE 0x00
+#define FRAY_BUF_NM_EN 0x04
+#define FRAY_BUF_NM_DIS 0x00
+#define FRAY_BUF_TX 0x08
+#define FRAY_BUF_RX 0x00
+#define FRAY_BUF_CHB_EN 0x10
+#define FRAY_BUF_CHB_DIS 0x00
+#define FRAY_BUF_CHA_EN 0x20
+#define FRAY_BUF_CHA_DIS 0x00
+#define FRAY_BUF_SFI_EN 0x40
+#define FRAY_BUF_SFI_DIS 0x00
+#define FRAY_BUF_SYNC_EN 0x80
+#define FRAY_BUF_SYNC_DIS 0x00
+#define FRAY_BUF_REJECT_NULL_FRAMES 0x100
+#define FRAY_BUF_ACCEPT_NULL_FRAMES 0x000
+#define FRAY_BUF_REJECT_STATIC_SEGMENT 0x200
+#define FRAY_BUF_ACCEPT_STATIC_SEGMENT 0x000
+#define FRAY_BUF_TXREQ_EN 0x800
+#define FRAY_BUF_TXREQ_DIS 0x000
+
+#define FR_CLUSTER_PARAMS_CNT 25
+#define FR_NODE_PARAMS_CNT 26
+#define FR_MSGRAM_PARAMS_CNT 5
+#define FR_STATIC_BUF_PARAMS_CNT 8
+#define FR_DYNAMIC_BUF_PARAMS_CNT 7
+#define FR_FIFO_BUF_PARAMS_CNT 6
/**
* This structure represents global FlexRay cluster parameters.
* Values of all those parameters have to be equal for all nodes in cluster.
*/
Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t* Fr_ConfigParamValuePtr);
+/**
+ * @brief Function sends prepared command on SPI and stores response
+ *
+ * @param[in] port Index of flexray 0 or 1
+ * @return 0 when success, -1 when bad parameter
+ */
+int Fr_spi_transfer(uint8_t port);
+
+/**
+ * @brief Returns last spi response of selected fray port
+ *
+ * @param[in] port Index of flexray 0 or 1
+ * @return spi response or -1 when bad parameter
+ */
+int Fr_spi_response(uint8_t port);
+
+/**
+ * @brief Returns last spi command of selected fray port
+ *
+ * @param[in] port Index of flexray 0 or 1
+ * @return spi command or -1 when bad parameter
+ */
+int Fr_spi_get_cmd(uint8_t port);
+
#endif /* FR_H_ */
/*
- * fray_spi.h
+ * fray.h
*
* Created on: 12.2.2013
* Author: Michal Horn
+ *
+ * This file contains
*/
-#ifndef FRAY_SPI_H_
-#define FRAY_SPI_H_
-
-//#include "hal_port_def.h"
-//#include "ti_drv_fray.h"
-#include "drv/drv.h"
-
-#define FRAY_SPICMD_INIT_VAL 0xFFFF
-#define FRAY_NUM_PORTS 2
-
-#define FRAY_BUF_MBI_EN 0x01
-#define FRAY_BUF_MBI_DIS 0x00
-#define FRAY_BUF_TX_MODE_CONTINUOUS 0x02
-#define FRAY_BUF_TX_MODE_SINGLE 0x00
-#define FRAY_BUF_NM_EN 0x04
-#define FRAY_BUF_NM_DIS 0x00
-#define FRAY_BUF_TX 0x08
-#define FRAY_BUF_RX 0x00
-#define FRAY_BUF_CHB_EN 0x10
-#define FRAY_BUF_CHB_DIS 0x00
-#define FRAY_BUF_CHA_EN 0x20
-#define FRAY_BUF_CHA_DIS 0x00
-#define FRAY_BUF_SFI_EN 0x40
-#define FRAY_BUF_SFI_DIS 0x00
-#define FRAY_BUF_SYNC_EN 0x80
-#define FRAY_BUF_SYNC_DIS 0x00
-#define FRAY_BUF_REJECT_NULL_FRAMES 0x100
-#define FRAY_BUF_ACCEPT_NULL_FRAMES 0x000
-#define FRAY_BUF_REJECT_STATIC_SEGMENT 0x200
-#define FRAY_BUF_ACCEPT_STATIC_SEGMENT 0x000
-#define FRAY_BUF_TXREQ_EN 0x800
-#define FRAY_BUF_TXREQ_DIS 0x000
-
-#define FRAY_ERR_CSINH_DIS -1
-#define FRAY_ERR_SW_CFG_READY -2
-#define FRAY_ERR_SW_STUP_AS_NCOLD -3
-#define FRAY_ERR_SW_STUP_FOLLOW -4
-#define FRAY_ERR_SW_STUP_READY -5
-
+#ifndef FRAY_H_
+#define FRAY_H_
-int fray_spi_transfer(uint8_t port);
-int fray_spi_response(uint8_t port);
-int fray_spi_get_cmd(uint8_t port);
-int fray_clear_msg_ram();
-void fray_wait_for_POC_ready();
-void fray_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer);
-void fray_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer);
-void fray_prepare_LPdu(const wrhs *Fr_LPduPtr);
-void fray_transmit_tx_LPdu(const bc *Fr_LSduPtr);
-void fray_receive_rx_LPdu(const bc *Fr_LSduPtr);
-int fray_controler_init();
-void fray_init_irq();
-void fray_buffer_set_data(uint32_t buf_num, const uint32_t* data, uint32_t len);
-void fray_buffer_transmit_data(uint32_t buf_num);
-void fray_buffer_get_data(uint32_t buf_num, uint32_t* data, uint32_t len);
-void fray_buffer_receive_data_header(uint32_t buf_num);
-void fray_wait_for_new_cycle();
-int fray_buffer_message_received(uint32_t buf_num);
-int fr_startup_procedure();
-int fray_go_to_ready_state_from_config_state(void);
-int fray_go_to_ready_state_from_startup_state(void);
-int fray_go_to_startup_state(void);
-void fray_delay();
-int fray_halt(void);
-int fray_header_crc_calc(const wrhs *Fr_LPduPtr);
-void fray_init(const cfg *Fr_ConfigPtr);
-int fray_startup_procedure(int is_coldstart);
-int fray_allow_coldstart(void);
#endif /* FRAY_SPI_H_ */
#define CMD_CLEAR_RAMS 0xC
#define CMD_ASYNCHRONOUS_TRANSFER_MODE 0xE
-// Masks for fields in configuration registers, used in init functions
+// Masks for fields in configuration registers
#define SUCC1_CSA_MSK (0x1F << 11)
-#define GTUC9_APO_MSK (0x3F << 0)
-#define PRTC1_CASM_MSK (0x7F << 4)
-#define GTUC9_DSI_MSK (0x3 << 16)
-#define GTUC8_MSL_MSK (0x3F << 0)
-#define GTUC9_MAPO_MSK (0x1F << 8)
-#define GTUC7_SSL_MSK (0x3FF << 0)
-#define PRTC1_TSST_MSK (0x7 << 0)
-#define PRTC2_RXI_MSK (0x3F << 0)
-#define PRTC2_RXL_MSK (0x3F << 8)
-#define PRTC1_RXW_MSK (0x1FF << 16)
-#define PRTC2_TXI_MSK (0xFF << 16)
-#define PRTC2_TXL_MSK (0x1F << 24)
-#define SUCC2_LTN_MSK (0xF << 24)
-#define GTUC2_MPC_MSK (0x3FFF << 0)
-#define SUCC3_WCF_MSK (0xF << 4)
-#define SUCC3_WCP_MSK (0xF << 0)
-#define SUCC8_NMS_MSK (0x1FFF << 16)
-#define GTUC4_OCS_MSK (0x3FFF << 16)
-#define MHDC_SFDL_MSK (0xFF << 0)
-#define GTUC2_SNM_MSK (0xF << 16)
-#define SUCC1_CCHA_MSK (0x1 << 26)
-#define SUCC1_CCHB_MSK (0x1 << 27)
-#define GTUC5_CDD_MSK (0x1F << 16)
-#define GTUC4_NIT_MSK (0x3FFF << 0)
-#define PRTC1_BRP_MSK (0x3 << 14)
-#define NEMC_NML_MSK (0x7F << 0)
-#define SUCC1_HCSE_MSK (0x1 << 23)
-#define SUCC1_PTA_MSK (0x1F << 16)
-#define GTUC6_ASR_MSK (0x7FF << 0)
-#define GTUC5_CDD_MSK (0x1F << 16)
-#define GTUC5_DEC_MSK (0xFF << 24)
-#define GTUC5_DCA_MSK (0xFF << 0)
-#define GTUC5_DCB_MSK (0xFF << 8)
-#define SUCC2_LT_MSK (0x1FFFFF << 8)
-#define GTUC6_MOD_MSK (0x7FF << 16)
-#define GTUC11_EOC_MSK (0x7 << 16)
-#define GTUC11_ERC_MSK (0x7 << 24)
-#define SUCC1_TXST_MSK (0x1 << 8)
-#define SUCC1_TXSY_MSK (0x1 << 9)
-#define MHDC_SLT_MSK (0x1FFF << 16)
-#define GTUC3_MIOA_MSK (0x7F << 16)
-#define GTUC3_MIOB_MSK (0x7F << 24)
-#define GTUC3_UIOA_MSK (0xFF << 0)
-#define GTUC3_UIOB_MSK (0xFF << 8)
-#define GTUC1_UT_MSK (0xFFFFF << 0)
-#define GTUC10_MOC_MSK (0x3FFF << 0)
-#define SUCC1_TSM_MSK (0x1 << 22)
-#define SUCC1_WUCS_MSK (0x1 << 21)
-#define PRTC1_RWP_MSK (0x3F << 26)
-#define GTUC8_NMS_MSK (0x1FFF << 16)
-#define GTUC7_NSS_MSK (0x3FF << 16)
-#define MRC_FDB_MSK (0xFF << 0)
-#define MRC_FFB_MSK (0xFF << 8)
-#define MRC_LCB_MSK (0xFF << 16)
-#define MRC_SEC_MSK (0x3 << 24)
-#define MRC_SPLM_MSK (0x1 << 26)
-#define FRF_RNF_MSK (0x1 << 24)
-#define FRF_RSS_MSK (0x1 << 23)
-#define FRF_CYF_MSK (0x7FF << 16)
-#define FRF_FID_MSK (0x7FF << 2)
-#define FRF_CH_MSK (0x3 << 0)
#define MTCCV_CCV_MSK (0x3F << 16)
#define MTCCV_MTV_MSK (0x3F << 0)
#define ESID_RXEA_MSK (0x1 << 14)
#define OSID_RXOB_MSK (0x1 << 15)
#define OSID_OID_MSK (0x3F << 0)
-
-
typedef volatile struct fray_registers
{
/* ------------------------------------------------------------------------- */
#include "drv/fr_tms570.h"
#include "sys/ti_drv_fray.h"
-#include "drv/fray.h"
#include "binary.h"
+#include "hal/port_def.h"
-Std_VersionInfoType Fr_versionInfo = {
+static Std_VersionInfoType Fr_versionInfo = {
.vendorID = 0x00000001,
.moduleID = 0x00000002,
.sw_major_version = 0,
.sw_patch_version = 0
};
+/** Prepared spi command */
+static uint32_t fray_spi_cmd = FRAY_SPICMD_INIT_VAL;
+/** Shadow variable used during command sending */
+static uint32_t fray_spi_cmd_sh;
+/** Array of responses for each fray driver */
+static uint32_t fray_spi_resp[FRAY_NUM_PORTS];
+/** Array of port names to be easily accessible by indexing */
+static const char* fray_port_names[FRAY_NUM_PORTS] = { PORT_NAME_FRAY1, PORT_NAME_FRAY2 };
+/** Array of integers, where FlexRay cluster and node configuration
+ * parameters are stored to be accessible by indexes defined in Fr_GeneralTypes.h.
+ */
static uint32_t Fr_ConfigParPtrs[FR_CIDX_CNT];
-const Fr_ConfigType* Fr_Config;
-const Fr_TMS570LS_BufferConfigType* Fr_BuffersPtrs[FR_MAX_BUFFERS_CNT]; /** < Array of address of configuration data to each buffer. */
-boolean_t Fr_BuffersConfigured[FR_MAX_BUFFERS_CNT]; /**< Array of flags to determine if the buffer was or was not configured. */
-int Fr_MsgRAMDataPtrs[FR_MAX_BUFFERS_CNT]; /**< Array of computed data pointers addresses for each buffer. */
-uint32_t Fr_MsgRAMDataOffset; /**< Address of the next free position in message RAM, which can be assigned to configured buffer. Addresses 32b words. */
-uint32_t Fr_MsgRAMDataStartAddress; /**< Address of the first free position in message RAM, which can be assigned to the first configured buffer. Addresses 32b words. */
+/**
+ * Address of the unified structure with complete configuration of
+ * the FlexRay node (cluster, node, message RAM and buffer configuration)
+ */
+static const Fr_ConfigType* Fr_Config;
+/** Array of address of configuration data to each buffer. */
+static const Fr_TMS570LS_BufferConfigType* Fr_BuffersPtrs[FR_MAX_BUFFERS_CNT];
+/** Array of flags to determine if the buffer was or was not configured. */
+static boolean_t Fr_BuffersConfigured[FR_MAX_BUFFERS_CNT];
+/** Array of computed data pointers addresses for each buffer. */
+static int Fr_MsgRAMDataPtrs[FR_MAX_BUFFERS_CNT];
+/**
+ * Address of the next free position in message RAM, which can be assigned
+ * to configured buffer. Addresses 32b words.
+ */
+static uint32_t Fr_MsgRAMDataOffset;
+/**
+ * Address of the first free position in message RAM, which can be assigned
+ * to the first configured buffer. Addresses 32b words.
+ */
+static uint32_t Fr_MsgRAMDataStartAddress;
+
+/**
+ * Development error detection.
+ * Comment this line to disable error detection and make function processing
+ * faster, but more dangerous.
+ */
+
+#define DET_ACTIVATED
+
+
#ifdef DET_ACTIVATED
-Fr_TMS570LS_DriverState Fr_DrvState = FR_ST_DRV_NOT_INITIALIZED;
+/**
+ * A variable for driver state monitoring. The state value is used in several
+ * functions to determine if they are called in right order.
+ */
+static Fr_TMS570LS_DriverState Fr_DrvState = FR_ST_DRV_NOT_INITIALIZED;
#endif
+/**
+ * Compute CRC for message RAM header data
+ *
+ * @param[in] Fr_LPduPtr Pointer to header data
+ * @return CRC code
+ */
+static int Fr_header_crc_calc(const wrhs *Fr_LPduPtr) {
+ unsigned int header;
+
+ int CrcInit = 0x1A;
+ int length = 20;
+ int CrcNext;
+ unsigned long CrcPoly = 0x385;
+ unsigned long CrcReg_X = CrcInit;
+ unsigned long header_temp, reg_temp;
+
+ header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
+ header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
+
+ header <<= 11;
+ CrcReg_X <<= 21;
+ CrcPoly <<= 21;
+
+ while(length--) {
+ header <<= 1;
+ header_temp = header & 0x80000000;
+ reg_temp = CrcReg_X & 0x80000000;
+
+ if(header_temp ^ reg_temp){ // Step 1
+ CrcNext = 1;
+ } else {
+ CrcNext = 0;
+ }
+
+ CrcReg_X <<= 1; // Step 2
+
+ if(CrcNext) {
+ CrcReg_X ^= CrcPoly; // Step 3
+ }
+ }
+
+ CrcReg_X >>= 21;
+
+ return CrcReg_X;
+}
+
+/**
+ * Retrieve data and header from message buffer into output buffer.
+ *
+ * Upper software layers have to read the header and data from RDDS and RDHS registers.
+ * @param[in] buf_num Number of buffer
+ */
+static void Fr_buffer_receive_data_header(uint32_t buf_num) {
+ bc read_buffer;
+
+ read_buffer.obrs=buf_num; // output buffer number
+ read_buffer.rdss=1; // read data section
+ read_buffer.rhss=1; // read header section
+
+ // ensure no transfer in progress on shadow registers
+ while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
+ frayREG->OBCM_UN.OBCM_UL=(((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
+ frayREG->OBCR_UN.OBCR_UL=((1 << 9) | (read_buffer.obrs & 0x3F)); //req=1, view=0
+ // wait for completion on shadow registers
+ while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
+
+ frayREG->OBCM_UN.OBCM_UL=(((read_buffer.rdss & 0x1) << 1) | (read_buffer.rhss & 0x1));
+ frayREG->OBCR_UN.OBCR_UL=((1 << 8) | (read_buffer.obrs & 0x3F)); //req=0, view=1
+
+}
+
+/**
+ * Transfer data to the message RAM using the input buffer
+ *
+ * @param[in] Fr_LSduPtr Pointer to data structure with input buffer settings
+ */
+inline void Fr_transmit_tx_LPdu(const bc *Fr_LSduPtr) {
+ // ensure nothing is pending
+ while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0);
+ frayREG->IBCM_UN.IBCM_UL=((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
+ frayREG->IBCR_UN.IBCR_UL=(Fr_LSduPtr->ibrh & 0x3F);
+ // optimization possible for future by not gating like below
+ // wait for completion on host registers
+ while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0));
+ // wait for completion on shadow registers
+ while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0));
+}
+
+/**
+ * Fill the buffer configuration data structure with given data and transfer it to the message RAM header using the input buffer.
+ *
+ * @param[in] buf_num number of buffer to be configured (0-128)
+ * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
+ * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
+ * @param[in] frame_id Id of the frame to be associated with the buffer
+ * @param[in] payload Maximum data size in half-word
+ * @param[in] data_pointer Address of the first word of data in buffer
+ */
+static void Fr_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
+ wrhs Fr_LPdu;
+ bc Fr_LSdu;
+ int wrhs1;
+ int wrhs2;
+
+ Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
+ Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 0 : 1; // transmission mode(0=continuous mode, 1=single mode)
+ Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
+ Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
+ Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
+ Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
+ Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
+ Fr_LPdu.fid = frame_id; // Frame ID
+
+ // Write Header Section 2 (WRHS2)
+ Fr_LPdu.pl = payload; // Payload Length
+
+ // Write Header Section 3 (WRHS3)
+ Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
+
+ Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
+ Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
+
+ // Write Header Section 2 (WRHS2)
+ Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? Fr_header_crc_calc(&Fr_LPdu) : 0;
+
+ // Input buffer configuration
+ Fr_LSdu.ibrh = buf_num; // input buffer number
+ Fr_LSdu.ibsyh = 1; // check for input buffer busy host
+ Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
+
+ Fr_LSdu.stxrh= (mode&FRAY_BUF_TXREQ_EN) ? 1 : 0; // set transmission request
+ Fr_LSdu.ldsh = 0; // load data section
+ Fr_LSdu.lhsh = 1; // load header section
+ Fr_LSdu.obrs = 0; // output buffer number
+ Fr_LSdu.rdss = 0; // read data section
+ Fr_LSdu.rhss = 0; // read header section
+
+ wrhs1 = ((Fr_LPdu.mbi) & 0x1) <<29;
+ wrhs1 |= (Fr_LPdu.txm & 0x1) << 28;
+ wrhs1 |= (Fr_LPdu.ppit & 0x1) << 27;
+ wrhs1 |= (Fr_LPdu.cfg & 0x1) << 26;
+ wrhs1 |= (Fr_LPdu.chb & 0x1) << 25;
+ wrhs1 |= (Fr_LPdu.cha & 0x1) << 24;
+ wrhs1 |= (Fr_LPdu.cyc & 0x7F) << 16;
+ wrhs1 |= (Fr_LPdu.fid & 0x7FF);
+ frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
+
+ wrhs2 = ((Fr_LPdu.pl & 0x7F) << 16) | (Fr_LPdu.crc & 0x7FF);
+ frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
+
+ frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPdu.dp & 0x7FF);
+
+ Fr_transmit_tx_LPdu(&Fr_LSdu);
+}
+
+/**
+ * Fill FIFO filter rejection configuration and configure the buffer.
+ *
+ * @param[in] buf_num number of buffer to be configured (0-128)
+ * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
+ * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
+ * @param[in] frame_id Id of the frame to be associated with the buffer
+ * @param[in] payload Maximum data size in half-word
+ * @param[in] data_pointer Address of the first word of data in buffer
+ */
+static void Fr_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
+ frayREG->FRF_UN.FRF_ST.rnf = (mode&FRAY_BUF_REJECT_NULL_FRAMES) ? 1 : 0;
+ frayREG->FRF_UN.FRF_ST.rss = (mode&FRAY_BUF_REJECT_STATIC_SEGMENT) ? 1 : 0;
+ frayREG->FRF_UN.FRF_ST.fid_B11 = frame_id;
+ frayREG->FRFM_UN.FRFM_ST.mfid_B11 = 0x0;
+ frayREG->FRF_UN.FRF_ST.cyf_B7 = cyc_filter;
+ if (mode&FRAY_BUF_CHB_EN && mode&FRAY_BUF_CHA_EN) {
+ frayREG->FRF_UN.FRF_ST.ch_B2 = 0;
+ }
+ else if (mode&FRAY_BUF_CHA_EN) {
+ frayREG->FRF_UN.FRF_ST.ch_B2 = 3;
+ }
+ else {
+ frayREG->FRF_UN.FRF_ST.ch_B2 = 2;
+ }
+ frame_id = 0;
+ Fr_config_buffer(buf_num, mode, cyc_filter, frame_id, payload, data_pointer);
+}
+
+/**
+ * Load data to message buffer. Data must be copied into WRDS register before this function is called.
+ *
+ * @param[in] buf_num Number of buffer
+ * @param[in] len Number of words to be loaded from data to buffer
+ */
+static void Fr_buffer_transmit_data(uint32_t buf_num) {
+ bc write_buffer;
+
+ write_buffer.ibrh = buf_num; // input buffer number
+ write_buffer.stxrh= 1; // set transmission request
+ write_buffer.ldsh = 1; // load data section
+ write_buffer.lhsh = 0; // load header section
+ write_buffer.ibsys = 0; // check for input buffer busy shadow
+ write_buffer.ibsyh = 1; // check for input buffer busy host
+ Fr_transmit_tx_LPdu(&write_buffer);
+}
+
+
/** @fn wait_for_POC_ready(void)
* @brief Wait until POC is not busy
*/
-void Fr_wait_for_POC_ready() {
+inline void Fr_wait_for_POC_ready() {
// Wait for PBSY bit to clear - POC not busy.
// 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
}
+/** @fn clear_msg_ram(void)
+* @brief Clears FRAY message RAMs
+*
+* Send command to POC to set all bits of message RAM to 0.
+* @return SUCCESS or FAILURE when command was not accepted
+*/
+static int Fr_clear_msg_RAM() {
+ Fr_wait_for_POC_ready();
+ frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
+ if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) {
+ return FAILURE;
+ }
+ Fr_wait_for_POC_ready();
+ return SUCCESS;
+}
+
+
/**
* @brief Switch POC to config state from any other state
*
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-Std_ReturnType Fr_POC_go_to_config() {
+static Std_ReturnType Fr_POC_go_to_config() {
// write SUCC1 configuration
frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CONFIG;
// Check if POC has accepted last command
return E_OK;
}
-/**
- * @brief Switch POC to clear_message_ram state from default_config and config state
- *
- * Send command to POC to set all bits of message RAM to 0. Returns when cleaning is done,
- * resulting in POC switch to origin state.
- *
- * @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
- */
-Std_ReturnType Fr_POC_go_to_clear_rams() {
- Fr_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) {
- return E_NOT_OK;
- }
- Fr_wait_for_POC_ready();
- return E_OK;
-}
-
/**
* @brief Switch POC to ready state from config state
*
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-Std_ReturnType Fr_POC_go_to_ready_from_config() {
+static Std_ReturnType Fr_POC_go_to_ready_from_config() {
Fr_wait_for_POC_ready();
// For CHA and CHB network
if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-Std_ReturnType Fr_POC_go_to_ready_from_startup() {
+static Std_ReturnType Fr_POC_go_to_ready_from_startup() {
Fr_wait_for_POC_ready();
frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
*
* @return E_OK: Call finished successfuly. E_NOT_OK: POC has not accepted command.
*/
-Std_ReturnType Fr_POC_go_to_startup() {
+static Std_ReturnType Fr_POC_go_to_startup() {
Fr_wait_for_POC_ready();
frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
}
/* Clear message RAM */
- if (fray_clear_msg_ram() == FAILURE) {
+ if (Fr_clear_msg_RAM() == FAILURE) {
return E_NOT_OK;
}
} while ( (state_value != FR_POCS_NORMAL_ACTIVE) && (state_value != FR_POCS_INTEGRATION_LISTEN));
if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == FR_POCS_NORMAL_ACTIVE) // Success, break the start up loop
break;
- // fray_delay();
if (Fr_POC_go_to_ready_from_startup() == E_NOT_OK) { // No success. Switch back to READY state
return E_NOT_OK | FR_STARTUP_ERR_SW_STUP_READY;
}
}
frayREG->WRDS[word] = buffer;
}
- fray_buffer_transmit_data(bufferIndex);
+ Fr_buffer_transmit_data(bufferIndex);
return E_OK;
}
}
mode |= (Fr_BuffersPtrs[i]->rejectStaticSegment == TRUE) ? FRAY_BUF_REJECT_STATIC_SEGMENT : FRAY_BUF_ACCEPT_STATIC_SEGMENT;
mode |= FRAY_BUF_TXREQ_DIS;
if (Fr_BuffersPtrs[i]->isTx == TRUE) {
- fray_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
+ Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
#ifdef DET_ACTIVATED
canceled = TRUE;
#endif
*/
// FIXME: Receiving for FID rejection filter other than zero is not working. Why?
if (bufferIndex >= frayREG->MRC_UN.MRC_ST.ffb_B8 && frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) { // This is RX FIFO buffer and it is not empty
- fray_buffer_receive_data_header(frayREG->MRC_UN.MRC_ST.ffb_B8); // Consume first element from FIFO
+ Fr_buffer_receive_data_header(frayREG->MRC_UN.MRC_ST.ffb_B8); // Consume first element from FIFO
if (frayREG->FSR_UN.FSR_ST.rfne_B1 == 1) { // FIFO not empty after last pop
*Fr_LPduStatusPtr = FR_RECEIVED_MORE_DATA_AVAILABLE;
}
}
else { // Static/dynamic segment buffer
if (*ndat[bufferIndex/32] & (0x1 << bufferIndex%32)) { // New data received
- fray_buffer_receive_data_header(bufferIndex); // Read data and header into output buffer
+ Fr_buffer_receive_data_header(bufferIndex); // Read data and header into output buffer
*Fr_LPduStatusPtr = FR_RECEIVED;
}
else { // No new data received
}
Fr_MsgRAMDataPtrs[i] = Fr_MsgRAMDataOffset;
if (i >= frayREG->MRC_UN.MRC_ST.ffb_B8) { // This is RX FIFO buffer
- fray_configure_fifo_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
+ Fr_configure_fifo_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
}
else { // Static/dynamic segment buffer
- fray_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
+ Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
}
/*
* Calculate new address.
mode = 0;
Fr_MsgRAMDataPtrs[i] = 0;
Fr_BuffersConfigured[i] = FALSE;
- fray_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
+ Fr_config_buffer(i, mode, Fr_BuffersPtrs[i]->cycleCounterFiltering, Fr_BuffersPtrs[i]->slotId, Fr_BuffersPtrs[i]->maxPayload, Fr_MsgRAMDataPtrs[i]);
#ifdef DET_ACTIVATED
disabled = TRUE;
#endif
}
Std_ReturnType Fr_ReadCCConfig( uint8_t Fr_CtrlIdx, uint8_t Fr_ConfigParamIdx, uint32_t* Fr_ConfigParamValuePtr) {
+
#ifdef DET_ACTIVATED
if (Fr_CtrlIdx != 0) {
return E_NOT_OK;
*Fr_ConfigParamValuePtr = Fr_ConfigParPtrs[Fr_ConfigParamIdx];
return E_OK;
}
+
+int Fr_spi_transfer(uint8_t port) {
+ uint32_t commands[2];
+ port_desc_t* desc;
+
+ if (port > FRAY_NUM_PORTS) return -1;
+ desc = hal_port_get_dsc(fray_port_names[port], -1);
+ fray_spi_cmd_sh = fray_spi_cmd;
+ commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
+ commands[1] = (fray_spi_cmd_sh & 0xFF);
+
+ fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
+ return 0;
+}
+
+int Fr_spi_response(uint8_t port) {
+ if (port > FRAY_NUM_PORTS) return -1;
+ return fray_spi_resp[port];
+}
+
+int Fr_spi_get_cmd(uint8_t port) {
+ if (port > FRAY_NUM_PORTS) return -1;
+ return fray_spi_cmd;
+}
//#include "drv_fray.h"
#include "drv/drv.h"
-/** Prepared spi command */
-uint32_t fray_spi_cmd = FRAY_SPICMD_INIT_VAL;
-/** Shadow variable used during command sending */
-uint32_t fray_spi_cmd_sh;
-/** Array of responses for each fray driver */
-uint32_t fray_spi_resp[FRAY_NUM_PORTS];
-/** Array of port names to be easily accessible by indexing */
-const char* fray_port_names[FRAY_NUM_PORTS] = { PORT_NAME_FRAY1, PORT_NAME_FRAY2 };
-/**
- * @brief Function sends prepared command on SPI and stores response
- *
- * @param[in] port Index of flexray 0 or 1
- * @return 0 when success, -1 when bad parameter
- */
-int fray_spi_transfer(uint8_t port) {
- uint32_t commands[2];
- port_desc_t* desc;
-
- if (port > FRAY_NUM_PORTS) return -1;
- desc = hal_port_get_dsc(fray_port_names[port], -1);
- fray_spi_cmd_sh = fray_spi_cmd;
- commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
- commands[1] = (fray_spi_cmd_sh & 0xFF);
-
- fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
- return 0;
-}
-
-/**
- * @brief Returns last spi response of selected fray port
- *
- * @param[in] port Index of flexray 0 or 1
- * @return spi response or -1 when bad parameter
- */
-int fray_spi_response(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_resp[port];
-}
-
-/**
- * @brief Returns last spi command of selected fray port
- *
- * @param[in] port Index of flexray 0 or 1
- * @return spi command or -1 when bad parameter
- */
-int fray_spi_get_cmd(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_cmd;
-}
-
-/** @fn clear_msg_ram(void)
-* @brief Clears FRAY message RAMs
-*
-* Send command to POC to set all bits of message RAM to 0.
-* @return SUCCESS or FAILURE when command was not accepted
-*/
-int fray_clear_msg_ram() {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) {
- return FAILURE;
- }
- fray_wait_for_POC_ready();
- return SUCCESS;
-}
-
-/** @fn wait_for_POC_ready(void)
-* @brief Wait until POC is not busy
-*/
-void fray_wait_for_POC_ready() {
- // Wait for PBSY bit to clear - POC not busy.
- // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
- while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
-}
-
-/** @fn fray_init(cfg *Fr_ConfigPtr)
-* @brief Set global configuration
-*
-* Copy configuration filled in structure into config registers
-* @param Fr_ConfigPtr Pointer to structure with configuration
-*/
-void fray_init(const cfg *Fr_ConfigPtr)
-{
- frayREG->SUCC1_UN.SUCC1_UL = 0x0C401000; // Keep default value
- frayREG->MRC_UN.MRC_UL = Fr_ConfigPtr->mrc;
- frayREG->PRTC1_UN.PRTC1_UL = Fr_ConfigPtr->prtc1;
- frayREG->PRTC2_UN.PRTC2_UL = Fr_ConfigPtr->prtc2;
- frayREG->MHDC_UN.MHDC_UL = Fr_ConfigPtr->mhdc;
- frayREG->GTUC1_UN.GTUC1_UL = Fr_ConfigPtr->gtu1;
- frayREG->GTUC2_UN.GTUC2_UL = Fr_ConfigPtr->gtu2;
- frayREG->GTUC3_UN.GTUC3_UL = Fr_ConfigPtr->gtu3;
- frayREG->GTUC4_UN.GTUC4_UL = Fr_ConfigPtr->gtu4;
- frayREG->GTUC5_UN.GTUC5_UL = Fr_ConfigPtr->gtu5;
- frayREG->GTUC6_UN.GTUC6_UL = Fr_ConfigPtr->gtu6;
- frayREG->GTUC7_UN.GTUC7_UL = Fr_ConfigPtr->gtu7;
- frayREG->GTUC8_UN.GTUC8_UL = Fr_ConfigPtr->gtu8;
- frayREG->GTUC9_UN.GTUC9_UL = Fr_ConfigPtr->gtu9;
- frayREG->GTUC10_UN.GTUC10_UL = Fr_ConfigPtr->gtu10;
- frayREG->GTUC11_UN.GTUC11_UL = Fr_ConfigPtr->gtu11;
- frayREG->SUCC2_UN.SUCC2_UL = Fr_ConfigPtr->succ2;
- frayREG->SUCC3_UN.SUCC3_UL = Fr_ConfigPtr->succ3;
- frayREG->SUCC1_UN.SUCC1_ST.txst_B1 = 1;
- frayREG->SUCC1_UN.SUCC1_ST.txsy_B1 = 1;
-}
-/**
- * Fill FIFO filter rejectin configuration and configure buffer.
- * @param[in] buf_num number of buffer to be configured (0-128)
- * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
- * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
- * @param[in] frame_id Id of the frame to be associated with the buffer
- * @param[in] payload Maximum data size in half-word
- * @param[in] data_pointer Address of the first word of data in buffer
- */
-void fray_configure_fifo_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
- frayREG->FRF_UN.FRF_ST.rnf = (mode&FRAY_BUF_REJECT_NULL_FRAMES) ? 1 : 0;
- frayREG->FRF_UN.FRF_ST.rss = (mode&FRAY_BUF_REJECT_STATIC_SEGMENT) ? 1 : 0;
- frayREG->FRF_UN.FRF_ST.fid_B11 = frame_id;
- frayREG->FRFM_UN.FRFM_ST.mfid_B11 = 0x0;
- frayREG->FRF_UN.FRF_ST.cyf_B7 = cyc_filter;
- if (mode&FRAY_BUF_CHB_EN && mode&FRAY_BUF_CHA_EN) {
- frayREG->FRF_UN.FRF_ST.ch_B2 = 0;
- }
- else if (mode&FRAY_BUF_CHA_EN) {
- frayREG->FRF_UN.FRF_ST.ch_B2 = 3;
- }
- else {
- frayREG->FRF_UN.FRF_ST.ch_B2 = 2;
- }
- frame_id = 0;
- fray_config_buffer(buf_num, mode, cyc_filter, frame_id, payload, data_pointer);
-}
-
-/**
- * Fill buffer configuration data structure with given data and transfer it to the message RAM header.
- * @param[in] buf_num number of buffer to be configured (0-128)
- * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
- * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
- * @param[in] frame_id Id of the frame to be associated with the buffer
- * @param[in] payload Maximum data size in half-word
- * @param[in] data_pointer Address of the first word of data in buffer
- */
-void fray_config_buffer(uint32_t buf_num, uint16_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
- wrhs Fr_LPdu;
- bc Fr_LSdu;
- Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
- Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 0 : 1; // transmission mode(0=continuous mode, 1=single mode)
- Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
- Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
- Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
- Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
- Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
- Fr_LPdu.fid = frame_id; // Frame ID
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.pl = payload; // Payload Length
-
- // Write Header Section 3 (WRHS3)
- Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
-
- Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
- Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? fray_header_crc_calc(&Fr_LPdu) : 0;
-
- // Input buffer configuration
- Fr_LSdu.ibrh = buf_num; // input buffer number
- Fr_LSdu.ibsyh = 1; // check for input buffer busy host
- Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
-
- Fr_LSdu.stxrh= (mode&FRAY_BUF_TXREQ_EN) ? 1 : 0; // set transmission request
- Fr_LSdu.ldsh = 0; // load data section
- Fr_LSdu.lhsh = 1; // load header section
- Fr_LSdu.obrs = 0; // output buffer number
- Fr_LSdu.rdss = 0; // read data section
- Fr_LSdu.rhss = 0; // read header section
-
- fray_prepare_LPdu(&Fr_LPdu);
- fray_transmit_tx_LPdu(&Fr_LSdu);
-}
-
-/**
- * Initialize POC. At first go to CONFIG state, then run the unlock sequence
- * and at the end go to READY state
- * @return SUCCESS or FAILURE
- */
-int fray_controler_init() {
- int result = SUCCESS;
- // write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_UL = 0x0F1FFB00 | CMD_CONFIG;
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0) return 1;
- // Wait for PBSY bit to clear - POC not busy
- fray_wait_for_POC_ready();
-
- // unlock CONFIG and enter READY state
- frayREG->LCK_UN.LCK_ST.clk_B8=0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8=0x31;
- // write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4=(0xFB00 | CMD_READY);
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0) {
- result = FAILURE;
- }
- // Wait for PBSY bit to clear - POC not busy
- fray_wait_for_POC_ready();
- return result;
-}
-
-/**
- * Enable IRQ on int1
- * Enable CYCSE interrupt
- * Clear Errors and statuses
- */
-void fray_init_irq() {
- frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF; // Clear Error Int.
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // Clear Status Int.
- frayREG->SILS_UN.SILS_UL = 0x00000000; // all Status Int. to eray_int0
- frayREG->SIER_UN.SIER_UL = 0xFFFFFFFF; // Disable all Status Int.
- frayREG->SIES_UN.SIES_UL = 0x00000004; // Enable CYCSE Int.
- frayREG->ILE_UN.ILE_UL = 0x00000002; // enable eray_int1
-}
-
-/**
- * Load data to message buffer.
- * @param[in] buf_num Number of buffer
- * @param[in] data Pointer to data array
- * @param[in] len Number of words to be loaded from data to buffer
- */
-void fray_buffer_set_data(uint32_t buf_num, const uint32_t* data, uint32_t len) {
- bc write_buffer;
- uint32_t i;
-
- write_buffer.ibrh = buf_num; // input buffer number
- write_buffer.stxrh= 1; // set transmission request
- write_buffer.ldsh = 1; // load data section
- write_buffer.lhsh = 0; // load header section
- write_buffer.ibsys = 0; // check for input buffer busy shadow
- write_buffer.ibsyh = 1; // check for input buffer busy host
- for (i = 0; i < len; i++) {
- frayREG->WRDS[i] = data[i];
- }
- fray_transmit_tx_LPdu(&write_buffer);
-}
-
-/**
- * Load data to message buffer. Data must be copied into WRDS register before thic function is called.
- * @param[in] buf_num Number of buffer
- * @param[in] len Number of words to be loaded from data to buffer
- */
-void fray_buffer_transmit_data(uint32_t buf_num) {
- bc write_buffer;
-
- write_buffer.ibrh = buf_num; // input buffer number
- write_buffer.stxrh= 1; // set transmission request
- write_buffer.ldsh = 1; // load data section
- write_buffer.lhsh = 0; // load header section
- write_buffer.ibsys = 0; // check for input buffer busy shadow
- write_buffer.ibsyh = 1; // check for input buffer busy host
- fray_transmit_tx_LPdu(&write_buffer);
-}
-
-
-/**
- * Retrieve data from message buffer.
- * @param[in] buf_num Number of buffer
- * @param[out] data Pointer to array, where retrieved data will be stored.
- * @param[in] len Number of words to be loaded from data to buffer
- */
-void fray_buffer_get_data(uint32_t buf_num, uint32_t* data, uint32_t len) {
- bc read_buffer;
- uint32_t i;
-
- read_buffer.obrs=buf_num; // output buffer number
- read_buffer.rdss=1; // read data section
- read_buffer.rhss=0; // read header section
- fray_receive_rx_LPdu(&read_buffer);
- for (i = 0; i < len; i++) {
- data[i] = frayREG->RDDS[i];
- }
-}
-
-/**
- * Retrieve data and header from message buffer into output buffer.
- *
- * Upper software layers have to read the header and data from RDDS and RDHS registers.
- * @param[in] buf_num Number of buffer
- */
-void fray_buffer_receive_data_header(uint32_t buf_num) {
- bc read_buffer;
-
- read_buffer.obrs=buf_num; // output buffer number
- read_buffer.rdss=1; // read data section
- read_buffer.rhss=1; // read header section
- fray_receive_rx_LPdu(&read_buffer);
-}
-
-
-/**
- * Wait for interrupt flag, that new communication cycle started
- * Clears status flags
- */
-void fray_wait_for_new_cycle() {
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // clear all status int. flags
- while ((frayREG->SIR_UN.SIR_UL & 0x4) == 0x0); // wait for CYCS interrupt flag
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // clear all status int. flags
-}
-
-/**
- * Check if some new message was received to the message buffer.
- * @param[in] buf_num Number of the buffer to be checked
- * @return 1 when new message is available, otherwise 0
- */
-int fray_buffer_message_received(uint32_t buf_num) {
- uint32_t ndat;
- uint32_t offset = 0;
- if (buf_num < 32) {
- ndat = frayREG->NDAT1_UN.NDAT1_UL;
- offset = buf_num;
- }
- else if (buf_num < 64) {
- ndat = frayREG->NDAT2_UN.NDAT2_UL;
- offset = buf_num - 32;
- }
- else if (buf_num < 96) {
- ndat = frayREG->NDAT3_UN.NDAT3_UL;
- offset = buf_num - 64;
- }
- else if (buf_num < 128) {
- ndat = frayREG->NDAT4_UN.NDAT4_UL;
- offset = buf_num - 96;
- }
- else {
- return -1;
- }
-
- return (ndat&(1<<offset));
-}
-
-/**
- * Process the FlexRay startup procedure according diagrams in FlexRay protocol specification.
- * @param[in] is_coldstar Specifies if node is coldstart or if it can be just integrated to existing network
- * @return SUCCESS or error code
- */
-int fray_startup_procedure(int is_coldstart) {
- uint32_t counter;
- uint32_t state_value;
- uint32_t csa;
- int ok = SUCCESS;
-
- ok = fray_go_to_ready_state_from_config_state();
- if(ok == FAILURE) {
- return FRAY_ERR_SW_CFG_READY; // Switching to ready state error
- }
- else {
- // Cold start branch
- if (is_coldstart){
- // Start up loop
- while(1) {
- counter = 0;
- // try as following cold starter
- ok = fray_go_to_startup_state();
- if(ok == FAILURE){
- return FRAY_ERR_SW_STUP_FOLLOW; // Switch to run error
- }
- // Wait until NORMAL_ACTIVE state or timeout
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- counter++;
- } while ((state_value != 0x02) && (counter < 10000000U));
-
- // No success in integration
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == 0x27){
- csa = frayREG->CCSV_UN.CCSV_ST.rca_B5;
- // Some cold starts attempts remains
- if (csa != 0){
- // Try allow cold start
- ok = fray_allow_coldstart();
- if(ok == FAILURE){
- return FRAY_ERR_CSINH_DIS; // Cold start inhibit disabled error
- }
- }
- }
-
- // Wait until NORMAL_ACTIVE or INTEGRATION_LISTEN state
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while ( (state_value != 0x02) && (state_value != 0x27));
-
- // Success, break the start up loop
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == 0x02)
- break;
-
- // No success. Switch back to READY state
- fray_delay();
- ok = fray_go_to_ready_state_from_startup_state();
- if (ok == FAILURE) {
- return FRAY_ERR_SW_STUP_READY; // Switch to READY failed
- }
- }
- }
- // Non-cold start branch
- else {
- ok = fray_go_to_startup_state();
- if(ok == FAILURE) {
- return FRAY_ERR_SW_STUP_AS_NCOLD; // Switching to startup state as non-cold start node
- }
- else {
- // Wait until NORMAL_ACTIVE
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while (state_value != 0x02);
- }
- }
- }
- if (ok != SUCCESS)
- return FAILURE;
- return SUCCESS;
-}
-
-/** @fn go_to_ready_state_from_config_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into READY state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_ready_state_from_config_state(void) {
- fray_wait_for_POC_ready();
-
- if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else if(frayREG->SUCC1_UN.SUCC1_ST.ccha_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- }
- else if (frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
-
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01)
- ; //cekam dokud POC neni v ready stavu
- return (SUCCESS);
-}
-
-/** @fn go_to_ready_state_from_startup_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into READY state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_ready_state_from_startup_state(void){
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) return (FAILURE);
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01); //cekam dokud POC neni v ready stavu
- return (SUCCESS);
-}
-
-/** @fn go_to_startup_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into RUN state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_startup_state(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/** @fn allow_coldstart(void)
-* @brief Allows cold start
-*
-* Send command to erase coldstart inhibit flag.
-* This allows the node to start as coldstart node.
-* @return SUCCESS or FAILURE
-*/
-int fray_allow_coldstart(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALLOW_COLDSTART;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/**
- * FlexRay delay used while network initiation.
- *
- * !This is busy waiting!
- */
-void fray_delay(void) {
- volatile uint32_t delayval;
-
- delayval = 375000; // 100000 are about 10ms
- while(delayval-- > 0 )
- ;
-}
-
-/** @fn send_halt_command
-* @brief Send HALT command
-*
-* Send command to the node to stop its activity after the end of
-* actual cycle.
-* @return SUCCESS or FAILURE
-*/
-int fray_halt(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = 6U;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/**
- * Compute CRC for message RAM header data
- * @param[in] Fr_LPduPtr Pointer to header data
- * @return CRC code
- */
-int fray_header_crc_calc(const wrhs *Fr_LPduPtr) {
- unsigned int header;
-
- int CrcInit = 0x1A;
- int length = 20;
- int CrcNext;
- unsigned long CrcPoly = 0x385;
- unsigned long CrcReg_X = CrcInit;
- unsigned long header_temp, reg_temp;
-
- header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
- header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
-
- header <<= 11;
- CrcReg_X <<= 21;
- CrcPoly <<= 21;
-
- while(length--) {
- header <<= 1;
- header_temp = header & 0x80000000;
- reg_temp = CrcReg_X & 0x80000000;
-
- if(header_temp ^ reg_temp){ // Step 1
- CrcNext = 1;
- } else {
- CrcNext = 0;
- }
-
- CrcReg_X <<= 1; // Step 2
-
- if(CrcNext) {
- CrcReg_X ^= CrcPoly; // Step 3
- }
- }
-
- CrcReg_X >>= 21;
-
- return CrcReg_X;
-}
-
-/**
- * Prepare data to be transmitted to message RAM by input buffer,
- * @param[in] Fr_LPduPtr Pointer to data structure to be send
- */
-void fray_prepare_LPdu(const wrhs *Fr_LPduPtr) {
- int wrhs1;
- int wrhs2;
- wrhs1 = ((Fr_LPduPtr->mbi) & 0x1) <<29;
- wrhs1 |= (Fr_LPduPtr->txm & 0x1) << 28;
- wrhs1 |= (Fr_LPduPtr->ppit & 0x1) << 27;
- wrhs1 |= (Fr_LPduPtr->cfg & 0x1) << 26;
- wrhs1 |= (Fr_LPduPtr->chb & 0x1) << 25;
- wrhs1 |= (Fr_LPduPtr->cha & 0x1) << 24;
- wrhs1 |= (Fr_LPduPtr->cyc & 0x7F) << 16;
- wrhs1 |= (Fr_LPduPtr->fid & 0x7FF);
- frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
-
- wrhs2 = ((Fr_LPduPtr->pl & 0x7F) << 16) | (Fr_LPduPtr->crc & 0x7FF);
- frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
-
- frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPduPtr->dp & 0x7FF);
-}
-
-/**
- * Transfer data from input buffer to message RAM
- * @param[in] Fr_LSduPtr Pointer to data structure with input buffer settings
- */
-void fray_transmit_tx_LPdu(const bc *Fr_LSduPtr) {
- // ensure nothing is pending
- while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0);
- frayREG->IBCM_UN.IBCM_UL=((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
- frayREG->IBCR_UN.IBCR_UL=(Fr_LSduPtr->ibrh & 0x3F);
- // optimization possible for future by not gating like below
- // wait for completion on host registers
- while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0));
- // wait for completion on shadow registers
- while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0));
-}
-
-/**
- * Receive data from message buffer into output buffer.
- * @param[in] Fr_LSduPtr Pointer to data structure with output buffer settings
- */
-void fray_receive_rx_LPdu(const bc *Fr_LSduPtr) {
- // ensure no transfer in progress on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
- frayREG->OBCM_UN.OBCM_UL=(((Fr_LSduPtr->rdss & 0x1) << 1) | (Fr_LSduPtr->rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 9) | (Fr_LSduPtr->obrs & 0x3F)); //req=1, view=0
- // wait for completion on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
-
- frayREG->OBCM_UN.OBCM_UL=(((Fr_LSduPtr->rdss & 0x1) << 1) | (Fr_LSduPtr->rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 8) | (Fr_LSduPtr->obrs & 0x3F)); //req=0, view=1
-}
projects / pes-rpp / rpp-lib.git / commitdiff