uio: mf624: Hopefully working interrupts

diff --git a/src/uio/mf624/kernel/mf624.c b/src/uio/mf624/kernel/mf624.c
index 39f6a9518d7b0ce31a710002e9120c83a1bc9118..1c88cf97cb29526d1567201607b09aa9733560a5 100644 (file)
--- a/src/uio/mf624/kernel/mf624.c
+++ b/src/uio/mf624/kernel/mf624.c
@@ -48,19 +48,22 @@ void mf624_disable_interrupt(enum mf624_interrupt_source source,
 
        switch (source) {
        case ADC:
-               iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_ADINT_ENABLE),
+               iowrite32(ioread32(INTCSR_reg)
+                       & ~(INTCSR_ADINT_ENABLE | INTCSR_PCIINT_ENABLE),
                        INTCSR_reg);
                break;
 
        case CTR4:
-               iowrite32(ioread32(INTCSR_reg) & ~(INTCSR_CTR4INT_ENABLE),
+               iowrite32(ioread32(INTCSR_reg)
+                       & ~(INTCSR_CTR4INT_ENABLE | INTCSR_PCIINT_ENABLE),
                        INTCSR_reg);
                break;
 
        case ALL:
        default:
                iowrite32(ioread32(INTCSR_reg)
-                       & ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE),
+                       & ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE
+                           | INTCSR_PCIINT_ENABLE),
                        INTCSR_reg);
                break;
        }
@@ -73,19 +76,22 @@ void mf624_enable_interrupt(enum mf624_interrupt_source source,
 
        switch (source) {
        case ADC:
-               iowrite32(ioread32(INTCSR_reg) | (INTCSR_ADINT_ENABLE),
+               iowrite32(ioread32(INTCSR_reg)
+                       | INTCSR_ADINT_ENABLE | INTCSR_PCIINT_ENABLE,
                        INTCSR_reg);
                break;
 
        case CTR4:
-               iowrite32(ioread32(INTCSR_reg) | (INTCSR_CTR4INT_ENABLE),
+               iowrite32(ioread32(INTCSR_reg)
+                       | INTCSR_CTR4INT_ENABLE | INTCSR_PCIINT_ENABLE,
                        INTCSR_reg);
                break;
 
        case ALL:
        default:
                iowrite32(ioread32(INTCSR_reg)
-                       | (INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE),
+                       | INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE
+                       | INTCSR_PCIINT_ENABLE,
                        INTCSR_reg);
                break;
        }
@@ -93,7 +99,7 @@ void mf624_enable_interrupt(enum mf624_interrupt_source source,
 
 static irqreturn_t mf624_irq_handler(int irq, struct uio_info *info)
 {
-       u8 __iomem *INTCSR_reg = (u8 *)info->mem[0].internal_addr + INTCSR;
+       void __iomem *INTCSR_reg = info->mem[0].internal_addr + INTCSR;
 
        if ((ioread32(INTCSR_reg) & INTCSR_ADINT_ENABLE)
            && (ioread32(INTCSR_reg) & INTCSR_ADINT_STATUS)) {
@@ -137,6 +143,8 @@ static int mf624_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
        info->name = "mf624";
        info->version = "0.0.1";
 
+       /* Note: Datasheet says device uses BAR0, BAR1, BAR2 -- do not trust it */
+
        /* BAR0 */
        info->mem[0].name = "PCI chipset, interrupts, status "
                        "bits, special functions";