2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "strongarm.h"
31 #include "qemu-error.h"
40 - Implement cp15, c14 ?
41 - Implement cp15, c15 !!! (idle used in L)
42 - Implement idle mode handling/DIM
43 - Implement sleep mode/Wake sources
44 - Implement reset control
45 - Implement memory control regs
47 - Maybe support MBGNT/MBREQ
52 - Enhance UART with modem signals
56 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
58 # define DPRINTF(format, ...) do { } while (0)
62 target_phys_addr_t io_base;
65 { 0x80010000, SA_PIC_UART1 },
66 { 0x80030000, SA_PIC_UART2 },
67 { 0x80050000, SA_PIC_UART3 },
71 /* Interrupt Controller */
91 #define SA_PIC_SRCS 32
94 static void strongarm_pic_update(void *opaque)
96 StrongARMPICState *s = opaque;
98 /* FIXME: reflect DIM */
99 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
100 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
103 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
105 StrongARMPICState *s = opaque;
108 s->pending |= 1 << irq;
110 s->pending &= ~(1 << irq);
113 strongarm_pic_update(s);
116 static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
119 StrongARMPICState *s = opaque;
123 return s->pending & ~s->is_fiq & s->enabled;
129 return s->int_idle == 0;
131 return s->pending & s->is_fiq & s->enabled;
135 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
141 static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
142 uint64_t value, unsigned size)
144 StrongARMPICState *s = opaque;
154 s->int_idle = (value & 1) ? 0 : ~0;
157 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
161 strongarm_pic_update(s);
164 static const MemoryRegionOps strongarm_pic_ops = {
165 .read = strongarm_pic_mem_read,
166 .write = strongarm_pic_mem_write,
167 .endianness = DEVICE_NATIVE_ENDIAN,
170 static int strongarm_pic_initfn(SysBusDevice *dev)
172 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
174 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
175 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
176 sysbus_init_mmio(dev, &s->iomem);
177 sysbus_init_irq(dev, &s->irq);
178 sysbus_init_irq(dev, &s->fiq);
183 static int strongarm_pic_post_load(void *opaque, int version_id)
185 strongarm_pic_update(opaque);
189 static VMStateDescription vmstate_strongarm_pic_regs = {
190 .name = "strongarm_pic",
192 .minimum_version_id = 0,
193 .minimum_version_id_old = 0,
194 .post_load = strongarm_pic_post_load,
195 .fields = (VMStateField[]) {
196 VMSTATE_UINT32(pending, StrongARMPICState),
197 VMSTATE_UINT32(enabled, StrongARMPICState),
198 VMSTATE_UINT32(is_fiq, StrongARMPICState),
199 VMSTATE_UINT32(int_idle, StrongARMPICState),
200 VMSTATE_END_OF_LIST(),
204 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
206 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
208 k->init = strongarm_pic_initfn;
211 static DeviceInfo strongarm_pic_info = {
212 .name = "strongarm_pic",
213 .desc = "StrongARM PIC",
214 .size = sizeof(StrongARMPICState),
215 .vmsd = &vmstate_strongarm_pic_regs,
216 .class_init = strongarm_pic_class_init,
219 /* Real-Time Clock */
220 #define RTAR 0x00 /* RTC Alarm register */
221 #define RCNR 0x04 /* RTC Counter register */
222 #define RTTR 0x08 /* RTC Timer Trim register */
223 #define RTSR 0x10 /* RTC Status register */
225 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
226 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
227 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
228 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
230 /* 16 LSB of RTTR are clockdiv for internal trim logic,
231 * trim delete isn't emulated, so
232 * f = 32 768 / (RTTR_trim + 1) */
242 QEMUTimer *rtc_alarm;
248 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
250 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
251 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
254 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
256 int64_t rt = qemu_get_clock_ms(rt_clock);
257 s->last_rcnr += ((rt - s->last_hz) << 15) /
258 (1000 * ((s->rttr & 0xffff) + 1));
262 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
264 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
265 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
267 qemu_del_timer(s->rtc_hz);
270 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
271 qemu_mod_timer(s->rtc_alarm, s->last_hz +
272 (((s->rtar - s->last_rcnr) * 1000 *
273 ((s->rttr & 0xffff) + 1)) >> 15));
275 qemu_del_timer(s->rtc_alarm);
279 static inline void strongarm_rtc_alarm_tick(void *opaque)
281 StrongARMRTCState *s = opaque;
283 strongarm_rtc_timer_update(s);
284 strongarm_rtc_int_update(s);
287 static inline void strongarm_rtc_hz_tick(void *opaque)
289 StrongARMRTCState *s = opaque;
291 strongarm_rtc_timer_update(s);
292 strongarm_rtc_int_update(s);
295 static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
298 StrongARMRTCState *s = opaque;
308 return s->last_rcnr +
309 ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
310 (1000 * ((s->rttr & 0xffff) + 1));
312 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
317 static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
318 uint64_t value, unsigned size)
320 StrongARMRTCState *s = opaque;
325 strongarm_rtc_hzupdate(s);
327 strongarm_rtc_timer_update(s);
332 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
333 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
335 if (s->rtsr != old_rtsr) {
336 strongarm_rtc_timer_update(s);
339 strongarm_rtc_int_update(s);
344 strongarm_rtc_timer_update(s);
348 strongarm_rtc_hzupdate(s);
349 s->last_rcnr = value;
350 strongarm_rtc_timer_update(s);
354 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
358 static const MemoryRegionOps strongarm_rtc_ops = {
359 .read = strongarm_rtc_read,
360 .write = strongarm_rtc_write,
361 .endianness = DEVICE_NATIVE_ENDIAN,
364 static int strongarm_rtc_init(SysBusDevice *dev)
366 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
372 qemu_get_timedate(&tm, 0);
374 s->last_rcnr = (uint32_t) mktimegm(&tm);
375 s->last_hz = qemu_get_clock_ms(rt_clock);
377 s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
378 s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
380 sysbus_init_irq(dev, &s->rtc_irq);
381 sysbus_init_irq(dev, &s->rtc_hz_irq);
383 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
384 sysbus_init_mmio(dev, &s->iomem);
389 static void strongarm_rtc_pre_save(void *opaque)
391 StrongARMRTCState *s = opaque;
393 strongarm_rtc_hzupdate(s);
396 static int strongarm_rtc_post_load(void *opaque, int version_id)
398 StrongARMRTCState *s = opaque;
400 strongarm_rtc_timer_update(s);
401 strongarm_rtc_int_update(s);
406 static const VMStateDescription vmstate_strongarm_rtc_regs = {
407 .name = "strongarm-rtc",
409 .minimum_version_id = 0,
410 .minimum_version_id_old = 0,
411 .pre_save = strongarm_rtc_pre_save,
412 .post_load = strongarm_rtc_post_load,
413 .fields = (VMStateField[]) {
414 VMSTATE_UINT32(rttr, StrongARMRTCState),
415 VMSTATE_UINT32(rtsr, StrongARMRTCState),
416 VMSTATE_UINT32(rtar, StrongARMRTCState),
417 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
418 VMSTATE_INT64(last_hz, StrongARMRTCState),
419 VMSTATE_END_OF_LIST(),
423 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
425 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
427 k->init = strongarm_rtc_init;
430 static DeviceInfo strongarm_rtc_sysbus_info = {
431 .name = "strongarm-rtc",
432 .desc = "StrongARM RTC Controller",
433 .size = sizeof(StrongARMRTCState),
434 .vmsd = &vmstate_strongarm_rtc_regs,
435 .class_init = strongarm_rtc_sysbus_class_init,
448 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
449 struct StrongARMGPIOInfo {
452 qemu_irq handler[28];
469 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
472 for (i = 0; i < 11; i++) {
473 qemu_set_irq(s->irqs[i], s->status & (1 << i));
476 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
479 static void strongarm_gpio_set(void *opaque, int line, int level)
481 StrongARMGPIOInfo *s = opaque;
487 s->status |= s->rising & mask &
488 ~s->ilevel & ~s->dir;
491 s->status |= s->falling & mask &
496 if (s->status & mask) {
497 strongarm_gpio_irq_update(s);
501 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
503 uint32_t level, diff;
506 level = s->olevel & s->dir;
508 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
510 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
513 s->prev_level = level;
516 static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
519 StrongARMGPIOInfo *s = opaque;
522 case GPDR: /* GPIO Pin-Direction registers */
525 case GPSR: /* GPIO Pin-Output Set registers */
526 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
528 return s->gpsr; /* Return last written value. */
530 case GPCR: /* GPIO Pin-Output Clear registers */
531 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
533 return 31337; /* Specified as unpredictable in the docs. */
535 case GRER: /* GPIO Rising-Edge Detect Enable registers */
538 case GFER: /* GPIO Falling-Edge Detect Enable registers */
541 case GAFR: /* GPIO Alternate Function registers */
544 case GPLR: /* GPIO Pin-Level registers */
545 return (s->olevel & s->dir) |
546 (s->ilevel & ~s->dir);
548 case GEDR: /* GPIO Edge Detect Status registers */
552 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
558 static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
559 uint64_t value, unsigned size)
561 StrongARMGPIOInfo *s = opaque;
564 case GPDR: /* GPIO Pin-Direction registers */
566 strongarm_gpio_handler_update(s);
569 case GPSR: /* GPIO Pin-Output Set registers */
571 strongarm_gpio_handler_update(s);
575 case GPCR: /* GPIO Pin-Output Clear registers */
577 strongarm_gpio_handler_update(s);
580 case GRER: /* GPIO Rising-Edge Detect Enable registers */
584 case GFER: /* GPIO Falling-Edge Detect Enable registers */
588 case GAFR: /* GPIO Alternate Function registers */
592 case GEDR: /* GPIO Edge Detect Status registers */
594 strongarm_gpio_irq_update(s);
598 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
602 static const MemoryRegionOps strongarm_gpio_ops = {
603 .read = strongarm_gpio_read,
604 .write = strongarm_gpio_write,
605 .endianness = DEVICE_NATIVE_ENDIAN,
608 static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
614 dev = qdev_create(NULL, "strongarm-gpio");
615 qdev_init_nofail(dev);
617 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
618 for (i = 0; i < 12; i++)
619 sysbus_connect_irq(sysbus_from_qdev(dev), i,
620 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
625 static int strongarm_gpio_initfn(SysBusDevice *dev)
627 StrongARMGPIOInfo *s;
630 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
632 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
633 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
635 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
637 sysbus_init_mmio(dev, &s->iomem);
638 for (i = 0; i < 11; i++) {
639 sysbus_init_irq(dev, &s->irqs[i]);
641 sysbus_init_irq(dev, &s->irqX);
646 static const VMStateDescription vmstate_strongarm_gpio_regs = {
647 .name = "strongarm-gpio",
649 .minimum_version_id = 0,
650 .minimum_version_id_old = 0,
651 .fields = (VMStateField[]) {
652 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
653 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
654 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
655 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
656 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
657 VMSTATE_UINT32(status, StrongARMGPIOInfo),
658 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
659 VMSTATE_END_OF_LIST(),
663 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
665 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
667 k->init = strongarm_gpio_initfn;
670 static DeviceInfo strongarm_gpio_info = {
671 .name = "strongarm-gpio",
672 .desc = "StrongARM GPIO controller",
673 .size = sizeof(StrongARMGPIOInfo),
674 .class_init = strongarm_gpio_class_init,
677 /* Peripheral Pin Controller */
684 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
685 struct StrongARMPPCInfo {
688 qemu_irq handler[28];
700 static void strongarm_ppc_set(void *opaque, int line, int level)
702 StrongARMPPCInfo *s = opaque;
705 s->ilevel |= 1 << line;
707 s->ilevel &= ~(1 << line);
711 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
713 uint32_t level, diff;
716 level = s->olevel & s->dir;
718 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
720 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
723 s->prev_level = level;
726 static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
729 StrongARMPPCInfo *s = opaque;
732 case PPDR: /* PPC Pin Direction registers */
733 return s->dir | ~0x3fffff;
735 case PPSR: /* PPC Pin State registers */
736 return (s->olevel & s->dir) |
737 (s->ilevel & ~s->dir) |
741 return s->ppar | ~0x41000;
747 return s->ppfr | ~0x7f001;
750 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
756 static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
757 uint64_t value, unsigned size)
759 StrongARMPPCInfo *s = opaque;
762 case PPDR: /* PPC Pin Direction registers */
763 s->dir = value & 0x3fffff;
764 strongarm_ppc_handler_update(s);
767 case PPSR: /* PPC Pin State registers */
768 s->olevel = value & s->dir & 0x3fffff;
769 strongarm_ppc_handler_update(s);
773 s->ppar = value & 0x41000;
777 s->psdr = value & 0x3fffff;
781 s->ppfr = value & 0x7f001;
785 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
789 static const MemoryRegionOps strongarm_ppc_ops = {
790 .read = strongarm_ppc_read,
791 .write = strongarm_ppc_write,
792 .endianness = DEVICE_NATIVE_ENDIAN,
795 static int strongarm_ppc_init(SysBusDevice *dev)
799 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
801 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
802 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
804 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
806 sysbus_init_mmio(dev, &s->iomem);
811 static const VMStateDescription vmstate_strongarm_ppc_regs = {
812 .name = "strongarm-ppc",
814 .minimum_version_id = 0,
815 .minimum_version_id_old = 0,
816 .fields = (VMStateField[]) {
817 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
818 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
819 VMSTATE_UINT32(dir, StrongARMPPCInfo),
820 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
821 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
822 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
823 VMSTATE_END_OF_LIST(),
827 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
829 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
831 k->init = strongarm_ppc_init;
834 static DeviceInfo strongarm_ppc_info = {
835 .name = "strongarm-ppc",
836 .desc = "StrongARM PPC controller",
837 .size = sizeof(StrongARMPPCInfo),
838 .class_init = strongarm_ppc_class_init,
850 #define UTCR0_PE (1 << 0) /* Parity enable */
851 #define UTCR0_OES (1 << 1) /* Even parity */
852 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
853 #define UTCR0_DSS (1 << 3) /* 8-bit data */
855 #define UTCR3_RXE (1 << 0) /* Rx enable */
856 #define UTCR3_TXE (1 << 1) /* Tx enable */
857 #define UTCR3_BRK (1 << 2) /* Force Break */
858 #define UTCR3_RIE (1 << 3) /* Rx int enable */
859 #define UTCR3_TIE (1 << 4) /* Tx int enable */
860 #define UTCR3_LBM (1 << 5) /* Loopback */
862 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
863 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
864 #define UTSR0_RID (1 << 2) /* Receiver Idle */
865 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
866 #define UTSR0_REB (1 << 4) /* Receiver end break */
867 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
869 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
870 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
871 #define UTSR1_PRE (1 << 3) /* Parity error */
872 #define UTSR1_FRE (1 << 4) /* Frame error */
873 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
875 #define RX_FIFO_PRE (1 << 8)
876 #define RX_FIFO_FRE (1 << 9)
877 #define RX_FIFO_ROR (1 << 10)
882 CharDriverState *chr;
894 uint16_t rx_fifo[12]; /* value + error flags in high bits */
898 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
900 QEMUTimer *rx_timeout_timer;
902 } StrongARMUARTState;
904 static void strongarm_uart_update_status(StrongARMUARTState *s)
908 if (s->tx_len != 8) {
912 if (s->rx_len != 0) {
913 uint16_t ent = s->rx_fifo[s->rx_start];
916 if (ent & RX_FIFO_PRE) {
917 s->utsr1 |= UTSR1_PRE;
919 if (ent & RX_FIFO_FRE) {
920 s->utsr1 |= UTSR1_FRE;
922 if (ent & RX_FIFO_ROR) {
923 s->utsr1 |= UTSR1_ROR;
930 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
932 uint16_t utsr0 = s->utsr0 &
933 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
936 if ((s->utcr3 & UTCR3_TXE) &&
937 (s->utcr3 & UTCR3_TIE) &&
942 if ((s->utcr3 & UTCR3_RXE) &&
943 (s->utcr3 & UTCR3_RIE) &&
948 for (i = 0; i < s->rx_len && i < 4; i++)
949 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
955 qemu_set_irq(s->irq, utsr0);
958 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
960 int speed, parity, data_bits, stop_bits, frame_size;
961 QEMUSerialSetParams ssp;
965 if (s->utcr0 & UTCR0_PE) {
968 if (s->utcr0 & UTCR0_OES) {
976 if (s->utcr0 & UTCR0_SBS) {
982 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
983 frame_size += data_bits + stop_bits;
984 speed = 3686400 / 16 / (s->brd + 1);
987 ssp.data_bits = data_bits;
988 ssp.stop_bits = stop_bits;
989 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
991 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
994 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
995 speed, parity, data_bits, stop_bits);
998 static void strongarm_uart_rx_to(void *opaque)
1000 StrongARMUARTState *s = opaque;
1003 s->utsr0 |= UTSR0_RID;
1004 strongarm_uart_update_int_status(s);
1008 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1010 if ((s->utcr3 & UTCR3_RXE) == 0) {
1015 if (s->wait_break_end) {
1016 s->utsr0 |= UTSR0_REB;
1017 s->wait_break_end = false;
1020 if (s->rx_len < 12) {
1021 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1024 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1027 static int strongarm_uart_can_receive(void *opaque)
1029 StrongARMUARTState *s = opaque;
1031 if (s->rx_len == 12) {
1034 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1035 if (s->rx_len < 8) {
1036 return 8 - s->rx_len;
1041 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1043 StrongARMUARTState *s = opaque;
1046 for (i = 0; i < size; i++) {
1047 strongarm_uart_rx_push(s, buf[i]);
1050 /* call the timeout receive callback in 3 char transmit time */
1051 qemu_mod_timer(s->rx_timeout_timer,
1052 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1054 strongarm_uart_update_status(s);
1055 strongarm_uart_update_int_status(s);
1058 static void strongarm_uart_event(void *opaque, int event)
1060 StrongARMUARTState *s = opaque;
1061 if (event == CHR_EVENT_BREAK) {
1062 s->utsr0 |= UTSR0_RBB;
1063 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1064 s->wait_break_end = true;
1065 strongarm_uart_update_status(s);
1066 strongarm_uart_update_int_status(s);
1070 static void strongarm_uart_tx(void *opaque)
1072 StrongARMUARTState *s = opaque;
1073 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1075 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1076 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1077 } else if (s->chr) {
1078 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1081 s->tx_start = (s->tx_start + 1) % 8;
1084 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1086 strongarm_uart_update_status(s);
1087 strongarm_uart_update_int_status(s);
1090 static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
1093 StrongARMUARTState *s = opaque;
1104 return s->brd & 0xff;
1110 if (s->rx_len != 0) {
1111 ret = s->rx_fifo[s->rx_start];
1112 s->rx_start = (s->rx_start + 1) % 12;
1114 strongarm_uart_update_status(s);
1115 strongarm_uart_update_int_status(s);
1127 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1132 static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1133 uint64_t value, unsigned size)
1135 StrongARMUARTState *s = opaque;
1139 s->utcr0 = value & 0x7f;
1140 strongarm_uart_update_parameters(s);
1144 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1145 strongarm_uart_update_parameters(s);
1149 s->brd = (s->brd & 0xf00) | (value & 0xff);
1150 strongarm_uart_update_parameters(s);
1154 s->utcr3 = value & 0x3f;
1155 if ((s->utcr3 & UTCR3_RXE) == 0) {
1158 if ((s->utcr3 & UTCR3_TXE) == 0) {
1161 strongarm_uart_update_status(s);
1162 strongarm_uart_update_int_status(s);
1166 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1167 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1169 strongarm_uart_update_status(s);
1170 strongarm_uart_update_int_status(s);
1171 if (s->tx_len == 1) {
1172 strongarm_uart_tx(s);
1178 s->utsr0 = s->utsr0 & ~(value &
1179 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1180 strongarm_uart_update_int_status(s);
1184 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1188 static const MemoryRegionOps strongarm_uart_ops = {
1189 .read = strongarm_uart_read,
1190 .write = strongarm_uart_write,
1191 .endianness = DEVICE_NATIVE_ENDIAN,
1194 static int strongarm_uart_init(SysBusDevice *dev)
1196 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1198 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1199 sysbus_init_mmio(dev, &s->iomem);
1200 sysbus_init_irq(dev, &s->irq);
1202 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1203 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1206 qemu_chr_add_handlers(s->chr,
1207 strongarm_uart_can_receive,
1208 strongarm_uart_receive,
1209 strongarm_uart_event,
1216 static void strongarm_uart_reset(DeviceState *dev)
1218 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1220 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1221 s->brd = 23; /* 9600 */
1222 /* enable send & recv - this actually violates spec */
1223 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1225 s->rx_len = s->tx_len = 0;
1227 strongarm_uart_update_parameters(s);
1228 strongarm_uart_update_status(s);
1229 strongarm_uart_update_int_status(s);
1232 static int strongarm_uart_post_load(void *opaque, int version_id)
1234 StrongARMUARTState *s = opaque;
1236 strongarm_uart_update_parameters(s);
1237 strongarm_uart_update_status(s);
1238 strongarm_uart_update_int_status(s);
1240 /* tx and restart timer */
1242 strongarm_uart_tx(s);
1245 /* restart rx timeout timer */
1247 qemu_mod_timer(s->rx_timeout_timer,
1248 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1254 static const VMStateDescription vmstate_strongarm_uart_regs = {
1255 .name = "strongarm-uart",
1257 .minimum_version_id = 0,
1258 .minimum_version_id_old = 0,
1259 .post_load = strongarm_uart_post_load,
1260 .fields = (VMStateField[]) {
1261 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1262 VMSTATE_UINT16(brd, StrongARMUARTState),
1263 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1264 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1265 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1266 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1267 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1268 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1269 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1270 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1271 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1272 VMSTATE_END_OF_LIST(),
1276 static Property strongarm_uart_properties[] = {
1277 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1278 DEFINE_PROP_END_OF_LIST(),
1281 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1283 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1285 k->init = strongarm_uart_init;
1288 static DeviceInfo strongarm_uart_info = {
1289 .name = "strongarm-uart",
1290 .desc = "StrongARM UART controller",
1291 .size = sizeof(StrongARMUARTState),
1292 .reset = strongarm_uart_reset,
1293 .vmsd = &vmstate_strongarm_uart_regs,
1294 .props = strongarm_uart_properties,
1295 .class_init = strongarm_uart_class_init,
1298 /* Synchronous Serial Ports */
1300 SysBusDevice busdev;
1308 uint16_t rx_fifo[8];
1311 } StrongARMSSPState;
1313 #define SSCR0 0x60 /* SSP Control register 0 */
1314 #define SSCR1 0x64 /* SSP Control register 1 */
1315 #define SSDR 0x6c /* SSP Data register */
1316 #define SSSR 0x74 /* SSP Status register */
1318 /* Bitfields for above registers */
1319 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1320 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1321 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1322 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1323 #define SSCR0_SSE (1 << 7)
1324 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1325 #define SSCR1_RIE (1 << 0)
1326 #define SSCR1_TIE (1 << 1)
1327 #define SSCR1_LBM (1 << 2)
1328 #define SSSR_TNF (1 << 2)
1329 #define SSSR_RNE (1 << 3)
1330 #define SSSR_TFS (1 << 5)
1331 #define SSSR_RFS (1 << 6)
1332 #define SSSR_ROR (1 << 7)
1333 #define SSSR_RW 0x0080
1335 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1339 level |= (s->sssr & SSSR_ROR);
1340 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1341 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1342 qemu_set_irq(s->irq, level);
1345 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1347 s->sssr &= ~SSSR_TFS;
1348 s->sssr &= ~SSSR_TNF;
1349 if (s->sscr[0] & SSCR0_SSE) {
1350 if (s->rx_level >= 4) {
1351 s->sssr |= SSSR_RFS;
1353 s->sssr &= ~SSSR_RFS;
1356 s->sssr |= SSSR_RNE;
1358 s->sssr &= ~SSSR_RNE;
1360 /* TX FIFO is never filled, so it is always in underrun
1361 condition if SSP is enabled */
1362 s->sssr |= SSSR_TFS;
1363 s->sssr |= SSSR_TNF;
1366 strongarm_ssp_int_update(s);
1369 static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
1372 StrongARMSSPState *s = opaque;
1383 if (~s->sscr[0] & SSCR0_SSE) {
1386 if (s->rx_level < 1) {
1387 printf("%s: SSP Rx Underrun\n", __func__);
1391 retval = s->rx_fifo[s->rx_start++];
1393 strongarm_ssp_fifo_update(s);
1396 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1402 static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1403 uint64_t value, unsigned size)
1405 StrongARMSSPState *s = opaque;
1409 s->sscr[0] = value & 0xffbf;
1410 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1411 printf("%s: Wrong data size: %i bits\n", __func__,
1412 (int)SSCR0_DSS(value));
1414 if (!(value & SSCR0_SSE)) {
1418 strongarm_ssp_fifo_update(s);
1422 s->sscr[1] = value & 0x2f;
1423 if (value & SSCR1_LBM) {
1424 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1426 strongarm_ssp_fifo_update(s);
1430 s->sssr &= ~(value & SSSR_RW);
1431 strongarm_ssp_int_update(s);
1435 if (SSCR0_UWIRE(s->sscr[0])) {
1438 /* Note how 32bits overflow does no harm here */
1439 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1441 /* Data goes from here to the Tx FIFO and is shifted out from
1442 * there directly to the slave, no need to buffer it.
1444 if (s->sscr[0] & SSCR0_SSE) {
1446 if (s->sscr[1] & SSCR1_LBM) {
1449 readval = ssi_transfer(s->bus, value);
1452 if (s->rx_level < 0x08) {
1453 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1455 s->sssr |= SSSR_ROR;
1458 strongarm_ssp_fifo_update(s);
1462 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1467 static const MemoryRegionOps strongarm_ssp_ops = {
1468 .read = strongarm_ssp_read,
1469 .write = strongarm_ssp_write,
1470 .endianness = DEVICE_NATIVE_ENDIAN,
1473 static int strongarm_ssp_post_load(void *opaque, int version_id)
1475 StrongARMSSPState *s = opaque;
1477 strongarm_ssp_fifo_update(s);
1482 static int strongarm_ssp_init(SysBusDevice *dev)
1484 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1486 sysbus_init_irq(dev, &s->irq);
1488 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1489 sysbus_init_mmio(dev, &s->iomem);
1491 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1495 static void strongarm_ssp_reset(DeviceState *dev)
1497 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1498 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1503 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1504 .name = "strongarm-ssp",
1506 .minimum_version_id = 0,
1507 .minimum_version_id_old = 0,
1508 .post_load = strongarm_ssp_post_load,
1509 .fields = (VMStateField[]) {
1510 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1511 VMSTATE_UINT16(sssr, StrongARMSSPState),
1512 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1513 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1514 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1515 VMSTATE_END_OF_LIST(),
1519 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1521 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1523 k->init = strongarm_ssp_init;
1526 static DeviceInfo strongarm_ssp_info = {
1527 .name = "strongarm-ssp",
1528 .desc = "StrongARM SSP controller",
1529 .size = sizeof(StrongARMSSPState),
1530 .reset = strongarm_ssp_reset,
1531 .vmsd = &vmstate_strongarm_ssp_regs,
1532 .class_init = strongarm_ssp_class_init,
1535 /* Main CPU functions */
1536 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1537 unsigned int sdram_size, const char *rev)
1543 s = g_malloc0(sizeof(StrongARMState));
1549 if (strncmp(rev, "sa1110", 6)) {
1550 error_report("Machine requires a SA1110 processor.");
1554 s->env = cpu_init(rev);
1557 error_report("Unable to find CPU definition");
1561 memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
1562 vmstate_register_ram_global(&s->sdram);
1563 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1565 pic = arm_pic_init_cpu(s->env);
1566 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1567 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1569 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1570 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1571 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1572 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1573 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1576 sysbus_create_simple("strongarm-rtc", 0x90010000,
1577 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1579 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1581 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1583 for (i = 0; sa_serial[i].io_base; i++) {
1584 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1585 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1586 qdev_init_nofail(dev);
1587 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1588 sa_serial[i].io_base);
1589 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1590 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1593 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1594 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1595 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1600 static void strongarm_register_devices(void)
1602 sysbus_register_withprop(&strongarm_pic_info);
1603 sysbus_register_withprop(&strongarm_rtc_sysbus_info);
1604 sysbus_register_withprop(&strongarm_gpio_info);
1605 sysbus_register_withprop(&strongarm_ppc_info);
1606 sysbus_register_withprop(&strongarm_uart_info);
1607 sysbus_register_withprop(&strongarm_ssp_info);
1609 device_init(strongarm_register_devices)