+/**
+ * usbcan_init_chip_data - Initialize chips
+ * @candev: Pointer to candevice/board structure
+ * @chipnr: Number of the CAN chip on the hardware card
+ *
+ * The function usbcan_init_chip_data() is used to initialize the hardware
+ * structure containing information about the CAN chips.
+ * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
+ * "sja1000".
+ * The @chip_base_addr entry represents the start of the 'official' memory map
+ * of the installed chip. It's likely that this is the same as the @io_addr
+ * argument supplied at module loading time.
+ * The @clock entry holds the chip clock value in Hz.
+ * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
+ * register. Options defined in the %sja1000.h file:
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
+ * The entry @sja_ocr_reg holds hardware specific options for the Output Control
+ * register. Options defined in the %sja1000.h file:
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
+ * The entry @int_clk_reg holds hardware specific options for the Clock Out
+ * register. Options defined in the %i82527.h file:
+ * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
+ * The entry @int_bus_reg holds hardware specific options for the Bus
+ * Configuration register. Options defined in the %i82527.h file:
+ * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
+ * The entry @int_cpu_reg holds hardware specific options for the cpu interface
+ * register. Options defined in the %i82527.h file:
+ * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
+ * Return Value: The function always returns zero
+ * File: src/usbcan.c
+ */
+int usbcan_init_chip_data(struct candevice_t *candev, int chipnr)
+{
+ struct canchip_t *chip=candev->chip[chipnr];
+
+ chip->chip_type="usbcan";
+ chip->max_objects=1;
+ usbcan_chipregister(chip->chipspecops);
+
+ CANMSG("initializing usbcan chip operations\n");
+ chip->chipspecops->chip_config=usbcan_chip_config;
+ chip->chipspecops->baud_rate=usbcan_baud_rate;
+ chip->chipspecops->standard_mask=usbcan_standard_mask;
+ chip->chipspecops->extended_mask=usbcan_extended_mask;
+ chip->chipspecops->message15_mask=usbcan_extended_mask;
+ chip->chipspecops->clear_objects=usbcan_clear_objects;
+ chip->chipspecops->config_irqs=usbcan_config_irqs;
+ chip->chipspecops->pre_read_config=usbcan_pre_read_config;
+ chip->chipspecops->pre_write_config=usbcan_pre_write_config;
+ chip->chipspecops->send_msg=usbcan_send_msg;
+ chip->chipspecops->check_tx_stat=usbcan_check_tx_stat;
+ chip->chipspecops->wakeup_tx=usbcan_wakeup_tx;
+ chip->chipspecops->remote_request=usbcan_remote_request;
+ chip->chipspecops->enable_configuration=usbcan_enable_configuration;
+ chip->chipspecops->disable_configuration=usbcan_disable_configuration;
+ chip->chipspecops->attach_to_chip=usbcan_attach_to_chip;
+ chip->chipspecops->release_chip=usbcan_release_chip;
+ chip->chipspecops->set_btregs=usbcan_set_btregs;
+ chip->chipspecops->start_chip=usbcan_start_chip;
+ chip->chipspecops->stop_chip=usbcan_stop_chip;
+ chip->chipspecops->irq_handler=usbcan_irq_handler;
+ chip->chipspecops->irq_accept=NULL;
+
+ candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->clock = 16000000;
+/* candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
+ candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
+ candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;*/
+
+ return 0;
+}
+