unsigned long it_mask,it_reg;
struct candevice_t *candev;
it_mask=0;
unsigned long it_mask,it_reg;
struct candevice_t *candev;
it_mask=0;
{
can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
{
can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
can_write_reg(chip,P2_2|P2_1,iP2C); // The pin P2_2,P2_1 of the 527 must be set as output
can_write_reg(chip,P2_2|P2_1,iP2O); // and P2_2 must be set to 1
can_write_reg(chip,P2_2|P2_1,iP2C); // The pin P2_2,P2_1 of the 527 must be set as output
can_write_reg(chip,P2_2|P2_1,iP2O); // and P2_2 must be set to 1
* card. If we can not, the card is not properly configured!
*/
canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
* card. If we can not, the card is not properly configured!
*/
canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
if (nsi_canpci_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
CANMSG("Error configuring interrupts\n");
return -ENODEV;
if (nsi_canpci_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
CANMSG("Error configuring interrupts\n");
return -ENODEV;
* io-memory. In case you reserved more memory, don't forget to free it here.
*/
int nsi_canpci_release_io(struct candevice_t *candev)
* io-memory. In case you reserved more memory, don't forget to free it here.
*/
int nsi_canpci_release_io(struct candevice_t *candev)
nsi_canpci_disconnect_irq(candev);
// First, set RESET signal to 0
reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
nsi_canpci_disconnect_irq(candev);
// First, set RESET signal to 0
reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
kfree((void*)(candev->dev_base_addr));
pci_release_region(pcidev,0);
pci_release_region(pcidev,1);
kfree((void*)(candev->dev_base_addr));
pci_release_region(pcidev,0);
pci_release_region(pcidev,1);
- pci_release_region(pcidev,2);
- pci_release_region(pcidev,3);
+ pci_release_region(pcidev,2);
+ pci_release_region(pcidev,3);
nsi_canpci_disconnect_irq(candev);
// First, set RESET signal to 0
reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
nsi_canpci_disconnect_irq(candev);
// First, set RESET signal to 0
reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
wmb();
udelay(2500); // Waiting for some additionnal time before writing in the 82527
DEBUGMSG("Reset done !!!\n");
wmb();
udelay(2500); // Waiting for some additionnal time before writing in the 82527
DEBUGMSG("Reset done !!!\n");
{
pci_release_region(pcidev,0);
pci_release_region(pcidev,1);
{
pci_release_region(pcidev,0);
pci_release_region(pcidev,1);
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
//PLX IO
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
//PLX IO
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
//Chip 1
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
//Chip 1
((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
//Short acces to plx register
candev->io_addr=(unsigned long)(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
//Short acces to plx register
candev->io_addr=(unsigned long)(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
//u8 irq_line;
CANMSG ("NSI chip data init %d\n",chipnr);
i82527_fill_chipspecops(candev->chip[chipnr]);
//u8 irq_line;
CANMSG ("NSI chip data init %d\n",chipnr);
i82527_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chipspecops->chip_config =nsi_canpci_i82527_chip_config;
candev->chip[chipnr]->chipspecops->start_chip=nsi_canpci_start_chip;
candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
/*candev->chip[chipnr]->chip_data = NULL;*/
candev->chip[chipnr]->chipspecops->chip_config =nsi_canpci_i82527_chip_config;
candev->chip[chipnr]->chipspecops->start_chip=nsi_canpci_start_chip;
candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
/*candev->chip[chipnr]->chip_data = NULL;*/
candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
candev->chip[chipnr]->clock = iCLOCK;
candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
candev->chip[chipnr]->clock = iCLOCK;
candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
* CAN chip. In case of the sja1000 there's only one message object but on the
* i82527 chip there are 15.
* The code below is for a i82527 chip and initializes the object base addresses
* CAN chip. In case of the sja1000 there's only one message object but on the
* i82527 chip there are 15.
* The code below is for a i82527 chip and initializes the object base addresses
* object. In case of the sja1000 obj_base_addr is taken the same as the chips
* base address.
* Unless the hardware uses a segmented memory map, flags can be set zero.
* object. In case of the sja1000 obj_base_addr is taken the same as the chips
* base address.
* Unless the hardware uses a segmented memory map, flags can be set zero.