SJA1000 clockout divisors listed explicitly.

[lincan.git] / lincan / include / sja1000p.h

diff --git a/lincan/include/sja1000p.h b/lincan/include/sja1000p.h
index 9b1f5d86aa43ac54deff44cf01c060269ab7411a..1aa09236629d683918b9e5a7d7f2d0aab1126d51 100644 (file)
--- a/lincan/include/sja1000p.h
+++ b/lincan/include/sja1000p.h
@@ -1,22 +1,26 @@
 /* sja1000p.h
  * Header file for the Linux CAN-bus driver.
  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
 /* sja1000p.h
  * Header file for the Linux CAN-bus driver.
  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl

- * This software is released under the GPL-License.
- * Version 0.6.1 T.Motylewski@bfad.de 13.03.2001
+ * Added by T.Motylewski@bfad.de

  * See app. note an97076.pdf from Philips Semiconductors 
  * and SJA1000 data sheet
  * PELICAN mode
  * See app. note an97076.pdf from Philips Semiconductors 
  * and SJA1000 data sheet
  * PELICAN mode

+ * This software is released under the GPL-License.
+ * Version lincan-0.3  17 Jun 2004

  */
 
  */
 

-int sja1000p_chip_config(struct chip_t *chip);
-int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask);
-int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int sja1000p_chip_config(struct canchip_t *chip);
+int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask);
+int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,

                int sampl_pt, int flags);
                int sampl_pt, int flags);

-int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
-int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
+int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,

                struct canmsg_t *msg);
                struct canmsg_t *msg);

-int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,

                struct canmsg_t *msg);
                struct canmsg_t *msg);

+int sja1000p_fill_chipspecops(struct canchip_t *chip);
+int sja1000p_irq_handler(int irq, struct canchip_t *chip);
+

 
 /* PeliCAN mode */
 enum SJA1000_PeliCAN_regs {
 
 /* PeliCAN mode */
 enum SJA1000_PeliCAN_regs {


@@ -72,44 +76,44 @@ enum SJA1000_PeliCAN_regs {
 
 /** Mode Register 0x00 */
 enum sja1000_PeliCAN_MOD {
 
 /** Mode Register 0x00 */
 enum sja1000_PeliCAN_MOD {

-       MOD_SM = 1<<4,  // Sleep Mode (writable only in OPERATING mode)
-       MOD_AFM= 1<<3,  // Acceptance Filter Mode (writable only in RESET)
-       MOD_STM= 1<<2,  // Self Test Mode (writable only in RESET)
-       MOD_LOM= 1<<1,  // Listen Only Mode (writable only in RESET)
-       MOD_RM = 1      // Reset Mode
+       sjaMOD_SM = 1<<4,  // Sleep Mode (writable only in OPERATING mode)
+       sjaMOD_AFM= 1<<3,  // Acceptance Filter Mode (writable only in RESET)
+       sjaMOD_STM= 1<<2,  // Self Test Mode (writable only in RESET)
+       sjaMOD_LOM= 1<<1,  // Listen Only Mode (writable only in RESET)
+       sjaMOD_RM = 1      // Reset Mode

 };
 
 /** Command Register 0x01 */
 enum sja1000_PeliCAN_CMR { 
 };
 
 /** Command Register 0x01 */
 enum sja1000_PeliCAN_CMR { 

-       CMR_SRR = 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
-       CMR_CDO = 1<<3, // Clear Data Overrun
-       CMR_RRB = 1<<2, // Release Receive Buffer
-       CMR_AT = 1<<1,  // Abort Transmission
-       CMR_TR = 1 };   // Transmission Request
+       sjaCMR_SRR= 1<<4,  // Self Reception Request (GoToSleep in BASIC mode)
+       sjaCMR_CDO= 1<<3,  // Clear Data Overrun
+       sjaCMR_RRB= 1<<2,  // Release Receive Buffer
+       sjaCMR_AT = 1<<1,  // Abort Transmission
+       sjaCMR_TR = 1 };   // Transmission Request

 
 /** Status Register 0x02 */
 enum sja1000_SR {
 
 /** Status Register 0x02 */
 enum sja1000_SR {

-       SR_BS = 1<<7,   // Bus Status
-       SR_ES = 1<<6,   // Error Status
-       SR_TS = 1<<5,   // Transmit Status
-       SR_RS = 1<<4,   // Receive Status
-       SR_TCS = 1<<3,  // Transmission Complete Status
-       SR_TBS = 1<<2,  // Transmit Buffer Status
-       SR_DOS = 1<<1,  // Data Overrun Status
-       SR_RBS = 1 };   // Receive Buffer Status
+       sjaSR_BS  = 1<<7,  // Bus Status
+       sjaSR_ES  = 1<<6,  // Error Status
+       sjaSR_TS  = 1<<5,  // Transmit Status
+       sjaSR_RS  = 1<<4,  // Receive Status
+       sjaSR_TCS = 1<<3,  // Transmission Complete Status
+       sjaSR_TBS = 1<<2,  // Transmit Buffer Status
+       sjaSR_DOS = 1<<1,  // Data Overrun Status
+       sjaSR_RBS = 1 };   // Receive Buffer Status

 
 /** Interrupt Enable Register 0x04 */
 enum sja1000_PeliCAN_IER {
 
 /** Interrupt Enable Register 0x04 */
 enum sja1000_PeliCAN_IER {

-       IER_BEIE= 1<<7, // Bus Error Interrupt Enable
-       IER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
-       IER_EPIE= 1<<5, // Error Passive Interrupt Enable
-       IER_WUIE= 1<<4, // Wake-Up Interrupt Enable
-       IER_DOIE = 1<<3,// Data Overrun Interrupt Enable
-       IER_EIE = 1<<2, // Error Warning Interrupt Enable
-       IER_TIE = 1<<1, // Transmit Interrupt Enable
-       IER_RIE = 1,    // Receive Interrupt Enable
-       ENABLE_INTERRUPTS = IER_BEIE|IER_EPIE|IER_DOIE|IER_EIE|IER_TIE|IER_RIE,
-       DISABLE_INTERRUPTS = 0
+       sjaIER_BEIE= 1<<7, // Bus Error Interrupt Enable
+       sjaIER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
+       sjaIER_EPIE= 1<<5, // Error Passive Interrupt Enable
+       sjaIER_WUIE= 1<<4, // Wake-Up Interrupt Enable
+       sjaIER_DOIE= 1<<3, // Data Overrun Interrupt Enable
+       sjaIER_EIE = 1<<2, // Error Warning Interrupt Enable
+       sjaIER_TIE = 1<<1, // Transmit Interrupt Enable
+       sjaIER_RIE = 1,    // Receive Interrupt Enable
+       sjaENABLE_INTERRUPTS = sjaIER_BEIE|sjaIER_EPIE|sjaIER_DOIE|sjaIER_EIE|sjaIER_TIE|sjaIER_RIE,
+       sjaDISABLE_INTERRUPTS = 0

 // WARNING: the chip automatically enters RESET (bus off) mode when 
        // error counter > 255
 };
 // WARNING: the chip automatically enters RESET (bus off) mode when 
        // error counter > 255
 };


@@ -117,73 +121,79 @@ enum sja1000_PeliCAN_IER {
 /** Arbitration Lost Capture Register 0x0b.
  * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
 enum sja1000_PeliCAN_ALC {
 /** Arbitration Lost Capture Register 0x0b.
  * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
 enum sja1000_PeliCAN_ALC {

-       ALC_SRTR = 0x0b, // Arbitration lost in bit SRTR
-       ALC_IDE = 0x1c,  // Arbitration lost in bit IDE
-       ALC_RTR = 0x1f, // Arbitration lost in RTR
+       sjaALC_SRTR = 0x0b,// Arbitration lost in bit SRTR
+       sjaALC_IDE  = 0x1c, // Arbitration lost in bit IDE
+       sjaALC_RTR  = 0x1f, // Arbitration lost in RTR

 };
 
 /** Error Code Capture Register 0x0c*/
 enum sja1000_PeliCAN_ECC {
 };
 
 /** Error Code Capture Register 0x0c*/
 enum sja1000_PeliCAN_ECC {

-       ECC_ERCC1 = 1<<7,
-       ECC_ERCC0 = 1<<6,
-       ECC_BIT = 0,
-       ECC_FORM = ECC_ERCC0,
-       ECC_STUFF = ECC_ERCC1,
-       ECC_OTHER = ECC_ERCC0 | ECC_ERCC1,
-       ECC_DIR = 1<<5, // 1 == RX, 0 == TX
-       ECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
+       sjaECC_ERCC1 = 1<<7,
+       sjaECC_ERCC0 = 1<<6,
+       sjaECC_BIT   = 0,
+       sjaECC_FORM  = sjaECC_ERCC0,
+       sjaECC_STUFF = sjaECC_ERCC1,
+       sjaECC_OTHER = sjaECC_ERCC0 | sjaECC_ERCC1,
+       sjaECC_DIR   = 1<<5,    // 1 == RX, 0 == TX
+       sjaECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet

 };
 
 /** Frame format information 0x10 */
 enum sja1000_PeliCAN_FRM {
 };
 
 /** Frame format information 0x10 */
 enum sja1000_PeliCAN_FRM {

-       FRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
-       FRM_RTR = 1<<6, // Remote request
-       FRM_DLC_M = (1<<4)-1 // Length Mask
+       sjaFRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
+       sjaFRM_RTR = 1<<6, // Remote request
+       sjaFRM_DLC_M = (1<<4)-1 // Length Mask

 };
 
 
 /** Interrupt (status) Register 0x03 */
 enum sja1000_PeliCAN_IR {
 };
 
 
 /** Interrupt (status) Register 0x03 */
 enum sja1000_PeliCAN_IR {

-       IR_BEI  = 1<<7, // Bus Error Interrupt
-       IR_ALI  = 1<<6, // Arbitration Lost Interrupt
-       IR_EPI  = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
-       IR_WUI = 1<<4,  // Wake-Up Interrupt
-       IR_DOI = 1<<3,  // Data Overrun Interrupt
-       IR_EI = 1<<2,   // Error Interrupt
-       IR_TI = 1<<1,   // Transmit Interrupt
-       IR_RI = 1       // Receive Interrupt
+       sjaIR_BEI = 1<<7,  // Bus Error Interrupt
+       sjaIR_ALI = 1<<6,  // Arbitration Lost Interrupt
+       sjaIR_EPI = 1<<5,  // Error Passive Interrupt (entered error passive state or error active state)
+       sjaIR_WUI = 1<<4,  // Wake-Up Interrupt
+       sjaIR_DOI = 1<<3,  // Data Overrun Interrupt
+       sjaIR_EI  = 1<<2,  // Error Interrupt
+       sjaIR_TI  = 1<<1,  // Transmit Interrupt
+       sjaIR_RI  = 1      // Receive Interrupt

 };
 
 };
 

-#if 0

 /** Bus Timing 1 Register 0x07 */
 enum sja1000_BTR1 {
 /** Bus Timing 1 Register 0x07 */
 enum sja1000_BTR1 {

-       MAX_TSEG1 = 15,
-       MAX_TSEG2 = 7
+       sjaMAX_TSEG1 = 15,
+       sjaMAX_TSEG2 = 7

 };
 };

-#endif

 
 /** Output Control Register 0x08 */
 enum sja1000_OCR {
 
 /** Output Control Register 0x08 */
 enum sja1000_OCR {

-       OCR_MODE_BIPHASE = 0,
-       OCR_MODE_TEST = 1,
-       OCR_MODE_NORMAL = 2,
-       OCR_MODE_CLOCK = 3,
+       sjaOCR_MODE_BIPHASE = 0,
+       sjaOCR_MODE_TEST = 1,
+       sjaOCR_MODE_NORMAL = 2,
+       sjaOCR_MODE_CLOCK = 3,

 /// TX0 push-pull not inverted
 /// TX0 push-pull not inverted

-       OCR_TX0_LH = 0x18,
+       sjaOCR_TX0_LH = 0x18,

 /// TX1 floating (off)
 /// TX1 floating (off)

-       OCR_TX1_ZZ = 0
+       sjaOCR_TX1_ZZ = 0

 };
 
 /** Clock Divider register 0x1f */
 enum sja1000_CDR {
 };
 
 /** Clock Divider register 0x1f */
 enum sja1000_CDR {

-       CDR_PELICAN = 1<<7,
+       sjaCDR_PELICAN = 1<<7,

 /// bypass input comparator
 /// bypass input comparator

-       CDR_CBP = 1<<6,
+       sjaCDR_CBP = 1<<6,

 /// switch TX1 to generate RX INT
 /// switch TX1 to generate RX INT

-       CDR_RXINPEN = 1<<5,
-       CDR_CLK_OFF = 1<<3,
+       sjaCDR_RXINPEN = 1<<5,
+       sjaCDR_CLK_OFF = 1<<3,

 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7

-       CDR_CLKOUT_MASK = 7
+       sjaCDR_CLKOUT_DIV1 = 7,
+       sjaCDR_CLKOUT_DIV2 = 0,
+       sjaCDR_CLKOUT_DIV4 = 1,
+       sjaCDR_CLKOUT_DIV6 = 2,
+       sjaCDR_CLKOUT_DIV8 = 3,
+       sjaCDR_CLKOUT_DIV10 = 4,
+       sjaCDR_CLKOUT_DIV12 = 5,
+       sjaCDR_CLKOUT_DIV14 = 6,
+       sjaCDR_CLKOUT_MASK = 7

 };
 
 /** flags for sja1000_baud_rate */
 };
 
 /** flags for sja1000_baud_rate */