* each register occupies 4 bytes
*/
-/*PSB4610 PITA-2 bridge control registers*/
+/*PSB4610 PITA-2 bridge control registers*/
#define PITA2_ICR 0x00 /* Interrupt Control Register */
#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
#define PITA2_ICR_GP0_INT 0x00000004 /* [RC] GP0 Interrupt */
/*
-The board configuration is probably following:
-" RX1 is connected to ground.
-" TX1 is not connected.
-" CLKO is not connected.
-" Setting the OCR register to 0xDA is a good idea.
- This means normal output mode , push-pull and the correct polarity.
-" In the CDR register, you should set CBP to 1.
+The board configuration is probably following:
+" RX1 is connected to ground.
+" TX1 is not connected.
+" CLKO is not connected.
+" Setting the OCR register to 0xDA is a good idea.
+ This means normal output mode , push-pull and the correct polarity.
+" In the CDR register, you should set CBP to 1.
You will probably also want to set the clock divider value to 7
- (meaning direct oscillator output) because the second SJA1000 chip
+ (meaning direct oscillator output) because the second SJA1000 chip
is driven by the first one CLKOUT output.
*/
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
- if (!(candev->aux_base_addr = ioremap(pita2_addr,
+ if (!(candev->aux_base_addr = ioremap(pita2_addr,
pci_resource_len(candev->sysdevptr.pcidev,0)))) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
goto error_ioremap_pita2;
candev->io_addr=io_addr;
candev->res_addr=pita2_addr;
-
- /*
- * this is redundant with chip initialization, but remap address
+
+ /*
+ * this is redundant with chip initialization, but remap address
* can change when resources are temporarily released
*/
for(i=0;i<candev->nr_all_chips;i++) {
#else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
pci_release_regions(candev->sysdevptr.pcidev);
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
-
+
return -ENODEV;
}
{
address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
*(EMS_CPCPCI_BYTES_PER_REG-1));
- can_writeb(data,address);
+ can_writeb(data,address);
}
unsigned ems_cpcpci_read_register(can_ioptr_t address)
icr=can_readl(candev->aux_base_addr + PITA2_ICR);
if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
-
+
/* correct way to handle interrupts from all chips connected to the one PITA-2 */
do {
can_writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->aux_base_addr + PITA2_ICR);
ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
-
+
ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
}
-
+
ems_cpcpci_connect_irq(candev);
return 0;
-}
+}
int ems_cpcpci_init_hw_data(struct candevice_t *candev)
{
pcidev = can_pci_get_next_untaken_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID);
if(pcidev == NULL)
return -ENODEV;
-
+
if (pci_enable_device (pcidev)){
printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
can_pci_dev_put(pcidev);
return -EIO;
}
candev->sysdevptr.pcidev=pcidev;
-
+
for(i=0;i<2;i++){
if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
* 0x600 the second SJA1000
* each register occupies 4 bytes
*/
-
+
/*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
-
+
for(l=0,i=0;i<4;i++){
l<<=8;
l|=can_readb(candev->dev_base_addr + i*4);
}
i=can_readb(candev->dev_base_addr + i*5);
-
+
CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
-
+
if(l!=0x55aa01cb) {
CANMSG("EMS CPC-PCI unexpected check values\n");
}
/* initialize common routines for the SJA1000 chip */
sja1000p_fill_chipspecops(candev->chip[chipnr]);
-
+
/* special version of the IRQ handler is required for CPC-PCI board */
candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
return 0;
-}
+}
int ems_cpcpci_init_obj_data(struct canchip_t *chip, int objnr)
{