2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
10 int i82527_enable_configuration(struct canchip_t *chip);
11 int i82527_disable_configuration(struct canchip_t *chip);
12 int i82527_chip_config(struct canchip_t *chip);
13 int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
14 int sampl_pt, int flags);
15 int i82527_standard_mask(struct canchip_t *chip, unsigned short code,
17 int i82527_extended_mask(struct canchip_t *chip, unsigned long code,
19 int i82527_message15_mask(struct canchip_t *chip, unsigned long code,
21 int i82527_clear_objects(struct canchip_t *chip);
22 int i82527_config_irqs(struct canchip_t *chip, short irqs);
23 int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
24 int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
25 struct canmsg_t *msg);
26 int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
27 struct canmsg_t *msg);
28 int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj);
29 int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
31 int i82527_start_chip(struct canchip_t *chip);
32 int i82527_stop_chip(struct canchip_t *chip);
33 int i82527_check_tx_stat(struct canchip_t *chip);
34 int i82527_irq_handler(int irq, struct canchip_t *chip);
35 int i82527_fill_chipspecops(struct canchip_t *chip);
38 #define MSG_OFFSET(object) ((object)*0x10)
40 #define iCTL 0x00 // Control Register
41 #define iSTAT 0x01 // Status Register
42 #define iCPU 0x02 // CPU Interface Register
43 #define iHSR 0x04 // High Speed Read
44 #define iSGM0 0x06 // Standard Global Mask byte 0
46 #define iEGM0 0x08 // Extended Global Mask byte 0
50 #define i15M0 0x0c // Message 15 Mask byte 0
54 #define iCLK 0x1f // Clock Out Register
55 #define iBUS 0x2f // Bus Configuration Register
56 #define iBT0 0x3f // Bit Timing Register byte 0
58 #define iIRQ 0x5f // Interrupt Register
59 #define iP1C 0x9f // Port 1 Register
60 #define iP2C 0xaf // Port 2 Register
61 #define iP1I 0xbf // Port 1 Data In Register
62 #define iP2I 0xcf // Port 2 Data In Register
63 #define iP1O 0xdf // Port 1 Data Out Register
64 #define iP2O 0xef // Port 2 Data Out Register
65 #define iSRA 0xff // Serial Reset Address
67 #define iMSGCTL0 0x00 /* First Control register */
68 #define iMSGCTL1 0x01 /* Second Control register */
69 #define iMSGID0 0x02 /* First Byte of Message ID */
73 #define iMSGCFG 0x06 /* Message Configuration */
74 #define iMSGDAT0 0x07 /* First Data Byte */
83 /* Control Register (0x00) */
85 iCTL_INI = 1, // Initialization
86 iCTL_IE = 1<<1, // Interrupt Enable
87 iCTL_SIE = 1<<2, // Status Interrupt Enable
88 iCTL_EIE = 1<<3, // Error Interrupt Enable
89 iCTL_CCE = 1<<6 // Change Configuration Enable
92 /* Status Register (0x01) */
94 iSTAT_TXOK = 1<<3, // Transmit Message Successfully
95 iSTAT_RXOK = 1<<4, // Receive Message Successfully
96 iSTAT_WAKE = 1<<5, // Wake Up Status
97 iSTAT_WARN = 1<<6, // Warning Status
98 iSTAT_BOFF = 1<<7 // Bus Off Status
101 /* CPU Interface Register (0x02) */
103 iCPU_CEN = 1, // Clock Out Enable
104 iCPU_MUX = 1<<2, // Multiplex
105 iCPU_SLP = 1<<3, // Sleep
106 iCPU_PWD = 1<<4, // Power Down Mode
107 iCPU_DMC = 1<<5, // Divide Memory Clock
108 iCPU_DSC = 1<<6, // Divide System Clock
109 iCPU_RST = 1<<7 // Hardware Reset Status
112 /* Clock Out Register (0x1f) */
114 iCLK_CD0 = 1, // Clock Divider bit 0
118 iCLK_SL0 = 1<<4, // Slew Rate bit 0
122 /* Bus Configuration Register (0x2f) */
124 iBUS_DR0 = 1, // Disconnect RX0 Input
125 iBUS_DR1 = 1<<1, // Disconnect RX1 Input
126 iBUS_DT1 = 1<<3, // Disconnect TX1 Output
127 iBUS_POL = 1<<5, // Polarity
128 iBUS_CBY = 1<<6 // Comparator Bypass
131 #define RESET 1 // Bit Pair Reset Status
132 #define SET 2 // Bit Pair Set Status
133 #define UNCHANGED 3 // Bit Pair Unchanged
135 /* Message Control Register 0 (Base Address + 0x0) */
136 enum i82527_iMSGCTL0 {
137 INTPD_SET = SET, // Interrupt pending
138 INTPD_RES = RESET, // No Interrupt pending
139 INTPD_UNC = UNCHANGED,
140 RXIE_SET = SET<<2, // Receive Interrupt Enable
141 RXIE_RES = RESET<<2, // Receive Interrupt Disable
142 RXIE_UNC = UNCHANGED<<2,
143 TXIE_SET = SET<<4, // Transmit Interrupt Enable
144 TXIE_RES = RESET<<4, // Transmit Interrupt Disable
145 TXIE_UNC = UNCHANGED<<4,
146 MVAL_SET = SET<<6, // Message Valid
147 MVAL_RES = RESET<<6, // Message Invalid
148 MVAL_UNC = UNCHANGED<<6
151 /* Message Control Register 1 (Base Address + 0x01) */
152 enum i82527_iMSGCTL1 {
153 NEWD_SET = SET, // New Data
154 NEWD_RES = RESET, // No New Data
155 NEWD_UNC = UNCHANGED,
156 MLST_SET = SET<<2, // Message Lost
157 MLST_RES = RESET<<2, // No Message Lost
158 MLST_UNC = UNCHANGED<<2,
159 CPUU_SET = SET<<2, // CPU Updating
160 CPUU_RES = RESET<<2, // No CPU Updating
161 CPUU_UNC = UNCHANGED<<2,
162 TXRQ_SET = SET<<4, // Transmission Request
163 TXRQ_RES = RESET<<4, // No Transmission Request
164 TXRQ_UNC = UNCHANGED<<4,
165 RMPD_SET = SET<<6, // Remote Request Pending
166 RMPD_RES = RESET<<6, // No Remote Request Pending
167 RMPD_UNC = UNCHANGED<<6
170 /* Message Configuration Register (Base Address + 0x06) */
171 enum i82527_iMSGCFG {
172 MCFG_XTD = 1<<2, // Extended Identifier
173 MCFG_DIR = 1<<3 // Direction is Transmit
176 void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address);
177 unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address);