2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.6.1 T.Motylewski@bfad.de 13.03.2001
6 * See app. note an97076.pdf from Philips Semiconductors
7 * and SJA1000 data sheet
11 int sja1000p_chip_config(struct chip_t *chip);
12 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask);
13 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
14 int sampl_pt, int flags);
15 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
16 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
17 struct canmsg_t *msg);
18 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
19 struct canmsg_t *msg);
22 enum SJA1000_PeliCAN_regs {
28 /// Interrupt register
32 /// Bus Timing register 0
34 /// Bus Timing register 1
36 /// Output Control register
38 /// Arbitration Lost Capture
40 /// Error Code Capture
42 /// Error Warning Limit
49 /// Rx Message Counter (number of msgs. in RX FIFO
51 /// Rx Buffer Start Addr. (address of current MSG)
53 /// Transmit Buffer (write) Receive Buffer (read) Frame Information
55 /// ID bytes (11 bits in 0 and 1 or 16 bits in 0,1 and 13 bits in 2,3 (extended))
56 SJAID0 = 0x11, SJAID1 = 0x12,
57 /// ID cont. for extended frames
58 SJAID2 = 0x13, SJAID3 = 0x14,
59 /// Data start standard frame
61 /// Data start extended frame
63 /// Acceptance Code (4 bytes) in RESET mode
65 /// Acceptance Mask (4 bytes) in RESET mode
68 SJA_PeliCAN_AC_LEN = 4,
73 /** Mode Register 0x00 */
74 enum sja1000_PeliCAN_MOD {
75 MOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
76 MOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
77 MOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
78 MOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
79 MOD_RM = 1 // Reset Mode
82 /** Command Register 0x01 */
83 enum sja1000_PeliCAN_CMR {
84 CMR_SRR = 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
85 CMR_CDO = 1<<3, // Clear Data Overrun
86 CMR_RRB = 1<<2, // Release Receive Buffer
87 CMR_AT = 1<<1, // Abort Transmission
88 CMR_TR = 1 }; // Transmission Request
90 /** Status Register 0x02 */
92 SR_BS = 1<<7, // Bus Status
93 SR_ES = 1<<6, // Error Status
94 SR_TS = 1<<5, // Transmit Status
95 SR_RS = 1<<4, // Receive Status
96 SR_TCS = 1<<3, // Transmission Complete Status
97 SR_TBS = 1<<2, // Transmit Buffer Status
98 SR_DOS = 1<<1, // Data Overrun Status
99 SR_RBS = 1 }; // Receive Buffer Status
101 /** Interrupt Enable Register 0x04 */
102 enum sja1000_PeliCAN_IER {
103 IER_BEIE= 1<<7, // Bus Error Interrupt Enable
104 IER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
105 IER_EPIE= 1<<5, // Error Passive Interrupt Enable
106 IER_WUIE= 1<<4, // Wake-Up Interrupt Enable
107 IER_DOIE = 1<<3,// Data Overrun Interrupt Enable
108 IER_EIE = 1<<2, // Error Warning Interrupt Enable
109 IER_TIE = 1<<1, // Transmit Interrupt Enable
110 IER_RIE = 1, // Receive Interrupt Enable
111 ENABLE_INTERRUPTS = IER_BEIE|IER_EPIE|IER_DOIE|IER_EIE|IER_TIE|IER_RIE,
112 DISABLE_INTERRUPTS = 0
113 // WARNING: the chip automatically enters RESET (bus off) mode when
114 // error counter > 255
117 /** Arbitration Lost Capture Register 0x0b.
118 * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
119 enum sja1000_PeliCAN_ALC {
120 ALC_SRTR = 0x0b, // Arbitration lost in bit SRTR
121 ALC_IDE = 0x1c, // Arbitration lost in bit IDE
122 ALC_RTR = 0x1f, // Arbitration lost in RTR
125 /** Error Code Capture Register 0x0c*/
126 enum sja1000_PeliCAN_ECC {
130 ECC_FORM = ECC_ERCC0,
131 ECC_STUFF = ECC_ERCC1,
132 ECC_OTHER = ECC_ERCC0 | ECC_ERCC1,
133 ECC_DIR = 1<<5, // 1 == RX, 0 == TX
134 ECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
137 /** Frame format information 0x10 */
138 enum sja1000_PeliCAN_FRM {
139 FRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
140 FRM_RTR = 1<<6, // Remote request
141 FRM_DLC_M = (1<<4)-1 // Length Mask
145 /** Interrupt (status) Register 0x03 */
146 enum sja1000_PeliCAN_IR {
147 IR_BEI = 1<<7, // Bus Error Interrupt
148 IR_ALI = 1<<6, // Arbitration Lost Interrupt
149 IR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
150 IR_WUI = 1<<4, // Wake-Up Interrupt
151 IR_DOI = 1<<3, // Data Overrun Interrupt
152 IR_EI = 1<<2, // Error Interrupt
153 IR_TI = 1<<1, // Transmit Interrupt
154 IR_RI = 1 // Receive Interrupt
158 /** Bus Timing 1 Register 0x07 */
165 /** Output Control Register 0x08 */
167 OCR_MODE_BIPHASE = 0,
171 /// TX0 push-pull not inverted
173 /// TX1 floating (off)
177 /** Clock Divider register 0x1f */
180 /// bypass input comparator
182 /// switch TX1 to generate RX INT
185 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
189 /** flags for sja1000_baud_rate */
190 #define BTR1_SAM (1<<1)