1 /**************************************************************************/
2 /* File: pimx1.c - MX1_DIS1 extension board for PiMX1 ARM based BCC */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Funded by OCERA and FRESCOR IST projects */
8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
10 /* LinCAN is free software; you can redistribute it and/or modify it */
11 /* under terms of the GNU General Public License as published by the */
12 /* Free Software Foundation; either version 2, or (at your option) any */
13 /* later version. LinCAN is distributed in the hope that it will be */
14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
16 /* General Public License for more details. You should have received a */
17 /* copy of the GNU General Public License along with LinCAN; see file */
18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
19 /* Cambridge, MA 02139, USA. */
21 /* To allow use of LinCAN in the compact embedded systems firmware */
22 /* and RT-executives (RTEMS for example), main authors agree with next */
23 /* special exception: */
25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
26 /* or templates, or linking other files with LinCAN objects to produce */
27 /* an application image/executable, does not by itself cause the */
28 /* resulting application image/executable to be covered by */
29 /* the GNU General Public License. */
30 /* This exception does not however invalidate any other reasons */
31 /* why the executable file might be covered by the GNU Public License. */
32 /* Publication of enhanced or derived LinCAN files is required although. */
33 /**************************************************************************/
35 #include "../include/can.h"
36 #include "../include/can_sysdep.h"
37 #include "../include/main.h"
38 #include "../include/sja1000p.h"
39 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) && defined(CONFIG_GENERIC_HARDIRQS)
40 #include <linux/irq.h>
42 #include <asm/arch/hardware.h>
43 #include <asm/arch/imx-regs.h>
45 #define EIM_CS1U __REG(IMX_EIM_BASE + 0x08)
46 #define EIM_CS1L __REG(IMX_EIM_BASE + 0x0C)
49 * IO_RANGE is the io-memory range that gets reserved, please adjust according
50 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
51 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
53 #define PIMX1_CAN_IO_ADDRESS 0x12000000
54 #define PIMX1_CAN_IO_RANGE 0x100
55 #define PIMX1_CAN_IRQ IRQ_GPIOB(17)
56 #define PIMX1_CAN_RESET_ADDR 0x0
60 static CAN_DEFINE_SPINLOCK(pimx1_setup_hardware_lock);
62 int pimx1_setup_hardware(struct candevice_t *candev)
64 can_spin_irqflags_t flags;
66 can_spin_lock_irqsave(&pimx1_setup_hardware_lock,flags);
67 /* CNC=0; WSC=10-1; WWS=0; EDC=2; OEA=6; OEN=2; WEA=8; WEN=2 */
68 EIM_CS1U = 0x00000902;
69 EIM_CS1L = 0x82820903;
70 imx_gpio_mode(PA21_PF_A0);
72 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14))
73 /* Setup IRQ port as input */
74 imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | GPIO_PUEN | 17);
75 /* Setup SJA1000 reset as output */
76 imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_OUT | GPIO_DR | 15);
78 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | GPIO_GPIO | 17);
79 imx_gpio_mode(GPIO_PORTB | GPIO_OUT | GPIO_GPIO | 15);
83 can_spin_unlock_irqrestore(&pimx1_setup_hardware_lock,flags);
85 set_irq_type(PIMX1_CAN_IRQ, IRQT_LOW);
92 * pimx1_request_io: - reserve io or memory range for can board
93 * @candev: pointer to candevice/board which asks for io. Field @io_addr
94 * of @candev is used in most cases to define start of the range
96 * The function pimx1_request_io() is used to reserve the io-memory. If your
97 * hardware uses a dedicated memory range as hardware control registers you
98 * will have to add the code to reserve this memory as well.
99 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
100 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
101 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
102 * Return Value: The function returns zero on success or %-ENODEV on failure
103 * File: src/pikronisa.c
105 int pimx1_request_io(struct candevice_t *candev)
107 can_ioptr_t remap_addr;
109 if(pimx1_setup_hardware(candev)<0){
110 CANMSG("PiMX1 board hardware setup failure\n");
114 if (!can_request_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE,DEVICE_NAME " - pimx1")) {
115 CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
118 if ( !( remap_addr = (long) ioremap( candev->io_addr, PIMX1_CAN_IO_RANGE ) ) ) {
119 CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
120 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
123 can_base_addr_fixup(candev, remap_addr);
124 CANMSG("Registered IO-memory: 0x%lx - 0x%lx (VMA 0x%lx)\n",
125 candev->io_addr, candev->io_addr + PIMX1_CAN_IO_RANGE - 1, (long)remap_addr);
130 * pimx1_elease_io - free reserved io memory range
131 * @candev: pointer to candevice/board which releases io
133 * The function pimx1_release_io() is used to free reserved io-memory.
134 * In case you have reserved more io memory, don't forget to free it here.
135 * IO_RANGE is the io-memory range that gets released, please adjust according
136 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
137 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
138 * Return Value: The function always returns zero
139 * File: src/pikronisa.c
141 int pimx1_release_io(struct candevice_t *candev)
143 /* release I/O memory mapping */
144 iounmap((void*)candev->dev_base_addr);
145 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
151 * pimx1_write_register - Low level write register routine
152 * @data: data to be written
153 * @address: memory address to write to
155 * The function pimx1_write_register() is used to write to hardware registers
156 * on the CAN chip. You should only have to edit this function if your hardware
157 * uses some specific write process.
158 * Return Value: The function does not return a value
159 * File: src/pikronisa.c
161 void pimx1_write_register(unsigned data, can_ioptr_t address)
163 /*DEBUGMSG("pimx1_write_register: addr=0x%lx data=0x%x\n",
165 can_writeb(data,address);
169 * pimx1_read_register - Low level read register routine
170 * @address: memory address to read from
172 * The function pimx1_read_register() is used to read from hardware registers
173 * on the CAN chip. You should only have to edit this function if your hardware
174 * uses some specific read process.
175 * Return Value: The function returns the value stored in @address
176 * File: src/pikronisa.c
178 unsigned pimx1_read_register(can_ioptr_t address)
180 return can_readb(address);
184 * pimx1_reset - hardware reset routine
185 * @candev: Pointer to candevice/board structure
187 * The function pimx1_reset() is used to give a hardware reset. This is
188 * rather hardware specific so I haven't included example code. Don't forget to
189 * check the reset status of the chip before returning.
190 * Return Value: The function returns zero on success or %-ENODEV on failure
191 * File: src/pikronisa.c
193 int pimx1_reset(struct candevice_t *candev)
196 struct canchip_t *chip=candev->chip[0];
199 pimx1_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
202 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
203 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
205 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
208 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
209 while (pimx1_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
210 if(!i--) return -ENODEV;
212 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
215 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
216 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
218 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
224 * pimx1_init_hw_data - Initialize hardware cards
225 * @candev: Pointer to candevice/board structure
227 * The function pimx1_init_hw_data() is used to initialize the hardware
228 * structure containing information about the installed CAN-board.
229 * %RESET_ADDR represents the io-address of the hardware reset register.
230 * %NR_82527 represents the number of intel 82527 chips on the board.
231 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
232 * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
233 * the hardware uses programmable interrupts.
234 * Return Value: The function always returns zero
235 * File: src/pikronisa.c
237 int pimx1_init_hw_data(struct candevice_t *candev)
239 candev->res_addr=PIMX1_CAN_RESET_ADDR;
240 candev->io_addr=PIMX1_CAN_IO_ADDRESS;
241 candev->dev_base_addr=PIMX1_CAN_IO_ADDRESS;
242 candev->nr_82527_chips=0;
243 candev->nr_sja1000_chips=1;
244 candev->nr_all_chips=1;
245 candev->flags |= CANDEV_PROGRAMMABLE_IRQ*0;
251 * pimx1_init_chip_data - Initialize chips
252 * @candev: Pointer to candevice/board structure
253 * @chipnr: Number of the CAN chip on the hardware card
255 * The function pimx1_init_chip_data() is used to initialize the hardware
256 * structure containing information about the CAN chips.
257 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
259 * The @chip_base_addr entry represents the start of the 'official' memory map
260 * of the installed chip. It's likely that this is the same as the @io_addr
261 * argument supplied at module loading time.
262 * The @clock entry holds the chip clock value in Hz.
263 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
264 * register. Options defined in the %sja1000.h file:
265 * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
266 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
267 * register. Options defined in the %sja1000.h file:
268 * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
269 * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
270 * The entry @int_clk_reg holds hardware specific options for the Clock Out
271 * register. Options defined in the %i82527.h file:
272 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
273 * The entry @int_bus_reg holds hardware specific options for the Bus
274 * Configuration register. Options defined in the %i82527.h file:
275 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
276 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
277 * register. Options defined in the %i82527.h file:
278 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
279 * Return Value: The function always returns zero
280 * File: src/pikronisa.c
282 int pimx1_init_chip_data(struct candevice_t *candev, int chipnr)
284 /*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
285 sja1000p_fill_chipspecops(candev->chip[chipnr]);
287 candev->chip[chipnr]->chip_base_addr=candev->io_addr;
288 candev->chip[chipnr]->chip_irq=PIMX1_CAN_IRQ;
289 candev->chip[chipnr]->clock = 24000000;
290 candev->chip[chipnr]->int_clk_reg = 0x0;
291 candev->chip[chipnr]->int_bus_reg = 0x0;
292 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
293 candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
299 * pimx1_init_obj_data - Initialize message buffers
300 * @chip: Pointer to chip specific structure
301 * @objnr: Number of the message buffer
303 * The function pimx1_init_obj_data() is used to initialize the hardware
304 * structure containing information about the different message objects on the
305 * CAN chip. In case of the sja1000 there's only one message object but on the
306 * i82527 chip there are 15.
307 * The code below is for a i82527 chip and initializes the object base addresses
308 * The entry @obj_base_addr represents the first memory address of the message
309 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
311 * Unless the hardware uses a segmented memory map, flags can be set zero.
312 * Return Value: The function always returns zero
313 * File: src/pikronisa.c
315 int pimx1_init_obj_data(struct canchip_t *chip, int objnr)
317 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
322 * pimx1_program_irq - program interrupts
323 * @candev: Pointer to candevice/board structure
325 * The function pimx1_program_irq() is used for hardware that uses
326 * programmable interrupts. If your hardware doesn't use programmable interrupts
327 * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
328 * leave this function unedited. Again this function is hardware specific so
329 * there's no example code.
330 * Return value: The function returns zero on success or %-ENODEV on failure
331 * File: src/pikronisa.c
333 int pimx1_program_irq(struct candevice_t *candev)
338 /* !!! Don't change this function !!! */
339 int pimx1_register(struct hwspecops_t *hwspecops)
341 hwspecops->request_io = pimx1_request_io;
342 hwspecops->release_io = pimx1_release_io;
343 hwspecops->reset = pimx1_reset;
344 hwspecops->init_hw_data = pimx1_init_hw_data;
345 hwspecops->init_chip_data = pimx1_init_chip_data;
346 hwspecops->init_obj_data = pimx1_init_obj_data;
347 hwspecops->write_register = pimx1_write_register;
348 hwspecops->read_register = pimx1_read_register;
349 hwspecops->program_irq = pimx1_program_irq;