1 /******************************************************************************
3 * $RCSfile: LPC214x.h,v $
6 * Header file for Philips LPC214x ARM Processors
7 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact or GPL license is applied.
13 *****************************************************************************/
18 ///////////////////////////////////////////////////////////////////////////////
19 // ISP_RAM2FLASH_BLOCK_SIZE for 210x CPU
20 #ifndef ISP_RAM2FLASH_BLOCK_SIZE
21 #define ISP_RAM2FLASH_BLOCK_SIZE 256
22 #endif /* ISP_RAM2FLASH_BLOCK_SIZE */
27 #include "lpcADC-214x.h"
29 // USB Phase Locked Loop Registers (PLL48)
30 #define PLLCON48 SCB->pll48.con /* Control Register */
31 #define PLLCFG48 SCB->pll48.cfg /* Configuration Register */
32 #define PLLSTAT48 SCB->pll48.stat /* Status Register */
33 #define PLLFEED48 SCB->pll48.feed /* Feed Register */
35 ///////////////////////////////////////////////////////////////////////////////
38 #define USBIntSt (*(REG32*)0xE01FC1C0) /* USB Interrupt Status (R/W) */
42 #define USB ((usbRegs_t *)0xE0090000)
44 #define USBDevIntSt USB->DevIntSt
45 #define USBDevIntEn USB->DevIntEn
46 #define USBDevIntClr USB->DevIntClr
47 #define USBDevIntSet USB->DevIntSet
48 #define USBDevIntPri USB->DevIntPri
49 #define USBEpIntSt USB->EpIntSt
50 #define USBEpIntEn USB->EpIntEn
51 #define USBEpIntClr USB->EpIntClr
52 #define USBEpIntSet USB->EpIntSet
53 #define USBEpIntPri USB->EpIntPri
54 #define USBReEp USB->ReEp
55 #define USBEpInd USB->EpInd
56 #define USBMaxPSize USB->MaxPSize
57 #define USBRxData USB->RxData
58 #define USBRxPLen USB->RxPLen
59 #define USBTxData USB->TxData
60 #define USBTxPLen USB->TxPLen
61 #define USBCtrl USB->Ctrl
62 #define USBCmdCode USB->CmdCode
63 #define USBCmdData USB->CmdData
64 #define USBDMARSt USB->DMARSt
65 #define USBDMARClr USB->DMARClr
66 #define USBDMARSet USB->DMARSet
67 #define USBUDCAH USB->UDCAH
68 #define USBEpDMASt USB->EpDMASt
69 #define USBEpDMAEn USB->EpDMAEn
70 #define USBEpDMADis USB->EpDMADis
71 #define USBDMAIntSt USB->DMAIntSt
72 #define USBDMAIntEn USB->DMAIntEn
73 #define USBEoTIntSt USB->EoTIntSt
74 #define USBEoTIntClr USB->EoTIntClr
75 #define USBEoTIntSet USB->EoTIntSet
76 #define USBNDDRIntSt USB->NDDRIntSt
77 #define USBNDDRIntClr USB->NDDRIntClr
78 #define USBNDDRIntSet USB->NDDRIntSet
79 #define USBSysErrIntSt USB->SysErrIntSt
80 #define USBSysErrIntClr USB->SysErrIntClr
81 #define USBSysErrIntSet USB->SysErrIntSet
82 #define USB_MODULE_ID USB->MODULE_ID
85 #define USB_REGS_BASE 0xE0090000
87 #define USBDevIntSt (*(REG32*)(USB_REGS_BASE+USBDevIntSt_o))
88 #define USBDevIntEn (*(REG32*)(USB_REGS_BASE+USBDevIntEn_o))
89 #define USBDevIntClr (*(REG32*)(USB_REGS_BASE+USBDevIntClr_o))
90 #define USBDevIntSet (*(REG32*)(USB_REGS_BASE+USBDevIntSet_o))
91 #define USBDevIntPri (*(REG_8*)(USB_REGS_BASE+USBDevIntPri_o))
92 #define USBEpIntSt (*(REG32*)(USB_REGS_BASE+USBEpIntSt_o))
93 #define USBEpIntEn (*(REG32*)(USB_REGS_BASE+USBEpIntEn_o))
94 #define USBEpIntClr (*(REG32*)(USB_REGS_BASE+USBEpIntClr_o))
95 #define USBEpIntSet (*(REG32*)(USB_REGS_BASE+USBEpIntSet_o))
96 #define USBEpIntPri (*(REG32*)(USB_REGS_BASE+USBEpIntPri_o))
97 #define USBReEp (*(REG32*)(USB_REGS_BASE+USBReEp_o))
98 #define USBEpInd (*(REG32*)(USB_REGS_BASE+USBEpInd_o))
99 #define USBMaxPSize (*(REG32*)(USB_REGS_BASE+USBMaxPSize_o))
100 #define USBRxData (*(REG32*)(USB_REGS_BASE+USBRxData_o))
101 #define USBRxPLen (*(REG32*)(USB_REGS_BASE+USBRxPLen_o))
102 #define USBTxData (*(REG32*)(USB_REGS_BASE+USBTxData_o))
103 #define USBTxPLen (*(REG32*)(USB_REGS_BASE+USBTxPLen_o))
104 #define USBCtrl (*(REG32*)(USB_REGS_BASE+USBCtrl_o))
105 #define USBCmdCode (*(REG32*)(USB_REGS_BASE+USBCmdCode_o))
106 #define USBCmdData (*(REG32*)(USB_REGS_BASE+USBCmdData_o))
107 #define USBDMARSt (*(REG32*)(USB_REGS_BASE+USBDMARSt_o))
108 #define USBDMARClr (*(REG32*)(USB_REGS_BASE+USBDMARClr_o))
109 #define USBDMARSet (*(REG32*)(USB_REGS_BASE+USBDMARSet_o))
110 #define USBUDCAH (*(REG32*)(USB_REGS_BASE+USBUDCAH_o))
111 #define USBEpDMASt (*(REG32*)(USB_REGS_BASE+USBEpDMASt_o))
112 #define USBEpDMAEn (*(REG32*)(USB_REGS_BASE+USBEpDMAEn_o))
113 #define USBEpDMADis (*(REG32*)(USB_REGS_BASE+USBEpDMADis_o))
114 #define USBDMAIntSt (*(REG32*)(USB_REGS_BASE+USBDMAIntSt_o))
115 #define USBDMAIntEn (*(REG32*)(USB_REGS_BASE+USBDMAIntEn_o))
116 #define USBEoTIntSt (*(REG32*)(USB_REGS_BASE+USBEoTIntSt_o))
117 #define USBEoTIntClr (*(REG32*)(USB_REGS_BASE+USBEoTIntClr_o))
118 #define USBEoTIntSet (*(REG32*)(USB_REGS_BASE+USBEoTIntSet_o))
119 #define USBNDDRIntSt (*(REG32*)(USB_REGS_BASE+USBNDDRIntSt_o))
120 #define USBNDDRIntClr (*(REG32*)(USB_REGS_BASE+USBNDDRIntClr_o))
121 #define USBNDDRIntSet (*(REG32*)(USB_REGS_BASE+USBNDDRIntSet_o))
122 #define USBSysErrIntSt (*(REG32*)(USB_REGS_BASE+USBSysErrIntSt_o))
123 #define USBSysErrIntClr (*(REG32*)(USB_REGS_BASE+USBSysErrIntClr_o))
124 #define USBSysErrIntSet (*(REG32*)(USB_REGS_BASE+USBSysErrIntSet_o))
125 #define USB_MODULE_ID (*(REG32*)(USB_REGS_BASE+USB_MODULE_ID_o))
130 ///////////////////////////////////////////////////////////////////////////////
132 #define ADC0 ((adc214xRegs_t *)0xE0034000)
134 #define AD0CR ADC0->cr // Control Register
135 #define AD0GDR ADC0->gdr // Global Data Register
136 #define AD0GSR ADC0->gsr // Global Start Register
137 #define AD0INTEN ADC0->inten // Interrupt Enable Register
138 #define AD0DR0 ADC0->dr0 // Channel 0 Data Register
139 #define AD0DR1 ADC0->dr1 // Channel 1 Data Register
140 #define AD0DR2 ADC0->dr2 // Channel 2 Data Register
141 #define AD0DR3 ADC0->dr3 // Channel 3 Data Register
142 #define AD0DR4 ADC0->dr4 // Channel 4 Data Register
143 #define AD0DR5 ADC0->dr5 // Channel 5 Data Register
144 #define AD0DR6 ADC0->dr6 // Channel 6 Data Register
145 #define AD0DR7 ADC0->dr7 // Channel 7 Data Register
146 #define AD0STAT ADC0->stat // Status Register
148 #define ADC1 ((adc214xRegs_t *)0xE0060000)
150 #define AD1CR ADC0->cr // Control Register
151 #define AD1GDR ADC0->gdr // Global Data Register
152 #define AD1GSR ADC0->gsr // Global Start Register
153 #define AD1INTEN ADC0->inten // Interrupt Enable Register
154 #define AD1DR0 ADC0->dr0 // Channel 0 Data Register
155 #define AD1DR1 ADC0->dr1 // Channel 1 Data Register
156 #define AD1DR2 ADC0->dr2 // Channel 2 Data Register
157 #define AD1DR3 ADC0->dr3 // Channel 3 Data Register
158 #define AD1DR4 ADC0->dr4 // Channel 4 Data Register
159 #define AD1DR5 ADC0->dr5 // Channel 5 Data Register
160 #define AD1DR6 ADC0->dr6 // Channel 6 Data Register
161 #define AD1DR7 ADC0->dr7 // Channel 7 Data Register
162 #define AD1STAT ADC0->stat // Status Register
165 #endif /*INC_LPC21xx_H*/