lincan/src/sja1000p.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * This software is released under the GPL-License.
   5  * Version 0.6 18 Sept 2000
   6  * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
   7  * T.Motylewski@bfad.de
   8  */
   9
  10 #include <linux/autoconf.h>
  11 #if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
  12 #define MODVERSIONS
  13 #endif
  14
  15 #if defined (MODVERSIONS)
  16 #include <linux/modversions.h>
  17 #endif
  18
  19 #include <linux/sched.h>
  20 #include <linux/delay.h>
  21 #include <asm/irq.h>
  22
  23 #include "../include/main.h"
  24 #include "../include/sja1000p.h"
  25
  26 struct chip_t *chip_irq=NULL;
  27 struct candevice_t *device_irq=NULL;
  28 struct canfifo_t *fifo_irq=NULL;
  29 void (*put_reg)(unsigned char data, unsigned long address);
  30 unsigned (*get_reg)(unsigned long address);
  31
  32
  33
  34 int sja1000p_enable_configuration(struct chip_t *chip)
  35 {
  36         int i=0;
  37         enum sja1000_PeliCAN_MOD flags;
  38
  39         disable_irq(chip->chip_irq);
  40
  41         flags=can_read_reg(chip,SJAMOD);
  42
  43         while ((!(flags & MOD_RM)) && (i<=10)) {
  44                 can_write_reg(chip, MOD_RM, SJAMOD);
  45 // TODO: chinfigurable MOD_AFM (32/16 bit acceptance filter)
  46 // config MOD_LOM (listen only)
  47                 udelay(100);
  48                 i++;
  49                 flags=can_read_reg(chip, SJAMOD);
  50         }
  51         if (i>=10) {
  52                 CANMSG("Reset error\n");
  53                 enable_irq(chip->chip_irq);
  54                 return -ENODEV;
  55         }
  56
  57         return 0;
  58 }
  59
  60 int sja1000p_disable_configuration(struct chip_t *chip)
  61 {
  62         int i=0;
  63         enum sja1000_PeliCAN_MOD flags;
  64
  65         flags=can_read_reg(chip,SJAMOD);
  66
  67         while ( (flags & MOD_RM) && (i<=10) ) {
  68                 can_write_reg(chip, 0, SJAMOD);
  69 // TODO: chinfigurable MOD_AFM (32/16 bit acceptance filter)
  70 // config MOD_LOM (listen only)
  71                 udelay(100);
  72                 i++;
  73                 flags=can_read_reg(chip, SJAMOD);
  74         }
  75         if (i>=10) {
  76                 CANMSG("Error leaving reset status\n");
  77                 return -ENODEV;
  78         }
  79
  80         enable_irq(chip->chip_irq);
  81
  82         return 0;
  83 }
  84
  85 int sja1000p_chip_config(struct chip_t *chip)
  86 {
  87         if (sja1000p_enable_configuration(chip))
  88                 return -ENODEV;
  89
  90         /* Set mode, clock out, comparator */
  91         can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
  92         /* Set driver output configuration */
  93         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
  94
  95         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
  96                 return -ENODEV;
  97
  98         if (!baudrate)
  99                 baudrate=1000;
 100         if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
 101                 return -ENODEV;
 102
 103         /* Enable hardware interrupts */
 104         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
 105
 106         sja1000p_disable_configuration(chip);
 107
 108         return 0;
 109 }
 110
 111 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned  long mask)
 112 {
 113         int i;
 114
 115         if (sja1000p_enable_configuration(chip))
 116                 return -ENODEV;
 117
 118 // LSB to +3, MSB to +0
 119         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 120                 can_write_reg(chip,code&0xff,SJAACR0+i);
 121                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 122                 code >>= 8;
 123                 mask >>= 8;
 124         }
 125
 126         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 127         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 128
 129         sja1000p_disable_configuration(chip);
 130
 131         return 0;
 132 }
 133
 134 /* Set communication parameters.
 135  * param rate baud rate in Hz
 136  * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
 137  * param sjw synchronization jump width (0-3) prescaled clock cycles
 138  * param sampl_pt sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 139  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 140  */
 141 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 142                                                         int sampl_pt, int flags)
 143 {
 144         int best_error = 1000000000, error;
 145         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 146         int tseg=0, tseg1=0, tseg2=0;
 147
 148         if (sja1000p_enable_configuration(chip))
 149                 return -ENODEV;
 150
 151         clock /=2;
 152
 153         /* tseg even = round down, odd = round up */
 154         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 155                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 156                 if (brp == 0 || brp > 64)
 157                         continue;
 158                 error = rate - clock/(brp*(1+tseg/2));
 159                 if (error < 0)
 160                         error = -error;
 161                 if (error <= best_error) {
 162                         best_error = error;
 163                         best_tseg = tseg/2;
 164                         best_brp = brp-1;
 165                         best_rate = clock/(brp*(1+tseg/2));
 166                 }
 167         }
 168         if (best_error && (rate/best_error < 10)) {
 169                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 170                                                                 rate, 2*clock);
 171                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 172                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 173                 return -EINVAL;
 174         }
 175         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 176         if (tseg2 < 0)
 177                 tseg2 = 0;
 178         if (tseg2 > MAX_TSEG2)
 179                 tseg2 = MAX_TSEG2;
 180         tseg1 = best_tseg-tseg2-2;
 181         if (tseg1>MAX_TSEG1) {
 182                 tseg1 = MAX_TSEG1;
 183                 tseg2 = best_tseg-tseg1-2;
 184         }
 185
 186         DEBUGMSG("Setting %d bps.\n", best_rate);
 187         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 188                                         best_brp, best_tseg, tseg1, tseg2,
 189                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 190
 191
 192         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 193         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 194                                         | tseg1, SJABTR1);
 195
 196         sja1000p_disable_configuration(chip);
 197
 198         return 0;
 199 }
 200
 201 void sja1000p_read(struct chip_t *chip, struct canfifo_t *fifo) {
 202         int i, flags, len, datastart;
 203         do {
 204                 flags = can_read_reg(chip,SJAFRM);
 205                 if(flags&FRM_FF) {
 206                         fifo->buf_rx_entry[fifo->head].id =
 207                                 (can_read_reg(chip,SJAID0)<<21) +
 208                                 (can_read_reg(chip,SJAID1)<<13) +
 209                                 (can_read_reg(chip,SJAID2)<<5) +
 210                                 (can_read_reg(chip,SJAID3)>>3);
 211                         datastart = SJADATE;
 212                 } else {
 213                         fifo->buf_rx_entry[fifo->head].id =
 214                                 (can_read_reg(chip,SJAID0)<<3) +
 215                                 (can_read_reg(chip,SJAID1)>>5);
 216                         datastart = SJADATS;
 217                 }
 218                 fifo->buf_rx_entry[fifo->head].flags =
 219                         ((flags & FRM_RTR) ? MSG_RTR : 0) |
 220                         ((flags & FRM_FF) ? MSG_EXT : 0);
 221                 len = flags & FRM_DLC_M;
 222                 for(i=0; i< len; i++) {
 223                         fifo->buf_rx_entry[fifo->head].data[i]=
 224                                 can_read_reg(chip,datastart+i);
 225                 }
 226                 fifo->buf_rx_entry[fifo->head].length = len;
 227                 fifo->head++; fifo->head %= MAX_BUF_LENGTH;
 228 // FIXME: what if fifo->head == fifo->tail again ?
 229                 can_write_reg(chip, CMR_RRB, SJACMR);
 230         } while (can_read_reg(chip, SJASR) & SR_RBS);
 231 }
 232
 233 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 234 {
 235         int i;
 236         i=can_read_reg(chip,SJASR);
 237
 238         if (!(i&SR_RBS)) {
 239                 return 0;
 240         }
 241
 242         can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 243         sja1000p_read(chip, obj->fifo);
 244         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
 245         return 1;
 246 }
 247
 248 #define MAX_TRANSMIT_WAIT_LOOPS 200
 249 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 250                                                         struct canmsg_t *msg)
 251 {
 252         int i=0;
 253         unsigned int id;
 254
 255         /* Wait until Transmit Buffer Status is released */
 256         while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 257                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 258                 udelay(i);
 259         }
 260
 261         if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 262                 CANMSG("Transmit timed out, cancelling\n");
 263 // here we should check if there is no write/select waiting for this
 264 // transmit. If so, set error ret and wake up.
 265 // CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
 266 // immediately
 267                 can_write_reg(chip, CMR_AT, SJACMR);
 268                 i=0;
 269                 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 270                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 271                         udelay(i);
 272                 }
 273                 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 274                         CANMSG("Could not cancel, please reset\n");
 275                         return -EIO;
 276                 }
 277         }
 278         msg->length &= FRM_DLC_M;
 279         can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
 280                 ((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
 281                 msg->length, SJAFRM);
 282         if(msg->flags&MSG_EXT) {
 283                 id=msg->id<<3;
 284                 can_write_reg(chip, id & 0xff, SJAID3);
 285                 id >>= 8;
 286                 can_write_reg(chip, id & 0xff, SJAID2);
 287                 id >>= 8;
 288                 can_write_reg(chip, id & 0xff, SJAID1);
 289                 id >>= 8;
 290                 can_write_reg(chip, id, SJAID0);
 291                 for(i=0; i < msg->length; i++) {
 292                         can_write_reg(chip, msg->data[i], SJADATE+i);
 293                 }
 294         } else {
 295                 id=msg->id >> 5;
 296                 can_write_reg(chip, id & 0xff, SJAID0);
 297                 id >>= 8;
 298                 can_write_reg(chip, id & 0xff, SJAID1);
 299                 for(i=0; i < msg->length; i++) {
 300                         can_write_reg(chip, msg->data[i], SJADATS+i);
 301                 }
 302         }
 303         return 0;
 304 }
 305
 306 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 307                                                         struct canmsg_t *msg)
 308 {
 309         can_write_reg(chip, CMR_TR, SJACMR);
 310
 311         return 0;
 312 }
 313
 314 int sja1000p_check_tx_stat(struct chip_t *chip)
 315 {
 316         if (can_read_reg(chip,SJASR) & SR_TCS)
 317                 return 0;
 318         else
 319                 return 1;
 320 }
 321
 322 int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
 323                                                         unsigned short btr1)
 324 {
 325         if (sja1000p_enable_configuration(chip))
 326                 return -ENODEV;
 327
 328         can_write_reg(chip, btr0, SJABTR0);
 329         can_write_reg(chip, btr1, SJABTR1);
 330
 331         sja1000p_disable_configuration(chip);
 332
 333         return 0;
 334 }
 335
 336 int sja1000p_start_chip(struct chip_t *chip)
 337 {
 338         enum sja1000_PeliCAN_MOD flags;
 339
 340         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 341         can_write_reg(chip, flags, SJAMOD);
 342
 343         return 0;
 344 }
 345
 346 int sja1000p_stop_chip(struct chip_t *chip)
 347 {
 348         enum sja1000_PeliCAN_MOD flags;
 349
 350         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 351         can_write_reg(chip, flags|MOD_RM, SJAMOD);
 352
 353         return 0;
 354 }
 355
 356
 357 int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 358 {
 359         CANMSG("sja1000p_remote_request not implemented\n");
 360         return -ENOSYS;
 361 }
 362
 363 int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
 364                 unsigned short mask)
 365 {
 366         CANMSG("sja1000p_standard_mask not implemented\n");
 367         return -ENOSYS;
 368 }
 369
 370 int sja1000p_clear_objects(struct chip_t *chip)
 371 {
 372         CANMSG("sja1000p_clear_objects not implemented\n");
 373         return -ENOSYS;
 374 }
 375
 376 int sja1000p_config_irqs(struct chip_t *chip, short irqs)
 377 {
 378         CANMSG("sja1000p_config_irqs not implemented\n");
 379         return -ENOSYS;
 380 }
 381
 382 void sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 383 {
 384         int irq_register;
 385         chip_irq=(struct chip_t *)dev_id;
 386         device_irq=(struct candevice_t *)chip_irq->hostdevice;
 387
 388         put_reg=device_irq->hwspecops->write_register;
 389         get_reg=device_irq->hwspecops->read_register;
 390
 391         irq_register=get_reg(chip_irq->chip_base_addr+SJAIR);
 392 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 393 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 394 //                                      get_reg(chip_irq->chip_base_addr+SJASR));
 395
 396         if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
 397                 return;
 398
 399         fifo_irq=chip_irq->msgobj[0]->fifo;
 400
 401         if ((irq_register & IR_RI) != 0) {
 402                 sja1000p_read(chip_irq,fifo_irq);
 403                 chip_irq->msgobj[0]->ret = 0;
 404                 if (waitqueue_active(&fifo_irq->readq))
 405                         wake_up_interruptible(&fifo_irq->readq);
 406         }
 407         if ((irq_register & IR_TI) != 0) {
 408                 chip_irq->msgobj[0]->ret = 0;
 409                 if (waitqueue_active(&fifo_irq->writeq))
 410                         wake_up_interruptible(&fifo_irq->writeq);
 411         }
 412         if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
 413                 // Some error happened
 414                 CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
 415                         get_reg(chip_irq->chip_base_addr+SJASR), irq_register);
 416 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 417 // Reset flag set to 0 if chip is already off the bus. Full state report
 418                 chip_irq->msgobj[0]->ret=-1;
 419                 if (waitqueue_active(&fifo_irq->writeq))
 420                         wake_up_interruptible(&fifo_irq->writeq);
 421                 if (waitqueue_active(&fifo_irq->readq))
 422                         wake_up_interruptible(&fifo_irq->readq);
 423         }
 424
 425         return;
 426 }
 427
 428 int sja1000p_register(struct chipspecops_t *chipspecops)
 429 {
 430         CANMSG("initializing sja1000p chip operations\n");
 431         chipspecops->chip_config=sja1000p_chip_config;
 432         chipspecops->baud_rate=sja1000p_baud_rate;
 433         chipspecops->standard_mask=sja1000p_standard_mask;
 434         chipspecops->extended_mask=sja1000p_extended_mask;
 435         chipspecops->message15_mask=sja1000p_extended_mask;
 436         chipspecops->clear_objects=sja1000p_clear_objects;
 437         chipspecops->config_irqs=sja1000p_config_irqs;
 438         chipspecops->pre_read_config=sja1000p_pre_read_config;
 439         chipspecops->pre_write_config=sja1000p_pre_write_config;
 440         chipspecops->send_msg=sja1000p_send_msg;
 441         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 442         chipspecops->remote_request=sja1000p_remote_request;
 443         chipspecops->enable_configuration=sja1000p_enable_configuration;
 444         chipspecops->disable_configuration=sja1000p_disable_configuration;
 445         chipspecops->set_btregs=sja1000p_set_btregs;
 446         chipspecops->start_chip=sja1000p_start_chip;
 447         chipspecops->stop_chip=sja1000p_stop_chip;
 448         chipspecops->irq_handler=sja1000p_irq_handler;
 449         return 0;
 450 }